Method for manufacturing polysilicon high resistance and structure

Abstract

The application provides a method for manufacturing a polysilicon high resistance and a structure. The method comprises the following steps: providing a semiconductor substrate and forming a polysilicon layer on the surface of the semiconductor substrate; transferring a photoetch mask pattern with a preset opening rate to a polysilicon resistance area by using an existing light doping and heavy doping photoetch process; performing ion implantation on the polysilicon resistance area by using the photoetch mask pattern as a barrier layer and by using a specified tilt angle; and finally performing annealing treatment on the semiconductor substrate to activate the implanted ions and form an adjustable polysilicon high resistance. The application does not need to increase an additional photoetch mask level, and by adjusting the photoetch opening rate and the implantation tilt angle, the photoresist shadow effect is used to realize linear regulation and control of the resistivity, the manufacturing cost is reduced, and the temperature coefficient performance of the polysilicon high resistance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and structure for fabricating high-resistivity polycrystalline silicon. Background Technology

[0002] In the manufacturing process of analog and mixed-signal CMOS integrated circuits, polysilicon high resistivity is often used not only to reduce layout area and circuit power consumption, but also plays an important role in core circuit modules such as electrostatic discharge (ESD) protection and digital-to-analog conversion.

[0003] Currently, in traditional semiconductor manufacturing processes, the following two typical methods are commonly used to produce high-resistivity polycrystalline silicon:

[0004] The first approach involves adding a dedicated high-resistivity photomask layer. This approach involves coating photoresist after the polysilicon layer is formed and performing additional exposure and development steps using a dedicated mask to define the high-resistivity region separately, followed by lightly doped ion implantation. While this approach allows for precise control of the resistance value, it requires introducing an additional photolithography layer, significantly increasing process complexity, manufacturing costs, and extending the product production cycle.

[0005] The second approach reuses the existing source / drain mask layer from the CMOS process. This approach involves indiscriminately implanting N-type and P-type sources / drains (Pdiff) into the polysilicon high-resistivity region (RPOLY region) during different photolithography steps, thus forming the polysilicon high-resistivity layer. However, the polysilicon surface fabricated using this approach suffers from significant drawbacks due to a lack of effective control over doping concentration and distribution: its high-resistivity is fixed and cannot be flexibly adjusted according to circuit design requirements (i.e., the resistance is not adjustable); simultaneously, the recovery of lattice damage in the resulting film is poor, leading to an extremely unsatisfactory temperature coefficient for the polysilicon high-resistivity layer, making it difficult to meet the stringent application requirements of high-end customers for wide-temperature-range stability.

[0006] Therefore, how to cleverly utilize existing CMOS processes to fabricate polycrystalline silicon with adjustable resistivity and excellent temperature coefficient without increasing the cost of additional photomasks has become an important technical challenge that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The main technical problem solved by this invention is to provide a method for fabricating high-resistivity polysilicon, which aims to overcome the technical defects of existing technologies, such as the need to add additional photolithography mask layers to fabricate high-resistivity polysilicon, resulting in high costs, or the use of existing source-drain implantation processes, which, although cost-saving, have non-adjustable resistance and poor temperature coefficient.

[0008] To solve the above-mentioned technical problems, the present invention provides a method for fabricating high-resistivity polycrystalline silicon, comprising:

[0009] Step 1: Provide a semiconductor substrate, form a polysilicon layer on the surface of the semiconductor substrate and perform a patterning operation to define the polysilicon resistive region;

[0010] Step 2: Using existing light and heavy doping photolithography processes, transfer the photolithographic mask pattern with a preset aperture ratio to the polysilicon resistive region;

[0011] Step 3: Using the photolithographic mask pattern as a barrier layer, perform ion implantation on the polysilicon resistive region at a specified tilt angle;

[0012] Step 4: Perform annealing on the semiconductor substrate to activate ions inside the implanted polysilicon resistive region and form tunable polysilicon high resistivity.

[0013] Preferably, in step one, the semiconductor substrate is a CMOS process semiconductor substrate, and the polysilicon layer is formed based on the CMOS process.

[0014] Preferably, in step two, the process mask used in the light and heavy doping photolithography process includes an N-type source / drain injection photolithography mask or a P-type source / drain injection photolithography mask.

[0015] Preferably, in step two, the preset aperture ratio is adjusted proportionally according to the target resistivity control requirements of the polycrystalline silicon resistive region.

[0016] Preferably, in step three, the conductive ions used for ion implantation include either first-type conductive ions or second-type conductive ions.

[0017] Preferably, in step three, the first type of conductive ions includes high-concentration P-type doped ions, and the second type of conductive ions includes high-concentration N-type doped ions.

[0018] Preferably, in step four, the annealing process includes a thermal activation process performed concurrently with the original N-type or P-type source / drain annealing process.

[0019] The present invention also provides a polycrystalline silicon high-resistivity structure, manufactured by the above method, comprising:

[0020] Semiconductor substrate; polycrystalline silicon resistor layer disposed on the upper surface of semiconductor substrate; multiple doped contour regions arranged at intervals along the horizontal direction inside the polycrystalline silicon resistor layer; wherein, the physical blanking spacing between each multi-segment doped contour region presents a periodic distribution matching a preset aperture ratio, and the downward extension contour lines of the multi-segment doped contour regions present a non-vertical bias distribution trace matching a specified tilt angle.

[0021] As described above, the method and structure for fabricating polycrystalline silicon high resistivity of the present invention have the following beneficial effects:

[0022] This method cleverly reuses existing source / drain implantation and other light / heavy doping photolithography mask layers in CMOS processes, eliminating the need for additional high-resistivity photolithography masks, thus significantly reducing production costs and shortening the wafer fabrication cycle. By introducing a pre-set aperture ratio and a specified tilt angle for oblique implantation, the shading effect of the photoresist is utilized to achieve precise linear control of the implantation dose and distribution, solving the problem of non-adjustable resistance in traditional fully open implantation. Simultaneously, existing source / drain annealing processes effectively repair polycrystalline silicon lattice damage, resulting in high-resistivity polycrystalline silicon exhibiting excellent temperature coefficient performance and good process stability, meeting the application requirements of high-performance analog circuits for precision resistors. Attached Figure Description

[0023] Figure 1 The diagram shown is a schematic representation of a method for fabricating high-resistivity polycrystalline silicon according to the present invention.

[0024] Figure 2 The diagram shown is a top view of a polysilicon high-resistivity photomask and a polysilicon layer according to the present invention.

[0025] Figure 3 The diagram shown is a schematic diagram of a tilted ion implantation cross-section structure of high-resistivity polycrystalline silicon according to the present invention. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See Figure 1 This disclosure provides a method for fabricating high-resistivity polycrystalline silicon, including the following steps.

[0028] First, in step one, a semiconductor substrate is provided, a polysilicon layer is formed on the surface of the semiconductor substrate, and a patterning operation is performed to define the polysilicon resistive region.

[0029] In some embodiments, in step one, the semiconductor substrate is a CMOS process semiconductor substrate, and the polysilicon layer is formed based on the CMOS process. The semiconductor substrate is selected from silicon substrates, germanium substrates, silicon-germanium substrates, silicon carbide substrates, gallium arsenide substrates, silicon-on-insulator (SOI) substrates, or germanium-on-insulator (GOI) substrates. Before forming the polysilicon layer, an electrically isolated region has been formed on the semiconductor substrate using a shallow trench isolation (STI) process or a localized silicon oxide (LOCOS) process. The formation of the polysilicon layer is completed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) processes, and the thickness range of the polysilicon layer is set according to the circuit design rules. The patterning operation includes coating photoresist on the surface of the polysilicon layer, forming an etching mask through exposure and development, and removing excess polysilicon using reactive ion etching (RIE). The remaining strip-shaped or zigzag-shaped portions constitute the polysilicon layer. Figure 2 The main structure of the polycrystalline silicon resistor region marked POLY.

[0030] The second step then proceeds, utilizing existing light and heavy doping photolithography processes to transfer a photolithographic mask pattern with a predetermined aperture ratio to the polysilicon resistive region. (See also...) Figure 2 , Figure 2 The relative positional relationship between the photolithographic mask pattern and the underlying polysilicon layer is shown.

[0031] In some embodiments, in step two, the process mask used in the existing light and heavy doping photolithography process includes an N-type source / drain injection photolithography mask or a P-type source / drain injection photolithography mask. This step directly reuses the photolithography steps prepared for transistor source / drain region doping in the CMOS process. For example, when fabricating a P-type polysilicon resistor, a P-type source / drain injection photolithography mask is used; when fabricating an N-type resistor, an N-type source / drain injection photolithography mask is used. This avoids adding a separate photolithography layer for high-resistivity devices, thereby saving the cost of expensive photolithography mask fabrication and the capacity occupation of photolithography equipment. In addition to the source / drain injection layer, existing light and heavy doping photolithography processes also include photolithography layers that require the formation of blocking patterns on polysilicon, such as lightly doped drain (LDD) injection layers, pocket injection layers, or halo injection layers.

[0032] In some embodiments, in step two, the preset aperture ratio is adjusted proportionally according to the desired target resistivity control requirements of the polycrystalline silicon resistive region. (See also...) Figure 2 The photolithographic mask pattern does not completely expose or cover the polysilicon resistive region; instead, it is designed as a grid structure with alternating photoresist blocking regions and photoresist opening regions. The preset aperture ratio is defined as the ratio of the opening region width per unit period to the total period. By adjusting this ratio, the total amount of ions implanted into the polysilicon can be changed. For example, to obtain a higher resistance value, the preset aperture ratio is decreased, and the photoresist coverage ratio is increased.

[0033] In some embodiments, in step two, the preset aperture ratio can be in the range of 10% to 90%. Setting the aperture ratio within this range can ensure the mechanical stability of the photolithographic pattern after development and prevent the high aspect ratio photoresist lines from collapsing or drifting.

[0034] Next, in step three, using the photolithographic mask pattern as a barrier layer, ion implantation is performed on the polysilicon resistive region at a specified tilt angle. (See also...) Figure 3 , Figure 3 The interaction mechanism between the ion beam (labeled as P+ oblique injection) and the photoresist pattern and polysilicon layer is clearly demonstrated.

[0035] In some embodiments, in step three, the conductive ions used for ion implantation include ions of a first conductivity type or ions of a second conductivity type. According to Figure 2 and Figure 3 The P+ designation shown here represents P-type doping, where the implanted ion is selected from boron (B), boron difluoride (BF2), or indium (In); for N-type doping, it is selected from phosphorus (P), arsenic (As), or antimony (Sb).

[0036] In some embodiments, in step three, the first conductivity type ions include high-concentration P-type doped ions, and the second conductivity type ions include high-concentration N-type doped ions. Using high-concentration source-drain implantation conditions ensures the formation of a good low-resistance conductive region in the polysilicon region corresponding to the photolithographic opening, which is the basis for achieving resistance linearity and ohmic contact. The high-resistance characteristics are mainly contributed by the shaded and obscured regions.

[0037] In some embodiments, in step three, the specified tilt angle can range from 7 degrees to 45 degrees. For example... Figure 3 As shown, the specified tilt angle refers to the angle between the ion beam incident direction and the normal direction of the wafer surface. Because the photoresist has a certain height, when the ion beam is incident at a tilt angle, a "shadow effect" occurs on the photoresist sidewalls. This means that the actual width of the area on the polysilicon surface receiving implantation will be smaller than the physical width of the photoresist opening. As the tilt angle increases, the shadow area expands, the effective implantation area decreases, and thus the overall resistance increases. This mechanism allows designers to flexibly fine-tune the final resistance value of the polysilicon resistor simply by adjusting the tilt and rotation angle parameters of the implantation equipment without modifying the photomask layout, greatly improving the process's adaptability to different product requirements.

[0038] Finally, in step four, the semiconductor substrate undergoes annealing to activate ions implanted into the polysilicon resistive region, forming tunable polysilicon high resistivity. (See also...) Figure 1 Step four in the process.

[0039] In some embodiments, step four, the annealing process includes a thermal activation process performed concurrently with the original N-type or P-type source / drain annealing process. This can be performed in a nitrogen or argon atmosphere at 900°C to 1150°C using rapid thermal annealing (RTA), millisecond laser annealing (LSA), or furnace tube annealing processes. The annealing process repairs... Figure 3 The high-energy particle bombardment damage generated during the injection process is shown, which drives impurity ions into the polycrystalline silicon lattice. Since this high-resistivity structure is composed of multiple highly doped regions and low-doped (or undoped) regions connected in series, its carrier transport mechanism is less affected by grain boundary scattering compared to traditional monolithically lightly doped high-resistivity structures, thus exhibiting superior temperature coefficient performance and better breakdown voltage reliability.

[0040] This disclosure also provides a polycrystalline silicon high-resistivity structure manufactured using the above method. The structure includes a semiconductor substrate; a polycrystalline silicon resistive layer disposed on the upper surface of the semiconductor substrate; and multiple doped contour regions arranged at intervals along the horizontal direction inside the polycrystalline silicon resistive layer.

[0041] In this structure, the physical spacing between the multi-segment doped contour regions exhibits a periodic distribution matching the preset aperture ratio, and the downward extending contour lines of the multi-segment doped contour regions show a non-vertical bias distribution pattern matching the specified tilt angle. This structure manifests as periodic fluctuations in doping depth in the physical cross-section. Combined with... Figure 3 As shown, below the photoresist-masked area, polysilicon maintains an intrinsic or low-doped state; below the opening region, a high-doped region is formed; and below the shadow of the photoresist edge, a transition region with gradually changing doping concentration is formed. This non-vertical bias distribution is a characteristic unique to the tilt implantation process and can be characterized by scanning capacitance microscopy or secondary ion mass spectrometry. The periodically distributed physical blanking intervals (i.e., low-doped regions) act as the main resistance contributing units, and by adjusting the duty cycle of these intervals, the resistance value can be precisely adjusted.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating high-resistivity polycrystalline silicon, characterized in that, At least including: Step 1: Provide a semiconductor substrate, form a polysilicon layer on the surface of the semiconductor substrate and perform a patterning operation to define the polysilicon resistive region; Step 2: Using existing light and heavy doping photolithography processes, transfer the photolithographic mask pattern with a preset aperture ratio to the polysilicon resistive region; Step 3: Using the photolithographic mask pattern as a barrier layer, perform ion implantation on the polysilicon resistive region at a specified tilt angle; Step 4: Perform annealing on the semiconductor substrate to activate ions inside the implanted polysilicon resistive region and form tunable polysilicon high resistivity.

2. The method for fabricating high-resistivity polycrystalline silicon according to claim 1, characterized in that: In step one, the semiconductor substrate is a CMOS process semiconductor substrate, and the polysilicon layer is formed based on the CMOS process.

3. The method for fabricating high-resistivity polycrystalline silicon according to claim 1, characterized in that: In step two, the process masks used in the light and heavy doping photolithography process include N-type source / drain injection photolithography masks or P-type source / drain injection photolithography masks.

4. The method for fabricating high-resistivity polycrystalline silicon according to claim 1, characterized in that: In step two, the preset aperture ratio is adjusted proportionally according to the target resistivity control requirements of the polycrystalline silicon resistive region.

5. The method for fabricating high-resistivity polycrystalline silicon according to claim 1, characterized in that: In step three, the conductive ions used for ion implantation include either first-type or second-type conductive ions.

6. The method for fabricating high-resistivity polycrystalline silicon according to claim 5, characterized in that: In step three, the first type of conductivity ions includes high-concentration P-type doped ions, and the second type of conductivity ions includes high-concentration N-type doped ions.

7. The method for fabricating high-resistivity polycrystalline silicon according to claim 1, characterized in that: In step four, the annealing process includes a thermal activation process that is performed concurrently with the original N-type or P-type source / drain annealing process.

8. A high-resistivity polycrystalline silicon structure, characterized in that, Manufactured using the method described in any one of claims 1 to 7, comprising: Semiconductor substrate; A polycrystalline silicon resistive layer is disposed on the upper surface of a semiconductor substrate; Multiple doped contour regions are arranged at intervals along the horizontal direction inside the polysilicon resistive layer; Among them, the physical spacing between the multi-segment doped contour regions presents a periodic distribution that matches the preset aperture ratio, and the downward extension contour lines of the multi-segment doped contour regions present a non-vertical bias distribution trace that matches the specified tilt angle.

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