Artificial intelligence processing chip, control method, device, equipment and storage medium

Abstract

This application discloses an artificial intelligence processing chip, control method, apparatus, device, and storage medium, belonging to the field of integrated circuit design technology. The artificial intelligence processing chip of this application includes a power partitioning subsystem. The power partitioning subsystem includes a power distribution network and a control module. The power distribution network includes multiple processing modules, each processing module including a power selection unit. Each power selection unit is used to connect to multiple power supply lines, and the nominal voltage values ​​transmitted by the multiple power supply lines are different. The control module, connected to the multiple power selection units, is used to control the switching of the multiple power selection units based on the timing margin of the multiple processing modules, so that each processing module is connected to one of the multiple power supply lines. In this way, fine-grained power supply in space is achieved, avoiding unnecessary dynamic power consumption and leakage current.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to an artificial intelligence processing chip, control method, control device, control equipment, and computer-readable storage medium. Background Technology

[0002] With the widespread application of deep learning algorithms, artificial intelligence (AI) systems on chips (SoCs) face enormous challenges in terms of computing power and power consumption. In current AI chip designs, to simplify the design, the array of neural network processing units within the chip is usually connected to the same power supply voltage. Even if some computing units are processing non-critical path tasks, they are forced to operate at the high voltage required by the most critical path, resulting in unnecessary dynamic power consumption and leakage current. Summary of the Invention

[0003] This application provides an artificial intelligence processing chip, a control method, a control device, a control equipment, and a computer-readable storage medium to solve at least one of the aforementioned technical problems.

[0004] The artificial intelligence processing chip according to embodiments of this application includes a power partitioning subsystem, the power partitioning subsystem comprising:

[0005] A power distribution network includes multiple processing modules, each of which includes a power selection unit. Each power selection unit is used to connect multiple power supply lines, and the nominal voltage values ​​transmitted by the multiple power supply lines are different. A control module, connected to multiple power selection units, is used to control the multiple power selection units to switch on and off based on the timing margin of multiple processing modules, so that each processing module is connected to one of the multiple power supply lines. The processing modules are arranged in a matrix, and the control module is used to control the multiple power selection units to switch on and off sequentially row by row. The switching time of the multiple power selection units in two adjacent rows differs by a first duration. The power selection unit includes multiple power switching transistors connected in parallel, the number of which is equal to the number of power supply lines, and the multiple power switching transistors are connected to the multiple power supply lines respectively. The control module is used to control the on / off state of multiple power switching transistors, so as to control the power selection unit to switch and connect with one of the multiple power supply lines.

[0006] In some embodiments, the artificial intelligence processing chip includes a voltage regulation subsystem, the voltage regulation subsystem comprising: The monitoring module is used to perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip; A power management module is connected to the monitoring module and at least one of the power supply lines, respectively, and is used to adjust the voltage of at least one of the power supply lines based on the timing monitoring results.

[0007] In some embodiments, the voltage regulation subsystem further includes a counting module, a scheduling module, and a voltage stabilizing module, wherein the counting module and the scheduling module are used to acquire data status signals; The power management module includes a prediction unit, which is connected to the counting module and is used to predict the current increment based on the data status signal. The voltage regulator module is connected to the power management module and at least one of the power supply lines respectively. The power management module is used to control the working state of the voltage regulator module based on the current increment, so as to regulate the voltage of at least one of the power supply lines.

[0008] In some embodiments, the artificial intelligence processing chip includes a hybrid coding subsystem and a communication bus, the hybrid coding subsystem comprising: A differential encoding module is used to differentially encode the first data, which is the data output by the processing module; The travel coding module is used to perform travel coding on the first data; A multiplexing module is connected to the differential coding module and the run-length coding module respectively. Based on the semantic signal corresponding to the first data, it outputs the first data to the communication bus through a straight path; or, based on the semantic signal corresponding to the first data, it selects the differential coding module or the run-length coding module to encode the first data and outputs it to the communication bus.

[0009] In some implementations, the aspect ratio of the power switch is positively correlated with the nominal value of the voltage transmitted by the connected power supply line.

[0010] In some embodiments, the monitoring module includes a trigger unit, a latch unit, and a logic gate unit, wherein the logic gate unit is connected to the trigger unit and the latch unit, respectively. Both the triggering unit and the latching unit are used to sample the second data, which is the data output by the processing module corresponding to at least a portion of the signal path. The sampling time of the latching unit is delayed by a first duration compared to the sampling time of the triggering unit. The logic gate unit is used to determine the timing monitoring result based on the sampled data from the trigger unit and the latch unit.

[0011] The control method of this application embodiment is applied to an artificial intelligence processing chip of any of the above embodiments, and the control method includes: The timing margin of each processing module is determined based on the actual signal transmission time and the upper limit of the transmission time of each processing module. Based on the timing margin, multiple power selection units are switched on and off, so that each processing module is connected to one of the multiple power supply lines.

[0012] In some embodiments, the artificial intelligence processing chip includes a voltage regulation subsystem, and the control method further includes: Timing monitoring is performed on at least a portion of the signal paths in the artificial intelligence processing chip, and a pre-error signal is generated when a timing violation is detected. If it is determined that the pre-error signal has not been received, control the voltage of at least one of the power supply lines to be reduced; If it is determined that the density of the received pre-error signal has reached the target density, the control of voltage reduction of at least one of the power supply lines is stopped.

[0013] In some implementations, the step of timing monitoring at least a portion of the signal paths in the artificial intelligence processing chip and generating a pre-error signal upon detecting a timing violation includes: At the rising edge of the clock, at least a portion of the signal path is sampled to obtain first sampled data, and the second data is the data output by the processing module. The second data is sampled after a second delay from the rising edge of the clock to obtain the second sampled data; The pre-error signal is generated when the first sampled data and the second sampled data are not equal.

[0014] In some embodiments, the artificial intelligence processing chip includes a voltage regulation subsystem, and the control method further includes: Predict the current increment based on the acquired data state signal; If it is determined that the current increment exceeds the increment threshold, current is injected into at least one of the power supply lines to increase the voltage of at least one of the power supply lines.

[0015] In some embodiments, the artificial intelligence processing chip includes a hybrid coding subsystem and a communication bus, and the control method further includes: The data type of the first data is determined based on the semantic signal corresponding to the first data, and the first data is the data output by the processing module. When the data type is of the first type, the first data is output to the communication bus through a direct path; When the data type is the second type, the first data is differentially encoded and then output to the communication bus; When the data type is the third type, the first data is encoded and then output to the communication bus; The first type of data includes default data, the second type of data includes spatial data, and the third type of data includes sparse data.

[0016] The control device of this application embodiment is applied to the artificial intelligence processing chip of any of the above embodiments, and the control device includes: A determining module is used to determine the timing margin of each processing module based on the actual signal transmission time and the upper limit of the transmission time of each processing module. The switching module is used to control the switching of multiple power selection units based on the timing margin, so that each processing module is connected to one of the multiple power supply lines.

[0017] The control device according to the embodiments of this application includes one or more processors and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the control method of any of the above embodiments.

[0018] The computer-readable storage medium of the present application embodiments stores a computer program thereon, which, when executed by a processor, implements the control method of any of the above embodiments.

[0019] In the artificial intelligence processing chip, control method, control device, control equipment, and computer-readable storage medium of this application, multiple power selection units are switched on and off based on the timing margin of the processing module, so that each power selection unit is connected to one of the multiple power supply lines, thereby connecting each corresponding processing module to one of the multiple power supply lines. The nominal voltage values ​​transmitted by the multiple power supply lines are different. In this way, fine-grained power supply in space is achieved, avoiding unnecessary dynamic power consumption and leakage current.

[0020] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0021] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein: Figure 1 This is a schematic diagram of the power partitioning subsystem in some embodiments of this application; Figure 2 This is a schematic diagram of an artificial intelligence processing chip according to certain embodiments of this application; Figure 3 This is a schematic diagram of a power selection unit according to certain embodiments of this application; Figure 4 This is a schematic diagram of the monitoring module outputting a pre-error signal in some embodiments of this application; Figure 5 This is a schematic diagram of the voltage regulation subsystem according to certain embodiments of this application; Figure 6 This is a schematic diagram of the modules of the hybrid coding subsystem of some embodiments of this application; Figure 7 This is a flowchart illustrating the control method of certain embodiments of this application; Figure 8 This is a flowchart illustrating the control method of certain embodiments of this application; Figure 9 This is a flowchart illustrating the control method of certain embodiments of this application; Figure 10 This is a schematic diagram of the control device according to certain embodiments of this application; Figure 11 This is a schematic diagram of the control device according to certain embodiments of this application; Figure 12 This is a schematic diagram illustrating the connection state between a computer-readable storage medium and a processor according to certain embodiments of this application.

[0022] Explanation of reference numerals in the attached figures: Artificial intelligence processing chip 100, power partitioning subsystem 10, power distribution network 11, processing module 111, power selection unit 112, configuration register 113, driver 114, first power switch M1, second power switch M2, third power switch M3, control module 12, voltage regulation subsystem 20, monitoring module 21, trigger unit 211, latch unit 212, logic gate unit 213, power management module 22, counting module 23, scheduling module 24, voltage regulation module 25, power conversion module 26, prediction unit 27, hybrid coding subsystem 30, differential coding module 31, travel coding module 32, multiplexing module 33, control device 200, determination module 210, switching module 220, control equipment 300, processor 310, memory 320, computer-readable storage medium 400, computer program 410, processor 420. Detailed Implementation

[0023] The embodiments of this application will be further described below with reference to the accompanying drawings. The same or similar reference numerals in the drawings denote the same or similar elements or elements having the same or similar functions throughout. Furthermore, the embodiments of this application described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.

[0024] Please see Figure 1 and Figure 2 This application provides an artificial intelligence processing chip 100, which includes a power partitioning subsystem 10. The power partitioning subsystem 10 includes a power distribution network 11 and a control module 12. The power distribution network 11 includes multiple processing modules 111, each processing module 111 including a power selection unit 112. Each power selection unit 112 is used to connect to multiple power supply lines, and the nominal voltage values ​​transmitted by the multiple power supply lines are different. The control module 12 is connected to the multiple power selection units 112 and is used to control the switching of the multiple power selection units 112 based on the timing margin of the multiple processing modules 111, so that each processing module 111 is connected to one of the multiple power supply lines.

[0025] In the artificial intelligence processing chip 100 of this application embodiment, multiple power selection units 112 are switched on and off based on the timing margin of the processing module 111, so that each power selection unit 112 is connected to one of the multiple power supply lines, thereby connecting each corresponding processing module 111 to one of the multiple power supply lines. The nominal voltage values ​​transmitted by the multiple power supply lines are different. In this way, fine-grained power supply in space is achieved, avoiding unnecessary dynamic power consumption and leakage current.

[0026] Specifically, the power partitioning subsystem 10 includes a power distribution network 11, which includes multiple processing modules 111. Each processing module 111 can be a processing element (PE) for executing computational tasks in the artificial intelligence processing chip 100. The multiple processing modules 111 can form a chip physical array.

[0027] The power distribution network 11 includes multiple power supply lines, which can be conductive channels formed inside the chip for transmitting operating voltage. Their physical implementation can be a power rail or any other method. Each processing module 111 may include a power selection unit 112, and each power selection unit 112 is connected to multiple power supply lines.

[0028] The specific number of power supply lines can be determined based on the actual application and is not limited here. Multiple power supply lines may transmit voltages with different nominal values, which can be determined based on the actual application. In one example, there are three power supply lines with nominal values ​​of 0.4V, 0.65V, and 0.9V respectively.

[0029] Of the three power supply lines, the first power supply line It is a high-performance rail with a nominal value of 0.9V, which can be used to drive high-frequency calculations on the critical path in the artificial intelligence processing chip 100.

[0030] Second power supply line This is a high-efficiency rail with a nominal voltage of 0.65V, which can be used to drive non-critical paths in the AI ​​processing chip 100, serving as the second power supply line. The voltage is close to the threshold voltage of the transistor inside the processing module 111 to maximize energy efficiency.

[0031] Third power supply line The data holding rail has a nominal value of 0.4V and is used only to prevent data loss in the Static Random-Access Memory (SRAM) inside the processing module 111. Logic gate unit 213 is in a sleep state.

[0032] The power partitioning subsystem 10 also includes a control module 12, which can be a wavefront switching controller. The control module 12 is connected to multiple power selection units 112. Based on the timing margin of the multiple processing modules 111, the multiple processing units can be dynamically divided into multiple voltage domains. For example, when there are three power supply lines, the multiple processing units can be divided into three voltage domains. The first voltage domain corresponds to multiple processing modules 111 related to the critical path; due to time constraints, the first power supply line is required. Power supply. The second voltage domain corresponds to multiple processing modules 111 that are not critical to the path, with time redundancy, which can be provided by the second power supply line. Power supply. The third voltage domain corresponds to the multiple sleep processing modules 111, which can be powered by the third power supply line. powered by.

[0033] Based on timing margin, the control module 12 can control multiple power selection units 112 to switch on and off, so that each power selection unit 112 is connected to one of the multiple power supply lines, thereby connecting each corresponding processing module 111 to one of the multiple power supply lines. The power supply lines are used to supply power to the multiple processing modules 111.

[0034] In practical applications, static analysis can be performed by the compiler to dynamically divide multiple processing modules 111 into different voltage domains based on timing margins to match the timing requirements of the computing task. A configuration bit stream is generated and sent to the control module 12, so that the control module 12 can control multiple power selection units 112 to switch on and off based on the configuration bit stream.

[0035] In related technologies, the voltage supply strategy of coarse-grained power supply ignores the timing margin (slack) differences of computing nodes in AI load, resulting in unnecessary dynamic power consumption and leakage current in PE on non-critical paths.

[0036] In this embodiment, based on the timing margin of the processing module 111, multiple processing modules 111 are divided into different voltage domains, and multiple power selection units 112 are controlled to switch on and off, so that each power selection unit 112 is connected to one of the multiple power supply lines, thereby connecting each corresponding processing module 111 to one of the multiple power supply lines. The critical path calculation is divided into the high voltage domain, and the non-critical path calculation is transferred to the low voltage domain. In this way, fine-grained power supply in space is achieved, avoiding unnecessary dynamic power consumption and leakage current.

[0037] Please see Figure 1 and Figure 3 In some embodiments, the power selection unit 112 includes multiple power switches connected in parallel, the number of which is equal to the number of power supply lines, and the multiple power switches are connected to multiple power supply lines respectively. The control module 12 is used to control the on / off state of the multiple power switches to control the power selection unit 112 to switch and connect to one of the multiple power supply lines.

[0038] Specifically, the power selection unit 112 has multiple power switching transistors connected in parallel. The number of power switching transistors is equal to the number of power supply lines, and multiple power switching transistors are connected one-to-one with multiple power supply lines.

[0039] In one example, there are three power supply lines and three power switches, all of which can be P-channel metal-oxide-semiconductor (PMOS) transistors, designated as power switch M1, power switch M2, and power switch M3. The source of power switch M1 is connected to the first power supply line. The source of the second power switch M2 is connected to the second power supply line. The source of the third power switch M3 is connected to the third power supply line. The drains of the first power switch M1, the second power switch M2, and the third power switch M3 are shorted and connected to the local power grid (VDD_INTERNAL) inside the processing module 111.

[0040] The power selection unit 112 also includes a configuration register 113 and a driver 114. The driver 114 includes a level shifter and a decoder. The gates of the first power switch M1, the second power switch M2, and the third power switch M3 are all connected to the driver 114. The configuration register 113 is connected to the driver 114. The driver 114 can receive low-voltage digital signals from the configuration register 113 and output signals that can directly and reliably control multiple power switches.

[0041] Configuration register 113 stores simple binary code. This binary code is input to the decoder, which outputs specific instructions to control the three power switches. The level shifter's function is to boost current and prevent leakage. The level shifter operates at a low voltage (e.g., 0.6V), while the first power switch M1 is connected to a high-performance voltage (e.g., 0.9V). A characteristic of PMOS transistors is that they only completely turn off when the gate voltage equals the source voltage. Without a level shifter, the decoder output high level would only be 0.6V, while the source of the first power switch M1 is 0.9V. The gate-source voltage difference of the PMOS is 0.3V, which would cause current leakage.

[0042] With the first power switch M1 turned on and the second power switch M2 and the third power switch M3 turned off, the power selection unit 112 is connected to the first power supply line. Connected, from the first power supply line Power is supplied to the processing module 111 where the power selection unit 112 is located. With the second power switch M2 turned on and the first power switch M1 and the third power switch M3 turned off, the power selection unit 112 is connected to the second power supply line. Connected, powered by the second power supply line. Power is supplied to the processing module 111 where the power selection unit 112 is located. With the third power switch M3 turned on and the first power switch M1 and the second power switch M2 turned off, the power selection unit 112 is connected to the third power supply line. Connected, powered by the third power line Power is supplied to the processing module 111 where the power selection unit 112 is located.

[0043] In some implementations, the aspect ratio of the power switch is positively correlated with the nominal value of the voltage transmitted by the connected power supply line.

[0044] Specifically, the width-to-length ratios of multiple power switching transistors can be designed differently. If the nominal voltage transmitted by multiple power supply lines decreases, then the width-to-length ratios of the corresponding connected power switching transistors can also be designed to decrease. For example, with the first power supply line... The aspect ratio of the first power switch M1 is set to the maximum to support peak current; and the second power supply line The aspect ratio of the second power switch M2 is smaller than that of the first power switch M1; and the third power supply line The width-to-length ratio of the third power switch M3 is smaller than that of the second power switch M2. This balances the on-resistance and leakage current.

[0045] In one example, the three power switches of power selection unit 112 are designed with asymmetrical dimensions according to their load current requirements. Assuming a 20nm process node, the channel width w1 of the first power switch M1 is set to 100μm and the channel length l1 is set to 20nm to provide minimum on-resistance; the channel width w2 of the second power switch M2 is set to 30μm (approximately 30% of w1) and the channel length l2 is set to 20nm to reduce chip area while meeting medium load current requirements; the channel width w3 of the third power switch M3 is set to 2μm (approximately 2% of w1) and its channel length l3 is set to 30nm (slightly larger than the minimum value) to maximize the suppression of leakage current in sleep mode by utilizing the long channel effect.

[0046] Please see Figure 1 In some implementations, multiple processing modules 111 are arranged in a matrix, and the control module 12 is used to control multiple power selection units 112 to switch on and off sequentially row by row, with the switching time of multiple power selection units 112 in adjacent rows differing by a first duration.

[0047] Specifically, if multiple processing modules 111 are arranged in a matrix, then the multiple power selection units 112 corresponding to the multiple processing modules 111 are also arranged in a matrix. The control module 12 can use a wavefront diffusion strategy to control the switching of the multiple power selection units 112, that is, to control the switching of the multiple power selection units 112 in rows, batches, and with delays.

[0048] For example, when the control module 12 receives a switching command, it first sends a switching signal to the multiple power selection units 112 in the first row, controlling the multiple power selection units 112 in the first row to switch on and off; after a delay Then, a switching signal is sent to the multiple power selection units 112 in the second row, and so on. The total switching time can be expressed as... ,in, This indicates the row number. This ensures that transient current peaks are spread out, preventing the generation of large di / dt noise from simultaneously switching multiple power selection units 112.

[0049] In some examples, control module 12 is configured with a programmable delay chain. To balance power supply noise suppression with system reconfiguration delay, the delay... The specific value range can be from 2 to 10 clock cycles. Assuming the processing module 111 array has 64 rows, if... =2ns, with a total switching time of 128ns. 128ns is a negligible overhead for the scheduling gap between layers (usually in the microsecond range) and will not affect pipeline throughput; at the same time, distributing the huge transient current over 128ns greatly reduces the risk to power integrity.

[0050] Please see Figure 2 , Figure 4 and Figure 5 In some embodiments, the artificial intelligence processing chip 100 includes a voltage regulation subsystem 20. The voltage regulation subsystem 20 includes a monitoring module 21 and a power management module 22. The monitoring module 21 is used to perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip 100. The power management module 22 is connected to the monitoring module 21 and at least one power supply line, respectively, and is used to adjust the voltage of at least one power supply line based on the timing monitoring results.

[0051] Specifically, the voltage regulation subsystem 20 includes a monitoring module 21, which can employ an in-situ canary monitor. Multiple monitoring modules 21 can be deployed in the AI ​​processing chip 100 along the most timing-critical critical paths (i.e., signal paths) to monitor timing on these critical paths and determine if timing violations are imminent. In one example, each monitoring module 21 is deployed in parallel at the end of a critical path, allowing timing monitoring at the critical path's endpoint. Monitoring in the middle of a critical path would not capture delays in subsequent logic, rendering the timing monitoring data meaningless.

[0052] The specific number of monitoring modules 21 can be determined based on the actual application conditions such as chip size. The number of critical paths in which monitoring modules 21 are deployed accounts for approximately 1% to 5% of the total number of critical paths. In one example, there are 50 monitoring modules 21, which are deployed at the end of 50 critical paths. These 50 critical paths represent the most timing-critical and error-prone parts of the chip, covering process deviations and local temperature hotspots in different physical regions of the chip.

[0053] The voltage regulation subsystem 20 includes a power management module 22, which may be a power management unit (PMU). The power management module 22 is connected to the monitoring module 21 and at least one power supply line. The power management module 22 can receive timing monitoring results from the monitoring module 21 and adjust the voltage of at least one power supply line based on these results. In one example, the power management module 22 is connected to the first power supply line... The connection and power management module 22 adjusts the first power supply line based on the timing monitoring results. The voltage.

[0054] The voltage regulation subsystem 20 may further include a power conversion module 26, which may employ a direct current to direct current (DCDC) converter. The power management module 22 regulates the voltage of at least one power supply line by controlling the power conversion module 26. In one example, the power management module 22 may operate an integral controller to control the power conversion module 26 to perform voltage regulation and continuously receive timing monitoring results from the monitoring module 21. If the timing monitoring results indicate that a timing violation is about to occur in multiple critical paths, the voltage regulation is stopped.

[0055] It is understandable that the impending timing violation indicates that the AI ​​processing chip 100 is operating at the edge of its physical limits, and there is no need to adjust the voltage of at least one power supply line.

[0056] In related technologies, to address process variations and aging, chip designers typically add a 10%-20% safety margin above the minimum operating voltage. This reserved 10%-20% voltage margin is wasted for most of the early to mid-stages of the chip's lifespan, directly leading to significant energy consumption losses.

[0057] In this embodiment, the voltage of the power supply line is steadily adjusted based on the timing monitoring results, which can make the artificial intelligence processing chip 100 operate at the edge of physical limits, completely eliminate static voltage margin, reduce energy loss, and achieve a balance between performance and reliability. This makes the artificial intelligence processing chip 100 perform better or consume less power at the same power consumption. The adjustment is based on the monitoring module 21, which can save power.

[0058] Please see Figure 4In some embodiments, the monitoring module 21 includes a trigger unit 211, a latch unit 212, and a logic gate unit 213, with the logic gate unit 213 connected to both the trigger unit 211 and the latch unit 212. Both the trigger unit 211 and the latch unit 212 are used to sample second data, which is data output by the processing module 111 corresponding to at least a portion of the signal path. The sampling time of the latch unit 212 is delayed by a first duration compared to the sampling time of the trigger unit 211. The logic gate unit 213 is used to determine the timing monitoring result based on the sampled data from the trigger unit 211 and the latch unit 212.

[0059] Specifically, each monitoring module 21 includes a trigger unit 211 and a latch unit 212. In the monitoring module 21, the trigger unit 211 can sample second data at the rising edge of the clock. The second data is the data output by the processing module 111 corresponding to the critical path where the monitoring module 21 is deployed. The latch unit 212 can be a shadow latch, and can sample the second data after a first delay at the rising edge of the clock. For example, if the trigger unit 211... If sampling is performed at any time, then latch unit 212 will be in Sampling at all times.

[0060] The logic gate unit 213 is connected to the trigger unit 211 and the latch unit 212 respectively, and the timing monitoring result can be determined based on the sampled data of the trigger unit 211 and the latch unit 212.

[0061] Please see Figure 2 , Figure 4 and Figure 5 In some embodiments, the voltage regulation subsystem 20 further includes a counting module 23, a scheduling module 24, and a voltage regulator module 25. The counting module 23 and the scheduling module 24 are used to acquire data status signals. The power management module 22 includes a prediction unit 27, which is connected to the counting module 23 and is used to predict current increments based on data status signals. The voltage regulator module 25 is connected to the power management module 22 and at least one power supply line. The power management module 22 is used to control the operating state of the voltage regulator module 25 based on current increments to regulate the voltage of at least one power supply line.

[0062] Specifically, the prediction unit 27 can employ a neural load predictor, which is a 3-layer lightweight perceptron embedded within the power management unit. The lightweight model has low hardware overhead but can provide preemptive response in milliseconds or even microseconds.

[0063] The input feature vector X (i.e., the data status signal) of the prediction unit 27 includes the instruction type, cache status, and direct memory access (DMA) queue depth. The scheduling module 24, which can employ a microcontroller or driver layer, is used to obtain the instruction type, which indicates whether the current instruction is convolution, pooling, or a fully connected operation. The counting module 23 can monitor the cache status in real time and read the DMA controller's registers to obtain the DMA queue depth. The cache status refers to the L2 cache miss rate; a high L2 cache miss value indicates that the pipeline will stall and the current will decrease. The DMA queue depth represents the amount of data to be moved. The prediction unit 27 outputs a predicted value Y, which represents the current increment VI over the next N cycles (e.g., 500 ns).

[0064] The voltage regulation subsystem 20 also includes a voltage regulator module 25, which may be a low dropout regulator (LDO). The voltage regulator module 25 is connected in parallel with a power management module 22 and at least one power supply line. The power management module 22 can control the operating state of the voltage regulator module 25 based on current increments, thereby enabling the voltage regulator module 25 to regulate the voltage of at least one power supply line. In one example, the voltage regulator module 25 is connected in parallel with a first power supply line. Connect to adjust the first power supply line. The voltage.

[0065] In related technologies, power management relies on operating system-level load statistics (such as CPU utilization), with sampling periods typically in the millisecond range. Millisecond-level dynamic voltage frequency scaling (DVFS) cannot keep up with the microsecond- or even nanosecond-level abrupt changes in AI loads (such as the instantaneous start of matrix multiplication), which can easily lead to sudden voltage drops causing timing errors, or the inability to reduce voltage in time in order to maintain stability.

[0066] In this embodiment, the power management module 22 adjusts the voltage through the voltage regulation module 25 based on the current increment predicted by the prediction unit 27, thereby achieving transient dynamic voltage drop compensation. This effectively solves the risk of voltage drop caused by DVFS response lag and improves the transient stability of the system. Research has shown that the voltage can be boosted 200ns before the actual occurrence of load mutation.

[0067] Please see Figure 2 and Figure 6In some embodiments, the artificial intelligence processing chip 100 includes a hybrid coding subsystem 30 and a communication bus. The hybrid coding subsystem 30 includes a differential coding module 31, a run-length encoding module 32, and a multiplexing module 33. The differential coding module 31 performs differential coding on first data, which is the data output by the processing module 111. The run-length encoding module 32 performs run-length encoding on the first data. The multiplexing module 33 outputs the first data to the communication bus through a direct path based on the semantic signal corresponding to the first data; or, based on the semantic signal corresponding to the first data, it selects either the differential coding module 31 or the run-length encoding module 32 to encode the first data and outputs it to the communication bus.

[0068] Specifically, the hybrid coding subsystem 30 includes a differential coding module 31. The differential coding module 31 can perform differential coding on the first data. Differential coding can utilize the local smoothness of the image or weights to transmit the difference between adjacent data, reducing the numerical amplitude and thus increasing the continuity of high-order "0"s or "1"s. The differential coding formula is as follows:

[0069] in, Data after differential encoding For data transmitted at the current moment, This refers to the data transmitted a moment ago.

[0070] The differential encoding module 31 includes a set of N-bit subtractors. Since the data difference between adjacent time steps is usually small, for example, when the pixel value of image data changes from 200 to 205, the difference is 5, the high-order data lines will remain at 0 and will not flip, thus significantly reducing the bus flip rate.

[0071] The hybrid encoding subsystem 30 includes a run-length encoding module 32, which performs run-length encoding on the first data. Run-length encoding counts the number of consecutive "0"s in the data. The data stream is compressed into {Value, Run_Length} pairs through run-length encoding. For example, the original data is 0, 0, 0, 0, 5, 0, 0, which is encoded into {(0, 4), (5, 1), (0, 2)} after run-length encoding. The run-length encoding module 32 may include a zero detector and a 4-bit counter. When a non-zero number is detected or the counter overflows, the encoded data is packaged and sent.

[0072] The hybrid coding subsystem 30 includes a multiplexing module 33. The multiplexing module 33 can receive the semantic signal corresponding to the first data, which is a sideband semantic signal from the Network on Chip (NoC) bus. Using the sideband signal in the AXI4-Stream protocol, a 2-bit semantic tag corresponding to the second data can be defined as follows: Semantic tag 2'b00: Represents default data, including high-entropy data such as instructions and addresses.

[0073] Semantic label 2'b01: Represents spatial data, including spatially correlated data such as weights and image pixels.

[0074] Semantic label 2'b10: Represents sparse data, including activated feature maps containing a large number of continuous zero values.

[0075] The multiplexing module 33 is connected to the differential coding module 31 and the run-length coding module 32 respectively. The multiplexing module 33 can select either the differential coding module 31 or the run-length coding module 32 to encode the first data based on the semantic signal corresponding to the first data, and output it to the communication bus. For example, for sparse data, the run-length coding module 32 is selected for encoding.

[0076] The multiplexing module 33 is also connected to a pass-through path. Based on the semantic signal corresponding to the first data, the multiplexing module 33 can also directly output the first data to the communication bus through the pass-through path. That is, the original first data is transmitted directly without introducing additional encoding delay. The data output to the communication bus can be transmitted to the processing unit of the next layer network, on-chip memory, or off-chip memory.

[0077] This data transmission event and its traffic characteristics can also be used as one of the input feature vectors (i.e., DMA queue depth or bus busyness) of the prediction unit 27 in the aforementioned embodiments to assist the power management unit in predicting future power consumption changes of the system, thereby achieving global collaborative optimization of computing, transmission and power management.

[0078] In related technologies, when transmitting data on the on-chip bus, raw data transmission or simple bus flip-code is usually used, without distinguishing the semantic type of the transmitted data (such as weights, sparse activation values, instructions, etc.). When transmitting a large amount of sparse data and highly spatially correlated data generated by AI calculations, the bus flip-rate is high, and the dynamic power consumption on the interconnect accounts for a large proportion of the total power consumption of the SoC, reaching 30%-50%.

[0079] In this embodiment, the NoC sideband semantic signal is used to dynamically switch the encoding method according to the data type, thereby reducing the bus toggle rate.

[0080] Research has shown that on-chip interconnect power consumption is mainly determined by dynamic switching power consumption, as shown in the following formula:

[0081] in, It is the activity factor that flips, and its value is between 0 and 1. This represents the sum of the parasitic capacitance of the on-chip interconnect wires and the input capacitance at the load end. At advanced process nodes, this applies to long-distance interconnects. It occupies the main part. The supply voltage of the on-chip network and its driving circuitry determines the voltage swing of the signal switching. This represents the clock frequency at which the on-chip network transmits data. , and Due to limitations in manufacturing processes and performance specifications, significant reductions in power consumption are difficult. This application focuses on reducing the switching activity factor by using semantically aware coding to decrease the number of bus signal transitions, thereby significantly reducing power consumption without sacrificing performance.

[0082] For sparse data, run-length encoding can reduce the flip rate of large amounts of data to approximately zero. For spatial data, differential encoding can keep the high-order bus silent; simulation tests have shown that... Reduced by 25%-40%.

[0083] Please see Figure 1 and Figure 7 This application also provides a control method applied to the artificial intelligence processing chip 100 in any of the above embodiments. The control method includes: 010: Determine the timing margin of each processing module 111 based on the actual signal transmission time and the upper limit of the transmission time of each processing module 111; 020: Based on timing margin control, multiple power selection units 112 are switched on and off, so that each processing module 111 is connected to one of the multiple power supply lines.

[0084] In the control method of this application embodiment, multiple power selection units 112 are switched on and off based on the timing margin of the processing module 111, so that each power selection unit 112 is connected to one of the multiple power supply lines, thereby connecting each corresponding processing module 111 to one of the multiple power supply lines. The nominal voltage values ​​transmitted by the multiple power supply lines are different. In this way, fine-grained power supply in space is achieved, avoiding unnecessary dynamic power consumption and leakage current.

[0085] Specifically, through static analysis performed by the compiler, the compiler backend can analyze the data flow graph of the neural network and calculate the timing margin of each computation node i (i.e., processing module 111). The calculation formula is as follows:

[0086] in, For timing margin, Arrival time represents the actual time it takes for the data signal to reach computing node i after passing through the logic gate. To require time, it means to satisfy the current clock cycle. The constraint is the latest time that the data signal must arrive.

[0087] After determining the timing margin, multiple power selection units 112 can be controlled to switch on and off based on the timing margin. A margin threshold can be set. Time margin With margin threshold For each processing module 111, if... This indicates that the processing module 111 is a critical computing node with tight deadlines. The power selection unit 112 controlling the processing module 111 switches the power supply to connect the processing module 111 to the first power supply line. .like This indicates that the processing module 111 is a non-critical computing node with time redundancy. The power selection unit 112 controlling the processing module 111 switches the power supply to connect the processing module 111 to the second power supply line. Although this will increase the logic gate latency, as long as the arrival time after the increased latency is still less than the required time... This will prevent timing errors and significantly reduce power consumption.

[0088] In one example The value refers to 10% of the system clock cycle. That is to say, a computing node will only be switched to low voltage mode if its idle time exceeds 10% of the entire clock cycle.

[0089] Research has revealed that the power consumption benefit formula for the AI ​​processing chip 100 is as follows: ,in, Effective load capacitance refers to the total equivalent capacitance that a circuit needs to charge and discharge during switching, including the gate capacitance of a transistor, source-drain parasitic capacitance, and parasitic capacitance of metal interconnects. This refers to the operating clock frequency, specifically the clock speed at which the processing unit or system logic flips. If the supply voltage of a non-critical node drops from 0.9V to 0.65V, the dynamic power consumption will be approximately (0.65 / 0.9V) of the original value. 2 ≈52%, which means it can save nearly half of the power consumption.

[0090] Please see Figure 5 and Figure 8 In some embodiments, the artificial intelligence processing chip 100 includes a voltage regulation subsystem 20. The control method further includes: 030: Perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip 100, and generate a pre-error signal if a timing violation is detected; 040: If it is determined that no pre-error signal has been received, control the voltage reduction of at least one power supply line; 050: If it is determined that the density of the received error signal has reached the target density, stop controlling the voltage reduction of at least one power supply line.

[0091] Please see Figure 5 and Figure 8 In some implementations, timing monitoring is performed on at least a portion of the signal paths in the artificial intelligence processing chip 100, and a pre-error signal is generated upon detection of a timing violation, including: At the rising edge of the clock, at least a portion of the signal path is sampled to obtain the first sampled data, and the second data is the data output by the processing module 111. The second data is sampled after a second delay from the rising edge of the clock to obtain the second sampled data; If the first sampled data and the second sampled data are not equal, a pre-error signal is generated.

[0092] Specifically, the trigger unit 211 is activated at the rising edge of the clock (e.g., At a certain time, at least a portion of the signal path's second data is sampled to obtain the first sampled data. Delay a second duration on the rising edge of the clock (e.g.) At time ( ), the second data is sampled to obtain the second sampled data. This is to perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip 100. If the first sampled data... Not equal to This indicates that the data signal transition occurs during ( , The circuit is in the danger window. At this time, although the trigger unit 211 may have sampled the correct value (or it may not have sampled it), it indicates that the circuit speed has been slowed down due to the voltage drop and a timing violation is about to occur. The logic gate unit 213 outputs a high level, generating a pre-error signal.

[0093] The power management unit operates an integral controller. If no pre-error signal is received, the power management unit can control the power converter to gradually reduce the output voltage of the power supply line. If the density of received pre-error signals reaches the target density, indicating that the AI ​​processing chip 100 is operating at the edge of its physical limits and no further voltage adjustment is needed, the power management unit stops controlling the power converter to reduce the voltage.

[0094] The target density can be set according to the actual application situation, and there is no limit here.

[0095] Please see Figure 5In some embodiments, the artificial intelligence processing chip 100 includes a voltage regulation subsystem 20, and the control method further includes: Predict the current increment based on the acquired data state signal; If the current increment exceeds the increment threshold, current is injected into at least one power supply line to increase the voltage of at least one power supply line.

[0096] Specifically, when the current increment exceeds the increment threshold, the power management module 22 immediately activates the voltage regulator module 25. The voltage regulator module 25 can directly inject current into at least one power supply line, raising the voltage 200ns before the actual load change occurs to prevent voltage drop. In this way, the risk of voltage drop caused by DVFS response lag is effectively solved, and the transient stability of the system is improved.

[0097] For example, if the predicted current increment is 0.5A, the power conversion module can react in time, and there is no need to start the voltage regulator module. If the predicted current increment is 3A, the power conversion module cannot react in time, and the voltage will drop instantly. In this case, the voltage regulator module must be triggered to "inject power".

[0098] Please see Figure 6 and Figure 9 In some embodiments, the artificial intelligence processing chip 100 includes a hybrid coding subsystem 30 and a communication bus, and the control method further includes: 060: Determine the data type of the first data based on the semantic signal corresponding to the first data. The first data is the data output by the processing module 111. 070: When the data type is type 1, the first data is output to the communication bus through a direct path; 080: When the data type is the second type, the first data is differentially encoded and then output to the communication bus; 090: When the data type is the third type, the first data is encoded and then output to the communication bus; The first type of data includes default data, the second type of data includes spatial data, and the third type of data includes sparse data.

[0099] Specifically, the data type of the first data is determined based on the semantic signal corresponding to the first data. The data types include a first type, a second type, and a third type. The first type of data includes default data, the second type of data includes spatial data, and the third type of data includes sparse data.

[0100] When the data type is type 1, the multiplexing module 33 can directly output the first data to the communication bus via a pass-through path. That is, it directly transmits the original first data without introducing additional encoding delay.

[0101] When the data type is the second type, the multiplexing module 33 can select the differential encoding module 31 to perform differential encoding on the first data, and then output the differentially encoded data to the communication bus.

[0102] When the data type is the third type, the multiplexing module 33 can select the travel encoding module 32 to perform travel encoding on the first data, and then output the travel-encoded data to the communication bus.

[0103] In this embodiment, the NoC sideband semantic signal is used to dynamically switch the encoding method according to the data type, thereby reducing the bus toggle rate.

[0104] Please see Figure 1 and 10 This application also provides a control device 200, which is applied to the artificial intelligence processing chip 100 of any of the above embodiments. The control device 200 includes a determining module 210 and a switching module 220. The determining module 210 is used to determine the timing margin of each processing module 111 based on the actual signal transmission time of each processing module 111 and the upper limit of the transmission time. The switching module 220 is used to control multiple power selection units 112 to switch on and off based on the timing margin, so that each processing module 111 is connected to one of the multiple power supply lines.

[0105] In some embodiments, the artificial intelligence processing chip 100 includes a voltage regulation subsystem 20, and the control device 200 further includes a first regulation module. The first regulation module is used to perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip 100, and generate a pre-error signal when a timing violation is detected; control the voltage reduction of at least one power supply line when it is determined that no pre-error signal has been received; and stop controlling the voltage reduction of at least one power supply line when it is determined that the density of the received pre-error signal has reached a target density.

[0106] In some implementations, the first adjustment module is specifically used to sample the second data of at least a portion of the signal path at the rising edge of the clock to obtain the first sampled data, the second data being the data output by the processing module 111; to sample the second data after a second delay at the rising edge of the clock to obtain the second sampled data; and to generate a pre-error signal if the first sampled data and the second sampled data are not equal.

[0107] In some embodiments, the artificial intelligence processing chip 100 includes a voltage regulation subsystem 20, and the control device 200 further includes a second regulation module. The second regulation module is used to predict the current increment based on the acquired data state signal; and if it is determined that the current increment exceeds the increment threshold, inject current into at least one power supply line to increase the voltage of at least one power supply line.

[0108] In some embodiments, the artificial intelligence processing chip 100 includes a hybrid coding subsystem 30 and a communication bus, and the control device 200 further includes a multiplexing module. The multiplexing module is used to determine the data type of the first data based on the semantic signal corresponding to the first data, where the first data is the data output by the processing module 111. If the data type is of type 1, the first data is output to the communication bus via a direct path. If the data type is of type 2, the first data is differentially encoded and then output to the communication bus. If the data type is of type 3, the first data is run-length encoded and then output to the communication bus. The first type of data includes default data, the second type of data includes spatial data, and the third type of data includes sparse data.

[0109] It should be noted that the explanations and descriptions of the artificial intelligence processing chip 100 and the control method in the foregoing embodiments also apply to the control device 200 in the embodiments of this application, and will not be elaborated here.

[0110] Please see Figure 11 This application also provides a control device 300300. The control device 300300 includes one or more processors 310 and a memory 320. The memory 320 stores a computer program, which, when executed by the processor 310, implements the control method of any of the above embodiments.

[0111] For example, when a computer program is executed by processor 310, the following control method is implemented: 010: Determine the timing margin of each processing module 111 based on the actual signal transmission time and the upper limit of the transmission time of each processing module 111; 020: Based on timing margin control, multiple power selection units 112 are switched on and off, so that each processing module 111 is connected to one of the multiple power supply lines.

[0112] For example, when a computer program is executed by processor 310, the following control method is implemented: 030: Perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip 100, and generate a pre-error signal if a timing violation is detected; 040: If it is determined that no pre-error signal has been received, control the voltage reduction of at least one power supply line; 050: If it is determined that the density of the received error signal has reached the target density, stop controlling the voltage reduction of at least one power supply line.

[0113] It should be noted that the explanations and descriptions of the artificial intelligence processing chip 100 and the control method in the foregoing embodiments also apply to the control device 300300 in the embodiments of this application, and will not be elaborated here.

[0114] Please see Figure 12 This application also provides a computer-readable storage medium 400 storing a computer program 410 thereon. When the program is executed by the processor 420, it implements the control method of any of the above embodiments.

[0115] For example, when the program is executed by processor 420, the following control method is implemented: 010: Determine the timing margin of each processing module 111 based on the actual signal transmission time and the upper limit of the transmission time of each processing module 111; 020: Based on timing margin control, multiple power selection units 112 are switched on and off, so that each processing module 111 is connected to one of the multiple power supply lines.

[0116] For example, when the program is executed by processor 420, the following control method is implemented: 030: Perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip 100, and generate a pre-error signal if a timing violation is detected; 040: If it is determined that no pre-error signal has been received, control the voltage reduction of at least one power supply line; 050: If it is determined that the density of the received error signal has reached the target density, stop controlling the voltage reduction of at least one power supply line.

[0117] It should be noted that the explanations and descriptions of the artificial intelligence processing chip 100 and the control method in the foregoing embodiments also apply to the computer-readable storage medium 400 in the embodiments of this application, and will not be elaborated here.

[0118] In summary, in the artificial intelligence processing chip 100, control method, control device 200, control equipment 300300, and computer-readable storage medium 400 of this application, multiple power selection units 112 are switched on and off based on the timing margin of the processing module 111, so that each power selection unit 112 is connected to one of the multiple power supply lines, thereby connecting each corresponding processing module 111 to one of the multiple power supply lines. The nominal voltage values ​​transmitted by the multiple power supply lines are different. In this way, fine-grained power supply in space is achieved, avoiding unnecessary dynamic power consumption and leakage current.

[0119] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0120] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0121] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable storage medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, a computer-readable storage medium can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable storage medium could be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0122] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0123] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments. Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0124] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. An artificial intelligence processing chip, characterized in that, Includes a power partitioning subsystem, the power partitioning subsystem comprising: A power distribution network includes multiple processing modules, each of which includes a power selection unit. Each power selection unit is used to connect multiple power supply lines, and the nominal voltage values ​​transmitted by the multiple power supply lines are different. A control module, connected to multiple power selection units, is used to control the multiple power selection units to switch on and off based on the timing margin of multiple processing modules, so that each processing module is connected to one of the multiple power supply lines. The processing modules are arranged in a matrix, and the control module is used to control the power selection units to switch on and off sequentially row by row. The switching time of the power selection units in two adjacent rows differs by a first duration. The power selection unit includes multiple power switching transistors connected in parallel, the number of which is equal to the number of power supply lines, and the multiple power switching transistors are connected to the multiple power supply lines respectively. The control module is used to control the on / off state of multiple power switching transistors, so as to control the power selection unit to switch and connect with one of the multiple power supply lines.

2. The artificial intelligence processing chip according to claim 1, characterized in that, The artificial intelligence processing chip includes a voltage regulation subsystem, which comprises: The monitoring module is used to perform timing monitoring on at least a portion of the signal paths in the artificial intelligence processing chip; A power management module is connected to the monitoring module and at least one of the power supply lines, respectively, and is used to adjust the voltage of at least one of the power supply lines based on the timing monitoring results.

3. The artificial intelligence processing chip according to claim 2, characterized in that, The voltage regulation subsystem further includes a counting module, a scheduling module, and a voltage stabilizing module, wherein the counting module and the scheduling module are used to acquire data status signals; The power management module includes a prediction unit, which is connected to the counting module and is used to predict the current increment based on the data status signal. The voltage regulator module is connected to the power management module and at least one of the power supply lines respectively. The power management module is used to control the working state of the voltage regulator module based on the current increment, so as to regulate the voltage of at least one of the power supply lines.

4. The artificial intelligence processing chip according to claim 1, characterized in that, The artificial intelligence processing chip includes a hybrid coding subsystem and a communication bus, wherein the hybrid coding subsystem includes: A differential encoding module is used to differentially encode the first data, which is the data output by the processing module; The travel coding module is used to perform travel coding on the first data; A multiplexing module is connected to the differential coding module and the run-length coding module respectively. Based on the semantic signal corresponding to the first data, it outputs the first data to the communication bus through a straight path; or, based on the semantic signal corresponding to the first data, it selects the differential coding module or the run-length coding module to encode the first data and outputs it to the communication bus.

5. The artificial intelligence processing chip according to claim 1, characterized in that, The aspect ratio of the power switch is positively correlated with the nominal value of the voltage transmitted by the connected power supply line.

6. The artificial intelligence processing chip according to claim 2, characterized in that, The monitoring module includes a trigger unit, a latch unit, and a logic gate unit, wherein the logic gate unit is connected to the trigger unit and the latch unit respectively; Both the triggering unit and the latching unit are used to sample the second data, which is the data output by the processing module corresponding to at least a portion of the signal path. The sampling time of the latching unit is delayed by a first duration compared to the sampling time of the triggering unit. The logic gate unit is used to determine the timing monitoring result based on the sampled data from the trigger unit and the latch unit.

7. A control method, characterized in that, The control method, applied to the artificial intelligence processing chip according to any one of claims 1-6, comprises: The timing margin of each processing module is determined based on the actual signal transmission time and the upper limit of the transmission time of each processing module. Based on the timing margin, multiple power selection units are switched on and off, so that each processing module is connected to one of the multiple power supply lines.

8. The control method according to claim 7, characterized in that, The artificial intelligence processing chip includes a voltage regulation subsystem, and the control method further includes: Timing monitoring is performed on at least a portion of the signal paths in the artificial intelligence processing chip, and a pre-error signal is generated when a timing violation is detected. If it is determined that the pre-error signal has not been received, control the voltage of at least one of the power supply lines to be reduced; If it is determined that the density of the received pre-error signal has reached the target density, the control of voltage reduction of at least one of the power supply lines is stopped.

9. The control method according to claim 8, characterized in that, The step of timing monitoring at least a portion of the signal paths in the artificial intelligence processing chip, and generating a pre-error signal upon detecting a timing violation, includes: At the rising edge of the clock, at least a portion of the signal path is sampled to obtain first sampled data, and the second data is the data output by the processing module. The second data is sampled after a second delay from the rising edge of the clock to obtain the second sampled data; The pre-error signal is generated when the first sampled data and the second sampled data are not equal.

10. The control method according to claim 7, characterized in that, The artificial intelligence processing chip includes a voltage regulation subsystem, and the control method further includes: Predict the current increment based on the acquired data state signal; If it is determined that the current increment exceeds the increment threshold, current is injected into at least one of the power supply lines to increase the voltage of at least one of the power supply lines.

11. The control method according to claim 7, characterized in that, The artificial intelligence processing chip includes a hybrid encoding subsystem and a communication bus, and the control method further includes: The data type of the first data is determined based on the semantic signal corresponding to the first data, and the first data is the data output by the processing module. When the data type is of the first type, the first data is output to the communication bus through a direct path; When the data type is the second type, the first data is differentially encoded and then output to the communication bus; When the data type is the third type, the first data is encoded and then output to the communication bus; The first type of data includes default data, the second type of data includes spatial data, and the third type of data includes sparse data.

12. A control device, characterized in that, The control device, applied to the artificial intelligence processing chip according to any one of claims 1-6, comprises: A determining module is used to determine the timing margin of each processing module based on the actual signal transmission time and the upper limit of the transmission time of each processing module. The switching module is used to control the switching of multiple power selection units based on the timing margin, so that each processing module is connected to one of the multiple power supply lines.

13. A control device, characterized in that, The control device includes one or more processors and a memory, the memory storing a computer program that, when executed by the processor, implements the control method according to any one of claims 7-11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the control method according to any one of claims 7-11.

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