An NPU verification system and method, an electronic device, and a storage medium
By using compilation rules consistent with the NPU under test to generate instructions and comparing the calculation results in the simulation model, the problem of insufficient comprehensiveness of NPU verification in the prior art is solved, and comprehensive verification of compiler and hardware computing functions is realized, thereby improving the comprehensiveness of verification and debugging efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-25
- Publication Date
- 2026-07-17
AI Technical Summary
In existing technologies, NPU verification only verifies the hardware computing function, resulting in low verification comprehensiveness and an inability to ensure the correctness of the instructions generated by the compiler and the accuracy of the NPU hardware calculations.
Instructions are generated using compilation rules consistent with those of the NPU under test. The compiler simulator, instruction dispatch component, and hardware simulation component in the simulation model are used to execute and compare the calculation results of the first and second instructions to determine whether the software compilation function and hardware calculation function are normal.
It improves the comprehensiveness of NPU verification, enabling simultaneous verification of whether the compiler-generated instructions are correct and whether the NPU hardware computing functions are accurate, reducing verification blind spots and improving debugging efficiency.
Smart Images
Figure CN122414286A_ABST