Dynamic vector mask generation and control flow optimization method and device
By developing a method and apparatus for generating and optimizing control flow in a RISC-V processor, the problems of high vector mask generation overhead, low data processing efficiency, and insufficient dynamic vector length adaptation are solved, thereby improving vector execution efficiency and control flow optimization capabilities.
Patent Information
- Application Number
- CN202610895992.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-22
- Publication Date
- 2026-07-21
- Estimated Expiration
- 2046-06-22
AI Technical Summary
In the RISC-V processor architecture, existing vector mask generation schemes suffer from high mask generation overhead, low data processing efficiency, and insufficient dynamic vector length adaptation capability. In particular, the control flow optimization effect is limited when dealing with complex condition judgments and dynamic vector length changes.
By acquiring and executing, the bit-level conditional expression information in the parsing program is parsed, and the bit-level conditions are parsed to obtain the parsing result. By converting the format of the compact bit vector, an adaptation vector mask generation and control flow optimization device is obtained. The generation and control flow optimization method and device control the execution behavior of data elements, realize conditional execution of elements, and reduce or replace control flow jumps based on conditional branch instructions.
This technology enables the reduction of mask generation latency, improvement of vector execution efficiency, enhanced adaptability to dynamic vector length environments, and reduction of control flow path overhead in RISC-V processors.