A method and apparatus for dynamic vector mask generation and control flow optimization

Abstract

The application discloses a dynamic vector mask generation and control flow optimization method and device, and relates to the technical field of computers. The method comprises the following steps: acquiring and analyzing bit-level condition expression information in an executed program; extracting, rearranging or combining a target bit to generate a compact bit vector representing an execution condition of a target data element; performing format conversion on the compact bit vector based on a vector configuration parameter to generate a vector mask adapted to the current vector register layout; controlling the execution behavior of the target data element based on the vector mask; and adaptively adjusting the vector mask when the vector length changes. By constructing a mapping relationship between the bit-level condition and the vector mask, the direct control of the bit operation result on the vector execution is realized, the mask generation overhead and the control flow branch overhead are reduced, and the vector execution efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method and apparatus for dynamic vector mask generation and control flow optimization. Background Technology

[0002] In processor architectures based on fifth-generation Reduced Instruction Set Computer (RISC-V) processors, the processor can implement conditional execution based on data elements using vector masks. Through vector masks, the processor can conditionally control whether each data element in the vector register participates in the computation, thereby reducing the performance overhead of some conditional branches.

[0003] However, existing partial vector mask generation schemes based on RISC-V vector extensions still have some areas for improvement. For example, when dealing with complex bit-level conditional judgments, multiple comparison and logical operation instructions are usually required to collaboratively construct the mask, increasing the number of instructions and incurring additional execution overhead. Meanwhile, in some scenarios, the conditional judgment result and the vector mask still require additional data organization or format conversion processes, thus increasing data processing overhead and affecting execution efficiency.

[0004] Furthermore, in execution environments where vector lengths can dynamically change, the vector masks generated by existing solutions are often related to specific vector configurations. When the vector length changes, the mask usually needs to be reconstructed or adjusted, further increasing system overhead. Regarding control flow optimization, for complex conditional decision-making scenarios, there may still be issues with high mask construction overhead or limited control flow optimization effectiveness.

[0005] Therefore, in view of the problems of high mask generation overhead, low data processing efficiency and insufficient dynamic vector length adaptation capability in the existing technology, there is an urgent need for a new vector mask generation and control flow optimization scheme. Summary of the Invention

[0006] This invention provides a method and apparatus for dynamic vector mask generation and control flow optimization. By constructing a mapping relationship between bit-level conditions and vector masks, it realizes direct control of vector execution by bit operation results, reduces mask generation overhead and data conversion overhead, improves control flow optimization capability and vector execution efficiency, and enhances adaptability in dynamic vector length environments.

[0007] In a first aspect, embodiments of this application provide a dynamic vector mask generation and control flow optimization method. The method includes: acquiring bit-level conditional expression information in an executable program, parsing the bit-level conditional expression information to obtain a parsing result, wherein the parsing result includes target bits involved in condition judgment and the logical combination relationship between the target bits; performing data processing on the target bits based on the logical combination relationship to obtain a compact bit vector, wherein the compact bit vector is used to characterize the execution conditions of each target data element, and each bit in the compact bit vector has an element index mapping relationship with the target data element; performing format conversion on the compact bit vector based on vector configuration parameters to obtain a vector mask adapted to a vector register; controlling the execution behavior of data elements based on the vector mask to reduce or replace control flow jumps based on conditional branch instructions; monitoring changes in vector length during the execution of the executable program; and updating the vector mask when the vector length changes to ensure the consistency of mask semantics under different vector lengths.

[0008] This application provides a dynamic vector mask generation and control flow optimization scheme. By processing bit-level conditions, the mask construction process, which originally required multiple scalar logic instructions, is transformed into a compact bit vector generation process. Furthermore, format conversion enables direct conversion from compact bit vectors to vector masks, thereby reducing intermediate data movement and instruction sequence length, lowering mask generation latency, and improving mask generation efficiency. In addition, by transforming conditional judgments into vector mask control, element-wise execution based on the mask is achieved, thus reducing or replacing some control flow paths based on conditional branch instructions.

[0009] One possible implementation is that the above vector configuration parameters include: Vector Length (VL), Standard Element Width (SEW), and Length Multiplier (LMUL); wherein, VL is used to indicate the number of data elements currently being processed, SEW is used to indicate the bit width of the data elements, and LMUL is used to indicate the vector register group multiplier.

[0010] Another possible implementation is that, based on the vector configuration parameters, the compact bit vector is format-converted to obtain a vector mask for the vector register. Specifically, this can be achieved by: padding the compact bit vector with bit spacing according to the SEW; determining the distribution relationship of the mask in the vector register according to the LMUL; and determining the effective bit boundaries of the mask according to the VL to obtain the vector mask for the vector register.

[0011] Another possible implementation is that, based on the logical combination relationship, the target bit is processed to obtain a compact bit vector. Specifically, this can be achieved by performing one or more of the following processes on the target bit: extraction, rearrangement, and combination, based on the logical combination relationship, to obtain the compact bit vector.

[0012] Another possible implementation, based on the vector mask, controls the execution behavior of data elements. Specifically, this can be achieved by: determining the validity of vector instructions in the executable program based on the vector mask; if the vector mask corresponding to the vector instruction includes partially invalid masks, suppressing the computation of data elements corresponding to the partially invalid masks; and if the vector mask corresponding to the vector instruction is entirely invalid, suppressing the vector instruction from entering the vector execution unit. By evaluating mask validity during the vector instruction dispatch stage and suppressing the computation of invalid elements or the issuance of invalid instructions, pipeline disturbances caused by branch prediction failures can be effectively reduced, improving the stability and throughput of processor execution.

[0013] Another possible implementation is that updating the vector mask described above can be specifically achieved by: adjusting the effective bit boundaries of the vector mask; and / or updating the correspondence between the mask and data elements. When the vector length changes, by adjusting the effective bit boundaries of the mask and the element mapping relationship, it is possible to avoid rebuilding all mask data, thereby reducing the execution overhead in a dynamic vector length environment.

[0014] Another possible implementation, the dynamic vector mask generation and control flow optimization method provided in this application, further includes: maintaining, updating, and reusing the remaining bit states or unaligned bit states in the vector mask during the cross-vector instruction execution process or cross-iteration execution process of the executor, so as to reduce the number of times the vector mask is repeatedly generated. By introducing a mask state buffering and propagation mechanism, the vector mask can be reused during cross-instruction or cross-iteration execution, avoiding repeated mask generation operations, thereby further reducing computational overhead and improving overall execution efficiency.

[0015] Another possible implementation is that the bit-level conditional expression information mentioned above includes one or more of the following: logical judgment expressions in the executor, conditional branch instructions, or intermediate representations generated by the compiler.

[0016] Another possible implementation is that the data processing of the target bit is achieved through bit manipulation logic.

[0017] Secondly, a dynamic vector mask generation and control flow optimization device is provided, the device comprising: a condition parsing module, a bit operation processing module, a mask generation module, a mask control execution module, and a dynamic adaptation module.

[0018] The condition parsing module is used to obtain bit-level condition expression information in the executable program, and parse the bit-level condition expression information to obtain the parsing result. The parsing result includes the target bits involved in the condition judgment and the logical combination relationship between the target bits.

[0019] The bit manipulation processing module is used to perform one or more of the following processes on the target bits based on the parsing result: extraction, rearrangement, and combination, to obtain a compact bit vector. The compact bit vector is used to characterize the execution conditions of each target data element, and each bit in the compact bit vector has an element index mapping relationship with the target data element.

[0020] The mask generation module is used to perform format conversion on the compact bit vector based on the vector configuration parameters to obtain a vector mask that adapts to the vector register.

[0021] The mask control execution module is used to control the execution behavior of data elements based on the vector mask.

[0022] The dynamic adaptation module is used to adjust the effective bit boundaries of the vector mask and / or update the correspondence between the vector mask and data elements when the vector length changes, so as to ensure the consistency of mask semantics under different vector lengths.

[0023] The dynamic vector mask generation and control flow optimization apparatus provided in the second aspect is used to execute the method provided in the first aspect or any possible implementation of the first aspect. The corresponding technical effects can be found in the first aspect above, and will not be repeated here.

[0024] Thirdly, embodiments of this application provide a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in any possible implementation of the first aspect.

[0025] Fourthly, embodiments of this application provide a computer program product, including a computer program, which, when executed by a processor, implements the method described in any possible implementation of the first aspect.

[0026] The solutions provided in the third and fourth aspects above are used to implement the method provided in the first aspect above. The specific implementation process can be found in the first aspect above, and will not be repeated here. The technical effects corresponding to any implementation method of the solutions provided in the third and fourth aspects above can be found in the technical effects corresponding to any implementation method in the first aspect above, and will not be repeated here.

[0027] It should be noted that any of the possible implementation methods in the above aspects can be combined with each other as long as the solutions do not conflict. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the architecture of a computing system provided in an exemplary embodiment of this application; Figure 2 This is a flowchart of a dynamic vector mask generation and control flow optimization method provided in an exemplary embodiment of this application; Figure 3 This is a flowchart of a dynamic vector mask generation and control flow optimization method provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram of a dynamic vector mask generation and control flow optimization system architecture provided in an exemplary embodiment of this application; Figure 5 This is a schematic diagram of vector mask generation and control flow optimization provided in an exemplary embodiment of this application; Figure 6 This is a schematic diagram of the structure of a dynamic vector mask generation and control flow optimization apparatus provided in an exemplary embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application. Detailed Implementation

[0030] In the embodiments of this application, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different. The technical features described by "first" and "second" have no sequential or size order.

[0031] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0032] In the embodiments of this application, at least one can also be described as one or more, and multiple can be two, three, four or more, and this application does not impose any restrictions.

[0033] Furthermore, the network architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0034] It should be noted that the information (including but not limited to device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the subject or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0035] In the RISC-V processor architecture, the processor can implement conditional execution based on data elements using vector masks. Through vector masks, the processor can conditionally control whether each data element in the vector register participates in the computation, thereby reducing the performance overhead of some conditional branches.

[0036] To address the conditional execution requirements in vectorized computation, the industry typically uses vector masking mechanisms to achieve element-wise selective computation.

[0037] Firstly, in terms of vector mask generation, the industry typically uses scalar comparison instructions or vector comparison instructions to generate conditional results. For example, the target bit pattern is gradually constructed by combining the conditional judgment result in the scalar register with logical operation instructions (such as AND, OR, shift, etc.), or an element-wise Boolean mask is directly generated using vector comparison instructions. This type of method relies on the combination of multiple instructions to complete the mask generation process. When complex bit conditions or multiple condition combinations are involved, the instruction sequence is long and the execution path is quite verbose.

[0038] Secondly, in converting scalar bit operation results into vector masks, the industry typically employs data movement and format conversion methods. For example, bit data in a scalar register is written back to memory and then read into a vector register by a vector load instruction, or a vector mask is constructed by element-by-element insertion. These methods require memory access or multiple register operations, resulting in long data paths and increased memory access overhead and execution latency.

[0039] Furthermore, in terms of control flow processing, the industry typically employs branch instructions or compiler-based if-conversion techniques to convert some conditional branches into masked vector execution. However, when dealing with complex bit conditions or control dependencies across basic blocks, some branch instructions still need to be retained, or additional intermediate masks need to be constructed, which limits the effectiveness of control flow optimization and makes it difficult to completely eliminate pipeline disturbances caused by branches.

[0040] In summary, the generation and use of vector masks still have shortcomings in terms of mask generation efficiency, data conversion overhead between scalars and vectors, control flow optimization capabilities, and adaptability to dynamic vector lengths, making it difficult to meet the needs of efficient bit-level condition processing and vectorized execution.

[0041] Based on this, this application provides a dynamic vector mask generation and control flow optimization scheme. It obtains bit-level conditional expression information from the executable program and parses this information to obtain the parsing result. Based on logical combination relationships, it processes the target bits to obtain a compact bit vector. Based on vector configuration parameters, it performs format conversion on the compact bit vector to obtain a vector mask adapted to the vector register. It controls the execution behavior of data elements based on the vector mask. During execution, it monitors changes in vector length and updates the vector mask when the length changes to ensure semantic consistency. By processing bit-level conditions, the mask construction process, which originally required multiple scalar logic instructions, is transformed into a compact bit vector generation process. Furthermore, format conversion enables direct mapping from compact bit vectors to vector masks, reducing intermediate data movement and instruction sequence length, lowering mask generation latency, and improving mask generation efficiency. In addition, by transforming conditional judgments into vector mask control, it achieves element-by-element execution based on the mask, thereby reducing or replacing some control flow paths based on conditional branch instructions. Furthermore, by adaptively updating the vector mask when the vector length changes dynamically, the mask semantics can be kept consistent under different vector configurations, thereby improving the system's adaptability to dynamic vector length environments and its execution stability.

[0042] The solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0043] The solution provided in this application can be applied to Figure 1 An illustrated computing system. (e.g.) Figure 1 As shown, the computing system includes: processor 100.

[0044] In some embodiments, the processor 100 may be a RISC-V processor that supports vector extensions, or other processors that support vector mask execution mechanisms.

[0045] Specifically, the processor 100 acquires the executable program, obtains the bit-level conditional expression information in the executable program, parses the bit-level conditional expression information, and obtains the parsing result; based on the logical combination relationship, it performs data processing on the target bits to obtain a compact bit vector; based on the vector configuration parameters, it performs format conversion on the compact bit vector to obtain a vector mask adapted to the vector register; based on the vector mask, it controls the execution behavior of the data elements, and updates the vector mask when the vector length changes, to obtain the program execution result. The specific implementation method can be referred to the description in the following embodiments.

[0046] It should be noted that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0047] Figure 2 A flowchart illustrating a dynamic vector mask generation and control flow optimization method provided in an exemplary embodiment of this application is shown. This embodiment illustrates the method as being executed by a processor. The processor can be... Figure 1 The processor 100 is shown in the diagram.

[0048] like Figure 2 As shown, the dynamic vector mask generation and control flow optimization method includes the following steps.

[0049] Step 201: Obtain bit-level condition expression information in the executable program, parse the bit-level condition expression information, and obtain the parsing result.

[0050] Bit-level condition information describes the expressions used for conditional logic judgments in the executable program; that is, the conditional judgments in the executable program. For example, performing a logical AND operation on the target bit in the register forms the result of the conditional judgment.

[0051] The parsing results include the target bits involved in the conditional judgment and the logical combination relationships between the target bits.

[0052] Optionally, the logical combination relationship includes "logical AND", "logical OR", and "logical NOT", but is not limited thereto, and the embodiments of this application do not specifically limit it.

[0053] Optionally, the bit-level condition expression information includes one or more of the logical judgment expression, conditional branch instruction, or intermediate representation generated by the compiler in the executable program, but is not limited thereto, and the embodiments of this application do not specifically limit it.

[0054] Optionally, the data processing of the target bit is implemented through bit manipulation logic.

[0055] The intermediate representation generated by the compiler refers to an intermediate code format used by the compiler in the process of converting source code into machine code. It is independent of specific machine instructions, making it easier for the compiler to analyze and optimize.

[0056] Step 202: Based on the logical combination relationship, perform data processing on the target bit to obtain a compact bit vector.

[0057] The compact bit vector is a bit sequence formed by extracting, rearranging, and combining the target bits involved in the conditional judgment. Each bit has a definite element index mapping relationship with the target data element. The compact bit vector is used to represent the execution condition of each target data element. The element index mapping relationship means that each bit in the compact bit vector corresponds to one target data element, thereby establishing a correspondence between bit-level conditions and target data elements.

[0058] Specifically, since the target bits involved in the conditional judgment are distributed across different register locations, different fields, or different data structures, the processor can centrally process these scattered target bits to form a compact bit vector. This mechanism enables the conversion from discrete bit conditional representation to structured bit representation, providing a unified input for subsequent vector mask generation.

[0059] For example, target bits that were originally distributed in multiple registers can be extracted and reorganized according to the order of the target data elements to form a continuous bit sequence.

[0060] Optionally, the compact bit vector has one or more of the following characteristics: each bit is organized in the order of the target data element; there is a definite mapping relationship between the bit sequence and the data element index; and it supports a unified expression of non-contiguous bits and cross-field bits.

[0061] In some embodiments, based on logical combination relationships, one or more of the following processes are performed on the target bits: extraction, rearrangement, and combination, to obtain a compact bit vector.

[0062] Specifically, after obtaining the parsing results, based on the logical combination relationships in the parsing results, extraction, rearrangement and combination operations are performed on the target bits involved in the condition judgment to compress the original scattered bit-level conditions into a compact bit vector.

[0063] The dynamic vector mask generation and control flow optimization method provided in this application transforms the mask construction process, which originally required multiple scalar logic instructions, into a compact bit vector generation process by extracting, rearranging, and combining bit-level conditions, thereby reducing the number of instructions and lowering the mask generation overhead.

[0064] Step 203: Based on the vector configuration parameters, perform format conversion on the compact bit vector to obtain the vector mask for the adapted vector register.

[0065] The vector mask is used to represent the execution state of each target data element and to control the execution behavior of vector instructions on the corresponding data elements.

[0066] Vector configuration parameters include, but are not limited to, vector length (VL), element width (SEW), and grouping factor (LMUL), and this application embodiment does not specifically limit these parameters.

[0067] VL is used to indicate the number of data elements currently being processed.

[0068] SEW is used to indicate the width of a data element.

[0069] LMUL is used to indicate the vector register set multiplier.

[0070] In some embodiments, a vector mask for adapting a vector register is obtained by format conversion of a compact bit vector based on vector configuration parameters, including: determining the correspondence between the compact bit vector and the target data element according to SEW; determining the organization and distribution of the mask in the vector register according to LMUL; and determining the effective bit boundaries of the mask according to VL.

[0071] Specifically, the processor performs position mapping and format adaptation on the compact bit vector based on the VL, SEW, and LMUL parameters in the current vector execution environment, so that the generated vector mask matches the current vector register layout and vector execution environment. Through the above processing, a direct mapping from the compact bit vector to the vector mask can be achieved, reducing the overhead caused by intermediate data movement and multi-level data conversion processes, and improving the mask generation efficiency. The dynamic vector mask generation and control flow optimization method provided in this application establishes a mapping relationship between bit-level conditions and vector masks, enabling vector execution to be directly driven by bit operation results, thereby achieving element-wise execution based on the mask and reducing or replacing some control flow paths based on conditional branch instructions.

[0072] Step 204: Based on the vector mask, control the execution behavior of data elements to reduce or replace control flow jumps based on conditional branch instructions.

[0073] Specifically, based on the vector mask, if the mask in the vector mask is to be executed, then the data element corresponding to the mask will be processed; if the mask in the vector mask is to be not executed, then the data element corresponding to the mask will not be processed.

[0074] In some embodiments, the validity of vector instructions in the executor is determined based on the vector mask. If the vector mask corresponding to a vector instruction includes partially invalid masks, the computation of data elements corresponding to the partially invalid masks is suppressed. If the vector mask corresponding to a vector instruction is entirely invalid, the vector instruction is suppressed from entering the vector execution unit.

[0075] Specifically, after generating the vector mask, the execution process of data elements is controlled using the vector mask, thereby reducing reliance on traditional branch control flow. This is manifested as follows: the vector mask is used as a control input, directly acting on the vector execution unit in the processor; for data elements with invalid mask bits, the vector execution unit in the processor suppresses their participation in computation; when the entire vector mask is invalid, suppression can be performed during the issue phase, i.e., suppressing the corresponding vector instruction from entering the vector execution unit in the processor. Through this mechanism, the control flow path that originally relied on conditional branches is transformed into an element-wise execution path based on the vector mask, thereby reducing the performance loss caused by branch prediction failures and improving pipeline stability.

[0076] In other words, before the vector instruction that processes data elements is sent to the vector execution unit in the processor, a judgment is made based on the vector mask. If the vector mask indicates that a certain part of the data elements is invalid, the calculation of the corresponding data elements is suppressed to save power. If the entire mask is invalid (all 0s), the vector instruction is directly canceled and enters the vector execution unit without performing any calculation on the data elements.

[0077] The vector execution unit is a hardware circuit in the processor specifically responsible for performing vector operations (such as vector addition and multiplication).

[0078] The dynamic vector mask generation and control flow optimization method provided in this application can effectively reduce pipeline disturbances caused by branch prediction failures and improve the stability and throughput of processor execution by evaluating the effectiveness of the vector mask during the vector instruction dispatch stage and suppressing invalid element calculations or invalid instruction issuance.

[0079] Step 205: During the execution of the program, monitor the change in vector length; if the vector length changes, update the vector mask to ensure the consistency of mask semantics under different vector lengths.

[0080] Optionally, updating the vector mask includes: adjusting the effective bit boundaries of the vector mask; and / or updating the correspondence between the mask and data elements.

[0081] For example, a vector mask that originally controlled 64 data elements now only needs to control the first 10, so the extra mask bits can be turned off. Updating the correspondence between the mask and data elements means ensuring that the Nth mask bit still corresponds to the Nth data element, and that there is no misalignment due to changes in length.

[0082] Specifically, the vector length VL can change dynamically during program execution. By introducing a dynamic adaptation mechanism, when a change in vector length is detected, the vector mask is adaptively reconstructed. For example, the effective bit boundaries of the vector mask are adjusted, the mapping relationship between bit indices and data elements is updated, or unused bits are re-marked or cleared. Through the above processing, the mask semantics are kept consistent under different VL configurations, thereby supporting stable execution across stages and loops.

[0083] The dynamic vector mask generation and control flow optimization method provided in this application can dynamically adjust the effective bit boundaries and element mapping relationships of the vector mask when a change in vector length is detected, thereby ensuring the consistency of mask semantics under different vector configurations and improving the system's adaptability and operational stability in various execution environments.

[0084] In summary, the technical solution provided in this application transforms the mask construction process, which originally required multiple scalar logic instructions, into a compact bit vector generation process by processing bit-level conditions. Furthermore, format conversion enables direct conversion from compact bit vectors to vector masks, thereby reducing intermediate data movement and instruction sequence length, lowering mask generation latency, and improving mask generation efficiency. In addition, by converting conditional judgments into vector mask control, element-wise execution based on the mask is achieved, thus reducing or replacing some control flow paths based on conditional branch instructions.

[0085] The above embodiments provide a simple description of the generation and use of vector masks. Furthermore, during vectorized execution, the mask state of the vector mask can also have continuity between adjacent instructions or loop iterations.

[0086] like Figure 3 As shown, the dynamic vector mask generation and control flow optimization method may also include the following steps.

[0087] Step 206: During the cross-vector instruction execution process or cross-iteration execution process of the execution program, the remaining bit state or unaligned bit state in the vector mask is maintained, updated and reused to reduce the number of times the vector mask is repeatedly generated.

[0088] Reuse refers to the process of not discarding the vector mask after a computation task is completed, but rather retaining its state for continued use.

[0089] Cross-vector instructions refer to the use of the same vector mask in multiple different vector instructions that follow (e.g., performing addition first, then multiplication, with the same conditions).

[0090] Cross-iteration refers to the reuse of the vector mask generated in the previous iteration in the next iteration of a loop structure.

[0091] The remaining bit state refers to the mask bit state that is not involved in the current execution because the current effective vector length VL is less than the mask storage capacity; the unaligned bit state refers to the mask bit state that is not yet mapped to the current data element due to different vector length configurations, element width configurations, or grouping configurations.

[0092] Reusing remaining or unaligned bits means making good use of the remaining or unaligned bits.

[0093] Specifically, during vectorized execution, some mask states are continuous between adjacent instructions or loop iterations. By setting up a mask state buffer unit, the state of the vector mask or its corresponding bit representation is maintained and propagated, thereby updating and reusing the remaining bit states or unaligned bit states in the vector mask. For example, unused bits from the previous round can be shifted or rearranged, combined with the current bit conditions, or a new compact bit vector input can be generated, thereby reducing repeated mask generation operations and improving overall execution efficiency.

[0094] The dynamic vector mask generation and control flow optimization method provided in this application introduces a mask state buffering and propagation mechanism, enabling mask data to be reused across instructions or iterations. By combining bit operations to update remaining or unaligned bits, the mask generation operation can be avoided, thereby further reducing computational overhead and improving overall execution efficiency.

[0095] The above embodiments mainly describe the dynamic vector mask generation and control flow optimization method in detail. The following will describe in detail the system architecture of the processor that implements the dynamic vector mask generation and control flow optimization method.

[0096] like Figure 4 The diagram shown illustrates the system architecture for dynamic vector mask generation and control flow optimization provided in this embodiment. This system architecture includes: a condition parsing module, a bit manipulation processing module, a mask generation module, a mask control execution module, a dynamic adaptation module, a mask management and reuse module, a vector configuration unit, a mask register, and a vector execution unit. Wherein: The condition parsing module is used to obtain bit-level condition expression information in the executable program and parse the target bits involved in the condition judgment and their logical combination relationships.

[0097] The bit manipulation processing module is used to perform extraction, rearrangement, and combination processing on the target bits according to the logical combination relationship to generate a compact bit vector.

[0098] The mask generation module is used to convert the format of the compact bit vector according to the vector configuration parameters and generate a vector mask that adapts to the vector register organization method.

[0099] The vector configuration unit is used to provide configuration parameters for the current vector execution environment, including vector length VL, element width SEW, and grouping coefficient LMUL.

[0100] The mask register is used to store the generated vector mask and provide mask control information to the vector execution unit.

[0101] The vector execution unit is used to execute vector instructions under the control of a vector mask, enabling conditional execution on an element-by-element basis.

[0102] The mask control execution module is used to determine the validity of vector instructions based on vector masks, and control the execution behavior of data elements according to the determination results, so as to reduce or replace control flow jumps based on conditional branch instructions.

[0103] The dynamic adaptation module is used to update the vector mask when the vector length changes, so as to ensure the consistency of the mask semantics under different vector length configurations.

[0104] The mask management and reuse module is used to maintain, update, and reuse the remaining bit state or unaligned bit state in the vector mask during cross-vector instruction execution or cross-iteration execution, so as to reduce the number of times the vector mask is repeatedly generated.

[0105] In summary, through the above system architecture, this embodiment achieves efficient mapping of scalar bit operation results to vector masks, and realizes adaptive adjustment and reuse of vector masks in a dynamic vector length environment, thereby improving vectorized execution efficiency and reducing control flow overhead.

[0106] The above provides a brief description of the overall architecture of the dynamic vector mask generation and control flow optimization system. The following section will describe the vector mask generation and control flow optimization (processing data elements) in detail.

[0107] like Figure 5 The diagram shown illustrates vector mask generation and control flow optimization.

[0108] In traditional implementations, bit-level conditions are typically calculated incrementally using multiple scalar logic instructions and exist in discrete form in scalar registers or memory, making them difficult to directly use for vector mask generation. In this embodiment, the target bits involved in the condition judgment are first extracted, rearranged, and combined in parallel, compressing the original scattered bit-level conditions into a compact bit vector. That is, the operation processing module performs extraction, rearrangement, and combination processing on the target bits involved in the condition judgment to generate a compact bit vector. This mechanism achieves the transformation from "discrete bit conditions" to "structured bit representation," providing a unified input for subsequent mask generation.

[0109] Optionally, the compact bit vector has the following characteristics: each bit is organized in the order of the target vector elements, there is a definite mapping relationship between the bit sequence and the vector element index, and it supports the unified expression of non-contiguous bits and cross-field bits, but it is not limited thereto, and the embodiments of this application do not specifically limit it.

[0110] After obtaining the compact bit vector, the vector mask generation logic converts the compact bit vector into a vector mask according to the vector configuration parameters and stores it in the mask register. This embodiment uses the compact bit vector as a unified input source, and in conjunction with the vector configuration parameters (VL, SEW, LMUL), performs bit expansion, alignment, and format adaptation within the same processing path. Specifically, the effective bit range of the mask is determined according to VL, the bit spacing is adjusted according to SEW to ensure that the mask bits are consistent with the granularity of the data elements, and the distribution relationship of the mask in the vector register group is determined according to LMUL. This achieves a direct mapping from the compact bit vector to the vector mask, avoiding the overhead of multi-level data conversion paths.

[0111] After generating the vector mask, this embodiment of the application uses the vector mask to control the vector execution process, thereby reducing the dependence on traditional branch control flow.

[0112] Specifically, the vector mask is used as a control input, directly applied to the vector execution unit. Based on the vector mask, the validity of vector instructions in the execution program is determined. For data elements with invalid mask bits, their participation in computation is suppressed. When the vector mask corresponding to a vector instruction includes partially invalid masks, computation of data elements corresponding to those partially invalid masks is suppressed (i.e., vectors are executed element-wise). When the entire vector mask is invalid, the corresponding instruction can be suppressed from entering the execution unit during the issue phase (i.e., vector instructions are suppressed). Through this mechanism, the control flow path that originally relied on conditional branches is transformed into an element-wise execution path based on vector masks, thereby reducing the performance loss caused by branch prediction failures and improving pipeline stability.

[0113] In RISC-V vector extensions, the vector length (VL) can dynamically change during program execution, which places higher demands on the correctness of the vector mask. In this embodiment, a dynamic adaptation mechanism is introduced to reconstruct the vector mask when a change in vector length is detected. Mask reconstruction includes adjusting the boundaries of valid mask bits, updating the mapping between bit indices and data elements, and re-marking or clearing unused bits. Through these processes, the mask semantics remain consistent across different VL configurations, thereby supporting stable execution across stages and loops.

[0114] During vectorized execution, some vector mask states are continuous between adjacent instructions or loop iterations. In this embodiment, a mask state buffer unit is set up to maintain and propagate the state of the mask data or its corresponding bit representation.

[0115] In summary, through the above mechanism, the embodiments of this application achieve a direct and efficient mapping from scalar bit operation results to vector masks, and can also replace execution based on the control flow of vector masks. Adaptive mask adjustment is possible in the face of dynamic vector length changes, and the vector mask state can be reused and propagated across instructions, thereby significantly reducing instruction overhead, minimizing branch disturbances, and improving vectorized execution efficiency while ensuring execution correctness.

[0116] The foregoing mainly describes the method provided in this application. Accordingly, this application also provides a dynamic vector mask generation and control flow optimization apparatus, which is used to implement the above-described method embodiments.

[0117] In some embodiments, the dynamic vector mask generation and control flow optimization apparatus includes hardware structures and / or software modules corresponding to the execution of each function in order to achieve the above-described functions. Those skilled in the art will readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0118] This application embodiment can divide the dynamic vector mask generation and control flow optimization device into functional modules according to the above method embodiment. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0119] In some embodiments, this application provides a dynamic vector mask generation and control flow optimization apparatus. For example... Figure 6 The diagram shows the structure of the dynamic vector mask generation and control flow optimization device. The dynamic vector mask generation and control flow optimization device may include: a condition parsing module 601, a bit operation processing module 602, a mask generation module 603, a mask control execution module 604, and a dynamic adaptation module 605.

[0120] The condition parsing module 601 is used to obtain bit-level condition expression information in the executable program, and parse the bit-level condition expression information to obtain a parsing result. The parsing result includes the target bits involved in the condition judgment and the logical combination relationship between the target bits.

[0121] Bit operation processing module 602 is used to perform combination processing on the target bits based on the logical combination relationship to obtain a compact bit vector. The compact bit vector is used to characterize the execution conditions of each target data element, and each bit in the compact bit vector has an element index mapping relationship with the target data element.

[0122] The mask generation module 603 is used to perform format conversion on the compact bit vector based on the vector configuration parameters to obtain a vector mask that adapts to the vector register.

[0123] The mask control execution module 604 is used to control the execution behavior of data elements based on the vector mask, so as to reduce or replace control flow jumps based on conditional branch instructions.

[0124] The dynamic adaptation module 605 is used to update the vector mask when the vector length changes, so as to ensure the consistency of the mask semantics under different vector lengths.

[0125] One possible implementation is that the vector configuration parameters include: VL, SEW, and LMUL; wherein VL is used to indicate the number of data elements currently being processed, SEW is used to indicate the bit width of the data elements, and LMUL is used to indicate the vector register group multiplier.

[0126] Another possible implementation is a mask generation module 603, which is specifically used to: fill the bit spacing of the compact bit vector according to the SEW; determine the distribution relationship of the mask in the vector register according to the LMUL; determine the effective bit boundary of the mask according to the VL, and generate a vector mask adapted to the vector register.

[0127] Another possible implementation is the bit manipulation processing module 602, which is specifically used to: extract, rearrange, or combine the target bits to obtain the compact bit vector.

[0128] Another possible implementation is a mask control execution module 604, which is specifically used to: determine the mask validity of vector instructions in the execution program based on the vector mask; if the vector mask corresponding to the vector instruction includes a partially invalid mask, suppress the data elements corresponding to the partially invalid mask from participating in the calculation; and if the vector mask corresponding to the vector instruction is a completely invalid mask, suppress the vector instruction from entering the vector execution unit.

[0129] Another possible implementation is the dynamic adaptation module 605, which is specifically used to: adjust the effective bit boundaries of the vector mask; and / or update the correspondence between the mask and the data elements.

[0130] Another possible implementation, the dynamic vector mask generation and control flow optimization apparatus provided in this application, further includes a mask management and reuse module 606. The mask management and reuse module 606 is specifically used to maintain, update, and reuse the remaining bit states or unaligned bit states in the vector mask during the cross-vector instruction execution process or cross-iteration execution process of the executable program, thereby reducing the number of times the vector mask is repeatedly generated.

[0131] Another possible implementation is that the bit-level conditional expression information includes one or more of the following: logical judgment expressions in the executor, conditional branch instructions, or intermediate representations generated by the compiler.

[0132] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7 As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740. The processor 710, communications interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can call logic instructions from the memory 730 to execute dynamic vector mask generation and control flow optimization methods.

[0133] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer is able to execute the dynamic vector mask generation and control flow optimization methods provided by the above methods.

[0135] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the dynamic vector mask generation and control flow optimization methods provided by the above methods.

[0136] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for dynamic vector mask generation and control flow optimization, characterized in that, The method includes: Obtain bit-level condition expression information from the executable program, and parse the bit-level condition expression information to obtain a parsing result. The parsing result includes the target bits involved in the condition judgment and the logical combination relationship between the target bits. Based on the logical combination relationship, the target bit is processed to obtain a compact bit vector. The compact bit vector is used to characterize the execution conditions of each target data element. Each bit in the compact bit vector has an element index mapping relationship with the target data element. Based on the vector configuration parameters, the compact bit vector is format-converted to obtain a vector mask that adapts to the vector register; Based on the vector mask, the execution behavior of data elements is controlled to reduce or replace control flow jumps based on conditional branch instructions; During the execution of the program, monitor changes in the vector length; When the vector length changes, the vector mask is updated to ensure the consistency of the mask semantics under different vector lengths.

2. The method according to claim 1, characterized in that, The vector configuration parameters include: vector length VL, element width SEW, and grouping coefficient LMUL; Wherein, VL is used to indicate the number of data elements currently being processed, SEW is used to indicate the bit width of the data element, and LMUL is used to indicate the vector register group multiplier.

3. The method according to claim 2, characterized in that, The step of performing format conversion on the compact bit vector based on vector configuration parameters to obtain a vector mask adapted to the vector register includes: The compact bit vector is padded with bit spacing according to the SEW; the distribution relationship of the mask in the vector register is determined according to the LMUL; the effective bit boundaries of the mask are determined according to the VL, and the vector mask adapted to the vector register is generated.

4. The method according to claim 1, characterized in that, The step of processing the target bit based on the logical combination relationship to obtain a compact bit vector includes: The target bits are subjected to one or more of the following processes: extraction, rearrangement, and combination, to obtain the compact bit vector.

5. The method according to claim 1, characterized in that, The control of execution behavior on data elements based on the vector mask includes: Based on the vector mask, the validity of the vector instructions in the executing program is determined. If the vector mask corresponding to the vector instruction includes a partially invalid mask, the data elements corresponding to the partially invalid mask shall be prevented from participating in the calculation. If the vector mask corresponding to the vector instruction is a completely invalid mask, the vector instruction is prevented from entering the vector execution unit.

6. The method according to claim 1, characterized in that, The update of the vector mask includes: Adjust the effective bit boundaries of the vector mask; And / or, Update the correspondence between the mask and the data elements.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: During the cross-vector instruction execution process or cross-iteration execution process of the execution program, the remaining bit state or unaligned bit state in the vector mask is maintained, updated and reused to reduce the number of times the vector mask is repeatedly generated.

8. The method according to any one of claims 1 to 6, characterized in that, The bit-level conditional representation information includes one or more of the following: logical judgment expressions in the executable program, conditional branch instructions, or intermediate representations generated by the compiler.

9. The method according to any one of claims 1 to 6, characterized in that, The data processing of the target bit is implemented through bit manipulation logic.

10. A dynamic vector mask generation and control flow optimization device, characterized in that, The device includes: The condition parsing module is used to obtain bit-level condition expression information in the executable program, and parse the bit-level condition expression information to obtain the parsing result; The bit manipulation processing module is used to perform one or more of the following processes on the target bits based on the parsing result: extraction, rearrangement, and combination, to obtain a compact bit vector. The mask generation module is used to perform format conversion on the compact bit vector based on the vector configuration parameters to obtain a vector mask. A mask control execution module is used to control the execution behavior of data elements based on the vector mask. The dynamic adaptation module is used to update the vector mask when the vector length changes, so as to ensure the consistency of the mask semantics under different vector lengths.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the dynamic vector mask generation and control flow optimization method as described in any one of claims 1 to 9.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the dynamic vector mask generation and control flow optimization method as described in any one of claims 1 to 9.

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