Display device and electronic device

Abstract

Disclosed are a display device and an electronic device. The display device includes a display panel including a plurality of pixels in a display area and a feedback line connected to a point within the display area, and a panel driver configured to drive the display panel. Each of the plurality of pixels generates an emission current based on a voltage difference between a data voltage and a reference voltage, and emits light having a luminance corresponding to the emission current. The panel driver receives the reference voltage at the point within the display area as a feedback reference voltage through the feedback line, and adjusts the data voltage according to the feedback reference voltage.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices and electronic devices, and more specifically, to display devices including feedback lines and electronic devices including the display devices. Background Technology

[0002] The display device may include a display panel containing multiple pixels, a data driver that provides data voltage to the multiple pixels, a scan driver that provides scan signals to the multiple pixels, a transmit driver that provides transmit signals to the multiple pixels, and a controller that controls the data driver, the scan driver, and the transmit driver.

[0003] Recently, a pixel has been developed in which the driving transistor generates an emission current based on the voltage difference between the data voltage and the reference voltage, and the light-emitting element emits light based on the emission current corresponding to the voltage difference. In the pixel, when the reference voltage has a constant voltage level, the current level of the emission current can be determined according to the voltage level of the data voltage, and the brightness of the pixel can be determined according to either the current level of the emission current or the voltage level of the data voltage. Summary of the Invention

[0004] Some embodiments provide a display device capable of preventing or reducing crosstalk defects caused by variations in reference voltage or ripple.

[0005] Some embodiments provide electronic devices that include a display device.

[0006] According to an embodiment, a display device is provided, comprising: a display panel including a plurality of pixels in a display area and feedback lines connected to the pixels in the display area; and a panel driver configured to drive the display panel. Each of the plurality of pixels generates an emission current based on a voltage difference between a data voltage and a reference voltage, and emits light having a brightness corresponding to the emission current. The panel driver receives a reference voltage at a pixel in the display area as a feedback reference voltage via the feedback lines, and adjusts the data voltage according to the feedback reference voltage.

[0007] In one embodiment, the panel driver can increase the data voltage as the feedback reference voltage increases, and decrease the data voltage as the feedback reference voltage decreases.

[0008] In an embodiment, the panel driver may include: a power management circuit configured to generate a reference voltage, a gamma top voltage, and a gamma bottom voltage; a data driver configured to generate a data voltage based on the gamma top voltage and the gamma bottom voltage, and to provide the data voltage to each of a plurality of pixels; and a controller configured to control the power management circuit and the data driver.

[0009] In this embodiment, the controller can receive a feedback reference voltage via a feedback line and generate a gamma control signal based on the feedback reference voltage. The power management circuitry can adjust the gamma top voltage and gamma bottom voltage in response to the gamma control signal. The data driver can adjust the data voltage based on the adjusted gamma top voltage and adjusted gamma bottom voltage.

[0010] In one embodiment, as the feedback reference voltage increases, the controller can generate a gamma control signal indicating that the gamma top voltage and gamma bottom voltage should be increased. The power management circuit can increase the gamma top voltage and gamma bottom voltage in response to the gamma control signal, and the data driver can increase the data voltage based on the increased gamma top voltage and increased gamma bottom voltage.

[0011] In an embodiment, when the feedback reference voltage increases by a certain amount, the power management circuit can increase the voltage by each of the gamma top voltage and the gamma bottom voltage, and the data driver can increase the data voltage by a certain amount based on the increased gamma top voltage and the increased gamma bottom voltage.

[0012] In an embodiment, the panel driver may further include: a scan driver configured to provide a write signal, a compensation signal, an initialization signal, and a bypass signal to each of the plurality of pixels; and an emit driver configured to provide an emit signal to each of the plurality of pixels.

[0013] In an embodiment, each of the plurality of pixels may include: a first capacitor including a first electrode receiving a first power supply voltage and a second electrode connected to a first node; a second capacitor including a first electrode connected to the first node and a second electrode connected to a second node; a first transistor configured to generate an emission current based on the voltage of the second node; a second transistor configured to transmit a data voltage to the first node in response to a write signal; a third transistor configured to connect the first transistor diode in response to a compensation signal; a fourth transistor configured to apply an initialization voltage to the second node in response to an initialization signal; a fifth transistor configured to apply a reference voltage to the first node in response to a compensation signal; and a light-emitting element configured to emit light based on the emission current.

[0014] In one embodiment, the first transistor may include a gate connected to the second node, a second terminal, and a first terminal receiving a first power supply voltage. The second transistor may include a gate receiving a write signal, a first terminal connected to a data line, and a second terminal connected to the first node. The third transistor may include a gate receiving a compensation signal, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the second node. The fourth transistor may include a gate receiving an initialization signal, a first terminal connected to the second node, and a second terminal receiving an initialization voltage. The fifth transistor may include a gate receiving a compensation signal, a first terminal connected to the first node, and a second terminal receiving a reference voltage. The light-emitting element may include an anode connected to the second terminal of the first transistor and a cathode receiving a second power supply voltage.

[0015] In an embodiment, each of the plurality of pixels may further include: a sixth transistor located between the first transistor and the light-emitting element and configured to connect the first transistor and the light-emitting element in response to an emission signal; and a seventh transistor configured to apply an initialization voltage to the light-emitting element in response to a bypass signal.

[0016] In one embodiment, the sixth transistor may include a gate for receiving a transmitted signal, a first terminal connected to the first transistor, and a second terminal connected to the light-emitting element. The seventh transistor may include a gate for receiving a bypass signal, a first terminal connected to the light-emitting element, and a second terminal for receiving an initialization voltage.

[0017] In an embodiment, the frame time period of the display device may include: a gate initialization time period in which a second node is initialized; a compensation time period in which a threshold voltage compensation operation of a first transistor is performed; a write time period in which a data voltage is provided to each of a plurality of pixels; an anode initialization time period in which a light-emitting element is initialized; and an emission time period in which the light-emitting element emits light based on an emission current.

[0018] According to an embodiment, a display device is provided, comprising: a display panel including a plurality of pixels in a display area and a plurality of feedback lines respectively connected to the plurality of pixels in the display area; and a panel driver configured to drive the display panel. Each of the plurality of pixels generates an emission current based on a voltage difference between a data voltage and a reference voltage, and emits light having a brightness corresponding to the emission current. The panel driver receives a reference voltage in the display area as a feedback reference voltage through one of the plurality of feedback lines, and adjusts the data voltage according to the feedback reference voltage.

[0019] In one embodiment, the panel driver can increase the data voltage as the feedback reference voltage increases, and decrease the data voltage as the feedback reference voltage decreases.

[0020] In one embodiment, the panel driver may include: a power management circuit configured to generate a reference voltage, a gamma top voltage, and a gamma bottom voltage; a data driver configured to generate a data voltage based on the gamma top voltage and the gamma bottom voltage, and to provide the data voltage to each of a plurality of pixels; and a controller configured to control the power management circuit and the data driver. The controller may be connected to one of the plurality of feedback lines, and may not be connected to the remaining feedback lines.

[0021] In this embodiment, based on the crosstalk characteristics of the display panel, one feedback line is selected from multiple feedback lines to be connected to the controller.

[0022] According to an embodiment, an electronic device is provided, comprising: a processor; a memory connected to the processor; a power module connected to the processor; and a display device as described above, configured to receive input image data from the processor and display an image based on the input image data.

[0023] As described above, in the display device and electronic device according to the embodiments, the panel driver can receive a reference voltage at a point in the display area as a feedback reference voltage via a feedback line, and can adjust the data voltage according to the feedback reference voltage. Accordingly, crosstalk defects caused by changes in the reference voltage or ripple can be effectively prevented or reduced. Attached Figure Description

[0024] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0025] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0026] Figure 2 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment.

[0027] Figure 3 It is used to describe Figure 2 A timing diagram showing examples of pixel operations.

[0028] Figure 4 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the gate initialization period.

[0029] Figure 5 It is used to describe Figure 2A circuit diagram illustrating an example of pixel operation during the compensation period.

[0030] Figure 6 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the write period.

[0031] Figure 7 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the anode initialization period.

[0032] Figure 8 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the emission period.

[0033] Figure 9 It is a timing diagram used to describe an example of a change or ripple in a reference voltage based on a change or transition in the data voltage.

[0034] Figure 10 This is a block diagram illustrating an example of a display device according to an embodiment.

[0035] Figure 11 This is a timing diagram illustrating examples of gamma top voltage, gamma bottom voltage, and reference voltage in a conventional display device, and examples of gamma top voltage, gamma bottom voltage, and feedback reference voltage in a display device according to an embodiment.

[0036] Figure 12 This is a block diagram illustrating a display device according to an embodiment.

[0037] Figure 13 This is a block diagram illustrating an example of a display device according to an embodiment.

[0038] Figure 14 This is a block diagram illustrating an electronic device according to an embodiment.

[0039] Figure 15 These are schematic diagrams illustrating electronic devices according to various embodiments. Detailed Implementation

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or variations thereof. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or variations thereof or “including” and / or variations thereof specify the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or combinations thereof.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., used herein may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings herein.

[0042] It will be understood that when an element is referred to as "connected to" another element, it can be directly connected to that other element, or an intermediary element may exist therein. Conversely, when an element is referred to as "directly connected to" another element, there is no intermediary element. Embodiments of the invention will be explained in detail below with reference to the accompanying drawings.

[0043] Figure 1 This is a block diagram illustrating a display device according to an embodiment. Figure 2 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment. Figure 3 It is used to describe Figure 2 A timing diagram illustrating examples of pixel operations. Figure 4 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the gate initialization period. Figure 5 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the compensation period. Figure 6 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the write period. Figure 7 It is used to describe Figure 2A circuit diagram illustrating an example of pixel operation during the anode initialization period. Figure 8 It is used to describe Figure 2 A circuit diagram illustrating an example of pixel operation during the emission period. Figure 9 It is a timing diagram used to describe an example of a change or ripple in a reference voltage based on a change or transition in the data voltage. Figure 10 This is a block diagram illustrating an example of a display device according to an embodiment, and Figure 11 This is a timing diagram illustrating examples of gamma top voltage, gamma bottom voltage, and reference voltage in a conventional display device, and examples of gamma top voltage, gamma bottom voltage, and feedback reference voltage in a display device according to an embodiment.

[0044] refer to Figure 1 The display device 100 may include a display panel 110 comprising a plurality of pixels PX and a panel driver 120 for driving the display panel 110. In some embodiments, the panel driver 120 may include a data driver 130 that provides a data voltage VDAT to the plurality of pixels PX, a scan driver 140 that provides a scan signal SS to the plurality of pixels PX, a transmit driver 150 that provides a transmit signal EM to the plurality of pixels PX, a power management circuit 160 that generates voltages VGT, VGB, ELVDD, ELVSS, VINT, and VREF for driving the display panel 110, and a controller 170 that controls the data driver 130, the scan driver 140, the transmit driver 150, and the power management circuit 160.

[0045] The display panel 110 may include a plurality of pixels PX in a display area DR. Each pixel PX may generate an emission current based on the voltage difference between a data voltage VDAT and a reference voltage VREF, and may emit light with a brightness corresponding to the current level of the emission current. In some embodiments, such as Figure 2 As illustrated, each pixel PX may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a light-emitting element EL. In some embodiments, each pixel PX may further include a sixth transistor T6 and a seventh transistor T7.

[0046] A first capacitor C1 may be connected between the line transmitting the first power supply voltage ELVDD (e.g., a high power supply voltage) and the first node N1, and a second capacitor C2 may be connected between the first node N1 and the second node N2. In some embodiments, the first capacitor C1 may be referred to as a storage capacitor, and the second capacitor C2 may be referred to as a holding capacitor. Furthermore, in some embodiments, the first capacitor C1 may include a first electrode receiving the first power supply voltage ELVDD and a second electrode connected to the first node N1, and the second capacitor C2 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0047] The first transistor T1 can generate an emitter current based on the voltage of the second node N2. In some embodiments, as shown below... Figure 8 As described, the first transistor T1 can generate a emitter current IEL having a current level corresponding to the voltage difference VREF-VDAT between the data voltage VDAT and the reference voltage VREF. Furthermore, in some embodiments, the first transistor T1 may be referred to as a driver transistor. In some embodiments, the first transistor T1 may include a gate connected to the second node N2, a first terminal receiving a first power supply voltage ELVDD, and a second terminal connected to the third transistor T3 and the sixth transistor T6.

[0048] The second transistor T2 can transmit the data voltage VDAT to the first node N1 in response to the write signal GW. In some embodiments, the second transistor T2 may be referred to as a scan transistor or a write transistor. Furthermore, in some embodiments, the second transistor T2 may include a gate for receiving the write signal GW, a first terminal connected to the data line DL, and a second terminal connected to the first node N1.

[0049] The third transistor T3 can connect the diode of the first transistor T1 in response to the compensation signal GC. In some embodiments, the third transistor T3 may be referred to as the compensation transistor. Furthermore, in some embodiments, the third transistor T3 may include a gate for receiving the compensation signal GC, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the second node N2.

[0050] The fourth transistor T4 can apply an initialization voltage VINT to the second node N2 in response to an initialization signal GI. In some embodiments, the fourth transistor T4 may be referred to as a gate initialization transistor. Furthermore, in some embodiments, the fourth transistor T4 may include a gate for receiving the initialization signal GI, a first terminal connected to the second node N2, and a second terminal for receiving the initialization voltage VINT.

[0051] The fifth transistor T5 can apply a reference voltage VREF to the first node N1 in response to a compensation signal GC. In some embodiments, the fifth transistor T5 may be referred to as a reference transistor. Furthermore, in some embodiments, the fifth transistor T5 may include a gate for receiving the compensation signal GC, a first terminal connected to the first node N1, and a second terminal for receiving the reference voltage VREF.

[0052] The sixth transistor T6 may be located between the first transistor T1 and the light-emitting element EL, and may connect the first transistor T1 and the light-emitting element EL to each other in response to the emission signal EM. In some embodiments, the sixth transistor T6 may be referred to as the emitting transistor. Furthermore, in some embodiments, the sixth transistor T6 may include a gate for receiving the emission signal EM, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the anode of the light-emitting element EL.

[0053] The seventh transistor T7 can apply an initialization voltage VINT to the anode of the light-emitting element EL in response to a bypass signal GB. In some embodiments, the seventh transistor T7 may be referred to as an anode initialization transistor. Furthermore, in some embodiments, the seventh transistor T7 may include a gate receiving the bypass signal GB, a first terminal connected to the anode of the light-emitting element EL, and a second terminal receiving the initialization voltage VINT. Although Figure 2 The illustration shows an example in which the fourth transistor T4 and the seventh transistor T7 receive the same initialization voltage VINT. However, in other embodiments, the fourth transistor T4 may receive the initialization voltage VINT and the seventh transistor T7 may receive an anode initialization voltage different from the initialization voltage VINT.

[0054] The light-emitting element EL can emit light based on the emission current generated by the first transistor T1. In some embodiments, the light-emitting element EL can be, but is not limited to, an organic light-emitting diode (“OLED”). In other embodiments, the light-emitting element EL can be any suitable light-emitting element. For example, the light-emitting element EL can be a micron-sized light-emitting diode, a nano-sized light-emitting diode (“nanoLED”), a quantum dot (“QD”) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In some embodiments, the light-emitting element EL can include an anode connected to a second terminal of the first transistor T1 via a sixth transistor T6 and a cathode receiving a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0055] In some embodiments, such as Figure 2As illustrated, the first transistor T1 through the seventh transistor T7 can be implemented as a P-type metal-oxide-semiconductor (“PMOS”) transistor, but is not limited thereto. In other embodiments, at least one of the first transistor T1 through the seventh transistor T7 can be implemented as an N-type metal-oxide-semiconductor (“NMOS”) transistor.

[0056] In some embodiments, such as Figure 3 As illustrated, the frame period FRP of the display device 100 may include a gate initialization period GIP in which the second node N2 is initialized, a compensation period CP in which the threshold voltage compensation operation of the first transistor T1 is performed, a write period WP in which the data voltage VDAT is provided to the pixel PX, an anode initialization period AIP in which the light-emitting element EL is initialized, and an emission period EP in which the light-emitting element EL emits light based on the emission current.

[0057] During the gate initialization phase (GIP), the transmit signal EM, compensation signal GC, write signal GW, and bypass signal GB can have cutoff levels (e.g., high levels), and the initialization signal GI can have on levels (e.g., low levels). For example, as Figure 4 As illustrated, the fourth transistor T4 can be turned on in response to the initialization signal GI and can transmit the initialization voltage VINT to the second node N2. Therefore, the second node N2 (or the gate node of the first transistor T1) can be initialized based on the initialization voltage VINT. Furthermore, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be turned off.

[0058] During the compensation period CP, the transmit signal EM, the initialization signal GI, the write signal GW, and the bypass signal GB can be at a cutoff level, while the compensation signal GC can be at a conduction level. For example, as Figure 5As illustrated, the third transistor T3 and the fifth transistor T5 can be turned on in response to the compensation signal GC. The third transistor T3 can diode-connect the first transistor T1, and the fifth transistor T5 can transmit the reference voltage VREF to the first node N1. When the first transistor T1 is diode-connected, it can be turned on until the voltage of the second node N2 becomes ELVDD-VTH, which is obtained by subtracting the threshold voltage VTH of the first transistor T1 from the first supply voltage ELVDD. Therefore, the voltage of the first node N1 can become the reference voltage VREF, and the voltage of the second node N2 can become ELVDD-VTH, which is obtained by subtracting the threshold voltage VTH of the first transistor T1 from the first supply voltage ELVDD. Accordingly, the second capacitor C2 can store the voltage ELVDD-VTH reflecting the threshold voltage VTH of the first transistor T1, and this operation can be referred to as the source follower type "threshold voltage compensation operation" of the first transistor T1. In addition, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 can be turned off.

[0059] During the write phase WP, the transmit signal EM, initialization signal GI, compensation signal GC, and bypass signal GB can be at cutoff levels, while the write signal GW can be at on levels. For example, as Figure 6 As shown, the second transistor T2 can be turned on in response to the write signal GW, and can transmit the data voltage VDAT from the data line DL to the first node N1. Therefore, the voltage of the first node N1 can be changed from the reference voltage VREF to the data voltage VDAT, thus changing the voltage difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF. Furthermore, when the voltage of the first node N1 connected to the first electrode of the second capacitor C2 is changed to the voltage difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF, the voltage of the second node N2 connected to the second electrode of the second capacitor C2 can also be changed to the voltage difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF through the coupling of the second capacitor C2. Accordingly, the voltage of the second node N2 can become “ELVDD-VTH+VDAT-VREF”. In addition, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be turned off.

[0060] During the anode initialization phase (AIP), the transmit signal EM, initialization signal GI, compensation signal GC, and write signal GW can have cutoff levels, while the bypass signal GB can have on levels. For example, as... Figure 7As illustrated, the seventh transistor T7 can be turned on in response to the bypass signal GB and can transfer the initialization voltage VINT to the anode of the light-emitting element EL. Therefore, the anode of the light-emitting element EL can be initialized based on the initialization voltage VINT. Furthermore, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off.

[0061] During the transmit phase (EP), the initialization signal GI, compensation signal GC, write signal GW, and bypass signal GB can be at cutoff levels, while the transmit signal EM can be at on levels. For example, as... Figure 8 As illustrated, the first transistor T1 can be turned on based on the voltage of the second node N2, and the sixth transistor T6 can be turned on in response to the emission signal EM. Furthermore, the source-gate voltage of the first transistor T1 can be obtained by subtracting the voltage of the second node N2 from the first supply voltage ELVDD (i.e., "ELVDD - VTH + VDAT - VREF") (i.e., "VTH + VREF - VDAT"), and the first transistor T1 can generate an emission current IEL corresponding to the voltage obtained by subtracting the threshold voltage VTH of the first transistor T1 from the source-gate voltage (i.e., "VTH + VREF - VDAT") (i.e., "VREF - VDAT"). That is, the emission current IEL generated by the first transistor T1 can be expressed by the equation "IEL = k·(VREF - VDAT"). 2 "In this configuration, IEL represents the emission current, VREF represents the reference voltage, VDAT represents the data voltage, and k is a coefficient determined based on the mobility, oxide capacitance, channel width, and channel length of the first transistor T1. Accordingly, the emission current IEL generated by the first transistor T1 can be determined based on the voltage difference VREF-VDAT between the data voltage VDAT and the reference voltage VREF. The sixth transistor T6 can transfer the emission current IEL generated by the first transistor T1 to the light-emitting element EL, and the light-emitting element EL can emit light based on the emission current IEL generated by the first transistor T1. Furthermore, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned off."

[0062] although Figure 2 An example of a pixel PX included in a display device 100 according to an embodiment is illustrated, but the pixel PX included in a display device 100 according to an embodiment is not limited to... Figure 2 Examples. Furthermore, although Figure 3Examples of signals EM, GI, GC, GW, and GB applied to pixels PX included in the display device 100 according to an embodiment are illustrated, but the signals EM, GI, GC, GW, and GB applied to pixels PX included in the display device 100 according to an embodiment are not limited to... Figure 3 Examples.

[0063] Refer again Figure 1 The display panel 110 may further include a feedback line FBL connected to a point FP (e.g., a feedback point) within the display area DR. For example, the feedback line FBL may be connected to a line transmitting a reference voltage VREF at point FP within the display area DR, and thus, the reference voltage VREF at point FP within the display area DR may be transmitted via the feedback line FBL as a feedback reference voltage VREF_FB.

[0064] The data driver 130 can receive a gamma top voltage VGT and a gamma bottom voltage VGB from the power management circuit 160, receive output image data ODAT and a data control signal DCTRL from the controller 170, and can provide a data voltage VDAT to multiple pixels PX based on the gamma top voltage VGT, the gamma bottom voltage VGB, the output image data ODAT, and the data control signal DCTRL. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. Furthermore, in some embodiments, the data driver 130 can generate multiple grayscale voltages corresponding to multiple grayscale levels (e.g., 256 grayscale levels from grayscale level 0 to grayscale level 255) by dividing the voltage between the gamma top voltage VGT and the gamma bottom voltage VGB, and can provide the grayscale voltage corresponding to the grayscale level indicated by the output image data ODAT as the data voltage VDAT to the multiple pixels PX. Here, the gamma top voltage VGT may refer to the gamma voltage with its maximum value, and the gamma bottom voltage VGB may refer to the gamma voltage with its minimum value. In some embodiments, the data driver 130 and the controller 170 may be implemented as a single integrated circuit, and this single integrated circuit may be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In other embodiments, the data driver 130 and the controller 170 may be implemented as separate integrated circuits.

[0065] The scan driver 140 can generate a scan signal SS based on a scan control signal SCTRL received from the controller 170, and can sequentially provide the scan signal SS to multiple pixels PX line by line. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal, a scan clock signal, etc. Furthermore, in some embodiments, the scan signal SS provided to each pixel PX may include, but is not limited to, [other parameters not specified in the original text]. Figures 1 to 3 The diagram illustrates the initialization signal GI, compensation signal GC, write signal GW, and bypass signal GB. In some embodiments, the scan driver 140 may be integrated or formed in the display panel 110 (e.g., in a peripheral region of the display panel 110 adjacent to the display area DR). In other embodiments, the scan driver 140 may be implemented using one or more integrated circuits.

[0066] The transmit driver 150 can generate a transmit signal EM based on a transmit control signal EMCTRL received from the controller 170, and can sequentially provide the transmit signal EM to multiple pixels PX row by row. In some embodiments, the transmit control signal EMCTRL may include, but is not limited to, a transmit start signal, a transmit clock signal, etc. Furthermore, in some embodiments, the transmit driver 150 may be integrated or formed in the display panel 110 (e.g., in the peripheral region of the display panel 110 adjacent to the display area DR). In other embodiments, the transmit driver 150 may be implemented using one or more integrated circuits.

[0067] Power management circuitry 160 can generate voltages VGT, VGB, ELVDD, ELVSS, VINT, and VREF for driving display panel 110. For example, power management circuitry 160 can generate a gamma top voltage VGT and a gamma bottom voltage VGB supplied to data driver 130, and can generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, an initialization voltage VINT, and a reference voltage VREF supplied to display panel 110. In some embodiments, reference is made as follows. Figure 10 and Figure 11 As described, the power management circuit 160 can receive a gamma control signal GCTRL from the controller 170 and can adjust the gamma top voltage VGT and gamma bottom voltage VGB supplied to the data driver 130 in response to the gamma control signal GCTRL. Furthermore, in some embodiments, the power management circuit 160 can be implemented as a power management integrated circuit (“PMIC”), but is not limited thereto. In other embodiments, the power management circuit 160 can be included in the controller 170 and / or the data driver 130.

[0068] Controller 170 (e.g., a timing controller) can receive input image data IDAT and control signals CTRL from an external processor (e.g., a graphics processing unit (“GPU”), application processor (“AP”), or graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 170 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. Controller 170 can control data driver 130 by providing the output image data ODAT and the data control signal DCTRL to data driver 130, control scan driver 140 by providing the scan control signal SCTRL to scan driver 140, and control transmit driver 150 by providing the transmit control signal EMCTRL to transmit driver 150.

[0069] like Figure 9 As illustrated, when the data voltage VDAT provided via the data line DL is changed or transitioned, the reference voltage VREF can be altered or exhibit ripple due to the coupling between the data line DL and the line transmitting the reference voltage VREF. For example, when the data voltage VDAT has a falling edge 210 from a high voltage level (e.g., corresponding to a relatively low gray level) to a low voltage level (e.g., corresponding to a relatively high gray level), the reference voltage VREF can also have a falling edge 230 or ripple due to coupling. A pixel PX receiving a compensation signal GC that changes from an on-level (e.g., low level) to an off-level (e.g., high level) when the reference voltage VREF has a falling edge 230 can store a reference voltage VREF with a voltage level lower than desired. A pixel PX storing a reference voltage VREF with a voltage level lower than desired can emit light with a brightness lower than desired. Furthermore, a pixel PX storing a reference voltage VREF with a voltage level higher than desired can emit light with a brightness higher than desired. Accordingly, the reference voltage VREF may change or ripple due to the change or transition of the data voltage VDAT, and crosstalk defects may occur due to the change or ripple of the reference voltage VREF.

[0070] However, in the display device 100 according to the embodiment, the panel driver 120 (or controller 170) can receive a reference voltage VREF at point FP in the display area DR as a feedback reference voltage VREF_FB via the feedback line FBL, and can adjust the data voltage VDAT according to the feedback reference voltage VREF_FB. For example, as Figure 10As illustrated, the feedback line FBL of the display panel 110 can be connected to a point FP in the display area DR where multiple pixels PX are formed, can pass through a flexible film FF on which the data driver 130 is mounted, and can be connected to a controller 170 mounted on a control board CBD. The controller 170 can receive a feedback reference voltage VREF_FB via the feedback line FBL and can generate a gamma control signal GCTRL based on the feedback reference voltage VREF_FB. The power management circuit 160 can adjust the gamma top voltage VGT and the gamma bottom voltage VGB in response to the gamma control signal GCTRL. The data driver 130 can adjust the data voltage VDAT based on the adjusted gamma top voltage VGT and the adjusted gamma bottom voltage VGB. In some embodiments, the panel driver 120 can increase the data voltage VDAT as the feedback reference voltage VREF_FB increases and decrease the data voltage VDAT as the feedback reference voltage VREF_FB decreases. For example, as the feedback reference voltage VREF_FB increases, the controller 170 can generate a gamma control signal GCTRL indicating that the gamma top voltage VGT and the gamma bottom voltage VGB should be increased. The power management circuit 160 can increase the gamma top voltage VGT and the gamma bottom voltage VGB in response to the gamma control signal GCTRL, and the data driver 130 can increase the data voltage VDAT based on the increased gamma top voltage VGT and the increased gamma bottom voltage VGB.

[0071] Figure 11 The first timing diagram 310 illustrates an example of the gamma top voltage VGT, gamma bottom voltage VGB, and reference voltage VREF in a conventional display device, and Figure 11 The second timing diagram 330 illustrates an example of the gamma top voltage VGT, gamma bottom voltage VGB, and feedback reference voltage VREF_FB in the display device 100 according to an embodiment. In conventional display devices, such as Figure 11 As illustrated in the first timing diagram 310, even if the reference voltage VREF is changed, the gamma top voltage VGT and the gamma bottom voltage VGB will not be adjusted. Therefore, when the reference voltage VREF is increased, the gamma top voltage VGT can have a voltage difference ΔV1' less than the expected first voltage difference ΔV1 relative to the reference voltage VREF, and the gamma bottom voltage VGB can have a voltage difference ΔV2' greater than the expected second voltage difference ΔV2 relative to the reference voltage VREF. In this case, the data voltage VDAT generated based on the gamma top voltage VGT and the gamma bottom voltage VGB can remain unchanged, the reference voltage VREF can be increased, and therefore the pixel PX receiving the increased reference voltage VREF can emit light with a brightness higher than the expected brightness.

[0072] However, in the display device 100 according to the embodiment, such as Figure 11 As illustrated in the second timing diagram 330, when the feedback reference voltage VREF_FB is increased by a voltage increase amount ΔV, the power management circuit 160 can increase each of the gamma top voltage VGT and gamma bottom voltage VGB by a voltage increase amount ΔV. Accordingly, the gamma top voltage VGT can maintain a desired first voltage difference ΔV1 relative to the feedback reference voltage VREF_FB, and the gamma bottom voltage VGB can maintain a desired second voltage difference ΔV2 relative to the feedback reference voltage VREF_FB. Furthermore, the data driver 130 can increase the data voltage VDAT by a voltage increase amount ΔV based on the increased gamma top voltage VGT and the increased gamma bottom voltage VGB. Accordingly, even though the reference voltage VREF is increased by a voltage increase amount ΔV, because the data voltage VDAT is also increased by a voltage increase amount ΔV, each pixel PX can emit light with the desired brightness (no brightness difference relative to the desired brightness), and crosstalk defects caused by changes or ripples in the reference voltage VREF can be effectively prevented or reduced.

[0073] As described above, in the display device 100 according to the embodiment, the panel driver 120 can receive a reference voltage VREF at point FP in the display area DR as a feedback reference voltage VREF_FB via the feedback line FBL, and can adjust the data voltage VDAT according to the feedback reference voltage VREF_FB. Accordingly, crosstalk defects caused by changes or ripples in the reference voltage VREF can be effectively prevented or reduced.

[0074] Figure 12 This is a block diagram illustrating a display device according to an embodiment, and Figure 13 This is a block diagram illustrating an example of a display device according to an embodiment.

[0075] refer to Figure 12 The display device 400 may include a display panel 410 and a panel driver 120. The panel driver 120 may include a data driver 130, a scan driver 140, a transmit driver 150, a power management circuit 160, and a controller 170. In addition to the display panel 410 including multiple feedback lines FBL1, FBL2, FBL3, and FBL4 respectively connected to multiple points FP1, FP2, FP3, and FP4 within the display area DR, and the panel driver 120 (or controller 170) being connected to one feedback line selected from the multiple feedback lines FBL1, FBL2, FBL3, and FBL4 (e.g., FBL2), Figure 12 The display device 400 can have the same as Figure 1 The display device 100 has a substantially the same structure and substantially the same operation.

[0076] The panel driver 120 can receive a reference voltage VREF within the display area DR as a feedback reference voltage VREF_FB via one feedback line selected from a plurality of feedback lines FBL1, FBL2, FBL3, and FBL4 (e.g., FBL2), and can adjust the data voltage VDAT according to the feedback reference voltage VREF_FB. In some embodiments, the panel driver 120 can increase the data voltage VDAT as the feedback reference voltage VREF_FB increases, and can decrease the data voltage VDAT as the feedback reference voltage VREF_FB decreases. Furthermore, in some embodiments, the feedback line connected to the panel driver 120 (or controller 170) can be selected from a plurality of feedback lines FBL1, FBL2, FBL3, and FBL4 according to the crosstalk characteristics of the display panel 410. For example, during the manufacturing process of the display device 400, a minimum data voltage corresponding to the maximum gray level (e.g., 255 gray levels) and a maximum data voltage corresponding to the minimum gray level (e.g., 0 gray level) can be alternately provided to the respective pixel rows of the display panel 410. The brightness of the display panel 410 can be measured, and the pixel row with the maximum crosstalk defect among the various pixel rows of the display panel 410 can be determined. Furthermore, among the multiple feedback lines FBL1, FBL2, FBL3, and FBL4, the feedback line (e.g., FBL2) connected to a point adjacent to the pixel row with the maximum crosstalk defect (e.g., FP2) can be connected to the controller 170. Additionally, in some embodiments, the feedback line (e.g., FBL2) can be connected to the controller 170 via a connecting resistor CR. For example, the connecting resistor CR can have a resistance value lower than a reference resistance value, and can have a resistance value close to approximately 0 Ω, but is not limited to this.

[0077] For example, such as Figure 13As illustrated, controller 170 can be connected to one of a plurality of feedback lines (e.g., FBL2) selected from FBL1, FBL2, FBL3, and FBL4 via a connecting resistor CR, and may not be connected to the remaining feedback lines (e.g., FBL1, FBL3, and FBL4). The plurality of feedback lines FBL1, FBL2, FBL3, and FBL4 are respectively connected to a plurality of points FP1, FP2, FP3, and FP4 within the display area DR. Controller 170 can receive a feedback reference voltage VREF_FB via the selected feedback line (e.g., FBL2) and can generate a gamma control signal GCTRL based on the feedback reference voltage VREF_FB. Power management circuitry 160 can adjust the gamma top voltage VGT and gamma bottom voltage VGB in response to the gamma control signal GCTRL. Data driver 130 can adjust the data voltage VDAT based on the adjusted gamma top voltage VGT and adjusted gamma bottom voltage VGB.

[0078] As described above, in the display device 400 according to the embodiment, the panel driver 120 can receive a reference voltage VREF at a point (e.g., FP2) within the display area DR as a feedback reference voltage VREF_FB via one of a plurality of feedback lines FBL1, FBL2, FBL3, and FBL4 (e.g., FBL2), and can adjust the data voltage VDAT according to the feedback reference voltage VREF_FB. Accordingly, crosstalk defects caused by variations or ripples in the reference voltage VREF can be effectively prevented or reduced.

[0079] Figure 14 This is a block diagram illustrating an electronic device according to an embodiment.

[0080] refer to Figure 14 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0081] The processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0082] The memory 13 can store data information for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can output image information via the display screen by processing the received signals.

[0083] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power for the operation of the electronic device 10.

[0084] At least one of the components of electronic device 10 may be included in the display device according to the embodiments described above. Furthermore, some of the individual modules functionally comprised in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include display module 11, and processor 12, memory 13, and power module 14 may be provided as other devices within electronic device 10 besides the display device.

[0085] Figure 15 These are schematic diagrams illustrating electronic devices according to various embodiments.

[0086] refer to Figure 15 The various electronic devices applied to the display devices according to the embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet personal computers (“PCs”) 10_1b, laptop computers 10_1c, televisions (“TVs”) 10_1d and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c, and vehicle electronic devices including display modules such as central information displays (“CIDs”) arranged on the dashboard, center instrument panel and dashboard of a car, and rearview mirror displays in the vehicle 10_3.

[0087] The foregoing is illustrative of the embodiments and should not be construed as limiting them. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without materially departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the invention as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels in the display area and feedback lines connected to the points in the display area; as well as Panel driver, drives the display panel. Each of the plurality of pixels generates an emission current based on the voltage difference between the data voltage and the reference voltage, and emits light with a brightness corresponding to the emission current. The panel driver receives the reference voltage at the point in the display area via the feedback line as a feedback reference voltage, and adjusts the data voltage according to the feedback reference voltage.

2. The display device according to claim 1, wherein, The panel driver increases the data voltage as the feedback reference voltage increases, and decreases the data voltage as the feedback reference voltage decreases.

3. The display device according to claim 1, wherein, The panel driver includes: The power management circuit generates the reference voltage, the gamma top voltage, and the gamma bottom voltage; A data driver that generates the data voltage based on the gamma top voltage and the gamma bottom voltage, and provides the data voltage to each of the plurality of pixels; and The controller controls the power management circuit and the data driver.

4. The display device according to claim 3, wherein, The controller receives the feedback reference voltage through the feedback line and generates a gamma control signal based on the feedback reference voltage. The power management circuit adjusts the top and bottom voltages of the gamma sensor in response to the gamma control signal. The data driver adjusts the data voltage based on the adjusted gamma top voltage and the adjusted gamma bottom voltage.

5. The display device according to claim 4, wherein, As the feedback reference voltage increases, the controller generates a gamma control signal indicating that the gamma top voltage and the gamma bottom voltage should be increased. The power management circuit increases the gamma top voltage and the gamma bottom voltage in response to the gamma control signal, and the data driver increases the data voltage based on the increased gamma top voltage and the increased gamma bottom voltage.

6. The display device according to claim 5, wherein, When the feedback reference voltage increases by a certain amount, the power management circuit increases each of the gamma top voltage and the gamma bottom voltage by that amount, and the data driver increases the data voltage by that amount based on the increased gamma top voltage and the increased gamma bottom voltage.

7. The display device according to claim 3, wherein, The panel driver further includes: The scan driver provides write signals, compensation signals, initialization signals, and bypass signals to each of the plurality of pixels; and The transmit driver provides the transmit signal to each of the plurality of pixels.

8. The display device according to claim 1, wherein, Each of the plurality of pixels includes: The first capacitor includes a first electrode that receives a first power supply voltage and a second electrode connected to a first node; The second capacitor includes a first electrode connected to the first node and a second electrode connected to the second node; The first transistor generates the emission current based on the voltage of the second node; The second transistor transmits the data voltage to the first node in response to the write signal; The third transistor connects the first transistor diode in response to the compensation signal; The fourth transistor applies an initialization voltage to the second node in response to an initialization signal; The fifth transistor, in response to the compensation signal, applies the reference voltage to the first node; and The light-emitting element emits light based on the emitted current.

9. The display device according to claim 8, wherein, The first transistor includes a gate connected to the second node, a second terminal, and a first terminal for receiving the first power supply voltage. The second transistor includes a gate for receiving the write signal, a first terminal connected to a data line, and a second terminal connected to the first node. The third transistor includes a gate for receiving the compensation signal, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the second node. The fourth transistor includes a gate for receiving the initialization signal, a first terminal connected to the second node, and a second terminal for receiving the initialization voltage. The fifth transistor includes a gate for receiving the compensation signal, a first terminal connected to the first node, and a second terminal for receiving the reference voltage. The light-emitting element includes an anode connected to the second terminal of the first transistor and a cathode that receives a second power supply voltage.

10. The display device according to claim 8, wherein, Each of the plurality of pixels further includes: A sixth transistor is located between the first transistor and the light-emitting element, and connects the first transistor and the light-emitting element in response to an emission signal; and The seventh transistor applies the initialization voltage to the light-emitting element in response to a bypass signal.

11. The display device according to claim 10, wherein, The sixth transistor includes a gate for receiving the transmitted signal, a first terminal connected to the first transistor, and a second terminal connected to the light-emitting element. The seventh transistor includes a gate for receiving the bypass signal, a first terminal connected to the light-emitting element, and a second terminal for receiving the initialization voltage.

12. The display device according to claim 10, wherein, The frame time period of the display device includes: During the gate initialization period, the second node is initialized. During the compensation period, the threshold voltage compensation operation of the first transistor is performed. A write period during which the data voltage is provided to each of the plurality of pixels; During the anode initialization period, the light-emitting element is initialized; and During the emission period, the light-emitting element emits light based on the emission current.

13. A display device, comprising: The display panel includes multiple pixels in the display area and multiple feedback lines respectively connected to multiple points in the display area; as well as Panel driver, drives the display panel. Each of the plurality of pixels generates an emission current based on the voltage difference between the data voltage and the reference voltage, and emits light with a brightness corresponding to the emission current. The panel driver receives the reference voltage in the display area as a feedback reference voltage through one of the plurality of feedback lines, and adjusts the data voltage according to the feedback reference voltage.

14. The display device according to claim 13, wherein, The panel driver increases the data voltage as the feedback reference voltage increases, and decreases the data voltage as the feedback reference voltage decreases.

15. The display device according to claim 13, wherein, The panel driver includes: The power management circuit generates the reference voltage, the gamma top voltage, and the gamma bottom voltage; A data driver that generates the data voltage based on the gamma top voltage and the gamma bottom voltage, and provides the data voltage to each of the plurality of pixels; and The controller controls the power management circuit and the data driver, and The controller is connected to one of the multiple feedback lines, but not to the remaining feedback lines.

16. The display device according to claim 15, wherein, Based on the crosstalk characteristics of the display panel, one feedback line is selected from the plurality of feedback lines and connected to the controller.

17. An electronic device comprising: processor; Memory, connected to the processor; The power module is connected to the processor; as well as The display device according to any one of claims 1 to 16 receives input image data from the processor and displays an image based on the input image data.

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