A communication chip testing method, a communication chip, an electronic device and a storage medium
By setting up a reset control module and a switching module between PCS and SerDes, and using AM code to detect the user_clock state of SerDes, the problems of insufficient testing and frequency imbalance of communication chips on the FPGA platform are solved, enabling more comprehensive testing and verification that is closer to real-world scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NEW H3C SEMICON TECH CO LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-21
AI Technical Summary
When testing communication chips on an FPGA-based prototyping platform, the SerDes user_clock state is difficult to lock, resulting in insufficient testing, an imbalance in clock frequency ratios, and severe SerDes bandwidth loss.
By setting a reset control module and a switching module between PCS and SerDes, the user_clock state of SerDes is detected using a preset alignment mark AM code, and a reset or data stream switching is performed to avoid external protocol transmission and frequency increase, ensuring that SerDes is fully loaded.
It improves the sufficiency and completeness of communication chip testing while avoiding clock frequency imbalance and bandwidth loss, and supports verification in hot-swappable scenarios.
Smart Images
Figure CN122437785A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a method for testing communication chips, communication chips, electronic devices, and storage media. Background Technology
[0002] The interface between the communication chip and the outside world is mostly a SerDes (Serialize / Deserializer) interface. Its function is to send the data output by the PCS (Physical Coding Sublayer) to the outside world in the form of a serial code stream, and to deserialize the serial code stream transmitted from the outside world, and then send the deserialized data back to the PCS.
[0003] During the normal operation and testing of the communication chip, it is necessary to obtain the status of the SerDes user_clock (user logic clock). A locked user_clock status indicates that the data received and transmitted by SerDes is phase-aligned with the clock signal, while an unlocked status indicates misalignment. When testing the communication chip, if an unlocked user_clock status is detected, SerDes needs to be reset to restore its locked user_clock status, allowing testing of the communication chip to continue.
[0004] In real communication chips, SerDes has a state self-detection function, capable of detecting the state of the user_clock and sending the user_clock state to the PCS. However, when simulating and testing the communication chip using an FPGA (Field-Programmable Gate Array)-based prototype verification platform, the SerDes built into this platform does not have the state self-detection function.
[0005] In order for the PCS to obtain the state of the SerDes user_clock, related technologies require controlling the SerDes to transmit data to the PCS based on a specified outer protocol. This outer protocol can be Aurora 64B / 66B, Aurora 8B / 10B, or 10GBASE-KR, etc., so that the PCS can parse the data transmitted by the SerDes based on the outer protocol and determine the state of the SerDes user_clock.
[0006] However, during the data transmission process from the SerDes layer to the PCS based on the outer protocol, redundant data is inserted into the data, resulting in bandwidth loss of the effective data. This makes it difficult to test the SerDes under full load, thus hindering the thorough testing and verification of the communication chip. Furthermore, since the clock frequencies of the MAC layer, PCS, and SerDes in the communication chip need to meet a fixed ratio, increasing the SerDes clock frequency to achieve full load will cause an imbalance in the clock frequency ratio among the MAC layer, PCS, and SerDes. Therefore, the method of testing communication chips using an FPGA-based prototyping platform faces the dilemma of clock frequency imbalance and the inability to fully load the SerDes. Summary of the Invention
[0007] The purpose of this invention is to provide a communication chip testing method, a communication chip, an electronic device, and a storage medium, to improve the sufficiency of testing during the testing of communication chips on an FPGA-based prototyping platform. The specific technical solution is as follows:
[0008] This invention first provides a communication chip testing method applied to an electronic device. The electronic device runs a prototype verification platform based on a Field-Programmable Gate Array (FPGA), and the prototype verification platform is loaded with a simulated communication chip. The communication chip includes a Physical Coding Sublayer (PCS) and a Serializer / Deserializer (SerDes). The method includes:
[0009] The SerDes deserializes the received external data stream to generate a first data stream and sends the first data stream to the PCS; wherein, a preset alignment mark AM code is inserted into the external data stream;
[0010] The PCS detects whether the first data stream contains the AM code; if it does not, it determines that the user logic clock user_clock of the SerDes is unlocked and resets the SerDes.
[0011] If the PCS detects that the first data stream contains the AM code after the SerDes is reset, it continues to execute the preset process of testing the communication chip.
[0012] In one possible embodiment, a reset control module is provided between the PCS and the SerDes;
[0013] The PCS sends an indication signal to the reset control module; wherein the indication signal indicates whether the first data stream contains the AM code;
[0014] The reset control module triggers the SerDes reset when it detects that the indication signal indicates that the first data stream does not contain the AM code.
[0015] In one possible embodiment, a switching module is provided between the PCS and SerDes; the method further includes:
[0016] The PCS transmits a second data stream to the switching module for serialization by the SerDes;
[0017] The switching module transmits the second data stream to the SerDes; if it detects that the second data stream has no level inversion within a preset time period, it switches the second data stream transmitted to the SerDes to the third data stream generated by the switching module; wherein, the third data stream has level inversion within any preset time period.
[0018] In one possible embodiment, the method further includes:
[0019] When the switching module is transmitting the third data stream to the SerDes, if it detects a level inversion in the second data stream, it will switch the third data stream transmitted to the SerDes to the second data stream.
[0020] In one possible embodiment, the third data stream is a pseudo-random code.
[0021] This invention also provides a communication chip, which is installed on a prototype verification platform based on a field-programmable gate array (FPGA); the communication chip includes a physical coding sublayer (PCS) and a serializer / deserializer (SerDes);
[0022] The SerDes is used to deserialize the received external data stream to generate a first data stream and send the first data stream to the PCS; wherein, a preset alignment mark AM code is inserted into the external data stream;
[0023] The PCS is used to detect whether the AM code is contained in the first data stream; if it is not contained, the user logic clock user_clock of the SerDes is determined to be unlocked, and the SerDes is reset.
[0024] The PCS is also configured to continue executing a preset process for testing the communication chip if the AM code is detected in the first data stream after the SerDes is reset.
[0025] In one possible embodiment, a reset control module is provided between the PCS and the SerDes;
[0026] The PCS is specifically used to send an indication signal to the reset control module; wherein the indication signal indicates whether the first data stream contains the AM code;
[0027] The reset control module is used to trigger the SerDes reset when the indication signal indicates that the first data stream does not contain the AM code.
[0028] In one possible embodiment, a switching module is also included;
[0029] The switching module is used to acquire the second data stream transmitted from the PCS to the SerDes; if the second data stream has no level inversion within a specified unit of time, the data stream transmitted from the PCS to the SerDes is switched to the third data stream; wherein the third data stream has level inversion within any unit of time.
[0030] This invention also provides an electronic device, including an FPGA, a communication interface, a memory, and a communication bus, wherein the FPGA, the communication interface, and the memory communicate with each other through the communication bus.
[0031] Memory, used to store computer programs;
[0032] When an FPGA is used to execute a program stored in its memory, it implements the steps of any of the communication chip testing methods described above.
[0033] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by an FPGA, implements the steps of any of the communication chip testing methods described above.
[0034] This invention also provides a computer program product containing instructions that, when run on a computer, causes the computer to execute any of the communication chip testing methods described above.
[0035] Beneficial effects of the embodiments of the present invention:
[0036] The communication chip testing method provided in this invention is applied to an electronic device. The electronic device runs an FPGA-based prototype verification platform, which loads a simulated communication chip. The communication chip includes a PCS and a SerDes. The SerDes deserializes the received external data stream to generate a first data stream and sends the first data stream to the PCS. A preset alignment marker (AM code) is inserted into the external data stream. The PCS detects whether the first data stream contains the AM code. If it does not, the user_clock state of the SerDes is determined to be unlocked, and the SerDes is reset. If the PCS detects that the first data stream contains the AM code after the SerDes reset, it continues to execute the preset testing process for the communication chip. Therefore, this invention determines whether the user_clock state of the SerDes is unlocked by detecting whether the first data stream contains the AM code. This eliminates the need for the SerDes to use an external protocol to transmit data to the PCS, and also eliminates the need to increase the frequency of the SerDes to achieve full load. This avoids clock frequency imbalance and bandwidth loss in the SerDes, thus improving the sufficiency of the communication chip testing and verification.
[0037] Of course, implementing any product or method of the present invention does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings.
[0039] Figure 1 This is a schematic diagram of the structure of a communication chip;
[0040] Figure 2 This is a schematic diagram of the first process of the communication chip testing method provided in the embodiment of the present invention;
[0041] Figure 3 This is a schematic diagram of a second process for the communication chip testing method provided in an embodiment of the present invention;
[0042] Figure 4 This is a schematic diagram of the reset control module in the communication chip testing method provided in an embodiment of the present invention;
[0043] Figure 5 This is a schematic diagram of the switching module in the communication chip testing method provided in the embodiment of the present invention;
[0044] Figure 6This is a schematic diagram of the structure of the communication chip provided in an embodiment of the present invention;
[0045] Figure 7 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation
[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on the present invention are within the scope of protection of the present invention.
[0047] The structure of a communication chip can be as follows Figure 1 As shown, SOC (System on Chip) 1 and SOC2 are two communication chips that interact with each other for data. IC_RTL refers to the RTL (Register Transfer Level) in IC (Integrated Circuit) design. tx_clock_lock indicates the state of the user_clock on the TX (Transmit) side; tx_clock indicates the signal of the user_clock on the TX side; tx_data indicates the data that needs to be sent by SerDes; rx_clock_lock indicates the state of the user_clock on the RX (receive) side; rx_clock indicates the signal of the user_clock on the RX side; rx_data indicates the data received by SerDes. PCS completes 64b / 66b or 8b / 10b encoding, and the SerDes interface is only responsible for the transmission of the serial code stream. Common rates are 10G (Gbps) / 25G / 50G / 56G / 100G.
[0048] When using an FPGA-based prototyping platform to simulate and test communication chips, related technologies require controlling the SerDes to transmit data to the PCS based on a specified outer protocol in order to obtain the SerDes user_clock state. However, this leads to bandwidth loss of the SerDes' effective data, making it difficult to test under full load on the SerDes and hindering the thorough testing and verification of the communication chip. Furthermore, IC design requirements dictate that the MAC layer clock frequency, PCS clock frequency, and SerDes clock frequency must be proportionally reduced from the actual chip frequency. For example, if the actual chip clock is: MAC layer: 1GHz; PCS: 500MHz; SerDes: 10GHz; and verification reduces the frequency to 1 / 10, then the requirements are: MAC layer: 100MHz; PCS: 50MHz; SerDes: 1GHz. Only by meeting this requirement can the data bandwidth of each stage be guaranteed, ensuring the correctness of the chip's function and the sufficiency of verification. Therefore, increasing the SerDes clock frequency to achieve full load would cause an imbalance in the clock frequency ratio between the MAC layer, PCS, and SerDes.
[0049] To address the aforementioned problems, embodiments of the present invention provide a communication chip testing method, a communication chip, an electronic device, and a storage medium. The communication chip testing method is described first below.
[0050] This method is applied to electronic devices that run FPGA-based prototyping platforms, which in turn load simulated communication chips. These communication chips include PCS and SerDes. Figure 2 As shown, the method includes:
[0051] S201, SerDes deserializes the received external data stream to generate a first data stream and sends the first data stream to PCS; wherein, a preset alignment mark AM code is inserted into the external data stream;
[0052] S202, PCS detects whether the first data stream contains AM code; if not, it determines that the user_clock state of SerDes is unlocked and resets SerDes.
[0053] S203, if the PCS detects that the first data stream contains AM code after the SerDes reset, it will continue to execute the preset process of testing the communication chip.
[0054] In this embodiment, the state of the SerDes user_clock is determined to be unlocked by detecting whether the first data stream obtained by the SerDes from deserializing external data contains AM code. This eliminates the need for the SerDes to transmit data to the PCS using an external protocol, and also eliminates the need to increase the frequency of the SerDes to make it fully loaded. This avoids clock frequency imbalance and bandwidth loss of the SerDes, thus improving the sufficiency of communication chip testing and verification.
[0055] In this embodiment, the simulated communication chip code can be loaded into an FPGA-based prototype verification platform, thereby enabling the FPGA's programmable features to simulate the communication chip's function and perform simulation testing on the communication chip.
[0056] Regarding step S201, the AM (alignment marker) code is a marker used for multi-channel data synchronization. A special marker is inserted at a fixed position in each data channel, allowing the receiver to align the data across channels and achieve bit-level synchronization by detecting these markers. However, if the SerDes user_clock loses lock, the data acquired by the SerDes will be incorrect, resulting in the first data stream sent to the PCS not containing the correct AM code. This embodiment utilizes the AM code used by the communication chip during interaction to determine the state of the user_clock.
[0057] During the testing process, methods such as... Figure 1 The structure involves setting up two communication chips in the prototype verification platform to enable data interaction. In this case, the external data stream received by the SerDes chip in one communication chip can be generated and sent by the other communication chip.
[0058] Regarding step S202, since the SerDes TX-side user_clock usually does not lose lock, the state of the SerDes user_clock in this embodiment can specifically be the state of the SerDes TX-side user_clock.
[0059] The following is an example of a method for detecting AM codes:
[0060] Taking the first data stream obtained by SerDes deserialization as 32 bits of parallel data as an example, in each clock cycle, PCS can write the first data stream into a shift register and concatenate it into a 96-bit data set. Then, the data can be compared with the standard AM code by shift comparison. If the first AM code block is detected in the first 1-56 bits of the data, the second-level detection can be performed on the first 1-56 bits of the next 96-bit data set in each subsequent clock cycle.
[0061] In the second-level detection process, the position of the first AM code block in the 56-bit data is first determined, and then subsequent AM code blocks are identified sequentially at fixed bit intervals. If the number of AM code blocks detected in the 56-bit data is greater than or equal to 9, it is determined that the first data stream contains AM code, and the AM code block interval counter is started (the time interval follows the standard protocol). When the AM code block interval counter reaches each interval period, if the number of AM code blocks detected in the current clock cycle according to the above process is greater than or equal to 9, it is determined that the first data stream still contains AM code, and this process is repeated. If the AM code block interval counter fails to detect AM code blocks for 5 consecutive interval periods, or the number detected is less than 9, it is determined that the first data stream does not contain AM code, and the PCS can then determine that the SerDes user_clock state is unlocked and reset the SerDes.
[0062] In step S203, after SerDes is reset, it will retry to lock the phase of the data and clock signal. Then, PCS can continue to detect whether the first data stream sent by SerDes to PCS contains AM code. If AM code is detected, it is determined that the current user_clock state of SerDes is locked, so the preset process of testing the communication chip can continue to be executed.
[0063] Since there is a requirement for proportional frequency reduction during prototype verification, this method can fully load the effective data of SerDes without increasing the user_clk frequency of SerDes. This achieves the goal of proportional frequency reduction of MAC layer, PCS, and SerDes in IC verification, while satisfying the proportional relationship of effective bandwidth. This makes the test closer to the real use scenario of the chip, thereby reducing the risk of chip failure and leakage, and ensuring functional correctness and verification integrity.
[0064] In practical use, hot-plugging SerDes can introduce clock jitter and other issues, leading to a loss of user clock lock. Using this invention, if the SerDes user clock loses lock due to a simulated hot-plugging scenario during testing, the PCS can detect this state and reset the SerDes. Testing can then proceed after the user clock is relocked following the reset. Therefore, this invention supports verification of hot-plugging scenarios for SerDes, filling a gap in existing technologies and further enhancing test completeness.
[0065] In one possible embodiment, a reset control module is provided between the PCS and the SerDes; such as Figure 3 As shown, SerDes is reset using the following steps:
[0066] S301, PCS sends an indication signal to the reset control module; wherein, the indication signal indicates whether the first data stream contains AM code;
[0067] S302, the reset control module triggers a SerDes reset when it detects an indication signal indicating that the first data stream does not contain AM code.
[0068] In this embodiment, a reset control module is set between PCS and SerDes, and the reset control module detects the indication signal sent by PCS. When the indication signal indicates that the first data stream does not contain AM code, the SerDes is reset. This enables the reset of SerDes when the user_clock state of SerDes is unlocked in the prototype verification platform.
[0069] For steps S301-S302 above, the aforementioned indication signal can specifically be am_lock (AM stream lock signal). am_lock being 1 indicates that the AM stream is locked, which also reflects that the SerDes user_clock is locked; am_lock being 0 indicates that the AM stream is unlocked, and at this time, the SerDes user_clock can be considered to be unlocked.
[0070] like Figure 4As shown, the reset control module may specifically include an AM signal detection submodule and an automatic reset submodule. The automatic reset submodule sends a reset control signal to the AM signal detection submodule. An enable switch is provided between the automatic reset submodule and the AM signal detection submodule. The AM signal detection submodule detects am_lock to determine whether the first data stream contains AM code. Thus, when the enable switch is on, if the AM signal detection submodule detects am_lock as 0, it triggers a SerDes reset. Specifically, the AM signal detection submodule can be connected to the SerDes reset pin, allowing it to send a high-level signal to this pin to trigger a SerDes reset. If the enable switch is not on, a manual reset is required when am_lock is 0.
[0071] In one possible embodiment, a switching module is provided between the PCS and SerDes; the communication chip testing method further includes:
[0072] PCS transmits the second data stream to the switching module for SerDes serialization processing;
[0073] The switching module transmits a second data stream to SerDes; if it detects that the second data stream has no level flip within a preset time period, it switches the second data stream transmitted to SerDes to a third data stream generated by the switching module; wherein, the third data stream has level flips within any preset time period.
[0074] In this embodiment, a switching module is provided between the PCS and SerDes. The switching module acquires the second data stream transmitted from the PCS to the SerDes. If the second data stream does not undergo level transitions within a preset time period, the data stream transmitted from the PCS to the SerDes is switched to a third data stream, and the third data stream undergoes level transitions within any preset time period. This avoids the user_clock from losing lock due to the data transmitted by the SerDes being constantly 0 or constantly 1.
[0075] The preset duration can be set based on experience and requirements. Due to the characteristics of SerDes, it cannot transmit constant 0 or constant 1 for extended periods, i.e., it cannot transmit signals without level transitions for long periods, otherwise the user_clock will lose lock, leading to functional abnormalities. PCS has a built-in encoding function, which sends a constant 0 data stream to SerDes in reset state or when it is considered to be in shutdown state, which may cause the SerDes user_clock to lose lock.
[0076] In this embodiment, a switching module is added between PCS and SerDes. This module can generate a third data stream. When it detects that the data stream output by PCS is a continuous fixed period of 0 or 1, it automatically switches the data stream to the third data stream to prevent SerDes from entering an abnormal state due to clock lockout.
[0077] In one possible embodiment, the communication chip testing method further includes:
[0078] When the switching module is transmitting a third data stream to SerDes, if it detects a level inversion in the second data stream, it will switch the third data stream transmitted to SerDes to the second data stream.
[0079] In this embodiment, the switching module can also switch the data stream transmitted from PCS to SerDes back to the second data stream if a level flip is detected in the second data stream, so that the process of testing the communication chip can continue.
[0080] In other words, after the communication chip is started, the switching module can first transmit the second data stream sent by the PCS to SerDes. If it detects that the second data stream has no level flip within a preset time, it will switch the data transmitted to SerDes to the third data stream. After that, the switching module will continue to receive and detect the second data stream until it detects that the second data stream has a level flip, and then switch the data stream transmitted to SerDes back to the second data stream.
[0081] In one possible embodiment, the aforementioned third data stream is a pseudo-random code.
[0082] In this embodiment, the switching module can generate a pseudo-random code as a third data stream to be transmitted to SerDes. Since the pseudo-random code is almost impossible to be constantly 0 or constantly 1, it can avoid the user_clock from losing its lock due to the data transmitted by SerDes being constantly 0 or constantly 1.
[0083] Among them, pseudo-random code is a deterministic sequence code with random sequence characteristics, which can be generated by an R-level shift register network.
[0084] In one specific implementation, such as Figure 5As shown, the switching module may include a signal detection submodule and a PRBS (Pseudo-Random Binary Sequence) submodule. The PRBS submodule is used to generate a pseudo-random binary sequence and send it to the signal detection submodule; the signal detection submodule is used to acquire the second data stream transmitted from the PCS to the SerDes; if the second data stream does not have a level flip within a preset time, the data stream transmitted from the PCS to the SerDes is switched to the random binary sequence generated by the PRBS submodule.
[0085] An enable switch can also be set between the signal detection submodule and the PRBS submodule, so that the function of the PRBS submodule can be turned off when necessary for fault location.
[0086] Based on the same inventive concept, embodiments of the present invention also provide a communication chip, which is a virtual device and is set on a prototype verification platform based on a field-programmable gate array (FPGA); such as Figure 6 As shown, the communication chip includes a physical coding sublayer PCS601 and a serial deserializer SerDes602;
[0087] The SerDes602 is used to deserialize the received external data stream to generate a first data stream and send the first data stream to the PCS601; wherein, a preset alignment mark AM code is inserted into the external data stream;
[0088] The PCS601 is used to detect whether the AM code is contained in the first data stream; if it is not contained, the user logic clock user_clock of the SerDes602 is determined to be unlocked, and the SerDes602 is reset.
[0089] The PCS601 is also configured to continue executing a preset process for testing the communication chip if the AM code is detected in the first data stream after the SerDes602 is reset.
[0090] In one possible embodiment, a reset control module is provided between the PCS601 and the SerDes602;
[0091] The PCS601 is also used to send an indication signal to the reset control module; wherein the indication signal indicates whether the first data stream contains the AM code;
[0092] The reset control module is used to trigger the SerDes602 to reset when the indication signal indicates that the first data stream does not contain the AM code.
[0093] In one possible embodiment, a switching module is provided between the PCS601 and the SerDes602;
[0094] The PCS601 is also used to transmit a second data stream to be serialized by the SerDes602 to the switching module;
[0095] The switching module is used to transmit the second data stream to the SerDes602; when it is detected that the second data stream has no level inversion within a preset time period, the second data stream transmitted to the SerDes602 is switched to the third data stream generated by the switching module; wherein, the third data stream has level inversion within any preset time period.
[0096] In one possible embodiment, the switching module is further configured to, when transmitting the third data stream to the SerDes602, switch the third data stream to the second data stream if a level inversion is detected in the second data stream.
[0097] In one possible embodiment, the third data stream is a pseudo-random code.
[0098] This invention also provides an electronic device, such as... Figure 7 As shown, it includes FPGA 701, communication interface 702, memory 703 and communication bus 704, wherein FPGA 701, communication interface 702 and memory 703 communicate with each other through communication bus 704.
[0099] Memory 703 is used to store computer programs;
[0100] When the FPGA701 executes the program stored in the memory 703, it implements any of the communication chip testing methods described above.
[0101] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.
[0102] The communication interface is used for communication between the aforementioned electronic devices and other devices.
[0103] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned FPGA.
[0104] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by an FPGA, implements the steps of any of the above-described communication chip testing methods.
[0105] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the communication chip testing methods described in the above embodiments.
[0106] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).
[0107] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0108] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for communication chips, electronic devices, computer-readable storage media, and computer program products are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0109] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A method for testing communication chips, characterized in that, The method is applied to an electronic device, wherein the electronic device runs a prototype verification platform based on a field-programmable gate array (FPGA), and the prototype verification platform is loaded with a simulated communication chip; the communication chip includes a physical coding sublayer (PCS) and a serializer / deserializer (SerDes); the method includes: The SerDes deserializes the received external data stream to generate a first data stream and sends the first data stream to the PCS; wherein, a preset alignment mark AM code is inserted into the external data stream; The PCS detects whether the first data stream contains the AM code; if it does not, it determines that the user logic clock user_clock of the SerDes is unlocked and resets the SerDes. If the PCS detects that the first data stream contains the AM code after the SerDes is reset, it continues to execute the preset process of testing the communication chip.
2. The method according to claim 1, characterized in that, A reset control module is provided between the PCS and the SerDes; The PCS sends an indication signal to the reset control module; wherein the indication signal indicates whether the first data stream contains the AM code; The reset control module triggers the SerDes reset when it detects that the indication signal indicates that the first data stream does not contain the AM code.
3. The method according to claim 1, characterized in that, A switching module is provided between the PCS and SerDes; the method further includes: The PCS transmits a second data stream to the switching module for serialization by the SerDes; The switching module transmits the second data stream to the SerDes; if it detects that the second data stream has no level inversion within a preset time period, it switches the second data stream transmitted to the SerDes to the third data stream generated by the switching module; wherein, the third data stream has level inversion within any preset time period.
4. The method according to claim 3, characterized in that, The method further includes: When the switching module is transmitting the third data stream to the SerDes, if it detects a level inversion in the second data stream, it will switch the third data stream transmitted to the SerDes to the second data stream.
5. The method according to claim 3 or 4, characterized in that, The third data stream is a pseudo-random code.
6. A communication chip, characterized in that, The communication chip is set up on a prototype verification platform based on a field-programmable gate array (FPGA); the communication chip includes a physical coding sublayer (PCS) and a serializer / deserializer (SerDes). The SerDes is used to deserialize the received external data stream to generate a first data stream and send the first data stream to the PCS; wherein, a preset alignment mark AM code is inserted into the external data stream; The PCS is used to detect whether the AM code is contained in the first data stream; if it is not contained, the user logic clock user_clock of the SerDes is determined to be unlocked, and the SerDes is reset. The PCS is also configured to continue executing a preset process for testing the communication chip if the AM code is detected in the first data stream after the SerDes is reset.
7. The communication chip according to claim 6, characterized in that, A reset control module is provided between the PCS and the SerDes; The PCS is specifically used to send an indication signal to the reset control module; wherein the indication signal indicates whether the first data stream contains the AM code; The reset control module is used to trigger the SerDes reset when the indication signal indicates that the first data stream does not contain the AM code.
8. The communication chip according to claim 6, characterized in that, It also includes a switching module; The switching module is used to acquire the second data stream transmitted from the PCS to the SerDes; if the second data stream has no level inversion within a specified unit of time, the data stream transmitted from the PCS to the SerDes is switched to the third data stream; wherein the third data stream has level inversion within any unit of time.
9. An electronic device, characterized in that, It includes an FPGA, a communication interface, a memory, and a communication bus. The FPGA, the communication interface, and the memory communicate with each other through the communication bus. Memory, used to store computer programs; An FPGA, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-5.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by the FPGA, implements the steps of the method described in any one of claims 1-5.