Determining available resources for storing data

Abstract

This application is directed to determining available resources for storing data. A host system can obtain data for writing to a memory system. The host system can send an indication to the memory system that the data is to be written to the memory system, and the memory system can remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system can delay background operations at the memory system until the data has been written to the memory system. The memory system can also create a recovery point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system can be delayed until after the data is written to the memory system.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese invention patent application entitled "Determining Available Resources for Storing Data", application number 202211031277.1, and application date August 26, 2022.

[0003] Cross-references

[0004] This patent application claims priority to U.S. Patent Application No. 17 / 488,205, filed September 28, 2021, entitled “Determining Available Resources for Storage Data,” and U.S. Provisional Patent Application No. 63 / 238,027, filed August 27, 2021, entitled “Determinating Available Resources for Storage Data,” each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field involves identifying available resources for storing data. Background Technology

[0006] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0007] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0008] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured such that the apparatus: receives an instruction to write data to a memory system; removes invalid data from the memory system at least in part based on the instruction to write the data, until the size of available resources in the memory system is greater than or equal to the size of the data; delays a garbage collection operation in the memory system at least in part based on the size of the available resources being greater than or equal to the size of the data after the removal of the invalid data; and writes the data to the available resources at least in part based on the delay in the garbage collection operation.

[0009] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured such that the apparatus: at least partially based on identifying that data will be written to the memory system, issues a request for the size of an available resource in the memory system; receives, in response to the request, an indication of the size of the available resource; determines whether the size of the available resource is greater than or equal to the size of the data; issues one or more commands, at least partially based on the size of the available resource being less than the size of the data, to instruct the memory system to remove invalid data; receives, in response to the one or more commands, a second indication of the size of the available resource; and issues the data to the memory system at least partially based on the second indication of the size of the available resource indicating that the size of the available resource is greater than or equal to the size of the data.

[0010] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured such that the apparatus: delays garbage collection operations on a set of resources at a memory system; receives a request indicating whether the memory system includes available resources for storing data; in response to the request, transmits the indication indicating whether the memory system includes available resources based at least in part on a comparison of the size of the resource set with the threshold size; receives the data based at least in part on the fact that the size of the resource set is less than the threshold size; and writes the data to the resource set.

[0011] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured such that the apparatus: identifies a set of resources at the memory system for its delayed garbage collection operation, at least in part based on data to be written at the memory system; transmits a request indicating whether the memory system includes available resources for storing the data; receives, in response to the request, the indication whether the memory system includes available resources; and transmits the data, at least in part based on the fact that the memory system includes available resources for storing the data.

[0012] Describe a method. The method may include: receiving an instruction to write data to a memory system including memory devices; removing invalid data in the memory system at least in part based on the instruction to write the data until the size of available resources in the memory system is greater than or equal to the size of the data; delaying a garbage collection operation in the memory system at least in part based on the size of the available resources being greater than or equal to the size of the data after the removal of the invalid data; and writing the data to the available resources at least in part based on the delay in the garbage collection operation. Attached Figure Description

[0013] Figure 1 This describes instances of systems that determine the available resources for storing data based on the examples disclosed herein.

[0014] Figures 2 to 4 This describes the set of instances of operations that are available for storing data, based on the examples disclosed herein.

[0015] Figure 5 This describes instances of a resource graph that are used to determine available resources for storing data, based on examples as disclosed herein.

[0016] Figure 6 A block diagram of a memory system is shown, based on the examples disclosed herein, to determine the available resources for storing data.

[0017] Figure 7 A block diagram of a host system is shown, based on the examples disclosed herein, to determine the available resources for storing data.

[0018] Figures 8 to 11 The flowchart illustrates one or more methods for determining the available resources for storing data, based on examples as disclosed herein. Detailed Implementation

[0019] The memory system can be used to store information for programs (e.g., operating system, applications) on the device. In some instances, data for said programs can be received at the host system from an external source (e.g., using over-the-air software updates). The size of the received data can be relatively large, such as multiple gigabytes. In some instances, the received data may contain multiple or batch updates. Based on or in response to the received data, the host system may attempt to store the data at the memory system. To store data at the memory system, the host system may issue a series of write commands to write data to the memory system. If the received data contains multiple updates, the host system may sequentially receive multiple updates and write said multiple updates to the memory system.

[0020] However, in some instances, the memory system may not have sufficient space to store the data for the program received at the host system. In these cases, operations(s) for writing data to the memory system may fail. Alternatively, background operations running at the memory system while data is being written to it may cause data stored at the memory system and associated with the program to move unexpectedly from its previous location or even to the host system. In these cases, the operation for writing data to the memory system may succeed, but the data for the program may be corrupted during or after the writing process. In such failures, the host system may not be able to roll back (e.g., restore) the memory system to its state before the data was written, and in some instances, the apparatus containing both the memory system and the host system may become inoperable due to the failure to properly write data to the memory system.

[0021] To increase the likelihood of successfully completing the operation of writing a data set into the memory system (which may be referred to as a programming operation), new technologies can be used to allocate (e.g., create, reserve) sufficient space for writing the data set. Furthermore, to prevent a failed programming operation from rendering the device inoperable, new technologies can be used to allow the program to revert to a version prior to the programming operation.

[0022] In some instances, the host system may obtain data for writing to the memory system. The host system may send an indication to the memory system that the data is to be written, and the memory system may remove invalid data from its storage until it has sufficient resources to store the data. Based on or in response to sufficient resources, the memory system may delay background operations (e.g., garbage collection) until the data has been written to it. The memory system may also create a recovery point based on or in response to sufficient resources and receipt of data.

[0023] In some instances, the host system may obtain data for writing to a memory system. The host system may begin writing data to a set of resources at the memory system, where the memory system may disable background operations (e.g., garbage collection) on the resource set. Before writing data to the resource set, the host system may request an indication from the memory system whether it contains available resources for storing the data. The memory system may issue an indication of whether it contains available resources based on or in response to comparing the size of the resource set to a threshold. If the size of the resource set is less than the threshold, the memory system may indicate that resources are available for the data. Based on or in response to determining whether available resources exist, the memory system may begin writing data to the memory system if available resources exist. The memory system may also create a recovery point based on or in response to starting data writing.

[0024] The features of this disclosure are first described in the context of a memory system. The features of this disclosure are also described in the context of processing flows and flowcharts. These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts relating to determining available resources for storing data.

[0025] Figure 1 This describes an instance of system 100 that determines available resources for storing data based on examples as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0026] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0027] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0028] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The image shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0029] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0030] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0031] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0032] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0033] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0034] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, it may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0035] Although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0037] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0038] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160, which may be memory dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0039] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to each store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to each store three bits of information, it may be referred to as a three-level cell (TLC); if configured to each store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to single-level memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0040] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations can occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0041] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0042] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0043] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise identify data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be preferable to erasing and rewriting the entire old block 170, for example, due to latency or wear and tear considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0044] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data due to a newer or more recent version of the data being stored in a different page 175 of memory device 130. Invalid data may have previously been programmed into an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by host system 105). Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0045] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0046] System 100 may include any number of non-transitory computer-readable media that support the determination of available resources for storing data. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0047] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0048] Memory system 110 can be used to store instructions for programs (e.g., operating system, applications) installed on the device. In some instances, data for the program can be received at host system 105 from an external source (e.g., using over-the-air software updates). The size of the received data can be relatively large, such as multiple gigabytes. In some instances, the received data may contain multiple updates. Based on or in response to the received data, host system 105 may attempt to store the data at memory system 110. To store data at memory system 110, host system 105 may issue a series of write commands to write data at memory system 110. If the received data contains multiple updates, host system 105 may sequentially receive and write the multiple updates to memory system 110.

[0049] In some instances, the space in memory system 110 may be insufficient to store the data for a program received at host system 105. In these cases, the operation to write data to memory system 110 may fail. Alternatively, when data is written to memory system 110, background operations running at memory system 110 may cause data stored at memory system 110 and associated with the program to move unexpectedly to a different location in order to reach host system 105. In these cases, the operation to write data to memory system 110 may succeed, but the data for the program may be corrupted during or after the writing process. In the event of a write failure, host system 105 may not be able to roll back memory system 110 to a state prior to the data writing, and in some instances, the apparatus including memory system 110 and host system 105 may become inoperable due to the failure to properly write data to memory system 110.

[0050] To increase the likelihood of successfully completing the operation of writing a data set into the memory system (which may be referred to as a programming operation), techniques for allocating (e.g., creating, reserving) sufficient space for writing the data set can be used. Furthermore, to prevent a failed programming operation from rendering the device inoperable, techniques that allow the program to revert to a version prior to the programming operation can be used.

[0051] In some instances, to increase the success rate of programming operations, garbage collection may be performed before the programming operation to ensure sufficient space is available for the data used in the programming operation. In some instances, host system 105 may receive software updates installed on the device containing host system 105. For example, host system 105 may receive updates to the operating system installed on host system 105, for instance, based on or in response to a user enabling an update to be performed. Updates may be received at host system 105 from an external server (e.g., over-the-air), and host system 105 may write the updates to memory system 110. In some instances, host system 105 may also receive an indication of the size of the update or determine an upper limit on the size of the update. Based on or in response to receiving an update, host system 105 may transmit an indication that the update is to be written to memory system 110. Based on or in response to receiving the indication, memory system 110 may remove invalid data at memory system 110 (e.g., by performing garbage collection to delete invalid data) until the available resources at memory system 110 are greater than or equal to the size of the update.

[0052] Based on or in response to freeing up sufficient space in memory system 110, memory system 110 may also delay (e.g., disable) background operations, such as garbage collection. Memory system 110 may indicate to host system 105 that sufficient space exists for updates, and host system 105 may begin writing updates to memory system 110. In some instances, before writing updates, host system 105 may send an indication to begin the update writing operation, allowing memory system 110 to create a recovery point that can be used to roll back the operation in case the update writing fails.

[0053] By freeing up sufficient space in memory for the update before performing it, failures that would otherwise be caused by updates requiring additional space can be avoided. Furthermore, by creating restore points, the program can be rolled back to a previous version if the update fails for any reason (e.g., insufficient space, data corruption, lost connection).

[0054] In some instances, to increase the success rate of programming operations, garbage collection operations may be delayed (e.g., disabled) for the set of resources used to store data for programming operations. In some instances, host system 105 may receive software updates installed on a device containing host system 105, as described similarly above. Based on or in response to receiving an update, host system 105 may send a request to memory system 110 indicating the size of resources available at memory system 110 for storing the update. Based on or in response to receiving the indication, memory system 110 may compare the size of the set of resources for which garbage collection has been delayed with a threshold, for example, the size of which may be based on or in response to the size of available resources at memory system 110. If the size of the set of resources is below the threshold, memory system 110 may indicate to host system 105 that there is sufficient space in memory system 110 for the update. Therefore, host system 105 may indicate the start of the update and begin writing the update to memory system 110, and memory system 110 may create a recovery point, as described above.

[0055] By delaying garbage collection for the set of resources reserved for storing updates (e.g., reserving a set of resources for updates), the data for the update can be written to memory as soon as it is received. Furthermore, if memory runs out of free space while updates are being written to, the memory may be able to revert the program to a pre-updated version.

[0056] Figure 2 This describes instances of operations that determine a set of available resources for storing data, based on the examples disclosed herein.

[0057] Processing flow 200 can be executed by host system 205 and memory system 210, which can be referred to above. Figure 1 The described instance is a host system or storage system. In some instances, process flow 200 describes a set of instance operations executed to support the determination of available resources for storing data. For example, process flow 200 depicts operations for increasing a sufficient amount of available resources to enable the execution of operations for writing a data set to the storage system (which may be referred to as a programming operation), while maintaining a recovery point in the event of a programming operation failure.

[0058] One or more operations described in processing flow 200 may be performed earlier or later in the process, omitted, replaced, supplemented, or combined with another operation. Furthermore, additional operations described herein may be included in processing flow 200.

[0059] Various aspects of the processing flow 200 may be implemented by a controller and other components. Alternatively, aspects of the processing flow 200 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to host system 205 or firmware stored in memory coupled to memory system 210). For example, when executed by a controller (e.g., at host system 205), the instructions may cause the controller to perform the operation of the processing flow 200.

[0060] At box 215, data is available, for example, host system 205 may receive data for writing to memory system 210. In some instances, host system 205 may receive an instruction that data is to be written to memory system 210. The data may be used to support updates to software (e.g., applications, operating systems) installed on the apparatus containing host system 205 and memory system 210. Data may be received at host system 205 from an external source (e.g., over the air). In some instances, host system 205 may determine the size of the data, for example, based on or in response to an instruction received with the data. In other instances, host system 205 may determine an upper limit on the size of the data, for example, based on or in response to the type of data received, a programmed upper limit, etc.

[0061] At arrow 220, an indication of the size of available resources can be signaled at the memory system. For example, host system 205 can issue a request for the size of available resources at memory system 210, and memory system 210 can indicate the size of available resources to the host system. In some instances, host system 205 issues a read descriptor for the size of a free logical address.

[0062] At box 225, it can be verified whether there are sufficient available resources at memory system 210. For example, host system 205 can verify whether there are sufficient available resources at memory system 210 to support the execution of the update. For instance, host system 205 can determine whether the size of the available resources at memory system 210 is greater than the update size. In some instances, host system 205 can determine whether the size of the available resources at memory system 210 is greater than the upper limit of the update size.

[0063] At arrow 230, if it is determined that available resources are insufficient, host system 205 may send a message to memory system 210 triggering a garbage collection operation. In some instances, the message may direct memory system 210 to perform garbage collection for a period of time, such as five minutes. In other instances, the message may direct memory system 210 to perform garbage collection until the amount of available resources at memory system 210 is sufficient to support updates. After completing the triggered garbage collection operation, memory system 210 may indicate the size of available resources at memory system 210 to host system 205.

[0064] In instances where the memory system 210 performs a garbage collection operation for a set duration (e.g., five minutes), the available resources may be insufficient to support the update. In such cases, the host system 205 may send an additional message to the memory system 210 to trigger another garbage collection operation for the set duration based on or in response to determining that the available resources are less than the update size. This sequence of operations may continue until the available resources at the memory system 210 are sufficient to support the update.

[0065] In instances where memory system 210 performs garbage collection until the available resources at memory system 210 are sufficient to support the update, host system 205 may disregard whether the available resources at memory system 210 are sufficient to support the update and proceed to the next operation. However, in some instances, host system 205 may still verify whether the available resources at memory system 210 are sufficient to support the update as an additional check.

[0066] At box 235, a programming operation for writing data can be performed; for example, host system 205 can perform a programming operation for writing data to memory system 210. Performing the programming operation may include sending a message containing an indication that the programming operation has started to memory system 210. Writing data may include writing data to the desired location within memory system 210.

[0067] At box 240, a recovery point can be created, for example, memory system 210 can create a recovery point based on or in response to receiving an indication that a programming operation has begun. Creating a recovery point may include an L2P table (e.g., a physical page table) and a physical validity table stored prior to the start of the programming operation.

[0068] At arrow 245, the result of the programming operation can be indicated. For example, memory system 210 can indicate the result of the programming operation to host system 205. In some instances, memory system 210 indicates that the programming operation failed. In other instances, memory system 210 indicates that the programming operation succeeded.

[0069] At box 250, the result of the programming operation can be determined. For example, host system 205 can determine the success or failure of the programming operation based on or in response to an instruction received from memory system 210. In some instances, host system 205 determines that the programming operation was successful, for example, data was successfully written to the appropriate location in memory system 210. In some instances, host system 205 determines that the programming operation was unsuccessful, for example, data was not successfully written to memory system 210.

[0070] At arrow 255, based on or in response to determining that the programming operation was successful, host system 205 may send an indication of the end of the programming operation to memory system 210.

[0071] At arrow 260, based on or in response to determining that the programming operation has failed, host system 205 may transmit a message to boot memory system 210 back to the state prior to the programming operation.

[0072] At block 265, the memory system 210 can restore its state prior to the programming operation; for example, the memory system 210 can restore itself to its state prior to the programming operation. In some instances, restoring the previous state may involve replacing the current L2P and validity tables with a mapping table stored before the programming operation began. Alternatively, restoring the previous state may involve unmapping logical addresses written during the programming operation. Restoring the previous state may also involve deleting data stored at the physical address corresponding to the unmapped logical address. To determine the logical addresses that changed (e.g., were written to or unmapped) during the programming operation, the memory system 210 may compare the current L2P and validity tables with the previously stored L2P and validity tables.

[0073] At arrow 270, the result of the rollback operation can be indicated (e.g., memory system 210 can indicate the result of the rollback operation to host system 205). In some instances, memory system 210 can indicate that the rollback operation was successful, for example, if the data stored in memory system 210 matches the data stored in memory system 210 before the programming operation. In some instances, memory system 210 can indicate that the rollback operation was unsuccessful, for example, if the data stored in memory system 210 is different from the data stored in memory system 210 before the programming operation.

[0074] At box 275, the success of the rollback operation can be determined. For example, host system 205 can determine the success of the rollback operation at memory system 210, for example, based on or in response to a received indication of the result of the rollback operation. In some instances, host system 205 can determine the rollback operation is successful, for example, based on or in response to receiving an indication that the rollback operation was successful. In other instances, host system 205 can determine the rollback operation is unsuccessful, for example, based on or in response to receiving an indication that the rollback operation was unsuccessful or any indication that the result of the rollback operation was not received.

[0075] At box 280, if the host system 205 determines that the rollback operation is unsuccessful, the host system 205 may execute the programming operation a second time.

[0076] Figure 3 This describes instances of operations that determine a set of available resources for storing data, based on the examples disclosed herein.

[0077] Flowchart 300 depicts a set of instance operations executed by the host system to support garbage collection prior to the execution of programmed operations (e.g., over-the-air updates). Aspects of flowchart 300 may be implemented by a controller and other components. Alternatively, aspects of flowchart 300 may be implemented as instructions stored in memory (e.g., stored in...). Figure 1 (The firmware in the memory coupled to the host system 105). For example, when the instructions are executed by the controller (e.g., at the host system 105), they can cause the controller to perform the operation of flowchart 300.

[0078] At box 305, data can be received. In some instances, the data may contain information for updating programs (e.g., operating systems) at a device containing a host system.

[0079] At box 310, an indication of available resources at the memory system can be requested. In some instances, the host system issues a command to request the indication by reading a register at the memory system that stores the size of the available resources. In some instances, the host system issues a command from the memory system requesting the size of the available resources to request the indication.

[0080] At rhombus 315, it can be determined whether the available resources at the memory system are sufficient to support writing the received data to the memory system.

[0081] At box 320, a garbage collection operation may be triggered at the memory system based on or in response to determining that the available resources at the memory system are insufficient for writing data. The garbage collection operation may be triggered based on or in response to a command to perform garbage collection for a specified period. After the duration has elapsed, the memory system may send an indication of the available resources following the garbage collection to the host system. In some instances, the process associated with determining the existence of available resources and triggering garbage collection continues until available resources at the memory system are available to support data storage.

[0082] Alternatively, a garbage collection operation can be triggered based on or in response to a command to perform garbage collection, until sufficient resources are available at the memory system for writing data; for example, the command may include an indication of the data size.

[0083] At box 325, based on or in response to determining that sufficient resources are available for writing data, a message indicating the start of an operation (which may be referred to as a programming operation) for writing data to the memory system may be emitted. This message may be referred to as a "checkpoint start" message. In some instances, the memory system may store information (e.g., L2P and validity tables) based on or in response to receiving a checkpoint start message.

[0084] At box 330, data may be written to the memory system, for example, based on or in response to a checkpoint start message during transmission. Simultaneously with data writing, the memory system may update the L2P and validity tables to reflect how data was written to the memory system.

[0085] At point 335 of the diamond, the success of writing data to the memory system can be determined. In other words, it can be determined whether the data was successfully or unsuccessfully written to the memory system.

[0086] At box 340, a rollback operation can be triggered at the memory system based on or in response to determining that data was not successfully written to the memory system. In some instances, if data is corrupted while being written to the memory system (e.g., during data transmission or storage), the data may not have been written successfully. In these cases, the memory system can, for example, use the stored L2P and validity table to roll back to the state prior to the programming operation.

[0087] In some instances, the memory system can compare the stored L2P and validity tables with the current L2P and validity tables to identify the logical and / or physical locations in the memory system to which data has been written. In some instances, the memory system can unmap logical addresses written during programming operations and mark physical addresses written during programming operations as invalid. After a rollback operation is completed, the memory system can indicate whether the rollback operation was successful or failed. In some instances, the host system retryes writing data to the memory system, for example, if the memory system indicates that the rollback operation failed.

[0088] At box 345, a message indicating the end of writing data to the memory system may be provided. This message may be referred to as a "checkpoint end" message. In some instances, the memory system may discard stored L2P and validity tables based on or in response to receiving a checkpoint end message.

[0089] Figure 4 This describes instances of operations that determine a set of available resources for storing data, based on the examples disclosed herein.

[0090] Flowchart 400 depicts a set of instance operations performed by the host system to support delayed garbage collection until after the programming operation (e.g., over-the-air update) is complete.

[0091] Flowchart 400 depicts a set of instance operations executed by the host system to support garbage collection prior to the execution of programmed operations (e.g., over-the-air updates). Aspects of flowchart 400 may be implemented by a controller and other components. Alternatively, aspects of flowchart 400 may be implemented as instructions stored in memory (e.g., stored in...). Figure 1 (The firmware in the memory coupled to the host system 105). For example, when the instructions are executed by the controller (e.g., at the host system 105), they can cause the controller to perform the operation of flowchart 400.

[0092] At box 405, data can be received at the host system, as shown in [reference]. Figure 3 The operation performed at box 305 is described similarly.

[0093] At box 410, the size of the obsolete cache at the memory system can be requested. The obsolete cache may refer to a set of data at the memory system for which background operations such as garbage collection have been disabled. In some instances, the memory system may mark a set of resources as obsolete. Therefore, the memory system may avoid performing garbage collection on the resource set until it is marked as obsolete. The size of the resource set marked as obsolete may decrease or increase over time.

[0094] At diamond 415, the availability of resources on the memory system for writing data can be determined, for example, based on or in response to comparing the size of the obsolete cache with a threshold. The threshold may indicate the maximum size the obsolete cache can grow to before garbage collection is performed. In some instances, the threshold is based on or in response to, for example, the amount of available resources on the memory system before the obsolete cache is created. For example, the threshold may be set to be less than 10 gigabytes of available resources on the memory system, for example, to at least accommodate writing data to a memory system smaller than 10 gigabytes.

[0095] At box 420, based on or in response to determining that the size of the obsolete cache is greater than a threshold, logical and / or physical addresses associated with the obsolete cache can be removed (e.g., cleared). Therefore, the memory system may be able to perform background operations (e.g., garbage collection) on the blocks of data used to store logical / physical addresses, as well as other blocks in the memory system, to free up additional space, for example. In some instances, the memory system may indicate to the host system that the obsolete cache has been cleared. Therefore, the host system may again compare the size of the obsolete cache with the threshold or proceed directly to the next operation.

[0096] At box 425, based on or in response to determining that the size of the obsolete cache is less than a threshold, a message indicating the start of an operation (which may be referred to as a programming operation) for writing data to the memory system may be emitted, as shown in the reference. Figure 3 The operation performed at box 325 is described similarly. In some instances, the host system may determine that there are sufficient available resources to write data to the storage system based on or in response to the size of the obsolete cache being less than a threshold.

[0097] At box 430, data can be written to the memory system, as referenced in... Figure 3 The operation performed at box 330 is described similarly. At diamond 435, the success of the data write can be confirmed, as shown in [reference]. Figure 3 The operation performed at rhombus 335 is described similarly. At box 440, the memory system can be rolled back to its pre-programming state, as referenced in... Figure 3 The operation performed at box 340 is described similarly. At box 445, a message indicating the end of writing data to the memory system may be provided, as referenced in... Figure 3 The operation performed at box 345 is described similarly.

[0098] Figure 5 This describes instances of a resource graph that are used to determine available resources for storing data, based on examples as disclosed herein.

[0099] Resource diagram 500 depicts how resource allocation may change based on or in response to garbage collection being delayed until after a programmatic operation (e.g., an over-the-air update) is complete, as described herein and in reference. Figure 4 As described. Resource graph 500 may include garbage collection candidate resources 505 on which garbage collection can be performed; stale cache resources 510 on which background operations (such as garbage collection) can be delayed (e.g., disabled); change record resources 515 for storing management information (e.g., the L2P table before update, the current L2P table, the validity table before update, and the current validity table); and available resources 520 (which may also be referred to as free resources). In some instances, resource graph 500 may also include occupancy resources for storing data (e.g., the current version of the operating system or application, operating system data, and application data).

[0100] First resource diagram 500-1 may depict the allocation of resources after a first data set is written to the memory system (e.g., after a first update that performs a larger update). The first data set may be written to a first stale cache resource 510-1. In some instances, the memory system may identify the corresponding resource set as the first stale cache resource 510-1 before or after the first data set is written to the memory system. The memory system may update information stored in a first change record resource 515-1 based on or in response to writing the first data set to the first stale cache resource 510-1.

[0101] In some instances, the memory system may, for example, indicate the size of the first obsolete cache resource 510-1 to the host system before writing the data set and based on or in response to a request for the size of the obsolete cache received from the host system. The host system may write the first data set to the first obsolete cache resource 510-1 based on or in response to determining that the size of the obsolete cache is less than a threshold. In some instances, the threshold may be based on or in response to the size of the first available resource 520-1; for example, the threshold may be equal to or less than (by offset) the size of the first available resource 520-1.

[0102] The second resource diagram 500-2 can depict the allocation of resources after the second data set is written to the memory system (e.g., after a second update that performs a larger update). The second data set can be written to a second obsolete cache resource 510-2, wherein the second obsolete cache resource 510-2 may contain resources of the first obsolete cache resource 510-1. The memory system can update the information stored in the second change record resource 515-2 based on or in response to the first data set being written to the first obsolete cache resource 510-1. As described similarly above, the memory system can indicate the size of the second obsolete cache resource 510-2 to the host system before the host system writes the second data set to the memory system.

[0103] The third resource diagram 500-3 depicts the allocation of resources after the third data set is written to the memory system (e.g., after a third update of a larger update). In some instances, the stale cache grows to a size exceeding a threshold; for example, the size of the third stale cache resource may exceed a threshold after the third data set is written to the memory system. In these cases, the host system may determine that there is insufficient space for the memory system to complete the larger update and may trigger the memory system to clear the stale cache, thus the larger update may fail. Clearing the stale cache may involve marking the third stale cache resource 510-3 as a garbage collection candidate resource and performing garbage collection on the current garbage collection candidate resource. In some instances, an increased amount of resources are available after clearing the stale cache (e.g., relative to the first update of the larger update being written to the memory system), and the host system may attempt to write the full update to the memory system again. In some instances, the host system may use the L2P and validity table stored before writing the first update to write the first update of the larger update to the memory system.

[0104] Figure 6 A block diagram 600 illustrates a memory system 620 that determines available resources for storing data based on examples disclosed herein. The memory system 620 may be as described in the references... Figures 1 to 5 Examples of aspects of the described memory system. Memory system 620 or its various components may be examples of constructs for performing the various aspects of determining available resources for storing data as described herein. For example, memory system 620 may include data component 625, memory management component 630, write component 635, garbage collection component 640, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0105] Data component 625 may be configured or otherwise supported to include means for receiving an instruction to write data to the memory system. Memory management component 630 may be configured or otherwise supported to remove invalid data from the memory system, at least in part, based on an instruction to write data, until the size of the available resources in the memory system is greater than or equal to the size of the data. In some instances, memory management component 630 may be configured or otherwise supported to delay garbage collection operations in the memory system, at least in part, based on the size of the available resources being greater than or equal to the size of the data after the removal of invalid data. Write component 635 may be configured or otherwise supported to write data to the available resources, at least in part, based on a delayed garbage collection operation.

[0106] In some instances, the memory management component 630 may be configured or otherwise supported to include a component for issuing an indication of the size of the available resources at a certain point in time before the removal of invalid data in response to receiving an indication that data will be written.

[0107] In some instances, the memory management component 630 may be configured or otherwise supported to receive a command to remove invalid data based at least in part on the indicated size of the available resources being smaller than the size of the data. In some instances, the garbage collection component 640 may be configured or otherwise supported to perform a garbage collection operation based at least in part on a command, wherein at least a portion of invalid data is removed based at least in part on the performance of the garbage collection operation. In some instances, the memory management component 630 may be configured or otherwise supported to emit a second indication of the size of the available resources based at least in part on the completion of a garbage collection operation, prior to a delayed garbage collection operation.

[0108] In some instances, the memory management component 630 may be configured or otherwise supported to receive a plurality of commands for removing invalid data, at least in part based on the indicated size of the available resources being smaller than the size of the data. In some instances, the garbage collection component 640 may be configured or otherwise supported to perform a plurality of garbage collection operations, at least in part based on a plurality of commands, wherein invalid data is removed at least in part based on the performance of the plurality of garbage collection operations. In some instances, the memory management component 630 may be configured or otherwise supported to emit a obtained indication of the available resource size before a delayed garbage collection operation and after the corresponding completion of each of the plurality of garbage collection operations.

[0109] In some instances, the last obtained indication of the size of the available resources is emitted, at least in part, based on the fact that the size of the available resources is greater than or equal to the size of the data.

[0110] In some instances, the memory management component 630 may be configured or otherwise supported to include means for receiving an indication of the size of data, at least in part, based on an indicated size of available resources. In some instances, the garbage collection component 640 may be configured or otherwise supported to perform multiple garbage collection operations, at least in part, based on the size of the data, until the size of available resources is greater than or equal to the size of the data, wherein invalid data is removed at least in part based on the performance of the multiple garbage collection operations. In some instances, the memory management component 630 may be configured or otherwise supported to include means for transmitting an indication that the size of available resources is greater than or equal to the size of the data, at least in part based on the performance of multiple garbage collection operations, before delaying garbage collection operations.

[0111] In some instances, the memory management component 630 may be configured or otherwise supported for determining whether the size of the available resource is greater than or equal to the size of the data, based at least in part on the last garbage collection in a plurality of garbage collection operations, wherein an indication that the size of the available resource is greater than or equal to the size of the data is emitted based at least in part on the fact that the size of the available resource is greater than or equal to the size of the data.

[0112] In some instances, the memory management component 630 may be configured or otherwise supported to provide a means for issuing an indication that the size of available resources is greater than or equal to the size of the data, based at least in part on the removal of invalid data.

[0113] In some instances, data component 625 may be configured or otherwise support a component for receiving an indication of the start of a write operation that is at least partially based on an indicated size of available resources that is greater than or equal to the size of the data. In some instances, data component 625 may be configured or otherwise support a component for receiving data that is at least partially based on receiving an indication of the start of a write operation, wherein writing data to available resources is at least partially based on receiving data.

[0114] In some instances, the write component 635 may be configured or otherwise supported to emit an indication that data has been successfully written to an available resource, at least in part based on the successful writing of data to the available resource. In some instances, the data component 625 may be configured or otherwise supported to receive an indication that the write operation has ended, at least in part based on the successful writing of data. In some instances, the garbage collection component 640 may be configured or otherwise supported to perform a set of delayed garbage collection operations, at least in part based on the end of the write operation.

[0115] In some instances, the memory management component 630 may be configured or otherwise support components for storing one or both of a first mapping or a second mapping based at least in part on an indication of the start of a write operation, the first mapping including a first association between a logical address and a physical address at the memory system, and the second mapping indicating the validity of data stored at a physical address at the memory system.

[0116] In some instances, the write component 635 may be configured or otherwise supported to include means for issuing an indication of a write operation failure based at least in part on writing data to an available resource. In some instances, the memory management component 630 may be configured or otherwise supported to replace a third mapping with a first mapping and a fourth mapping with a second mapping based at least in part on a write operation failure, the third mapping comprising a third association between a logical address and a physical address at the memory system, the fourth mapping indicating the validity of data stored at a physical address at the memory system.

[0117] In some instances, the memory management component 630 may be configured or otherwise support a component for transmitting an indication that the third and fourth mappings have been successfully replaced by the first and second mappings.

[0118] In some instances, the data includes over-the-air updates for the memory system.

[0119] In some instances, the memory management component 630 may be configured to, or otherwise support means for delaying garbage collection operations on a set of resources at the memory system. In some instances, the memory management component 630 may be configured to, or otherwise support means for receiving a request indicating whether the memory system contains available resources for storing data. In some instances, the memory management component 630 may be configured to, or otherwise support means for issuing an indication of whether the memory system contains available resources in response to the request, at least in part based on a comparison of the size of the resource set with a threshold size. In some instances, the data component 625 may be configured to, or otherwise support means for receiving data at least in part based on the indicated size of the resource set being less than a threshold size. In some instances, the write component 635 may be configured to, or otherwise support means for writing data to the resource set.

[0120] In some instances, the memory management component 630 may be configured or otherwise support means for delaying garbage collection operations for the second resource set. In some instances, the memory management component 630 may be configured or otherwise support means for receiving a second request for a second indication of whether the memory system contains available resources for storing the second data. In some instances, the memory management component 630 may be configured or otherwise support means for transmitting a second indication of whether the memory system contains available resources in response to the second request, at least in part based on a second comparison of a threshold size with the combined size of the resource set and the second resource set.

[0121] In some instances, the memory management component 630 may be configured or otherwise supported to receive a command to enable garbage collection operations on the resource set and the second resource set, at least in part based on an indicated combined size greater than a threshold size. In some instances, the garbage collection component 640 may be configured or otherwise supported to perform one or more garbage collection operations on the resource set and the second resource set, at least in part based on a command to enable garbage collection operations.

[0122] In some instances, the memory management component 630 may be configured or otherwise supported to receive an indication of the start of a write operation for data, at least in part based on the indicated size of the resource set being less than a threshold size. In some instances, the data component 625 may be configured or otherwise supported to receive data, at least in part based on the receipt of an indication of the start of a write operation, wherein writing data to the resource set is at least in part based on the receipt of data.

[0123] In some instances, the write component 635 may be configured or otherwise supported to emit an indication that data has been successfully written to the resource set, at least in part based on the fact that data has been written to the resource set. In some instances, the data component 625 may be configured or otherwise supported to receive an indication that the write operation has ended, at least in part based on the fact that the data has been successfully written. In some instances, the garbage collection component 640 may be configured or otherwise supported to perform a delayed set of garbage collection operations on the resource set, at least in part based on the indication that the write operation has ended.

[0124] In some instances, the memory management component 630 may be configured or otherwise support components for storing one or both of a first mapping or a second mapping based at least in part on an indication of the start of a write operation, the first mapping including a first association between a logical address and a physical address at the memory system, and the second mapping indicating the validity of data stored at a physical address at the memory system.

[0125] In some instances, the write component 635 may be configured or otherwise supported to include means for indicating, at least in part, the failure of a write operation that emits data based on the writing of data to a resource set. In some instances, the memory management component 630 may be configured or otherwise supported to replace a third mapping with a first mapping and a fourth mapping with a second mapping based at least in part on the failure of a write operation, wherein the third mapping contains a third association between a logical address and a physical address at the memory system, and the fourth mapping indicates the validity of data stored at a physical address at the memory system.

[0126] In some instances, the memory management component 630 may be configured or otherwise support a component for transmitting an indication that the third and fourth mappings have been successfully replaced by the first and second mappings.

[0127] In some instances, the threshold size is at least in part based on the amount of available resources at the memory system.

[0128] Figure 7 A block diagram 700 illustrates a host system 720 that determines available resources for storing data based on the examples disclosed herein. The host system 720 may be as described in the references... Figures 1 to 5 Examples of aspects of the described host system. Host system 720 or its various components may be examples of constructs for performing the various aspects of determining available resources for storing data as described herein. For example, host system 720 may include storage component 725, memory management component 730, programming component 735, recovery component 740, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0129] Storage component 725 may be configured or otherwise supported to provide means for issuing a request for the size of available resources at the memory system, at least in part based on the identification that data will be written to the memory system. In some instances, storage component 725 may be configured or otherwise supported to provide means for receiving an indication of the size of available resources in response to the request. In some instances, storage component 725 may be configured or otherwise supported to provide means for determining whether the size of available resources is greater than or equal to the size of the data. Memory management component 730 may be configured or otherwise supported to provide means for issuing one or more commands to guide the memory system to remove invalid data, at least in part based on the size of available resources being less than the size of the data. In some instances, storage component 725 may be configured or otherwise supported to provide means for receiving a second indication of the size of available resources in response to the one or more commands. Programming component 735 may be configured or otherwise supported to provide means for issuing data to the memory system, at least in part based on the size of available resources indicated in the second indication of the size of available resources being greater than or equal to the size of the data.

[0130] In some instances, programming component 735 may be configured or otherwise support a component for initiating an instruction to transmit a write operation of data based at least in part on the fact that the size of the available resource indicated in the second instruction is greater than or equal to the size of the data.

[0131] In some instances, programming component 735 may be configured or otherwise support a component for receiving an indication of successful data writing, at least in part based on transmitted data. In some instances, programming component 735 may be configured or otherwise support a component for indicating the end of a write operation that transmits data, at least in part based on successful data writing.

[0132] In some instances, programming component 735 may be configured or otherwise supported to receive an indication that data has been improperly written, at least in part based on transmitted data. In some instances, recovery component 740 may be configured or otherwise supported to transmit a second command, at least in part based on an indication that data has been improperly written, to restore a first mapping to a first state or a second mapping to a second state, wherein the first mapping contains an association between a logical address and a physical address at a memory system, and the second mapping indicates the validity of data stored at a physical address at a memory system, and the first state and the second state existed prior to the transmission of data.

[0133] In some instances, programming component 735 may be configured or otherwise supported to receive an indication, in response to a second command, that the first mapping has failed to be restored to a first state or that the second mapping has failed to be restored to a second state, or both. In some instances, recovery component 740 may be configured or otherwise supported to issue a demapping command, in response to a failure-to-restore indication, invalidating data stored in a set of logical block addresses containing written data. In some instances, recovery component 740 may be configured or otherwise supported to issue data to the memory system, at least in part based on the completion of the demapping command.

[0134] In some instances, storage component 725 may be configured or otherwise support a component for determining an upper limit of the size of data, wherein determining whether the size of the available resource is greater than or equal to the size of the data includes comparing the size of the available resource with an upper limit of the size of the data, at least in part based on the fact that the size of the data is unknown.

[0135] In some instances, storage component 725 may be configured or otherwise supported to include means for identifying a set of resources at the memory system for its delayed garbage collection operations, at least in part, based on data to be written at the memory system. In some instances, storage component 725 may be configured or otherwise supported to include means for issuing a request indicating whether the memory system contains available resources for storing data. In some instances, storage component 725 may be configured or otherwise supported to include means for receiving an indication of whether the memory system contains available resources in response to said request. In some instances, programming component 735 may be configured or otherwise supported to include means for issuing data, at least in part, based on the memory system containing available resources for storing data.

[0136] In some instances, the memory management component 730 may be configured or otherwise supported to include means for issuing commands that delay garbage collection operations on a second resource set, at least in part based on the intention to write second data to the memory system. In some instances, the storage component 725 may be configured or otherwise supported to include means for issuing a second request for a second indication of whether the memory system contains available resources for storing the second data. In some instances, the storage component 725 may be configured or otherwise supported to include means for receiving a second indication of whether the memory system contains available resources in response to the second request, the second indication being at least in part based on a threshold size and the combined size of the resource set and the second resource set.

[0137] In some instances, the memory management component 730 may be configured or otherwise support a component for issuing a second command to enable garbage collection operations on the resource set and the second resource set, based at least in part on the indicated combined size being greater than a threshold size.

[0138] Figure 8 The flowchart illustrates a method 800 for determining available resources for storing data based on examples disclosed herein. The operation of method 800 may be implemented by a memory system or its components as described herein. For example, the operation of method 800 may be implemented by... (See reference...) Figures 1 to 6 The described memory system performs the functions described herein. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0139] At 805, the method may include receiving an instruction to write data to the memory system. The operation of 805 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 805 may be as described in references... Figure 6 The described data component 625 is executed.

[0140] At 810, the method may include removing invalid data at the memory system based at least in part on an instruction to write data, until the size of the available resources at the memory system is greater than or equal to the size of the data. The operation of 810 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 810 may be as described in references... Figure 6 The memory management component 630 described is executed.

[0141] At 815, the method may include delaying garbage collection operations at the memory system, at least in part, based on the premise that the size of available resources after the removal of invalid data is greater than or equal to the size of the data. The operation at 815 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 815 may be as described in references... Figure 6 The memory management component 630 described is executed.

[0142] At 820, the method may include writing data to an available resource, at least in part based on a delayed garbage collection operation. The operation at 820 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 820 may be as described in the references... Figure 6 The described writing component 635 is executed.

[0143] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: receiving an instruction to write data to a memory system; removing invalid data from the memory system, at least in part based on the instruction to write data, until the size of available resources in the memory system is greater than or equal to the size of the data; delaying a garbage collection operation in the memory system, at least in part based on the size of available resources being greater than or equal to the size of the data after the removal of invalid data; and writing data to available resources, at least in part based on the delayed garbage collection operation.

[0144] Some examples of the methods 800 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting an indication of the size of the available resources at a certain time before the removal of invalid data in response to receiving an indication that data may be written.

[0145] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving a command to remove invalid data based at least in part on the indicated size of the available resources being less than the size of the data; performing a garbage collection operation based at least in part on the command, wherein at least a portion of the invalid data may be removed based at least in part on the performance of the garbage collection operation; and transmitting a second indication of the size of the available resources based at least in part on the completion of the garbage collection operation and prior to delaying the garbage collection operation.

[0146] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving multiple commands to remove invalid data based at least in part on the indicated size of the available resources being less than the size of the data; performing multiple garbage collection operations based at least in part on the multiple commands, wherein invalid data may be removed based at least in part on the execution of the multiple garbage collection operations; and transmitting an indication of the available resource size before delaying the garbage collection operations and after the corresponding completion of each of the multiple garbage collection operations.

[0147] In some instances of the method 800 and device described herein, the last obtained indication of the size of the available resources may be transmitted, at least in part, based on the fact that the size of the available resources is greater than or equal to the size of the data.

[0148] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving an indication of the size of data based at least in part on the indicated size of the available resources; performing multiple garbage collection operations based at least in part on the size of the data until the size of the available resources is greater than or equal to the size of the data, wherein invalid data may be removed based at least in part on the performance of the multiple garbage collection operations; and transmitting an indication that the size of the available resources may be greater than or equal to the size of the data based at least in part on the performance of the multiple garbage collection operations and before delaying the garbage collection operations.

[0149] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: determining, at least in part, whether the size of an available resource is greater than or equal to the size of data based on the last garbage collection of a plurality of garbage collection operations, wherein an indication that the size of an available resource is greater than or equal to the size of data may be emitted, at least in part, based on the size of an available resource being greater than or equal to the size of data.

[0150] Some examples of the methods 800 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting an available resource of a size greater than or equal to the size of the data, at least in part based on the removal of invalid data.

[0151] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving an indication to begin a write operation of data based at least in part on an indicated size of an available resource being greater than or equal to a data size; and receiving data based at least in part on the indication to begin the write operation, wherein writing data to an available resource may be based at least in part on receiving said data.

[0152] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following operations: transmitting an indication that data has been successfully written to an available resource, at least in part based on writing data to an available resource; receiving an indication that the write operation has ended, at least in part based on the successful writing of data; and performing a set of delayed garbage collection operations, at least in part based on the end of the write operation.

[0153] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for storing components of one or both of a first mapping or a second mapping, at least in part based on receiving an indication of the start of a write operation, wherein the first mapping includes a first association between a logical address and a physical address at a memory system, and the second mapping indicates the validity of data stored at a physical address at a memory system.

[0154] Some examples of the methods 800 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: issuing an indication of failure of a write operation based at least in part on writing data to an available resource; and replacing a third mapping with a first mapping and a fourth mapping with a second mapping based at least in part on the failure of the write operation, the third mapping containing a third association between a logical address and a physical address at a memory system, the fourth mapping indicating the validity of data stored at a physical address at a memory system.

[0155] Some examples of the methods 800 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting indications that the third and fourth mappings may have been successfully replaced by the first and second mappings.

[0156] In some instances of the method 800 and device described herein, the data includes over-the-air updates for the memory system.

[0157] Figure 9 The flowchart illustrates a method 900 for determining available resources for storing data based on examples disclosed herein. The operation of method 900 can be implemented by a host system or its components as described herein. For example, the operation of method 900 can be implemented by, as referenced... Figures 1 to 5 The host system described in section 7 performs the functions described herein. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0158] At 905, the method may include issuing a request for the size of available resources at the memory system, at least in part based on identifying that data will be written to the memory system. The operation of 905 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 905 may be as described in references... Figure 7 The described storage component 725 is executed.

[0159] At 910, the method may include receiving an indication of the size of available resources in response to the request. The operation of 910 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 910 may be as described in the references... Figure 7 The described storage component 725 is executed.

[0160] At 915, the method may include determining whether the size of the available resource is greater than or equal to the size of the data. The operation at 915 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 915 may be as described in the references... Figure 7 The described storage component 725 is executed.

[0161] At 920, the method may include issuing one or more commands to remove invalid data from the boot memory system, at least in part based on the fact that the size of the available resources is less than the size of the data. The operation of 920 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 920 may be as described in references... Figure 7 The memory management component 730 described is executed.

[0162] At 925, the method may include a second indication of the size of the available resources in response to the one or more commands. The operation of 925 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 925 may be as described in references... Figure 7 The described storage component 725 is executed.

[0163] At 930, the method may include transmitting the data to the memory system at least in part based on the second indication of the size of the available resources being greater than or equal to the size of the data. Operation 930 may be performed according to examples disclosed herein. In some instances, aspects of operation of 930 may be as described in references... Figure 7 The described programming component 735 is executed.

[0164] In some instances, the device described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: issuing a request for the size of available resources at a memory system based at least in part on recognizing that data will be written to the memory system; receiving an indication of the size of the available resources in response to the request; determining whether the size of the available resources is greater than or equal to the size of the data; issuing one or more commands to instruct the memory system to remove invalid data based at least in part on the size of the available resources being less than the size of the data; receiving a second indication of the size of the available resources in response to the one or more commands; and issuing data to the memory system based at least in part on the size of the available resources indicated in the second indication of the size of the available resources being greater than or equal to the size of the data.

[0165] Some examples of the method 900 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for issuing an indication of the start of a write operation for data based at least in part on the fact that the size of the available resources indicated in the second indication is greater than or equal to the size of the data.

[0166] Some examples of the method 900 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: an indication that data has been successfully written, at least in part based on transmitted data; and an indication that the write operation of transmitted data has ended, at least in part based on the successful writing of data.

[0167] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving an indication that data has been improperly written, at least in part based on transmitted data; and transmitting a second command, at least in part based on the indication that data has been improperly written, to restore a first mapping to a first state or a second mapping to a second state, wherein the first mapping contains an association between a logical address and a physical address at a memory system, and the second mapping indicates the validity of data stored at a physical address at a memory system, and the first state and the second state existed prior to the transmission of data.

[0168] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving an indication, in response to a second command, that a first mapping has failed to be restored to a first state or a second mapping has failed to be restored to a second state, or both; issuing a demapping command, in response to the failure to restore, invalidating data stored in a set of logical block addresses containing written data; and issuing data to a memory system, at least in part based on the completion of the demapping command.

[0169] Some instances of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: determining an upper limit on the size of data, wherein determining whether the size of an available resource is greater than or equal to the size of the data includes comparing the size of the available resource with the upper limit on the size of the data, at least in part based on the fact that the size of the data is unknown.

[0170] Figure 10 The flowchart illustrates a method 1000 for determining available resources for storing data based on examples disclosed herein. The operation of method 1000 can be implemented by a memory system or its components as described herein. For example, the operation of method 1000 can be implemented by reference to... Figures 1 to 6 The described memory system performs the functions described herein. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0171] At 1005, the method may include delaying garbage collection operations on the resource set at the memory system. The operation at 1005 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 1005 may be as described in references... Figure 6 The memory management component 630 described is executed.

[0172] At 1010, the method may include receiving a request indicating whether the memory system contains available resources for storing data. The operation of 1010 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1010 may be as described in references... Figure 6 The memory management component 630 described is executed.

[0173] At 1015, the method may include issuing an indication, at least in part based on a comparison of the size of the resource set with a threshold size, in response to the request, whether the memory system contains available resources. The operation of 1015 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1015 may be as described in references... Figure 6The memory management component 630 described is executed.

[0174] At 1020, the method may include receiving data at least in part based on the fact that the indicated size of the resource set is less than a threshold size. The operation of 1020 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1020 may be as described in the references... Figure 6 The described data component 625 is executed.

[0175] At 1025, the method may include writing data to the resource collection. The operation at 1025 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 1025 may be as described in the references... Figure 6 The described writing component 635 is executed.

[0176] In some instances, the device described herein may perform one or more methods, such as method 1000. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: delaying a garbage collection operation on a set of resources at a memory system; receiving a request indicating whether the memory system contains available resources for storing data; in response to the request, transmitting the indication whether the memory system contains available resources based at least in part on a comparison of the size of the resource set to a threshold size; receiving the data based at least in part on the fact that the size of the resource set is less than the threshold size; and writing the data to the resource set.

[0177] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: delaying a garbage collection operation for a second resource set; receiving a second request for a second indication of whether the memory system contains available resources for storing second data; and, in response to the second request, transmitting a second indication of whether the memory system contains available resources based at least in part on a second comparison of a threshold size with the combined size of the resource set and the second resource set.

[0178] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving a command to enable garbage collection operations on the resource set and the second resource set, at least in part based on an indicated combination size greater than a threshold size; and performing one or more garbage collection operations on the resource set and the second resource set, at least in part based on the command to enable garbage collection operations.

[0179] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving an indication to begin a write operation for data based at least in part on the indicated size of the resource set being less than a threshold size; and receiving data based at least in part on the receipt of the indication to begin the write operation, wherein writing data to the resource set may be based at least in part on the receipt of the data.

[0180] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following operations: transmitting an indication that data has been successfully written to a resource set, at least in part based on writing data to the resource set; receiving an indication that the write operation has ended, at least in part based on the successful writing of data; and performing a set of delayed garbage collection operations on the resource set, at least in part based on the end of the write operation.

[0181] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for storing, at least in part, one or both of a first mapping or a second mapping based on receiving an indication of the start of a write operation, wherein the first mapping includes a first association between a logical address and a physical address at a memory system, and the second mapping indicates the validity of data stored at a physical address at a memory system.

[0182] Some instances of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: issuing an indication of failure of a write operation based at least in part on writing data to a resource set; and replacing a third mapping with a first mapping and a fourth mapping with a second mapping based at least in part on the failure of the write operation, the third mapping containing a third association between a logical address and a physical address at a memory system, the fourth mapping indicating the validity of data stored at a physical address at a memory system.

[0183] Some instances of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting indications that the third and fourth mappings may have been successfully replaced by the first and second mappings.

[0184] In some instances of the method 1000 and device described herein, the threshold size may be based at least in part on the size of the available resources at the memory system.

[0185] Figure 11The flowchart illustrates a method 1100 for determining available resources for storing data based on examples disclosed herein. The operation of method 1100 can be implemented by a host system or its components as described herein. For example, the operation of method 1100 can be implemented by, as referenced... Figures 1 to 5 The host system described in section 7 performs the functions described herein. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0186] At 1105, the method may include identifying, at least in part, a set of resources at the memory system for which delayed garbage collection operations will be performed, based on data to be written to the memory system. The operation at 1105 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 1105 may be as described in references... Figure 7 The described storage component 725 is executed.

[0187] At 1110, the method may include issuing a request indicating whether the memory system contains available resources for storing data. The operation of 1110 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1110 may be as described in references... Figure 7 The described storage component 725 is executed.

[0188] At 1115, the method may include receiving an indication of whether the memory system contains available resources in response to the request. The operation of 1115 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1115 may be as described in references... Figure 7 The described storage component 725 is executed.

[0189] At 1120, the method may include transmitting data based at least in part on the memory system having available resources for storing data. The operation of 1120 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 1120 may be as described in references... Figure 7 The described programming component 735 is executed.

[0190] In some instances, the device described herein may perform one or more methods, such as method 1100. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: identifying a set of resources at a memory system for its delayed garbage collection operation based at least in part on the fact that data will be written at the memory system; issuing a request indicating whether the memory system contains available resources for storing data; receiving an indication of whether the memory system contains available resources in response to the request; and issuing data based at least in part on the fact that the memory system contains available resources for storing data.

[0191] Some examples of the method 1100 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: issuing a command to delay a garbage collection operation on a second resource set based at least in part on writing second data to a memory system; issuing a second request for a second indication of whether the memory system contains available resources for storing the second data; and receiving, in response to the second request, a second indication of whether the memory system contains available resources, the second indication being at least in part based on a threshold size and the combined size of the resource set and the second resource set.

[0192] Some instances of the method 1100 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for issuing a second command to enable garbage collection operations on the resource set and the second resource set, based at least in part on the indicated combination size being greater than a threshold size.

[0193] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0194] Describe another device. The device may include: a memory device; and a controller coupled to the memory device and configured such that the device: receives an instruction to write data to a memory system containing the memory device; removes invalid data from the memory system at least in part based on the instruction to write the data, until the size of available resources in the memory system is greater than or equal to the size of the data; delays a garbage collection operation in the memory system at least in part based on the fact that the size of the available resources is greater than or equal to the size of the data after the removal of the invalid data; and writes the data to the available resources at least in part based on the delay in the garbage collection operation.

[0195] In some instances, the controller may be further configured such that the device, in response to receiving the indication that data may be written, transmits an indication of the size of the available resources at a certain time before the invalid data is removed.

[0196] In some instances, the controller may be further configured such that the device: receives a command to remove the invalid data based at least in part on the indicated size of the available resource being less than the size of the data; performs a garbage collection operation based at least in part on the command, wherein at least a portion of the invalid data may be removed based at least in part on the execution of the garbage collection operation; and transmits a second indication of the size of the available resource based at least in part on the completion of the garbage collection operation and before delaying the garbage collection operation.

[0197] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, wherein the bus may have various bit widths.

[0198] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0199] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0200] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0201] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0202] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least partially as a result of the occurrence of the preceding condition or action (whether directly after or after one or more other intermediate conditions or actions following the first condition or action).

[0203] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0204] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "off" or "deactivated."

[0205] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0206] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral distinguishing them from each other. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0207] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0208] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0209] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0210] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, these coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0211] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: At least one memory device; as well as At least one controller coupled to and configured to cause the device to: Receive an instruction to write a set of data to a memory system including the at least one memory device; Invalid data at the memory system is removed, at least in part, based on the instruction to write to the data set, until the size of the available resources at the memory system is greater than or equal to the size of the data set; The garbage collection operation at the memory system is delayed at least in part because the size of the available resources after the removal of the invalid data is greater than or equal to the size of the data set; Based at least in part on the removal of the invalid data, an indication is emitted that the size of the available resources is greater than or equal to the size of the data set; The indication to begin a write operation on the data set is received, at least in part, based on the fact that the indicated size of the available resources is greater than or equal to the size of the data set. The data set is received at least in part based on the indication that the write operation has begun; as well as The data set is written to the available resource, at least in part based on receiving the data set and at least in part based on delaying the garbage collection operation.

2. The device of claim 1, wherein the at least one controller is further configured to cause the device to: In response to receiving the instruction to write to the data set, an indication of the size of the available resources is emitted at a certain time before the removal of the invalid data.

3. The device of claim 2, wherein the at least one controller is further configured to cause the device to: The command to remove the invalid data is received at least in part based on the fact that the indicated size of the available resource is smaller than the size of the data set; The garbage collection operation is performed at least in part based on the command, wherein at least a portion of the invalid data is removed based at least in part on the execution of the garbage collection operation; as well as A second indication of the size of the available resources is emitted, at least in part based on the completion of the garbage collection operation and before the garbage collection operation is delayed.

4. The device of claim 2, wherein the at least one controller is further configured to cause the device to: Multiple commands to remove invalid data are received, at least in part, based on the fact that the indicated size of the available resources is less than the size of the data set; Multiple garbage collection operations are performed at least in part based on the multiple commands, wherein invalid data is removed at least in part based on the execution of the multiple garbage collection operations; as well as Before delaying the garbage collection operation and after the corresponding completion of each of the plurality of garbage collection operations, an indication of the size of the available resources is transmitted.

5. The device of claim 4, wherein the last obtained indication of the size of the available resources is transmitted at least in part based on the fact that the size of the available resources is greater than or equal to the size of the data set.

6. The device of claim 2, wherein the at least one controller is further configured to cause the device to: The indication of the size of the data set is received at least in part based on the indicated size of the available resources; Multiple garbage collection operations are performed, at least in part based on the size of the data set, until the size of the available resources is greater than or equal to the size of the data set, wherein invalid data is removed, at least in part based on the performance of the multiple garbage collection operations; as well as At least in part, based on performing the plurality of garbage collection operations and, before delaying the garbage collection operations, issuing an indication that the size of the available resources is greater than or equal to the size of the data set.

7. The device of claim 6, wherein the at least one controller is further configured to cause the device to: The size of the available resource is determined to be greater than or equal to the size of the data set, at least in part based on the execution of the last garbage collection operation among the plurality of garbage collection operations, wherein the indication that the size of the available resource is greater than or equal to the size of the data set is emitted at least in part based on the fact that the size of the available resource is greater than or equal to the size of the data set.

8. The device of claim 1, wherein the at least one controller is further configured to cause the device to: At least in part, based on writing the data set to the available resource, an indication is emitted that the data set has been successfully written to the available resource; At least in part based on the successful writing of the data set, an indication of the end of the write operation is received; as well as A set of delayed garbage collection operations are performed, at least in part, based on the completion of the write operation.

9. The device of claim 1, wherein the at least one controller is further configured to cause the device to: Based at least in part on the indication of the start of the write operation, one or both of a first mapping or a second mapping are stored, the first mapping including a first association between a logical address and a physical address at the memory system, and the second mapping indicating the validity of data stored at a physical address at the memory system.

10. The device of claim 9, wherein the at least one controller is further configured to cause the device to: At least in part, based on writing the data set to the available resource, an indication of failure of the write operation is emitted; and Based at least in part on the failure of the write operation, the third mapping is replaced with the first mapping and the fourth mapping is replaced with the second mapping, the third mapping including a third association between a logical address and a physical address at the memory system, and the fourth mapping indicating the validity of the data stored at the physical address at the memory system.

11. The device of claim 10, wherein the at least one controller is further configured to cause the device to: The system transmits an indication that the third and fourth mappings have been successfully replaced by the first and second mappings.

12. The device of claim 1, wherein the data set includes over-the-air updates for the memory system.

13. An apparatus comprising: At least one controller configured to cause the device to: A request for the size of available resources at the memory system is issued, at least in part, based on the identification of the set of data to be written at the memory system; In response to the request, receive an indication of the size of the available resources; Determine whether the size of the available resources is greater than or equal to the size of the data set; One or more commands are issued to guide the memory system to remove invalid data, at least in part based on the fact that the size of the available resources is smaller than the size of the data set; In response to the one or more commands, a second indication of the size of the available resources is received; An indication to initiate a write operation on the data set is issued, at least in part based on the second indication indicating that the size of the available resources is greater than or equal to the size of the data set; as well as The data set is emitted to the memory system at least in part based on the second indication that the size of the available resources is greater than or equal to the size of the data set, and at least in part based on the indication that the write operation begins.

14. An apparatus comprising: At least one controller configured to cause the device to: A request for the size of available resources at the memory system is issued, at least in part, based on the identification of the set of data to be written at the memory system; In response to the request, receive an indication of the size of the available resources; Determine whether the size of the available resources is greater than or equal to the size of the data set; One or more commands are issued to guide the memory system to remove invalid data, at least in part based on the fact that the size of the available resources is smaller than the size of the data set; In response to the one or more commands, a second indication of the size of the available resources is received; The data set is transmitted to the memory system at least in part based on the second indication that the size of the available resources is greater than or equal to the size of the data set; At least in part, based on transmitting the data set, receiving an indication that the data set has been successfully written; as well as At least in part based on the fact that the data set has been successfully written, an indication is issued indicating the end of the write operation for the data set.

15. An apparatus comprising: At least one controller configured to cause the device to: A request for the size of available resources at the memory system is issued, at least in part, based on the identification of the set of data to be written at the memory system; In response to the request, receive an indication of the size of the available resources; Determine whether the size of the available resources is greater than or equal to the size of the data set; One or more commands are issued to guide the memory system to remove invalid data, at least in part based on the fact that the size of the available resources is smaller than the size of the data set; In response to the one or more commands, a second indication of the size of the available resources is received; The data set is transmitted to the memory system at least in part based on the second indication that the size of the available resources is greater than or equal to the size of the data set; At least in part, based on transmitting the data set, receiving an indication that the data set has been inappropriately written; as well as Based at least in part on the indication that the data set has been improperly written, a second command is issued to perform one or both of restoring a first mapping to a first state or restoring a second mapping to a second state, the first mapping containing an association between logical and physical addresses at the memory system, and the second mapping indicating the validity of data stored at physical addresses at the memory system, the first state and the second state existing prior to the issuance of the data set.

16. The device of claim 15, wherein the at least one controller is further configured to cause the device to: In response to the second command, an indication is received that one or both of restoring the first mapping to the first state or restoring the second mapping to the second state have failed to be executed; In response to the instruction that recovery is not possible, issue a demapping command that invalidates the data stored in the set of logical block addresses containing the data set; and The data set is emitted to the memory system at least in part based on the completion of the unmapping command.

17. An apparatus comprising: At least one controller configured to cause the device to: A request for the size of available resources at the memory system is issued, at least in part, based on the identification of the set of data to be written at the memory system; In response to the request, receive an indication of the size of the available resources; The upper limit of the size of the data set is determined at least in part based on the fact that the size of the data set is unknown; Whether the size of the available resource is greater than or equal to the size of the data set is determined at least in part based on comparing the size of the available resource with the upper limit of the size of the data set; One or more commands are issued to guide the memory system to remove invalid data, at least in part based on the fact that the size of the available resources is smaller than the size of the data set; In response to the one or more commands, receive a second indication of the size of the available resources; and The data set is transmitted to the memory system at least in part based on the second indication that the size of the available resources is greater than or equal to the size of the data set.

18. An apparatus comprising: At least one memory device; as well as At least one controller coupled to and configured to cause the device to: While enabling a second garbage collection operation on the second resource set at the memory system, the first garbage collection operation on the first resource set at the memory system is delayed. Receive a request indicating whether the memory system contains available resources for storing a set of data; In response to the request, at least in part based on a comparison of the size of the first resource set with a threshold size, an indication is transmitted as to whether the memory system contains the available resources for storing the data set; The data set is received at least in part based on the fact that the size of the first resource set is less than the threshold size; The instruction to begin a write operation on the data set is received at least in part based on the fact that the size of the first resource set is less than the threshold size; The data set is received at least in part based on the indication that the write operation has begun; as well as The data set is written into the first resource set, at least in part, based on the receipt of the data set.

19. The device of claim 18, wherein the at least one controller is further configured to cause the device to: Delay the second garbage collection operation on the second resource set; Receive a second request for a second indication of whether the memory system includes available resources for storing a second set of data; and In response to the second request, a second indication is issued regarding whether the memory system includes available resources for storing the second data set, based at least in part on a second comparison of the threshold size with the combined size of the first resource set and the second resource set.

20. The device of claim 19, wherein the at least one controller is further configured to cause the device to: At least in part based on the fact that the combined size is greater than the threshold size, a command is received to enable a third garbage collection operation on the first resource set and the second resource set; and One or more garbage collection operations on the first resource set and the second resource set are performed, at least in part, based on the command that enables the third garbage collection operation.

21. The device of claim 18, wherein the at least one controller is further configured to cause the device to: At least in part, based on writing the data set to the first resource set, an indication is emitted that the data set has been successfully written to the first resource set; At least in part based on the successful writing of the data set, an indication of the end of the write operation is received; as well as At least in part based on the indication of the end of the write operation, a set of garbage collection operations delayed for the first resource set are performed.

22. The device of claim 18, wherein the at least one controller is further configured to cause the device to: Based at least in part on the indication of the start of the write operation, one or both of a first mapping or a second mapping are stored, the first mapping including a first association between a logical address and a physical address at the memory system, and the second mapping indicating the validity of data stored at a physical address at the memory system.

23. The device of claim 22, wherein the at least one controller is further configured such that the device: At least in part, based on writing the data set to the first resource set, an indication of failure of the write operation on the data set is emitted; and Based at least in part on the failure of the write operation, the third mapping is replaced with the first mapping and the fourth mapping is replaced with the second mapping, the third mapping including a third association between a logical address and a physical address at the memory system, and the fourth mapping indicating the validity of the data stored at the physical address at the memory system.

24. The device of claim 23, wherein the at least one controller is further configured such that the device: The system transmits an indication that the third and fourth mappings have been successfully replaced by the first and second mappings.

25. The device of claim 18, wherein the threshold size is at least in part based on the size of the available resources at the memory system.

26. An apparatus comprising: At least one controller configured to cause the device to: Based at least in part on the set of data to be written to the memory system, a first set of resources at the memory system is identified, and a first garbage collection operation on the first set of resources at the memory system is delayed while a second garbage collection operation is enabled on a second set of resources at the memory system. A request is sent to indicate whether the memory system includes available resources for storing the data set; In response to the request, receive an indication of whether the memory system includes the available resources for storing the data set; The data set is launched at least in part based on the available resources of the memory system for storing the data set; The command is issued to delay the second garbage collection operation on the second resource set, based at least in part on the second set of data to be written to the memory system. A second request is sent to indicate whether the memory system contains available resources for storing the second data set; as well as In response to the second request, a second indication is received as to whether the memory system contains available resources, the second indication being at least in part based on a threshold size and the combined size of the first resource set and the second resource set.

27. The device of claim 26, wherein the at least one controller is further configured to cause the device to: A second command is issued at least in part based on the fact that the combined size is greater than the threshold size to enable a third garbage collection operation on the first resource set and the second resource set.

28. A method comprising: Receive an instruction to write a set of data to the memory system; Invalid data at the memory system is removed, at least in part, based on the instruction to write to the data set, until the size of the available resources at the memory system is greater than or equal to the size of the data set; The garbage collection operation at the memory system is delayed at least in part because the size of the available resources after the removal of the invalid data is greater than or equal to the size of the data set; An indication is issued that the size of the available resources is greater than or equal to the size of the data set, based at least in part on the removal of the invalid data. The indication for the start of a write operation on the data set is received, at least in part, based on the fact that the indicated size of the available resources is greater than or equal to the size of the data set. The data set is received at least in part based on the indication that the write operation has begun; as well as The data set is written to the available resource at least in part based on the receipt of the data set and at least in part based on the delay of the garbage collection operation.

29. The method of claim 28, further comprising: In response to receiving the instruction to write data, an indication of the size of the available resources is emitted at a certain time before the invalid data is removed.

30. The method of claim 29, further comprising: The command to remove the invalid data is received at least in part based on the fact that the indicated size of the available resource is smaller than the size of the data set; The garbage collection operation is performed at least in part based on the command, wherein a portion of the invalid data is removed based at least in part on the execution of the garbage collection operation; as well as A second indication of the size of the available resources is emitted, at least in part based on the completion of the garbage collection operation and before delaying the garbage collection operation.

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