Data transfer method and chip for direct memory access device

Abstract

The application provides a data transmission method and a chip for a direct memory access device. The method comprises the following steps: in response to a received write operation instruction, using a write module of the direct memory access device to store compressed data corresponding to original data in a preset data storage address; and in response to a received write operation stop instruction, using the write module to store a compressed data amount corresponding to the compressed data in a preset data amount storage address after the compressed data transmission is completed. According to some embodiments, after the data transmission is completed, the data amount of the compression result is written into a storage unit by a write unit, so that the write module does not need to be configured with the data amount of the compression result, thereby solving the problem of low data transmission efficiency caused by a dynamic decompression mode.

Description

Technical Field

[0001] This invention relates to the field of data stream accelerator cards, and more specifically, to a data transmission method and chip for a direct memory access device, an electronic device, and a non-transitory computer-readable storage medium. Background Technology

[0002] DMA (Direct Memory Access) is a common on-chip technology that allows hardware devices of different speeds to communicate with each other without relying on a large interrupt load on the CPU. Otherwise, the CPU needs to copy each piece of data from the source to a temporary register and then write them back to the new location. During this time, the CPU cannot be used for other tasks. DMA eliminates the need for direct CPU control of the transfer and avoids the context saving and restoring process required by interrupt handling. By establishing a direct data transfer path between RAM and I / O devices in hardware, it significantly improves CPU efficiency.

[0003] DMA's function is to transfer data, determining both the source and destination addresses, and the amount of data transferred. Data addresses are typically defined by application software or the operating system, ensuring no address conflicts and data overwriting. Handling data volume is far more complex, as the size of the data directly determines the time required for transmission, directly impacting system efficiency. For example, a chip might contain functional modules A / B / C, all using the same data bus to exchange data. When module A is transmitting data, other modules must wait until A's data transfer is complete before B / C can preempt the bus to transmit their own data. Clearly, the larger the data volume of A, the longer the bus transmission time for A's data will be, resulting in longer waiting times for B / C and slower functional responses. Externally, this manifests as decreased chip performance or inefficiency.

[0004] To address the issue of long transmission times caused by large datasets, a feasible approach is to introduce compression and decompression functions. This is common in video processing and AI computing, as these fields handle massive amounts of data. The decompression process involves the source end compressing the large amount of raw data to reduce its size before transmission. The reduced data size corresponds to a shorter transmission time, and the receiving end performs decompression to recover the original data. Combining compression and decompression can reduce bus data transmission time and improve bus utilization and performance. However, this method of data transmission through decompression introduces a problem: the data size changes before and after compression, and the compressed data size is often unpredictable. This is especially problematic with dynamic compression, where DMA data configuration can only occur after each compression cycle, significantly impacting data storage efficiency. Summary of the Invention

[0005] The present invention aims to provide a data transmission method for direct memory access devices, as well as chips, electronic devices, and non-transitory computer-readable storage media, to solve the problem of low data transmission efficiency caused by the data transmission processing method of decompression in the prior art.

[0006] According to one aspect of the present invention, a method for data storage using a direct memory access device is provided, comprising: In response to the received write operation command, the write module of the direct memory access device stores the compressed data corresponding to the original data into a preset data storage address. In response to the received write operation stop command, after the compressed data transmission is completed, the write module stores the compressed data corresponding to the compressed data into a preset data storage address.

[0007] According to some embodiments, before the write module of the direct memory access device stores the compressed data corresponding to the original data into a preset data storage address, the method further includes: The write module is used to obtain the data storage address; Before using the write module to store the compressed data corresponding to the compressed data into a preset data storage address, the method further includes: The data storage address is determined according to a preset address relationship.

[0008] According to some embodiments, the data storage address is the address adjacent to the first write address in the data storage address.

[0009] According to some embodiments, the amount of compressed data is obtained by statistical analysis after the original data has been compressed.

[0010] According to some embodiments, the method further includes: In response to a received read operation command, the read module of the direct memory access device obtains the amount of compressed data according to the read operation command; Based on the amount of compressed data, the read module reads the compressed data stored at the data storage address.

[0011] According to some embodiments, the read operation instruction includes the data storage address, wherein the read module using the direct memory access device obtains the compressed data volume according to the read operation instruction, including: The read module uses a preset address relationship to obtain the data storage address based on the data storage address; The compressed data volume is read from the data volume storage address using the read module.

[0012] According to some embodiments, the read operation instruction includes the data storage address, wherein the read module using the direct memory access device obtains the compressed data volume according to the read operation instruction, including: The compressed data volume is read from the data volume storage address using the read module; The read module calculates the data storage address based on the amount of compressed data according to a preset address relationship.

[0013] According to one aspect of the invention, a chip is provided that stores data stored using the methods described above.

[0014] According to one aspect of the present invention, an electronic device is provided, comprising one or more processing units; a storage unit for storing one or more programs; wherein when the one or more programs are executed by the one or more processing units, the one or more processing units perform the method as described in any of the preceding embodiments.

[0015] According to one aspect of the present invention, a non-transitory computer-readable storage medium is provided, having stored thereon computer-readable instructions that, when executed by a processor, cause the processor to perform the method as described in any of the preceding embodiments.

[0016] According to an embodiment of the present invention, after the data transmission is completed, the data volume of the compressed result is written to the storage unit through the writing unit, so that it is no longer necessary to configure the amount of compressed data in the writing module, thereby solving the problem of low data transmission efficiency caused by dynamic decompression.

[0017] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the invention. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The above and other objectives, features, and advantages of the present invention will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0019] Figure 1 This diagram illustrates an architecture for transmitting data via dynamic decompression.

[0020] Figure 2 A flowchart illustrating a method for data storage and transmission using a direct memory access device according to an exemplary embodiment of the present invention is shown.

[0021] Figure 3A schematic diagram of a read operation process according to an exemplary embodiment of the present invention is shown.

[0022] Figure 4 A flowchart illustrating another method for data storage and transmission using a direct memory access device according to an exemplary embodiment of the present invention is shown.

[0023] Figure 5 A flowchart illustrating another method for data storage and transmission using a direct memory access device according to an exemplary embodiment of the present invention is shown.

[0024] Figure 6 An electronic device according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same drawings in the figures show the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0026] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of these specific details, or other methods, components, materials, apparatus, or operations may be employed. In these cases, well-known structures, methods, apparatuses, implementations, materials, or operations will not be shown or described in detail.

[0027] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0028] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0029] Figure 1 This diagram illustrates an architecture for transmitting data via dynamic decompression, such as... Figure 1 As shown, DMA includes a DMA read module and a DMA write module.

[0030] In the prior art, before the DMA read module reads data from the storage module, it needs to receive read configuration data from the configuration module, including but not limited to read address configuration, read data volume configuration and read operation mode, and communicate with the on-chip bus to read bus data.

[0031] If the dynamic decompression function is enabled, the bus data read by the DMA read module is the compressed result data. The dynamic decompression module decompresses the data to obtain the original data before compression, which is then processed by subsequent modules.

[0032] Before writing data to the storage module, the DMA write module needs to receive configuration data from the configuration module, including but not limited to write address configuration, write data volume configuration, and write operation mode. Afterward, it communicates with the on-chip bus to write the compressed result data to the storage module.

[0033] If dynamic compression is enabled, the compressed data output from the dynamic compression module will be written out as bus data, and the compressed data will ultimately come from the preceding module.

[0034] The configuration module is responsible for configuring the various modules in the DMA, as well as the dynamic compression and decompression modules, and controlling their operation. The on-chip bus connects the various functional modules together, forming an information transmission path.

[0035] In specific embodiments, the storage module includes, but is not limited to, DDR memory.

[0036] As mentioned earlier, the combined use of dynamic compression and decompression can reduce bus data transmission time and improve bus utilization and performance. However, this method of data transmission processing through decompression can also significantly impact data storage efficiency.

[0037] For example, when writing data without dynamic compression, suppose the DMA writes five batches of 10KB raw data to DDR, corresponding to five configurable DMA write operations, each with a data size configuration of 10KB. Since the data size is known, the five DMA writes can be configured in advance or promptly, making the writing of the five batches of data essentially continuous and without intervals. However, for DMA transfers with compression, the five batches of 10KB raw data might result in compressed values ​​of 6 / 7 / 5 / 8 / 4KB. To improve transmission efficiency, an intuitive approach would be to compress the data while simultaneously having the DMA write the compressed result to DDR, ensuring continuous write operations. However, this is difficult to achieve because the compressed data size cannot be obtained before the 10KB data compression is complete, making timely DMA configuration impossible. Therefore, the current technology uses a data transmission method that first compresses the first batch of 10KB data, calculates the result as 6KB, notifies the software of this data size, and then the software configures the data size configuration for the first DMA write to be 6KB. This operation, which requires compression before DMA configuration, is clearly serial, resulting in significant intervals between the five write batches and reducing efficiency. Furthermore, frequent software interaction itself introduces substantial time overhead, further exacerbating the efficiency drop.

[0038] For example, when reading uncompressed data, suppose the DMA reads five batches of data from DDR. This corresponds to five DMA read operations that can be configured, with each read data size configured to be 10KB. Since the data size is known, the five DMA reads can be configured in advance or promptly. From a time perspective, reading five batches of data can be considered to be essentially continuous with no intervals.

[0039] Corresponding to the aforementioned dynamic compression, in order to obtain the original data, it is necessary to perform a decompression operation on the read compressed data. Because the aforementioned compression method requires external software to record the amount of data after each compression, and then configure the read data volume for the DMA read module, it is possible to accurately and quantitatively read the compressed results for each batch. Only by correctly reading the compressed results can the original data be correctly decompressed. While this processing method is not a problem for small amounts of data, for the massive amounts of AI data, where data operations may involve millions or tens of millions of batches, this decompression processing method makes software implementation extremely difficult.

[0040] Therefore, the difficulty in introducing dynamic compression and decompression lies in the fact that the amount of data in the compression result is unknown. This unknown makes it difficult to configure the write data volume of the DMA write module and the read data volume of the DMA read module in a timely manner, which in turn leads to a decrease in system efficiency.

[0041] To address the aforementioned problems, according to an embodiment of the present invention, after data transmission is completed, the compressed data amount is written to the storage unit via the DMA write unit, thereby eliminating the need to configure the compressed data amount for the DMA write module. This not only solves the problem of low data transmission efficiency caused by the dynamic compression process but also solves the problem of the difficulty in implementing the dynamic decompression process.

[0042] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0043] Figure 2 A flowchart illustrating a method for data storage using a direct memory access device according to an exemplary embodiment of the present invention is shown, such as... Figure 2 The method shown includes steps S101 and S103. The following will use... Figure 2 Taking an example, a method for data storage using a direct memory access device according to an exemplary embodiment of the present invention will be described in detail.

[0044] like Figure 2 As shown, in step S201, in response to the received write operation instruction, the write module of the direct memory access device stores the compressed data corresponding to the original data into a preset data storage address.

[0045] According to an embodiment of the present invention, in step S201, before using the write module of the direct memory access device to store the compressed data corresponding to the original data into the preset data storage address, it is also necessary to use the write module to obtain the data storage address so as to store the compressed data into the data storage address.

[0046] In existing technologies, before performing dynamic decompression, the write module of the direct memory access device needs to obtain configuration data. This configuration data includes not only the data storage address but also the amount of compressed data. However, in this invention, the write module of the direct memory access device does not need to obtain the amount of compressed data before performing the write operation, thus avoiding the storage problems caused by dynamic data compression.

[0047] To ensure complete storage of compressed data, in some embodiments, a large write data volume CFG_WR needs to be configured for the DMA write module. For example, CFG_WR can be set to a configurable limit value to ensure that the DMA can continuously write data and will not stop transmitting before the dynamic compression ends.

[0048] According to some embodiments, after determining the data storage address, it is also necessary to determine the data storage address according to a preset address relationship.

[0049] It should be noted that the preset address relationship may include various preset mapping relationships, but in this invention, the address relationship between the data volume storage address and the data storage address is not specifically limited. For example, in a specific embodiment, the data volume storage address may be the address adjacent to the first write address in the data storage address.

[0050] In step S203, in response to the received write operation stop instruction, after the compressed data transmission is completed, the write module stores the compressed data corresponding to the compressed data into a preset data storage address.

[0051] In existing technology, before the write module of a direct memory access device (DMemory Access) performs a write operation, a dynamic compression module needs to perform a data compression operation and send the compressed data to the write module of the DMemory Access device after the data compression is complete. Only then can the write module of the DMemory Access device perform the write operation.

[0052] In this invention, the DMA write module does not need to acquire the compressed data amount when performing a write operation. The compressed data amount is obtained by statistics after the original data is compressed. After the compressed data transmission is completed, the DMA write module stores the compressed data amount in the data storage address according to the preset address relationship.

[0053] like Figure 3 As shown, assuming the original data is X and the dynamically compressed data is Y, the initial value of the data storage address configured for the DMA write module is ADDR_WR_INI before the write operation. Then, the DMA write module performs the write operation, storing the first piece of data in ADDR_WR_INI, and subsequent data is stored incrementally according to the address. After all modules in the write direction are started, the dynamic compression module continuously outputs the compression results, and the DMA write module continuously writes data to the bus. When the dynamic compression module outputs the last compression result, it also outputs the compressed data and a write operation stop instruction, which stops the DMA write module. At this point, the DMA write module has output all compression results. Then, the DMA write module automatically initiates a new write operation, writing out the compressed data Y. For ease of understanding, assume the write address of the data is ADDR_WR_INI-1, the purpose of which is to store the value of Y in DDR.

[0054] according to Figure 2 In the embodiment shown, after the data transmission is completed, the compressed data is written to the storage unit through the writing unit, so there is no need to configure the amount of compressed data in the writing module, thereby solving the problem of low data transmission efficiency caused by dynamic decompression.

[0055] Figure 4A flowchart illustrating another method for data storage using a direct memory access device according to an exemplary embodiment of the present invention is shown, such as... Figure 4 The method shown includes steps S201 and S203, as well as steps S205 and S207. To avoid redundancy, this invention only describes... Figure 2 The differences will not be elaborated upon, and the similarities will not be repeated.

[0056] In step S205, in response to the received read operation instruction, the read module of the direct memory access device obtains the compressed data volume according to the read operation instruction.

[0057] In an embodiment of the present invention, the read operation instruction includes the data storage address. In step S205, firstly, the read module obtains the data storage address based on the data storage address according to a preset address relationship; then, the read module reads the compressed data from the data storage address.

[0058] In some other embodiments, in step S205, firstly, the read module reads the compressed data from the data storage address; then, the read module calculates the data storage address based on the compressed data according to a preset address relationship.

[0059] In the prior art, before performing a read operation using the read module of the direct memory access device, it is necessary to obtain the amount of compressed data corresponding to the compressed data, which undoubtedly increases the difficulty of data processing for big data.

[0060] In this invention, assuming the compressed result Y corresponding to the original data X is located in DDR, and the data volume is Y, the read module of the direct memory access device needs to read the compressed result from DDR so that the dynamic decompression module can recover the original data. In this invention, the read module of the direct memory access device does not need to obtain the compressed data volume. The specific execution process is as follows: the read module of the direct memory access device obtains the initial value ADDR_RD_INI of the read address, where ADDR_RD_INI corresponds to... Figure 3 In the illustrated embodiment, the first compression result is stored at address ADDR_WR_INI. Subsequently, the read module of the direct memory access device automatically initiates an independent read operation. Assuming the compressed data occupies address 1, the read address of the compressed data, determined according to a preset address relationship, is ADDR_RD_INI-1, to read the compressed data and extract the Y value. Then, using the compressed data Y and based on the initial value ADDR_RD_INI of the acquired read data, a new read operation is initiated to read all the compression results. It should be noted that ADDR_WR_INI and ADDR_RD_INI are generated by external software. Even without dynamic compression and decompression functions, the software still needs to plan and allocate storage addresses, and this invention does not increase the software complexity. Furthermore, this invention simplifies the process by allocating an additional address range for each batch of compression results to store the compressed data, in addition to the normally planned addresses.

[0061] Furthermore, typically one address stores one byte of information. If the compressed data size is in the range of 256 to 65535, then two bytes of address are needed, and so on. Since any system's underlying layer can only process a finite number of values, the compressed data size has a range, thus corresponding to a finite address range. For example, if 8 bytes of address are allocated to store the compressed data size, and this is fixed before ADDR_WR_INI, then ADDR_WR_INI-8 to ADDR_WR_INI-1 is the storage area for the compressed data size. The chip's hardware design consistently uses this range. In addition to reading and writing the compressed data, the hardware design automatically adds one additional read / write operation, corresponding to a very small amount of compressed data, thus having minimal impact on bus efficiency.

[0062] In step S207, based on the amount of compressed data, the compressed data stored at the data storage address is read using the read module.

[0063] according to Figure 4 The illustrated embodiment not only solves the problem of dynamically changing data in dynamic compression by adding an extra read / write operation, but also, since the extra DMA read / write operation only transfers a single value, the data volume is very small and can be completed automatically by hardware, with minimal impact on the internal bus. Furthermore, the software is unaware of this, resulting in minimal impact on the system.

[0064] Figure 5 A flowchart illustrating another method for data storage using a direct memory access device according to an exemplary embodiment of the present invention is shown, such as... Figure 5 As shown, in step S1, addresses are allocated for the compressed data and the corresponding data volume.

[0065] The addresses corresponding to the compressed data and the addresses corresponding to the quantity are determined according to a preset address relationship.

[0066] In step S2, an operation instruction is received, which includes a write operation instruction or a read operation instruction.

[0067] In step S3, if the received operation instruction is a write operation instruction, the compression result is written, the DMA write module is configured, and the obtained configuration data includes the address corresponding to the compression result allocated in step S1, etc.

[0068] In a specific implementation, the write data volume needs to be configured to a maximum value to ensure that the DMA write module does not stop working before outputting all the compressed results. Once configured, the DMA write is started.

[0069] In step S4, the dynamic compression module continuously outputs the compression results, which are then continuously written to the bus by the DMA write module.

[0070] In step S5, the dynamic compression module continuously counts the number of compression results and finally outputs a flag indicating that compression has ended. This flag signals the first DMA write module to stop operating.

[0071] In step S6, the DMA write module immediately and automatically initiates a write operation again, writing the compressed data into the address range allocated in step S1.

[0072] This operation requires no external configuration. The data volume configuration for this write operation is the number of compression results counted in step S5, and the write address configuration is the address where the number of compression results is stored. These can be calculated according to the fixed relationship in step S1, so it can be entirely completed by hardware.

[0073] In step S7, if the received operation instruction is a read operation instruction, the DMA read module is configured. The configuration parameters include the address of the compressed result allocated in step S1. In this step, it is not necessary to configure the read data volume. Once configured, the DMA read operation is initiated.

[0074] In step S8, the DMA read module initiates the first read operation to read the amount of data from the compressed result. The address corresponding to the data amount can be obtained from the address of the compressed result configured in step S7, based on the address relationship in step S1.

[0075] In step S9, based on the amount of data in the compressed result read in step S8 and the read address configuration in step S7, a second read operation is performed to read the compressed result.

[0076] Step S10: The write or read operation ends.

[0077] According to an embodiment of the present invention, a chip is provided which stores data stored using the methods described above.

[0078] The following describes embodiments of the apparatus of the present invention. For details not described in the embodiments of the apparatus of the present invention, please refer to the embodiments of the method of the present invention.

[0079] Figure 6 An electronic device according to an exemplary embodiment of the present invention is shown below. Figure 6 To describe an electronic device 200 according to this embodiment of the present invention. Figure 6The electronic device 200 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0080] like Figure 6 As shown, the electronic device 200 is presented in the form of a general-purpose computing device. The components of the electronic device 200 may include, but are not limited to: at least one processing unit 210, at least one storage unit 220, a bus 230 connecting different system components (including storage unit 220 and processing unit 210), a display unit 240, etc.

[0081] The storage unit stores program code, which can be executed by the processing unit 210 to perform the methods described in this specification according to various exemplary embodiments of the present invention. For example, the processing unit 210 can perform the methods described above.

[0082] Storage unit 220 may include readable media in the form of volatile storage units, such as random access memory (RAM) 2201 and / or cache memory 2202, and may further include read-only memory (ROM) 2203.

[0083] Storage unit 220 may also include a program / utility 2204 having a set (at least one) program module 2205, such program module 2205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0084] Bus 230 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0085] Electronic device 200 can also communicate with one or more external devices 300 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 200, and / or with any device that enables electronic device 200 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 250. Furthermore, electronic device 200 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 260. Network adapter 260 can communicate with other modules of electronic device 200 via bus 230. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0086] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. The technical solutions of the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, portable hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the methods described above according to the embodiments of the present invention.

[0087] Software products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0088] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0089] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0090] The aforementioned computer-readable medium carries one or more programs, which, when executed by a device, cause the computer-readable medium to perform the aforementioned functions.

[0091] Those skilled in the art will understand that the above modules can be distributed in the device as described in the embodiments, or they can be modified accordingly and placed in one or more devices that are unique to this embodiment. The modules in the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0092] According to an embodiment of the present invention, a computer program is provided, comprising a computer program or instructions, which, when executed by a processor, can perform the methods described above.

[0093] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of the present invention, its specific implementation methods, and its application scope, are all within the scope of protection of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for data storage using a direct memory access device, characterized in that, include: In response to the received write operation command, the write module of the direct memory access device stores the compressed data corresponding to the original data into a preset data storage address. In response to the received write operation stop command, after the compressed data transmission is completed, the write module stores the compressed data corresponding to the compressed data into a preset data storage address.

2. The method according to claim 1, characterized in that, Before the write module of the direct memory access device stores the compressed data corresponding to the original data into the preset data storage address, the method further includes: The write module is used to obtain the data storage address; Before using the write module to store the compressed data corresponding to the compressed data into a preset data storage address, the method further includes: The data storage address is determined according to a preset address relationship.

3. The method according to claim 1, characterized in that, The data storage address is the address adjacent to the first write address in the data storage address.

4. The method according to claim 1, characterized in that, The amount of compressed data is obtained by statistical analysis after the original data has been compressed.

5. The method according to claim 1, characterized in that, The method further includes: In response to a received read operation command, the read module of the direct memory access device obtains the amount of compressed data according to the read operation command; Based on the amount of compressed data, the read module reads the compressed data stored at the data storage address.

6. The method according to claim 5, characterized in that, The read operation instruction includes the data storage address, wherein the read module using the direct memory access device obtains the compressed data volume according to the read operation instruction, including: The read module uses a preset address relationship to obtain the data storage address based on the data storage address; The compressed data volume is read from the data volume storage address using the read module.

7. The method according to claim 5, characterized in that, The read operation instruction includes the data storage address, wherein the read module using the direct memory access device obtains the compressed data volume according to the read operation instruction, including: The compressed data volume is read from the data volume storage address using the read module; The read module calculates the data storage address based on the amount of compressed data according to a preset address relationship.

8. A chip, characterized in that, It stores data stored using the method described in any one of claims 1-7.

9. An electronic device, comprising: processor; as well as A memory storing a computer program that, when executed by the processor, causes the processor to perform the method as described in any one of claims 1-7.

10. A non-transitory computer-readable storage medium having stored thereon computer-readable instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 1-7.

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