A multi-board stacked PXIe bus controller based on function unit layering
The PXIe bus controller, designed with multiple boards stacked, solves the problems of insufficient layout area for high-performance domestic processors and large-capacity memory, as well as the signal integrity issues of PCIe bus communication, achieving high-density integration and signal integrity.
Patent Information
- Application Number
- CN202610613973.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-07
- Publication Date
- 2026-07-24
AI Technical Summary
Existing technologies make it difficult to achieve the layout of high-performance domestic processors and large-capacity memory within a limited PCB area, and PCIe bus communication faces signal integrity issues, affecting transmission rate and distance.
It adopts a multi-board stacking design based on functional unit layering, including processor units, memory units, interface circuit units and interface conversion units, and achieves high-density integration through board-to-board connectors to meet the standard PXIe pluggable compatibility requirements.
It achieves high-density integration of high-performance domestic processors and large-capacity memory within a 3U standard size, solving the problem of insufficient layout area, while meeting the signal integrity requirements of PCIe bus communication.
Smart Images
Figure CN122450878A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of bus controller technology, and more specifically to a multi-board stacked PXIe bus controller based on functional unit layering. Background Technology
[0002] As the core control unit of the PXIe test and measurement system, the PXIe bus controller plays a crucial role in system operation, bus protocol processing, peripheral interface scheduling, and high-speed data interaction. Its performance, integration, and hardware autonomy directly determine the operating efficiency and application adaptability of the entire PXIe system. Currently, it has been widely used in high-end fields such as aerospace, defense, and industrial testing.
[0003] PCIe bus communication is characterized by high-speed serial point-to-point connections, placing extremely high demands on signal integrity. As frequency increases, the losses (conductor and dielectric losses) of the printed circuit board (PCB) material increase dramatically, signal amplitude decreases, and signals become difficult to identify, becoming the primary factor limiting speed and transmission distance. Secondly, impedance discontinuities (such as vias, connectors, and chip packages) can cause signal reflections, resulting in waveform overshoot, undershoot, and ringing, interfering with subsequent signals. Crosstalk (near-end NEXT and far-end FEXT) occurs between parallel traces due to electromagnetic coupling, and noise intensifies with increasing wiring density and speed. Therefore, to achieve PCIe bus communication of ≥16GB, a reasonable PCB layout and routing strategy, along with strict impedance matching and control, is required within a limited PCB area.
[0004] Therefore, in view of the shortcomings of the existing technology, how to provide a multi-board stacked PXIe bus controller based on functional unit layering is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] In view of this, the present invention provides a multi-board stacked PXIe bus controller based on functional unit layering. Within the standard 3U size, the processor unit, memory unit, interface circuit unit, and interface conversion unit are functionally modularly stacked and layered. High-density integration is achieved with high-speed board-to-board connectors (FMC / Com Express), which solves the problem of insufficient layout area for high-performance domestic processors and large-capacity memory devices, while meeting the standard PXIe pluggable compatibility requirements.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: a multi-board stacked PXIe bus controller based on functional unit layering, comprising: a processor unit, a memory unit, an interface circuit unit, and an interface conversion unit; The processor unit is connected to the memory unit and the interface circuit unit via communication connections. The interface circuit unit is connected to the interface conversion unit; The processor unit, memory unit, interface circuit unit, and interface conversion unit are respectively disposed on at least two independent printed circuit boards, and the circuit boards are fixed together by board-to-board connectors to form a layered stacked structure.
[0007] Preferably, the interface circuit unit includes a PCIe bus communication interface, which is connected to the processor unit and is used to realize data interaction and power supply access with the PXIe chassis backplane.
[0008] Preferably, the processor unit and the memory unit are stacked via a board-to-board connector; The processor unit and the interface circuit unit are stacked together via board-to-board connectors; The interface conversion unit and the interface circuit unit are stacked using PCB or cable.
[0009] Preferably, it also includes a heat dissipation component, which is attached to the surface of the processor unit.
[0010] Preferably, the processor unit includes a processor and a bridge chip; the processor and the bridge chip exchange data and instructions.
[0011] Preferably, the memory unit provides DDR interface memory for the processor for temporary storage of program instructions and data.
[0012] Preferably, the interface circuit unit is an interface expansion circuit between the processor and the bridge chip, used to provide signal interfaces to the outside world, and also includes a hard disk interface, a display interface, a network communication interface, an RS232 serial communication interface, a USB interface, and a PXI bus trigger system circuit.
[0013] Preferably, the interface conversion unit adopts a general-purpose physical interface for computers, and all general-purpose physical interfaces of the interface conversion unit are brought out through the front panel.
[0014] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a multi-board stacked PXIe bus controller based on functional unit layering. Within the 3U standard size, the processor unit, memory unit, interface circuit unit, and interface conversion unit are functionally modularly stacked and layered. High-density integration is achieved with high-speed board-to-board connectors (FMC / ComExpress), which solves the problem of insufficient layout area for high-performance domestic processors and large-capacity memory devices, while meeting the standard PXIe pluggable compatibility requirements. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of the PXIe bus controller structure provided in an embodiment of the present invention.
[0017] Figure 2 This is a schematic diagram illustrating the interface relationships between circuit units provided in an embodiment of the present invention.
[0018] Figure 3 This is a schematic diagram of the overall hardware architecture of the PXIe bus controller provided in an embodiment of the present invention.
[0019] Figure 4 This is a schematic diagram illustrating the health management principle provided in an embodiment of the present invention.
[0020] Figure 5 This is a schematic diagram of the stacking relationship provided for an embodiment of the present invention. Detailed Implementation
[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] This invention discloses a multi-board stacked PXIe bus controller based on functional unit layering, comprising: a processor unit, a memory unit, an interface circuit unit, and an interface conversion unit; The processor unit is connected to the memory unit and the interface circuit unit respectively for communication connection, and is used to perform system operations, PXIe bus protocol processing and peripheral interface scheduling. The interface circuit unit is connected to the interface conversion unit and is used to convert the internal bus signal of the processor unit into peripheral expansion signal; The processor unit, memory unit, interface circuit unit, and interface conversion unit are respectively disposed on at least two independent printed circuit boards. The circuit boards are electrically interconnected and mechanically fixed through board-to-board connectors to form a layered stacked structure.
[0023] Specifically, the PXIe bus controller hardware architecture is as follows: Figure 1As shown, the PXIe bus controller is a high-performance bus controller based on the domestic Phytium 32-core Tengyun S5000C processor, implemented using all domestically produced components. It utilizes the domestically produced Phytium X100 bridge chip for bus interface expansion. The PXIe bus controller is designed based on the 3U PXIe bus specification, with a 3U 4-slot width, and can be inserted into a PXIe chassis system slot. Powered by the PXIe chassis, it implements PXIe bus communication, VGA display interface, DP display interface, gigabit network communication, USB interface, and RS232 serial communication functions.
[0024] Specifically, the PXIe bus controller is designed according to the PXIe bus technical specifications, providing a PCIe bus communication interface for interconnection with the PXIe system backplane, and providing external interfaces such as gigabit network communication interface, USB interface, RS232 serial communication interface, VGA display interface, DP display interface, trigger input / output interface, etc., to realize the functions required by the PXIe bus controller.
[0025] The PXIe bus controller is designed using the 3U PXIe bus specification, with a 4-slot width. Based on the 3U PXIe bus specification, the printed circuit board size is 160mm × 100mm, making a single-board design difficult. Multiple boards must be stacked, and board-to-board connectors can be used for signal interconnection between them. The circuit board can be functionally divided into processor units, memory units, interface circuit units, and interface conversion units.
[0026] Specifically, the interface circuit unit includes a PCIe bus communication interface, which is connected to the processor unit to enable high-speed data interaction and power supply access with the PXIe chassis backplane.
[0027] Specifically, the processor units and memory units are stacked together via board-to-board connectors; The processor unit and the interface circuit unit are stacked together via board-to-board connectors; The interface conversion unit and the interface circuit unit are stacked using PCB or cable.
[0028] Specifically, the bus controller adopts a 4-slot width design. In order to avoid interference with other peripheral modules when the bus controller is inserted, the width of the bus controller should be planned from right to left. Each circuit unit is stacked from right to left, and a compact structure stacking technology is adopted to rationally divide functions and allocate stacking interfaces and stacking methods between circuit board units.
[0029] In one specific embodiment of the present invention, the processor unit and the memory unit are planned to use a high-speed differential board-to-board connector for interface stacking, such as an FMC connector. This type of connector has a minimum mating height of 5mm and a maximum transmission rate of 25Gbps, which can meet the transmission requirements of high-speed signals of the memory interface.
[0030] The processor unit and interface circuit unit are connected via ultra-high-speed differential board-to-board connectors for interface stacking, such as COM Express connectors. These connectors have a maximum mating height of 16mm and can meet the high-speed signal transmission requirements of PCIe 3.0. Various connector sizes are available, including 5mm, 6mm, 7mm, 8mm, 11mm, 12mm, and 16mm, to meet the stacking structure requirements of processor units, memory units, and interface circuit units.
[0031] The interface conversion unit and the interface circuit unit communicate with low-speed signals, and flexible PCBs or cables can be designed for interface stacking.
[0032] The circuit board stacking order is planned as follows: First, memory units → processor units → interface circuit units; finally, interface conversion units → interface circuit units, and the stacking relationship is as follows. Figure 5 As shown.
[0033] The processor unit circuit board is designed with solderable nut posts to enhance the tightness and reliability of the connection between the memory unit and the processor unit. The interface circuit unit circuit board is also designed with solderable nut posts to reinforce the tightness and reliability of the connection between the processor unit and the interface circuit unit. Screws are designed for secure connection between the interface conversion unit circuit board and the interface panel.
[0034] The interface panel is designed with 4 slots, and the interface design includes: 2 RJ45 ports, 1 DP port, 2 USB 3.0 ports, 1 reset button, 1 indicator light, 1 trigger input, 1 trigger output, 2 USB 2.0 ports, 1 DB9 port (serial port), and 1 DB15 (VGA) port.
[0035] Specifically, it also includes a heat dissipation component, which is attached to the surface of the processor unit to achieve system thermal management.
[0036] Specifically, the heat dissipation components are designed using a vapor chamber to quickly achieve thermal equilibrium. A copper heatsink is used to conduct heat from the processor and CPU chips to the vapor chamber, where it is then rapidly dissipated through the chassis's air-cooling system and its own airflow channels. Other power components, such as memory, hard drives, and DC-DC converters, utilize the chassis's Euro-Karabakh-style airflow design for cooling.
[0037] Specifically, the processor unit includes a processor and a bridge chip; the processor and the bridge chip exchange data and instructions.
[0038] The processor unit is based on the Phytium S5000C processor and the X100 bridge chip, and implements the corresponding interface circuit design.
[0039] Specifically, the processor unit mainly includes the processor, bridge chip, power management, health management and other parts, and implements the corresponding circuit design.
[0040] The processor used is Phytium Tengyun S5000C, which is the central processing unit of the PXIe bus controller. It is the core of the PXIe bus controller for operation and control, and is the final execution unit for information processing and program execution.
[0041] The bridge chip uses Phytium X100, which directly exchanges data and instructions with the processor, acts as a connecting bridge, and provides communication interfaces such as USB, DP, UART, SATA, and PCIe for the PXIe bus controller.
[0042] Health management is implemented based on a CPLD to monitor processor temperature, communicating with the processor via an I2C bus. The CPLD acquires the processor's temperature and uses PWM to adjust the speed of the cooling system's fans, thus completing the temperature monitoring of the bus controller and the speed monitoring of the cooling fans. The health management principle block diagram is shown below. Figure 4 As shown.
[0043] Power Management: Power management is the secondary power supply and power timing management section on the PXIe bus controller, including the secondary power supply of the interface circuit unit and the secondary power supply and power timing management circuit of the processor unit.
[0044] Specifically, the memory unit provides DDR interface memory for the processor to temporarily store program instructions and data.
[0045] Specifically, the PXIe bus controller is designed with 64GB of DDR memory for temporary storage of program instructions and data, connected to the CPU's DDR interface. The CPU, Tengyun S5000C-32 processor, integrates four DDR interfaces, supporting a maximum of four DDR channels, with each channel supporting a maximum of two ranks. The DDR interfaces support 1.1V DDR5 RDIMM and 1.2V DDR4 RDIMM / UDIMM, with a maximum speed of DDR5 4000MT / s and DDR4 3200MT / s. The design utilizes 32 16Gb memory chips connected to the CPU's four DDR interfaces to achieve 64GB of DDR memory.
[0046] The memory chip selected is the SM40A1G16MP from Guowei Electronics. The SM40A1G16MP is a high-capacity DDR4 synchronous dynamic random access memory with a total capacity of 16Gb and a maximum data transfer rate of 2400MT / s. It is used in conjunction with the processor for storing large amounts of data and enabling fast data access, primarily to meet the needs of large-capacity memory in computers. This product uses a 25nm CMOS process and is packaged in an FBGA96 plastic package.
[0047] The SM40A1G16MP 16Gb DDR4 Synchronous Dynamic Random Access Memory (SDRAM) is a high-speed SDRAM that utilizes a double-rate data architecture. It features a 16-bit data width, differential dual-clock inputs (CK_t and CK_c), a maximum data transfer rate of 2400MT / s, supports 8n-bit prefetching, and supports automatic refresh mode under low power consumption. It conforms to the JEDEC JESD-79-4 standard and allows selection of internal memory cells via row address A[15:0], column address A[9:0], bank address BA[1:0], and bank group address. Read and write operations are performed after activating the device using standard instructions.
[0048] Specifically, the interface circuit unit is an interface expansion circuit between the processor and the bridge chip, used to provide a high-speed signal interface to the outside world. It also includes a hard disk interface, a display interface, a network communication interface, an RS232 serial communication interface, a USB interface, and a PXIe bus trigger system circuit.
[0049] The interface circuit unit mainly includes an RS232 transceiver, a network controller, a VGA controller, a DP display interface, a USB 3.0 interface, a hard disk interface, a PCIe bus communication interface, a PXI bus triggering system, etc., to realize the corresponding circuit design.
[0050] Specifically, the interface conversion unit adopts a general-purpose computer physical interface, and all general-purpose physical interfaces of the interface conversion unit are brought out through the front panel. The interface conversion unit implements electrical interfaces such as VGA display, RS232 serial communication, and USB2.0.
[0051] The interface conversion unit converts the PXIe bus controller's display interface, network communication interface, serial communication interface, USB interface, etc., into common computer interfaces such as DP, VGA, RJ45, DB9 serial communication, USB, etc.
[0052] This embodiment, based on the overall hardware scheme of the PXIe bus controller, is mainly divided into processor units, memory units, and interface conversion units. The product adopts an Eurocard architecture, with each unit using a stacked design. Board-to-board connectors are used for interface connection between units. Figure 3As shown. The interface relationships between circuit units are as follows. Figure 2 As shown.
[0053] In one specific embodiment of the present invention, the PXIe bus controller needs to implement the design of Phytium Cloud S5000C and bridge chip X100 on a standard 3U PXIe module. The circuit board size is 160mm × 100mm. It needs to accommodate 32 16Gb memory chips to achieve 64GB of memory. It also needs to implement the layout design of hard disk, power management, PCIe bus communication interface connectors, interface circuits, and common computer interfaces such as network (RJ45), VGA display (DB15), serial communication (DB9), USB, and DP. The Phytium Cloud S5000C-32 processor has a package size of 61mm × 61mm, the bridge chip X100 has a package size of 31mm × 31mm, and the 16Gb memory chip has a package size of 16.5mm × 11mm (32 chips total 11616mm). 2 The hard drive's dimensions are 29.85mm × 50.8mm. Since the processor and bridge are located on the back of the circuit board, it's generally impossible to place other components there; therefore, a minimum thickness of 22496.38mm is required. 2 The circuit board area must also include space for power management chips, interface circuit chips, resistors, inductors, capacitors, and connectors for USB, VGA, DB9, DP, and RJ45 interfaces. The circuit board layout area should be no less than 40,000 mm². 2 The effective area of a single side of the 3U PXIe module circuit board, after deducting the area around the PXIe bus interface connector and the edge of the rail slot, is estimated to be 13800 mm². 2 The effective area on both sides is estimated to be 27600 mm². 2 This makes it difficult to meet the layout requirements of various components. According to the technical requirements of this embodiment, the bus controller panel adopts a 4-slot width design, with a total width of 16HP (4×20.32mm=81.28mm), to accommodate 2 RJ45 sockets, 1 DB9 socket, 4 USB Type-A sockets, 1 DP socket, and 1 DB15 socket to realize its required interface functions.
[0054] In this embodiment, a stacked structure of multiple circuit boards is used for design. The distribution of heat dissipation devices and the interconnection between circuit boards are closely related to the final layout area of the product. Furthermore, the stacked structure between circuit boards requires connectors for signal cross-linking. Therefore, a reasonable circuit board stacking structure and component layout design is a technical challenge that needs to be addressed in this embodiment.
[0055] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0056] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A multi-board stacked PXIe bus controller based on functional unit hierarchies, characterized in that, include: Processor unit, memory unit, interface circuit unit, and interface conversion unit; The processor unit is connected to the memory unit and the interface circuit unit via communication connections. The interface circuit unit is connected to the interface conversion unit; The processor unit, memory unit, interface circuit unit, and interface conversion unit are respectively disposed on at least two independent printed circuit boards, and the circuit boards are fixed together by board-to-board connectors to form a layered stacked structure.
2. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 1, characterized in that, The interface circuit unit includes a PCIe bus communication interface, which is connected to the processor unit and is used to realize data interaction and power supply access with the PXIe chassis backplane.
3. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 1, characterized in that, The processor units and memory units are stacked together via board-to-board connectors; The processor unit and the interface circuit unit are stacked together via board-to-board connectors; The interface conversion unit and the interface circuit unit are stacked using PCB or cable.
4. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 1, characterized in that, It also includes a heat dissipation component, which is attached to the surface of the processor unit.
5. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 1, characterized in that, The processor unit includes a processor and a bridge chip; the processor and the bridge chip exchange data and instructions.
6. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 5, characterized in that, The memory unit provides DDR interface memory for the processor, used for temporary storage of program instructions and data.
7. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 1, characterized in that, The interface circuit unit is an interface expansion circuit between the processor and the bridge chip, used to provide signal interfaces to the outside world. It also includes a hard disk interface, a display interface, a network communication interface, an RS232 serial communication interface, a USB interface, and a PXI bus trigger system circuit.
8. A multi-board stacked PXIe bus controller based on functional unit layering according to claim 1, characterized in that, The interface conversion unit adopts a general-purpose physical interface for computers, and all general-purpose physical interfaces of the interface conversion unit are brought out through the front panel.