I2c bus signal delay transmission control method and delay transmission control system

By adjusting the delays of the serial clock and data signals in the I2C bus system, and utilizing counters and XOR logic operations, the data anomaly problem caused by timing errors in the I2C bus was solved, achieving correct data transmission and reception timing and enhancing the system's compatibility and adaptability.

CN122450883APending Publication Date: 2026-07-24AMICRO SEMICONDUCTOR CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
AMICRO SEMICONDUCTOR CO LTD
Filing Date
2025-01-16
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

In the I2C bus system, timing errors such as clock stretching, unreasonable phase difference between clock and data signals, noise, and timing jitter can cause abnormal data transmission and reception. Furthermore, I2C devices from different manufacturers may have specific timing requirements, and existing technologies have not been able to effectively solve these problems.

Method used

In the I2C bus signal delay transmission control method, a counter is used to count the level length of the serial clock signal, and the delay of the serial clock enable signal and the data signal is adjusted through XOR logic operation to ensure that the signal phase difference is within a reasonable range. The delay transmission control system includes an I2C bus signal generator, a preprocessing module, a delay logic controller, a serial clock enabler, and an I2C configuration register to realize the line delay adjustment of the I2C clock bus and data bus.

Benefits of technology

It effectively solves the phase difference problem caused by line delay in the I2C bus, ensures correct data transmission and reception timing, adapts to different types of I2C devices, enhances system compatibility and flexibility, and avoids data anomalies.

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Abstract

The application discloses an I2C bus signal delay transmission control method and a delay transmission control system. The I2C bus signal delay transmission control method comprises the following steps: under the enablement of a pre-configured serial clock enable signal SCL_oen, a first pre-processing serial clock signal SCL_sin is generated, then the length of the level of the first pre-processing serial clock signal SCL_sin is counted by a counter, until a preset level count value is counted, then the delay clock enable signal ~SCL_oen is controlled to perform an exclusive-OR logical operation with the first pre-processing serial clock signal SCL_sin, after the result of the exclusive-OR logical operation is a high level, under the enablement of the delay clock enable signal ~SCL_oen, a serial data signal is generated, and is transmitted to a receiver according to an I2C protocol; and / or, a second pre-processing serial clock signal transmitted from outside is acquired, a second pre-processing serial data signal is sampled according to the rising edge of the second pre-processing serial clock signal, and a serial data enable signal is generated by triggering the second pre-processing serial data signal.
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