Chip layout track generation method, model training method, and chip layout method

Abstract

Embodiments of the present application disclose a chip layout trajectory generation method, a model training method and a chip layout method. The method comprises: generating a layout state feature according to a current layout state of a first circuit netlist of a chip layout; generating a style control feature vector and a style control reward function under the current layout state according to a specified style control parameter during the chip layout; generating a chip layout action according to the layout state feature and the style control feature vector; and generating a chip layout trajectory under the style control parameter according to the layout state feature, the style control feature vector, the chip layout action and the style control reward function. By specifying the style control parameter during the generation of the chip layout trajectory, controllable generation of the chip layout trajectory in a style can be realized, and the chip layout style and the circuit netlist can be decoupled and independently adjusted.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method for generating chip layout trajectories, a model training method, and a chip layout method. Background Technology

[0002] Chip placement is a core step in the physical design of very large-scale integrated circuits (VLSI). The goal of chip placement is to allocate the functional modules within the chip to reasonable locations on the chip layout while meeting design constraints, in order to achieve design specifications.

[0003] Existing technologies using deep learning for chip placement typically mix circuit structure information and optimization objectives in the same input or latent space. These methods lack explicit decoupling between chip placement trajectories and style control parameters. Consequently, when style control requirements change, the chip placement model needs to be retrained, making it impossible to flexibly control chip placement preferences during inference through style control condition injection. Summary of the Invention

[0004] This invention provides a method for generating chip layout trajectories, a model training method, and a chip layout method, so as to achieve decoupling and independent adjustment of chip layout style and circuit netlist, and realize the style controllable generation of chip layout trajectory.

[0005] According to one aspect of the present invention, a method for generating chip layout traces is provided, the method comprising: Layout state features are generated based on the current layout state of the first circuit netlist of the chip layout; Generate a style control feature vector and a style control reward function in the current layout state based on the style control parameters specified during chip layout. Based on the layout state features and the style control feature vector, a chip layout action is generated; Based on the layout state features, the style control feature vector, the chip layout action, and the style control reward function, a chip layout trajectory under style control parameters is generated.

[0006] According to one aspect of the present invention, a chip layout model training method is provided, the method comprising: Graph structure encoding is performed on the second circuit netlist during offline chip layout training to obtain circuit feature vectors; Based on the style control parameters of the second circuit netlist, a style control feature vector is generated; The circuit feature vector, the style control feature vector, and the layout states and chip layout actions of each chip layout trajectory in the preset style control layout trajectory set are input into the chip layout model for model training. The chip layout trajectories in the preset style control layout trajectory set are obtained using the chip layout trajectory generation method described in any embodiment of the present invention.

[0007] According to one aspect of the present invention, a chip layout method is provided, the method comprising: The fourth circuit netlist to be laid out is graph-structured to obtain circuit feature vectors. Generate a style control feature vector based on the specified style control parameters corresponding to the fourth circuit netlist; The circuit feature vector and the style control feature vector are input into the chip layout model, and the chip layout action sequence is output through the chip layout model; The chip layout model is trained using the chip layout model training method described in any embodiment of the present invention.

[0008] According to another aspect of the present invention, a chip layout trajectory generation apparatus is provided, the apparatus comprising: The first layout state feature generation module is used to generate layout state features based on the current layout state of the first circuit netlist of the chip layout. The style information generation module is used to generate a style control feature vector and a style control reward function in the current layout state based on the style control parameters specified during chip layout. The chip layout action generation module is used to generate chip layout actions based on the layout state features and the style control feature vector; The chip layout trajectory generation module is used to generate a chip layout trajectory under style control parameters based on the layout state features, the style control feature vector, the chip layout action, and the style control reward function.

[0009] According to another aspect of the present invention, a chip layout model training apparatus is provided, the apparatus comprising: The first circuit feature vector determination module is used to perform graph structure encoding on the second circuit netlist during chip layout offline training to obtain circuit feature vectors. The first style control feature vector generation module is used to generate style control feature vectors based on the style control parameters of the second circuit netlist. The chip layout model training module is used to input the circuit feature vector, the style control feature vector, and the layout states and chip layout actions of each chip layout trajectory in the preset style control layout trajectory set into the chip layout model for model training. The chip layout trajectories in the preset style control layout trajectory set are obtained using the chip layout trajectory generation method described in any embodiment of the present invention.

[0010] According to one aspect of the present invention, a chip layout apparatus is provided, the apparatus comprising: The second circuit feature vector determination module is used to perform graph structure encoding on the fourth circuit netlist to be laid out in the chip to obtain the circuit feature vector. The second style control feature vector generation module is used to generate a style control feature vector based on the specified style control parameters corresponding to the fourth circuit netlist. The first chip layout action sequence determination module is used to input the circuit feature vector and the style control feature vector into the chip layout model, and output the chip layout action sequence through the chip layout model; The chip layout model is trained using the chip layout model training method described in any embodiment of the present invention.

[0011] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to said at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to execute the chip layout trajectory generation method, chip layout model training method, or chip layout method according to any embodiment of the present invention.

[0012] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the chip layout trajectory generation method, chip layout model training method, or chip layout method described in any embodiment of the present invention.

[0013] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the chip layout trajectory generation method, chip layout model training method, or chip layout method described in any embodiment of the present invention.

[0014] The technical solution of this invention generates layout state features based on the current layout state of the first circuit netlist of the chip layout; generates a style control feature vector and a style control reward function in the current layout state based on the style control parameters specified during chip layout; generates chip layout actions based on the layout state features and the style control feature vector; and generates a chip layout trajectory under the style control parameters based on the layout state features, the style control feature vector, the chip layout actions, and the style control reward function. This solves the problem of not being able to establish an explicit decoupling relationship between the circuit netlist and the layout style in chip layout, enabling controllable generation of the chip layout trajectory style and achieving decoupled independent adjustment of the chip layout style and the circuit netlist.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a chip layout trajectory generation method according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a chip layout according to Embodiment 1 of the present invention; Figure 3 This is a flowchart of a chip layout trajectory generation method according to Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of a chip layout trajectory generation structure provided in Embodiment 2 of the present invention; Figure 5 This is a flowchart of a chip layout model training method provided in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of a chip layout model training method according to Embodiment 3 of the present invention; Figure 7 This is a schematic diagram of the structure of a sequence modeling module based on a causal self-attention mechanism according to Embodiment 3 of the present invention; Figure 8 This is a flowchart of a chip layout model training method provided in Embodiment 4 of the present invention; Figure 9This is a flowchart of a chip layout method provided in Embodiment 5 of the present invention; Figure 10 This is a schematic diagram of a chip layout according to Embodiment 5 of the present invention; Figure 11 This is a schematic diagram of a chip layout trajectory generation device according to Embodiment Six of the present invention; Figure 12 This is a schematic diagram of the structure of a chip layout model training device according to Embodiment Six of the present invention; Figure 13 This is a schematic diagram of a chip layout device according to Embodiment Six of the present invention; Figure 14 This is a schematic diagram of the structure of an electronic device that implements the method of the embodiments of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Example 1 Figure 1This is a flowchart illustrating a chip layout trajectory generation method according to Embodiment 1 of the present invention. This embodiment is applicable to situations where a chip layout style is specified based on chip layout requirements when generating chip layout trajectories. The chip layout trajectory generated in this embodiment can be used for offline or online training of chip layout models. This chip layout trajectory generation method can be executed by a chip layout trajectory generation device. This chip layout trajectory generation device can be implemented in hardware and / or software. The chip layout trajectory generation device can be configured in an electronic device, such as a computer, mobile phone, or chip design equipment, etc. Figure 1 As shown, the method includes: Step 110: Generate layout state features based on the current layout state of the first circuit netlist of the chip layout.

[0021] The first circuit netlist can be used to generate chip layout trajectories. These trajectories can then be used for subsequent chip layout model training. The circuit netlist can be a wiring specification for circuit components in a chip design. For example, a circuit netlist describes the connection topology between chip modules, including the size of each module, pin offsets, and net connections, but does not contain any spatial layout information. Circuit netlists can be constructed from open-source chip circuits, such as academic or industrial circuits.

[0022] In chip placement, macrocells can be placed at each time step to obtain the current placement state at that time step. Initially, the current placement state can be empty, meaning no macrocells have been placed. Placement state features can be characteristic information representing the current placement state of the chip. For example, feature extraction can be performed on the current placement state to obtain placement state features. Feature extraction can be implemented using a convolutional neural network. For instance, the current placement state can be represented by a multi-channel mask image. By using a convolutional neural network to extract image features from the multi-channel mask image, the placement state features can be obtained. Optionally, the multi-channel mask image may include connection cost information, placed area information, and unplaced area information.

[0023] Optionally, a layout state feature is generated based on the current layout state of the first circuit netlist of the chip layout, including: extracting features based on the current layout state of the first circuit netlist of the chip layout to obtain the connection cost features, placed area features, and unplaced area features of the current layout state; concatenating the connection cost features, placed area features, and unplaced area features to obtain the concatenated layout state feature; and extracting features again from the concatenated layout state feature to obtain the layout state feature of the current layout state.

[0024] The interconnect cost feature of the current layout state can be the interconnect overhead corresponding to different positions on the current chip layout. The interconnect overhead can be the pre-calculated bus increase caused by placing the module to be placed at each possible position on the chip canvas. For example, the interconnect cost feature can be used to characterize the degree of change in half-perimeter wirelength (HWPL) caused by placing the macrocell to be placed at different candidate positions in the current layout state.

[0025] For example, Figure 2 This is a schematic diagram of a chip layout according to Embodiment 1 of the present invention. Figure 2 As shown, chip layout is performed on a two-dimensional planar area, such as the chip layout area can be defined as... .in, This represents the maximum width of the layout area along the horizontal X-axis. This represents the maximum height of the placement area along the Y-axis. Chip placement involves allocating space for all macrocells within the placement area to meet design constraints and optimize placement quality. Macrocells are the basic objects in chip placement; they are functional modules with dimensions larger than a preset value. For example... Figure 2 As shown, for the i-th macrounit, it can be denoted as In the formula, The coordinates of the macrocell center. These are the width and height of the macrocell, respectively. This refers to the macrocell index. In chip layout, a macrocell can be viewed as a rectangular object in a two-dimensional plane, its spatial position uniquely determined by its center coordinates. A macrocell may contain several pins used to describe electrical connections. For example, a macrocell... The number of pins included is For its k-th pin, it can be represented as The corresponding spatial coordinates are In the formula, For pins absolute coordinates, For pins Geometric offset relative to the center of the macrocell The pin positions are determined by both the macrocell location and its internal structure. For example... Figure 2 As shown, a wire is a basic building block in a circuit netlist, used to describe the electrical connections between multiple pins. For example, if a chip has m wires, the set is defined as follows: For the j-th connection, its pin set is as follows: In the formula, This represents the number of pins connected to wire j. For the l-th pin of connection j, .

[0026] like Figure 2 As shown, for the j-th connection, its HPWL is In the formula, Let be the spatial coordinates of pin p. The overall bus length of the chip layout is... HPWL is the semi-perimeter of the smallest bounding rectangle of the pin set corresponding to each connection. HPWL can approximate the actual chip wiring length.

[0027] The placed region feature can be a binary mask indicating whether different positions on the current chip layout allow the placement of the macrocell to be placed. The placed region feature can characterize whether placing the macrocell to be placed at each candidate position in the current layout state will cause overlap (i.e., violate the no-overlap hard constraint). For example, the chip canvas can be divided into a uniform two-dimensional grid structure. , This is the grid index along the Y-axis. The grid index is located along the horizontal X-axis. The entire canvas contains a total of [number missing] grid elements. Each cell (grid cell) This corresponds to a rectangular sub-region on the canvas. Each grid position on the chip canvas is marked with "1" to indicate that a macrocell can be safely placed at that position (without overlapping with other modules); marked with "0" to indicate that placement is prohibited (which would result in illegal overlap). By using the features of the placed areas, the legality of the layout (i.e., no overlap) can be enforced, and the action search space of the policy network can be narrowed to the legal area.

[0028] Unplaced area features can be binary masks indicating whether different grid locations on the current chip canvas are occupied by placed modules. These features represent the actual spatial occupancy distribution (i.e., a "topographical map") of the chip in the current layout state. For example, each grid cell on the chip canvas is marked as "1" to indicate that the location is covered by a macrocell, and "0" to indicate that it is free. The core function of unplaced area features is to provide global spatial context information, enabling the chip layout to perceive the density of the overall layout and supporting accurate modeling of the actual physical occupancy of non-unit-size modules.

[0029] After concatenating the connection cost features, placed area features, and unplaced area features, a convolutional neural network can be used to extract features to obtain the layout state features of the current layout state. In the formula, For connection cost characteristics, For the characteristics of the area that has been placed, For the unplaced region features, Concat means concatenation, and CNN means convolutional neural network.

[0030] By considering the characteristics of interconnect cost, placed area, and unplaced area in the layout state features, the current layout state of the circuit netlist can be accurately identified, which facilitates the accurate generation of chip layout actions, avoids violating the hard constraints of chip design, and optimizes the chip layout.

[0031] Step 120: Generate style control feature vectors and style control reward functions in the current layout state based on the style control parameters specified during chip layout.

[0032] Style control parameters can represent the preference for different design metrics during multi-objective optimization of chip layout. For example, different weights can be assigned to each design metric, resulting in different layout optimization strategies. For instance, in some design stages, prioritizing reducing trace length is necessary, while in others, routing feasibility or layout uniformity is more important. This invention, by using style control parameters as adjustable information, can express multi-objective optimization preferences and achieve flexible control over the chip layout results.

[0033] Optionally, style control parameters include at least two of the following: chip layout parameters such as line length, congestion, density, power consumption, performance, area, timing metrics, thermal distribution, and power integrity. A style control feature vector can be generated for each style control parameter. The style control feature vector can be obtained by mapping the preference information of each design metric, such as weights, into a high-dimensional feature space using a fully connected neural network. A style control reward function can be generated based on the style control parameters and the current layout state. The style control reward function characterizes the layout quality under the current layout state.

[0034] For example, the reward function for chip placement line length can be related to the half-circumference line length. The reward function for chip placement congestion can be related to the congestion level of the chip placement area. The reward function for dense chip placement can be related to the macrocell coverage area of ​​the chip placement area. The reward function for chip placement power consumption can be related to the device switching frequency of the chip placement area. The reward function for chip placement performance can be related to the path delay or time margin of the chip placement area. The reward function for chip placement area can be related to the area occupied by the entire chip placement. The reward function for chip placement timing metrics can be related to the path delay or time margin of the chip placement area. The reward function for chip placement thermal distribution can be related to the power density of the chip placement area. The reward function for chip placement power integrity can be related to the voltage drop, current density, or power supply noise of the chip placement area. For a specified design metric, the style control reward function for the current placement state can be obtained by weighted summing the set preference (style control parameters) with the quantified value (reward function) of the design metric under the current placement state.

[0035] For example, consider style control parameters that include line length, congestion, and density parameters in chip layout. Style control parameters can be expressed as... .in, This characterizes the chip designer's relative preference for line length, congestion, and density. The style control feature vector is... This indicates that style control parameters are mapped to high-dimensional features. This is a mapping function, such as mapping via a convolutional network. The reward function for the chip placement line length at each time step t is... . Indicates the layout state The length of the lower half-circumference line.

[0036] Chip layout congestion can be addressed by performing proxy routing on each connection, calculating and smoothing the horizontal or vertical usage of each cell, and then taking the average congestion value of the top 10% of cells within a certain proportion of the congestion ranking. In the formula, For chip layout congestion in layout state S, Avg represents the mean operation. This represents the congestion value of the top 10% of cells. The reward function for chip layout congestion at each time step t is... .

[0037] Density can be calculated as the ratio of the area of ​​macro cells placed within each cell to the total area of ​​that cell. , This represents a cell (grid). The chip layout density can be the maximum density of each cell, i.e. The reward function for chip layout density at each time step t is: , This indicates the chip layout density under layout state S.

[0038] Style control reward function can be When using the style control reward function to generate chip layout trajectories, the style control reward function can be weighted and summed into a scalar based on the style control parameters. Alternatively, scalarization methods, nonlinear utility functions, frontier preference sampling methods, or learning-based preference modeling methods can be used to transform multi-objective optimization into a single optimization signal or conditional control signal.

[0039] By generating style control feature vectors from style control parameters, chip layout trajectories under a specified style can be generated, decoupling the chip layout style from the circuit netlist display and achieving style controllability. Generating a style control reward function facilitates subsequent generation of chip layout trajectories under a specified style.

[0040] Step 130: Generate chip layout actions based on layout state features and style control feature vectors.

[0041] Chip placement can be implemented using neural network models or reinforcement learning networks. For example, placement state features can be used... Style control feature vectors are input into a predefined policy network. In the process, the chip layout action is obtained. The pre-trained policy network can be pre-trained or trained through multiple iterations.

[0042] Step 140: Generate the chip layout trajectory under the style control parameters based on the layout state features, style control feature vector, chip layout action, and style control reward function.

[0043] The obtained chip placement actions can be evaluated using a style control reward function to select target chip placement actions and ultimately obtain the chip placement trajectory. For example, a preset value network can be used to obtain the value of the current placement state based on placement state features and style control feature vectors. The chip placement action can then be determined based on this value, ultimately generating the chip placement trajectory. The style control reward function can be used to adjust the parameters of the preset value network, and further, to adjust the preset policy network.

[0044] For example, chip layout can be modeled as a style-conditional Markov decision process. . For the state space, the layout state features Describes the location information of currently placed macrocells, which may include, for example, a three-channel image: connection cost features, placed region features, and unplaced region features, with a resolution of [resolution missing]. , . For the action space, chip layout actions This represents the placement decision for the current macrocell at time step t, and can be expressed as a two-dimensional discrete coordinate system. , This indicates that the macro cell to be placed will be placed in the grid coordinates. . For style control reward function, i.e. . These are style control parameters. This is the first circuit netlist. A style-controlled reward function provides immediate rewards to the layout states of the circuit netlist under a specified style, thereby generating a chip layout trajectory consisting of a sequence of chip layout actions. The chip layout trajectory can include layout states, layout actions, and reward sequences.

[0045] By generating chip layout actions based on layout state features and style control feature vectors, calculating rewards for the generated chip layout actions through a style control reward function, updating the chip layout actions, and finally generating chip layout trajectories under style control parameters, the style-controllable generation of chip layout trajectories is achieved, decoupling the layout style from the circuit netlist display.

[0046] The technical solution of this embodiment generates layout state features based on the current layout state of the first circuit netlist in chip layout; generates style control feature vectors and style control reward functions in the current layout state based on style control parameters specified during chip layout; generates chip layout actions based on the layout state features and style control feature vectors; and generates chip layout trajectories under style control parameters based on the layout state features, style control feature vectors, chip layout actions, and style control reward functions. This solves the problem of not being able to establish an explicit decoupling relationship between the circuit netlist and the layout style in chip layout, enabling style-controllable generation of chip layout trajectories and achieving independent adjustment of chip layout style and circuit netlist decoupled. Flexible style layout trajectory generation is achieved through independent style control parameter adjustment. By introducing style conditions for multi-objective optimization of chip layout, high-quality layout trajectory data covering different optimization preferences can be generated, providing a data foundation for subsequent offline learning of chip layout models.

[0047] Example 2 Figure 3 This is a flowchart of a chip layout trajectory generation method according to Embodiment 2 of the present invention. This embodiment is a further refinement of the above technical solution, and the technical solution in this embodiment can be combined with various optional solutions in one or more of the above embodiments. Figure 3 As shown, the method includes: Step 310: Generate layout state features based on the current layout state of the first circuit netlist of the chip layout.

[0048] Optionally, a layout state feature is generated based on the current layout state of the first circuit netlist of the chip layout, including: extracting features based on the current layout state of the first circuit netlist of the chip layout to obtain the connection cost features, placed area features, and unplaced area features of the current layout state; concatenating the connection cost features, placed area features, and unplaced area features to obtain the concatenated layout state feature; and extracting features again from the concatenated layout state feature to obtain the layout state feature of the current layout state.

[0049] Step 320: Generate style control feature vectors and style control reward functions in the current layout state based on the style control parameters specified during chip layout.

[0050] Optionally, style control parameters may include at least two of the following: chip layout line length, congestion, density, power consumption, performance, area, timing metrics, thermal distribution, and power integrity parameters.

[0051] Step 330: Generate chip layout actions based on layout state features and style control feature vectors.

[0052] Figure 4 This is a schematic diagram of a chip layout trajectory generation structure provided by Embodiment 2 of the present invention. Figure 4 As shown, chip layout actions can be generated by concatenating layout state features and style control feature vectors and inputting them into a preset strategy network.

[0053] Step 340: Update the current layout state of the first circuit netlist according to the chip layout action, and return to the step of generating layout state features according to the current layout state of the first circuit netlist, until the chip layout is completed and the current layout trajectory of the current strategy is obtained.

[0054] By returning to step 310, the complete chip placement for the current round can be completed. Subsequent steps can be performed based on the placement states, actions, and style control reward function within the complete chip placement trajectory to evaluate the current placement trajectory. Through iterative execution, the final chip placement trajectory that conforms to the style control parameters can be obtained.

[0055] Step 350: Generate the value vector corresponding to each layout state based on the layout state features and style control feature vectors of each layout state in the current layout trajectory of the current strategy.

[0056] For example, such as Figure 4 As shown, inputting layout state features and style control feature vectors into a preset value network yields a value vector. In application, the value vectors corresponding to multiple style control parameters can be processed as follows: Weighted merging, that is, the value vector corresponding to the layout state is .

[0057] Step 360: Determine the strategy parameters based on the value vectors of each layout state in the current layout trajectory of the current strategy and the style control reward function.

[0058] The strategy parameters are used to generate chip placement actions. These parameters can be those from a preset strategy network. The value vector of the placement state and the style control reward function are used to evaluate the advantages of the placement actions. For example, the value vector and style control reward function can be used to evaluate the merits of each placement state, and the merits of each placement state can be used to evaluate the merits of the entire placement trajectory. Therefore, the strategy parameters of the preset strategy network are adjusted based on the merits of the placement trajectory. For example, when the placement trajectory performance is good, the strategy parameters are updated to allow the preset strategy network to learn placement trajectories with better performance. When updating the strategy parameters of the preset strategy network, the update range of the strategy parameters can be limited to avoid performance instability caused by excessive policy shifts. The strategy parameters can be updated by constructing a loss function for the placement trajectory based on the value vector and style control reward function, and then using backpropagation through the loss function.

[0059] Optionally, strategy parameters are determined based on the value vector of each layout state in the current layout trajectory of the current strategy and the style control reward function, including: determining the comprehensive advantage function of each layout state of the current strategy based on the value vector of each layout state in the current layout trajectory of the current strategy, the style control reward function, the discount factor, the style control parameter, and the adjustment parameter of the time step; and determining strategy parameters based on the comprehensive advantage function of each layout state of the current strategy.

[0060] Among them, discount factor Used to measure the importance of future returns. Adjustment parameters for the time step. The style control parameters are used to control the rate of error decay at different time steps during the accumulation process. These parameters are used to weight and combine the advantages of each chip design metric. By performing arithmetic operations on the value vector of the layout state, the style control reward function, the discount factor, the style control parameters, and the time step adjustment parameters based on the effects of these parameters, the comprehensive advantage function for each layout state of the current strategy can be determined.

[0061] Optionally, based on the value vector, style control reward function, discount factor, style control parameters, and time step adjustment parameters corresponding to each layout state in the current layout trajectory of the current strategy, the comprehensive advantage function of each time step of the current strategy is determined, including: determining the temporal difference error at the current moment based on the value vector, discount factor, and style control reward function corresponding to the layout state at the current moment and the layout state at the next moment, respectively; and calculating the accumulated temporal difference error from the current moment to the end moment of the current layout trajectory based on the style control parameters, discount factor, and time step adjustment parameters, as the comprehensive advantage function of the layout state at the current moment.

[0062] The discount factor adjusts the value vector of the layout state at the next time step. The difference between the adjusted value and the value vector of the layout state at the current time step, combined with the style control reward function, determines the timing difference error at the current time step. For example, for the i-th chip design metric (the i-th parameter in style control), the timing difference error at time t is... , For style control reward function, Layout state The value vector below.

[0063] The overall advantage function of the current layout state is: This indicates that the advantages of each chip design metric are weighted and accumulated through style control parameters. Among them, Let represent the accumulated timing difference error of the i-th chip design specification from the current time to the end time of the current placement trajectory, and T represent the total time of the current placement trajectory. By considering the time steps... Adjustment parameters of time step The impact on time-series differencing errors can lead to a larger contribution of error in closer timeframes, while the contribution of error in farther timeframes gradually decreases. The dominance function achieves a smooth transition between single-step estimation and multi-step accumulation. When the variance is small, it tends to be more inclined towards single-step estimation and has lower variance; when When the value is larger, it is closer to a multi-step cumulative estimate and can better reflect the long-term return trend.

[0064] The strategy parameters can be determined based on the comprehensive advantage function of each layout state under the current strategy. For example, a loss function can be constructed based on the comprehensive advantage function of each layout state under the current strategy, and the strategy parameters can be updated through backpropagation using the loss function. By considering the advantage influence of style control parameters on the layout state, the preset strategy network can dynamically weigh multiple chip design metrics based on the given style control parameters, thereby achieving chip layout trajectory generation under a specified style.

[0065] Optionally, strategy parameters are determined based on the comprehensive advantage function of each layout state of the current strategy, including: generating strategy parameters based on the pruning coefficient, the probability ratio of the current strategy and the historical strategy at the same time step, and the comprehensive advantage function.

[0066] like Figure 4 As shown, the probability ratio and the comprehensive advantage function are used to update the policy parameters of the preset policy network, thereby realizing the updated generation of chip placement actions. When updating the policy parameters, the policy update magnitude can be limited by the pruning coefficient to avoid excessive deviation of the new policy from the old policy.

[0067] Wherein, the probability ratio of the current strategy to the historical strategy at the same time step is . .in, For the current strategy The preset strategy network outputs the probability of chip layout actions when the layout state and style control feature vector are input at time step t. Historical strategy The preset strategy network outputs the probability of chip layout actions when the layout state and style control feature vector are input at time step t. The current strategy and the historical strategy can be the chip layout trajectory obtained in the current complete layout cycle and the chip layout trajectory obtained in the previous complete layout cycle, respectively, by iteratively executing steps 310 to 340. Initially, the current strategy and the historical strategy can be the same.

[0068] Policy parameters can be updated by constructing a loss function through the product of the probability ratio and the overall advantage function, and then backpropagating using the gradient of the loss function. A pruning coefficient can be used to constrain the probability ratio. For example, the loss function of the pre-defined policy network is... . This indicates that the mean value is calculated for each time step. This represents the policy parameters in the current policy. This represents the pruning function, which adds the probability ratio to the loss function of the predefined policy network. Limited to the range Inside, This is the clipping factor. That is, when... When the value exceeds the specified range, it is truncated to the boundary value; when it falls within the range, it remains unchanged. This pruning operation effectively limits the range of probability ratio changes during policy updates, preventing excessive deviations in the current policy relative to historical policies. When the policy update magnitude is too large, the pruning term will affect the loss function. Constraints are introduced to make the optimization process more conservative, thereby preventing training instability or performance degradation. Furthermore, the loss function... The operation of taking the minimum value in the middle makes the dominant function... Regardless of whether the result is positive or negative, a more conservative update direction is always adopted to ensure the stability and robustness of the strategy optimization process.

[0069] Step 370: When the strategy parameter update termination condition is met, the chip layout trajectory corresponding to the target strategy parameter is taken as the chip layout trajectory under the style control parameter.

[0070] The termination condition for policy parameter updates can be reaching the required number of policy parameter update iterations, or the loss function. Convergence. The policy parameters at the point where the policy parameter update terminates are used as the target policy parameters. The sequence of chip placement actions generated based on the current placement state of the first circuit netlist and the style control feature vector using the target policy parameters is used as the chip placement trajectory under the style control parameters.

[0071] like Figure 4 As shown, when generating the chip layout trajectory, a preset value network can also be trained to improve the fitting accuracy of the value vector. Optionally, after determining the strategy parameters based on the value vectors of each layout state in the current layout trajectory of the current strategy and the style control reward function, the method further includes: determining the reward function of each layout state in the current layout trajectory of the current strategy based on the style control parameters; generating value parameters based on the value vectors of each layout state in the current layout trajectory of the current strategy and the reward function, wherein the value parameters are used to generate the value vectors corresponding to each layout state.

[0072] For example, the reward function at time step t is , This represents the reward corresponding to the i-th chip design metric in the style control parameters. The reward function can be determined in several ways. For example, the reward function can be related to one or more of the comprehensive advantage function, value vector, and style control reward function. In other words, the reward function can be determined based on at least one of the comprehensive advantage function, value vector, and style control reward function.

[0073] Optionally, based on style control parameters, the reward function for each layout state in the current layout trajectory of the current strategy is determined, including: determining the reward function for each layout state based on the comprehensive advantage function and value vector of each layout state in the current layout trajectory of the current strategy; or, calculating the accumulated reward from the corresponding time of the layout state to the end time of the current layout trajectory based on the style control reward function and discount factor of each layout state in the current layout trajectory of the current strategy, and using it as the reward function for the layout state.

[0074] For example, the reward function is , This indicates that the i-th chip design parameter in the style control parameters is in state. and style control feature vectors The value of what is below. This represents the overall advantage function of the i-th chip design metric in the style control parameters at time step t.

[0075] Alternatively, the reward function is In the formula, As a discount factor, This indicates the i-th chip design specification in the style control parameters at time step. Style control reward function.

[0076] Training a pre-defined value network allows the output to approximate a reward function. In this embodiment of the invention, a loss function for the pre-defined value network can be constructed based on the value vector and the reward function to update the parameters of the pre-defined value network, i.e., the value parameters. For example, taking style control parameters including chip layout line length, congestion, and density as an example, the loss function of the pre-defined value network is: By using a pre-defined loss function for the value network, backpropagation can be performed to update the value parameters, thereby improving the fitting accuracy of the value vector. The pre-defined loss function can utilize long-term cumulative return information while reducing the variance introduced by directly using long-sequence returns, thus improving the stability of value vector learning. In this embodiment of the invention, the pre-defined value network can learn the long-term returns of different optimization objectives and provide an accurate benchmark estimate for the multi-objective comprehensive advantage function, thereby ensuring the stability and effectiveness of the strategy optimization process under multi-objective trade-offs.

[0077] The chip layout trajectory generation method described above can be used to generate layout trajectories for multiple academic and / or industrial circuits under different style control parameters, ultimately resulting in an offline dataset of chip layouts. In the formula To specify style control parameters The chip layout trajectory at that time, For style control feature vectors, , , These represent the layout state, chip layout action, and style control reward function at time step T, respectively, where T is the total number of time steps for the chip layout trajectory. The offline dataset can be used for offline or online generation of chip layout models to achieve style-controlled chip layout.

[0078] The technical solution of this invention involves generating layout state features based on the current layout state of the first circuit netlist for chip placement; generating a style control feature vector and a style control reward function in the current layout state based on the style control parameters specified during chip placement; generating chip placement actions based on the layout state features and the style control feature vector; updating the current layout state of the first circuit netlist based on the chip placement actions; and returning to the step of generating layout state features based on the current layout state of the first circuit netlist, until chip placement is completed to obtain the current layout trajectory of the current strategy; and then, based on the layout state features and style control feature vectors of each layout state in the current layout trajectory of the current strategy, ... The system generates value vectors corresponding to each layout state; based on the value vectors of each layout state in the current layout trajectory of the current policy and the style control reward function, it determines the policy parameters; the policy parameters are used to generate chip layout actions; when the policy parameter update termination condition is met, the chip layout trajectory corresponding to the target policy parameters is used as the chip layout trajectory under the style control parameters. This solves the problem of not being able to establish an explicit decoupling relationship between the circuit netlist and the layout style in chip layout, enabling style-controllable generation of chip layout trajectories, and achieving decoupling and independent adjustment of chip layout style and circuit netlist. The decoupling design ensures that circuit features are not disturbed when style switching, improving the interpretability of model predictions.

[0079] Example 3 Figure 5 This is a flowchart of a chip layout model training method according to Embodiment 3 of the present invention. This embodiment is applicable to situations where offline training of the chip layout model is performed when a chip layout style is specified according to chip layout requirements. The chip layout model generated in this embodiment can be used for chip layout based on a circuit netlist. This chip layout model training method can be executed by a chip layout model training device. The chip layout model training device can be implemented in hardware and / or software. The chip layout model training device can be configured in an electronic device, such as a computer, mobile phone, or chip design equipment, etc. Figure 5 As shown, the method includes: Step 510: Perform graph structure encoding on the second circuit netlist during offline chip layout training to obtain circuit feature vectors.

[0080] The second circuit netlist can be the same as the first circuit netlist, meaning the chip layout model is retrained using the circuit generated during chip layout trajectory generation. Alternatively, the second circuit netlist can be different from the first circuit netlist. There are various ways to perform graph structure encoding on the circuit netlist. For example, encoding methods that can extract node connectivity and semantic information, such as graph neural networks, graph Transformer structure modeling, sequence modeling, or variational graph autoencoders, can be used to achieve feature encoding of the circuit topology. For instance, the circuit netlist can be converted into an undirected graph. In the formula For nodes such as macrocells, standard cells, or registers, Edges are the connections in the circuit netlist. For undirected graphs, the circuit feature vectors can be obtained by graph structure encoding using a variational graph autoencoder (VGAE). .in, Let N be the hidden variable of node i in the circuit netlist c output by the encoder, and N be the total number of nodes. In graph-structured coding, the variational lower bound can be optimized. This enables VGAE training. Among other things, These are the trainable parameters for VGAE. This indicates that circuit c is sampled from the circuit netlist dataset D. This is the adjacency matrix of the circuit netlist. It is a node feature matrix (containing macrocell width, height, area, and arrangement order, etc.). These are the hidden node variables output by the encoder; For the decoder, reconstruct the adjacency matrix from the latent variables; It is the prior distribution; The encoder encodes the graph structure into a latent variable distribution; The KL divergence is used to constrain latent variables to approximate a standard normal distribution. It represents the expected value, i.e., the average or mean calculation.

[0081] Step 520: Generate style control feature vectors based on the style control parameters of the second circuit netlist.

[0082] There are various ways to inject style control parameters, such as vector concatenation, high-dimensional vector mapping, conditional normalization, cross-attention mechanism, cue vector, or prefix modulation.

[0083] Step 530: Input the circuit feature vector, style control feature vector, and the layout states and chip layout actions of each chip layout trajectory in the preset style control layout trajectory set into the chip layout model for model training.

[0084] Figure 6 This is a schematic diagram of a chip layout model training method provided in Embodiment 3 of the present invention. Figure 6 As shown, graph structure encoding is performed on the circuit netlist to obtain the circuit feature vector. The style control parameters are encoded to obtain the style control feature vector. . , The layout state of each chip layout trajectory is controlled by a preset style and is set together with the layout trajectory of each chip (which can be defined by layout state features). (Indication) and chip layout actions These can be input together into the chip layout model for chip layout action prediction of the circuit netlist, and the chip layout action sequence of the circuit netlist can be obtained through sequence regression. By iteratively executing each chip layout trajectory in the preset style-controlled layout trajectory set, offline training of the chip layout model can be achieved.

[0085] The chip layout trajectories in the preset style-controlled layout trajectory set are obtained using the chip layout trajectory generation method described in any embodiment of the present invention. Alternatively, the preset style-controlled layout trajectory set can be generated through electronic automation tools, manual design, simulation design, rule formulation, etc. The preset style-controlled layout trajectory set needs to include circuit netlist information, chip layout trajectories, and style control parameters.

[0086] Chip layout models can be sequences modeling modules, offline reinforcement learning models with behavior cloning, or policy modeling methods based on latent variable generation models, which are capable of learning state-action mapping relationships from offline data.

[0087] Optionally, the chip layout model includes a sequence modeling module based on a causal self-attention mechanism; the sequence modeling module is used to: constrain the current layout state to perform autoregressive modeling of the chip layout process based on the sequence of chip layout actions prior to the current layout state through a causal masking mechanism.

[0088] Figure 7 This is a schematic diagram of the structure of a sequence modeling module based on a causal self-attention mechanism according to Embodiment 3 of the present invention. Figure 7 As shown, a causal mask is introduced into the attention calculation to restrict the current layout state to autoregressive modeling of the chip layout process based on the sequence of chip layout actions preceding the current layout state. The sequence modeling module based on the causal self-attention mechanism avoids the leakage of future information when accessing the complete sequence, ensuring that the chip layout model's decisions at the current moment rely only on the generated layout states and chip layout action information, making it more suitable for sequential decision-making in chip layout.

[0089] Optionally, the circuit feature vector, style control feature vector, and each layout state and chip layout action of each chip layout trajectory in the preset style control layout trajectory set are input into the chip layout model for model training, including: training the chip layout model by maximizing the log-likelihood function of the chip layout model predicting each real action on the chip layout trajectory; and obtaining the chip layout model when the model training iteration termination condition is reached.

[0090] For example, the maximized log-likelihood function is: In the formula, These are the trainable parameters for the chip layout model. This indicates that the layout trajectory set is controlled from the preset style. Style control parameters are obtained by mid-sampling Circuit netlist and chip layout trace . This represents the historical state and action sequence up to time step t. Indicates a given Circuit eigenvectors Style control feature vector At that time, the chip layout model predicts the actual chip layout actions. The probability of.

[0091] The offline training process of the chip placement model is performed iteratively with the objective of maximizing the log-likelihood function. Upon reaching the termination condition, the model parameters are saved, and the model can be directly used for subsequent chip placement inference. The termination condition for model training iteration can be reaching the maximum number of iterations or iteration convergence. For example, 800 iterations can be performed on 39 circuit netlists to complete the chip placement model training with the objective of maximizing the log-likelihood function.

[0092] The technical solution of this invention addresses the offline training problem of chip layout models by encoding the second circuit netlist during offline chip layout training with a graph structure to obtain circuit feature vectors; generating style control feature vectors based on the style control parameters of the second circuit netlist; and inputting the circuit feature vectors, style control feature vectors, and the layout states and chip layout actions of each chip layout trajectory in a preset style control layout trajectory set into the chip layout model for model training. This solves the problem of offline training of chip layout models. By utilizing a large amount of historical layout trajectory data for offline learning during the training phase, cross-circuit knowledge transfer can be achieved. The style feature vectors can regulate the final layout style. By introducing style feature vectors as conditional inputs, the model can improve its ability to predict and optimize layouts. The design phase generates layout results with corresponding styles based on different preferences; it learns the mapping relationship from "circuit features + style preferences" to "layout action sequence" to achieve style-controllable layout generation; it avoids the problem of training multiple models independently for different optimization objectives, resulting in huge computational overhead when switching design objectives; by introducing style control parameters as conditional input, this invention can support real-time switching from line length priority to congestion priority within a single chip layout model framework, without retraining, significantly reducing the time cost and computational resource consumption of multi-style design; it avoids the repetitive overhead of online exploration from scratch every time a new design task is encountered, effectively improving the utilization rate of training samples, and the offline training method can improve training efficiency.

[0093] Building upon the above implementation, online fine-tuning can be performed when the chip layout model encounters a new circuit netlist not present in the training set. There are many ways to perform online fine-tuning, such as using efficient parameter fine-tuning methods, reinforcement learning-based online fine-tuning methods, or meta-learning-based fast adaptation methods to quickly adapt the model to a small number of new circuits, thereby improving the chip layout performance.

[0094] Example 4 Figure 8 This is a flowchart of a chip layout model training method according to Embodiment 4 of the present invention. This embodiment is a further addition to the above-described technical solution, and the technical solution in this embodiment can be combined with various optional solutions in one or more of the above embodiments. The chip layout model training method provided by the present invention is mainly used for online fine-tuning of the chip layout model to further improve the chip layout effect and adapt to new circuits. The chip layout model training method provided by the present invention can be executed after the chip layout model training method provided in the above embodiments, or it can be executed when fine-tuning the model during inference applications of the chip layout model.

[0095] like Figure 8 As shown, the method includes: Step 810: Perform graph structure encoding on the third circuit netlist to be laid out to obtain the circuit feature vector.

[0096] The graph structure encoding method of circuit netlists can be the same as or similar to the above content, and will not be repeated here.

[0097] Step 820: Generate a style control feature vector based on the specified style control parameters corresponding to the third circuit netlist.

[0098] The generation method for style control feature vectors can be the same as before, and will not be repeated here.

[0099] Step 830: Input the circuit feature vector and style control feature vector into the chip layout model to obtain the chip layout action sequence.

[0100] The chip placement model has been trained. Using the chip placement model, a complete sequence of chip placement actions can be obtained based on circuit feature vectors and style control feature vectors. For the same circuit netlist, multiple chip placement action sequences can be obtained by applying the chip placement model multiple times.

[0101] Step 840: Perform forward propagation of the chip layout action sequence using the chip layout model; and adjust the parameters of the chip layout model based on the forward propagation results under a preset loss function.

[0102] When fine-tuning the chip layout model, trajectory sampling can be performed in multiple chip layout action sequences, or the entire sequence can be used for forward propagation to predict the action distribution. Then, the model parameters are adjusted using a preset loss function based on the forward propagation results.

[0103] Optionally, a chip layout model is used to perform forward propagation on the chip layout action sequence, including: determining the trajectory gain of the chip layout action sequence based on style control parameters, and determining the sampling probability of the chip layout action sequence based on the trajectory gain; performing trajectory sampling in multiple chip layout action sequences based on the sampling probability, and performing forward propagation using the chip layout model based on the sampling results.

[0104] The trajectory gain can be obtained by accumulating the rewards under each indicator in the style control parameters. That is, the trajectory gain of the chip layout action sequence is determined based on the style control parameters and the style control reward function under each layout state. For example, the trajectory gain of the chip layout action sequence is... . For style control parameters, Let be the style control reward function corresponding to the layout state at time step t. The trajectory reward is positively correlated with the sampling probability; that is, the greater the trajectory reward, the greater the sampling probability of the trajectory. For example, the sampling probability can be directly proportional to the exponential function of the trajectory reward, meaning that trajectories with better layout performance are more likely to be sampled.

[0105] Optionally, before determining the sampling probability of the chip placement action sequence based on trajectory gains, the process may further include: sorting the generated chip placement action sequences according to trajectory gains and placing them into a priority replay buffer; re-inputting the circuit feature vector and style control feature vector into the chip placement model to obtain a new chip placement action sequence, and updating the chip placement action sequences in the priority replay buffer based on the trajectory gains of the newly generated chip placement action sequences. For example, if the trajectory gains of the newly generated chip placement action sequence are greater than the chip placement action sequence with the worst trajectory gains in the priority replay buffer, the newly generated chip placement action sequence replaces the chip placement action sequence with the worst trajectory gains in the priority replay buffer. By updating the trajectories in the priority replay buffer according to trajectory gains, it can be ensured that the chip placement model learns better-performing trajectories during parameter updates, thereby improving the performance of the chip placement model.

[0106] Optionally, before adjusting the parameters of the chip layout model under a preset loss function based on the forward propagation results, the method further includes: determining the trajectory weights of each chip layout action sequence based on the trajectory gains and sampling temperature of each chip layout action sequence; determining a first loss function based on the log-likelihood function and trajectory weights of the chip layout model in the chip layout action sequence prediction; calculating the entropy of each layout action distribution output by the chip layout model in the prediction of the third circuit netlist, as a second loss function; and determining a preset loss function based on the first loss function, the second loss function, the lower bound threshold of the entropy, and the entropy loss weight.

[0107] For example, the trajectory weight is In the formula, The sampling temperature is [value]. The first loss function is [function]. In the formula, To sample the trajectory from the priority playback buffer, For the chip layout model in the chip layout action sequence In the middle, based on the circuit characteristic vector of the circuit netlist and style control feature vectors Predicting chip layout actions The log-likelihood function. The first loss function allows the chip layout model to learn more about actions in high-yield trajectories during fine-tuning.

[0108] The second loss function is In the formula, Represents the chip layout model The entropy of the action distribution of each layout output in the prediction of the third circuit netlist: high entropy indicates uniform action distribution, and low entropy indicates that the model is too deterministic. It represents all possible actions.

[0109] The preset loss function can be In the formula, Weights for entropy loss. The lower bound threshold of entropy is determined by constraints. To ensure the chip layout model doesn't converge to a local optimum too quickly during fine-tuning, a certain degree of exploratory nature is maintained. Fine-tuning the chip layout model using a preset loss function comprised of a first and second loss function allows the model to mimic actions from trajectories with better returns, while preventing overfitting.

[0110] The technical solution of this invention involves graph-encoding the third circuit netlist to be placed into a chip to obtain circuit feature vectors; generating style control feature vectors based on specified style control parameters corresponding to the third circuit netlist; inputting the circuit feature vectors and style control feature vectors into a chip placement model to obtain a chip placement action sequence; performing forward propagation on the chip placement action sequence using the chip placement model; and adjusting the parameters of the chip placement model under a preset loss function based on the forward propagation results. This solves the problem of online fine-tuning of the chip placement model when encountering newly appearing circuits. For unseen circuits, only a small number of online inference samples are needed for fine-tuning to complete the adaptation. Compared with training from scratch, the required sample size is significantly reduced, which has practical engineering value. In the fine-tuning stage, by introducing a lower bound constraint on policy entropy, the model is effectively prevented from overfitting to local optima on a small number of inference samples. Sufficient exploration space is preserved under a limited fine-tuning budget, ensuring the diversity and robustness of the placement schemes after fine-tuning.

[0111] Example 5 Figure 9 This is a flowchart of a chip placement method according to Embodiment 5 of the present invention. This embodiment is applicable to situations where chip placement is performed when a chip placement style is specified according to chip placement requirements. This chip placement method can be executed by a chip placement device. The chip placement device can be implemented in hardware and / or software. The chip placement device can be configured in an electronic device, such as a computer, mobile phone, or chip design equipment, etc. Figure 9 As shown, the method includes: Step 910: Perform graph structure encoding on the fourth circuit netlist to be laid out to obtain the circuit feature vector.

[0112] Step 920: Generate a style control feature vector based on the specified style control parameters corresponding to the fourth circuit netlist.

[0113] Step 930: Input the circuit feature vector and style control feature vector into the chip layout model, and output the chip layout action sequence through the chip layout model.

[0114] The chip layout model is trained using the chip layout model training method provided in any embodiment of the present invention. For example, the chip layout model may be trained using the method provided in Embodiment 3, or fine-tuned using the method provided in Embodiment 4, or it may be trained and fine-tuned using the methods provided in Embodiments 3 and 4.

[0115] Figure 10 This is a schematic diagram of a chip layout according to Embodiment 5 of the present invention. Figure 10As shown, the circuit feature vector obtained by graph structure encoding of the circuit netlist is input into the chip layout model. Simultaneously, the style control feature vector corresponding to the style control parameters is input into the chip layout model. For example, the first style control parameter has weights of 0.1, 0.7, and 0.2 for chip layout line length, congestion, and density, respectively; or, the second style control parameter has weights of 0.8, 0.1, and 0.1 for chip layout line length, congestion, and density, respectively. Under the first style control parameter, the chip layout model can obtain a chip layout that prioritizes low congestion. Under the second style control parameter, the chip layout model can obtain a chip layout that prioritizes short line lengths. In this embodiment of the invention, since the style control parameters participate in the decision-making process as global conditions, the generated chip layout result can be dynamically adjusted according to the input style, achieving a trade-off between different optimization objectives under a single model, without needing to retrain the model for different optimization objectives, significantly reducing the time cost and computational resource consumption of multi-style design.

[0116] The technical solution of this invention involves graph-encoding the fourth circuit netlist to be placed into a chip to obtain a circuit feature vector; generating a style control feature vector based on specified style control parameters corresponding to the fourth circuit netlist; inputting the circuit feature vector and the style control feature vector into a chip placement model; and outputting a chip placement action sequence through the chip placement model. This solves the chip placement problem under multiple placement styles, enables style-controllable chip placement, and allows for flexible configuration of chip placement to adapt to various chip design scenarios. It decouples circuit structure features from style preference information, achieving cross-style generalization capability.

[0117] Example 6 Figure 11 This is a schematic diagram of a chip layout trajectory generation device according to Embodiment Six of the present invention. Figure 11 As shown, the device includes: a first layout state feature generation module 1101, a style information generation module 1102, a chip layout action generation module 1103, and a chip layout trajectory generation module 1104. Wherein: The first layout state feature generation module 1101 is used to generate layout state features based on the current layout state of the first circuit netlist of the chip layout. The style information generation module 1102 is used to generate a style control feature vector and a style control reward function in the current layout state based on the style control parameters specified during chip layout. The chip layout action generation module 1103 is used to generate chip layout actions based on layout state features and style control feature vectors. The chip layout trajectory generation module 1104 is used to generate a chip layout trajectory under style control parameters based on layout state features, style control feature vector, chip layout action and style control reward function.

[0118] Optionally, the chip layout trajectory generation module 1104 includes: The current layout trajectory generation unit is used to update the current layout state of the first circuit netlist according to the chip layout action, and return to the step of generating layout state feature according to the current layout state of the first circuit netlist until the chip layout is completed and the current layout trajectory of the current strategy is obtained. The value vector generation unit is used to generate the value vector corresponding to each layout state based on the layout state features and style control feature vectors of each layout state in the current layout trajectory of the current strategy. The strategy parameter generation unit is used to determine the strategy parameters based on the value vector of each layout state in the current layout trajectory of the current strategy and the style control reward function; the strategy parameters are used to generate chip layout actions. The chip layout trajectory determination unit is used to determine the chip layout trajectory corresponding to the target strategy parameters as the chip layout trajectory under the style control parameters when the strategy parameter update termination condition is met.

[0119] Optionally, the strategy parameter generation unit includes: The comprehensive advantage function determination sub-unit is used to determine the comprehensive advantage function of each layout state of the current strategy based on the value vector of each layout state in the current layout trajectory of the current strategy, the style control reward function, the discount factor, the style control parameters, and the adjustment parameters of the time step. The strategy parameter generation subunit is used to generate strategy parameters based on the pruning coefficient, the probability ratio of the current strategy to the historical strategy at the same time step, and the comprehensive advantage function.

[0120] Optionally, the sub-unit is determined by the comprehensive advantage function, specifically used for: The temporal difference error at the current moment is determined based on the value vector, discount factor, and style control reward function corresponding to the current moment's layout state and the next moment's layout state, respectively. Based on style control parameters, discount factors, and time step adjustment parameters, the accumulated temporal difference error from the current moment to the end moment of the current layout trajectory is calculated and used as the comprehensive advantage function of the layout state at the current moment.

[0121] Optionally, the device may also include: The reward function determination module is used to determine the reward function of each layout state in the current layout trajectory of the current strategy after determining the strategy parameters based on the value vector of each layout state in the current layout trajectory of the current strategy and the style control reward function. The value parameter generation module is used to generate value parameters based on the value vectors of each layout state in the current layout trajectory of the current strategy and the reward function. The value parameters are used to generate the value vectors corresponding to each layout state.

[0122] Optional, the reward function determination module includes: The first reward function determination unit is used to determine the reward function of each layout state based on the comprehensive advantage function and value vector of each layout state in the current layout trajectory of the current strategy; or, The second reward function determination unit is used to calculate the accumulated reward from the time corresponding to the current layout state to the end time of the current layout trajectory based on the style control reward function and discount factor of each layout state in the current layout trajectory of the current strategy, and use it as the reward function of the layout state.

[0123] Optionally, the first layout state feature generation module 1101 includes: The first feature extraction unit is used to extract features based on the current layout state of the first circuit netlist of the chip layout, and obtain the connection cost features, placed area features and unplaced area features of the current layout state. The feature splicing unit is used to splice the connection cost feature, the placed area feature, and the unplaced area feature to obtain the spliced ​​layout state feature. The second feature extraction unit is used to extract features from the spliced ​​layout state features again to obtain the layout state features of the current layout state.

[0124] Optionally, style control parameters may include at least two of the following: chip layout line length, congestion, density, power consumption, performance, area, timing metrics, thermal distribution, and power integrity parameters.

[0125] The chip layout trajectory generation apparatus provided in this embodiment of the invention can execute the chip layout trajectory generation method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0126] Example 7 Figure 12 This is a schematic diagram of the structure of a chip layout model training device according to Embodiment Six of the present invention. Figure 12 As shown, the device includes: a first circuit feature vector determination module 1201, a first style control feature vector generation module 1202, and a chip layout model training module 1203. Wherein: The first circuit feature vector determination module 1201 is used to perform graph structure encoding on the second circuit netlist during chip layout offline training to obtain circuit feature vectors. The first style control feature vector generation module 1202 is used to generate style control feature vectors based on the style control parameters of the second circuit netlist. The chip layout model training module 1203 is used to input the circuit feature vector, style control feature vector, and the layout states and chip layout actions of each chip layout trajectory in the preset style control layout trajectory set into the chip layout model for model training. The chip layout trajectories in the preset style control layout trajectory set are obtained using the chip layout trajectory generation method provided in any embodiment of the present invention.

[0127] Optionally, the chip layout model includes a sequence modeling module based on a causal self-attention mechanism; the sequence modeling module is used for: By using a causal masking mechanism, the chip layout process is modeled autoregressively based on the chip layout action sequence preceding the current layout state, limiting the current layout state.

[0128] Optionally, the chip layout model training module 1203 includes: The chip layout model training unit is used to train the chip layout model by maximizing the log-likelihood function of the chip layout model to predict each real action on the chip layout trajectory. The chip layout model determination unit is used to obtain the chip layout model when the model training iteration termination condition is met.

[0129] Optionally, the device may also include: The third circuit feature vector determination module is used to perform graph structure encoding on the third circuit netlist to be laid out in the chip to obtain the circuit feature vector. The third style control feature vector generation module is used to generate style control feature vectors based on the specified style control parameters corresponding to the third circuit netlist. The second chip layout action sequence determination module is used to input the circuit feature vector and style control feature vector into the chip layout model to obtain the chip layout action sequence. The model parameter adjustment module is used to perform forward propagation of the chip layout action sequence using the chip layout model; and to adjust the parameters of the chip layout model under a preset loss function based on the forward propagation results.

[0130] Optional, the model parameter tuning module includes: The sampling probability determination unit is used to determine the trajectory gain of the chip layout action sequence based on the style control parameters, and to determine the sampling probability of the chip layout action sequence based on the trajectory gain. The forward propagation unit is used to sample trajectories in multiple chip layout action sequences according to the sampling probability, and to perform forward propagation using the chip layout model based on the sampling results.

[0131] Optionally, the device may also include: The trajectory weight determination module is used to determine the trajectory weight of each chip layout action sequence based on the trajectory gain of each chip layout action sequence and the sampling temperature before adjusting the parameters of the chip layout model according to the forward propagation results and the preset loss function. The first loss function determination module is used to determine the first loss function based on the log-likelihood function and trajectory weights of the chip layout model in the chip layout action sequence prediction. The second loss function determination module is used to calculate the entropy of each layout action distribution output by the chip layout model in the prediction of the third circuit netlist, as the second loss function. The preset loss function determination module is used to determine the preset loss function based on the first loss function, the second loss function, the lower bound threshold of entropy, and the entropy loss weight.

[0132] The chip layout model training device provided in this embodiment of the invention can execute the chip layout model training method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0133] Example 8 Figure 13 This is a schematic diagram of a chip layout device according to Embodiment Six of the present invention. Figure 13 As shown, the device includes: a second circuit feature vector determination module 1301, a second style control feature vector generation module 1302, and a first chip layout action sequence determination module 1303. Wherein: The second circuit feature vector determination module 1301 is used to perform graph structure encoding on the fourth circuit netlist to be laid out in the chip to obtain the circuit feature vector. The second style control feature vector generation module 1302 is used to generate a style control feature vector based on the specified style control parameters corresponding to the fourth circuit netlist. The first chip layout action sequence determination module 1303 is used to input circuit feature vectors and style control feature vectors into the chip layout model and output the chip layout action sequence through the chip layout model. The chip layout model is trained using the chip layout model training method provided in any embodiment of the present invention.

[0134] The chip layout apparatus provided in the embodiments of the present invention can execute the chip layout method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0135] Example 9 Figure 14 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0136] like Figure 14 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) or random access memory (RAM), communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.

[0137] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0138] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as methods for generating chip layout traces, methods for training chip layout models, or chip layout methods.

[0139] In some embodiments, the method for generating chip layout traces, the method for training chip layout models, or the chip layout method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the method for generating chip layout traces, the method for training chip layout models, or the chip layout method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the method for generating chip layout traces, the method for training chip layout models, or the chip layout method by any other suitable means (e.g., by means of firmware).

[0140] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0141] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0142] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0143] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0144] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0145] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0146] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0147] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating chip layout trajectories, characterized in that, include: Layout state features are generated based on the current layout state of the first circuit netlist of the chip layout; Generate a style control feature vector and a style control reward function in the current layout state based on the style control parameters specified during chip layout. Based on the layout state features and the style control feature vector, a chip layout action is generated; Based on the layout state features, the style control feature vector, the chip layout action, and the style control reward function, a chip layout trajectory under style control parameters is generated.

2. The method according to claim 1, characterized in that, Based on the layout state features, the style control feature vector, the chip layout action, and the style control reward function, a chip layout trajectory under style control parameters is generated, including: Update the current layout state of the first circuit netlist according to the chip layout action, and return to the step of generating layout state features according to the current layout state of the first circuit netlist until the chip layout is completed and the current layout trajectory of the current strategy is obtained. Based on the layout state features of each layout state in the current layout trajectory of the current strategy and the style control feature vector, a value vector corresponding to each layout state is generated. Based on the value vector of each layout state in the current layout trajectory of the current strategy and the style control reward function, the strategy parameters are determined; the strategy parameters are used to generate chip layout actions. When the termination condition for updating the strategy parameters is met, the chip layout trajectory corresponding to the target strategy parameters is used as the chip layout trajectory under the style control parameters.

3. The method according to claim 2, characterized in that, Based on the value vectors of each layout state in the current layout trajectory of the current strategy and the style control reward function, the strategy parameters are determined, including: Based on the value vector, style control reward function, discount factor, style control parameters, and time step adjustment parameters of each layout state in the current layout trajectory of the current strategy, determine the comprehensive advantage function of each layout state of the current strategy; The strategy parameters are generated based on the pruning coefficient, the probability ratio of the current strategy to the historical strategy at the same time step, and the comprehensive advantage function.

4. The method according to claim 3, characterized in that, Based on the value vector, style control reward function, discount factor, style control parameters, and time step adjustment parameters corresponding to each layout state in the current layout trajectory of the current strategy, the comprehensive advantage function of the current strategy at each time step is determined, including: The temporal difference error at the current moment is determined based on the value vector, discount factor, and style control reward function corresponding to the current moment's layout state and the next moment's layout state, respectively. Based on the style control parameters, the discount factor, and the time step adjustment parameters, the accumulated temporal difference error from the current moment to the end moment of the current layout trajectory is calculated and used as the comprehensive advantage function of the layout state at the current moment.

5. The method according to claim 3, characterized in that, After determining the policy parameters based on the value vectors of each layout state in the current layout trajectory of the current policy and the style control reward function, the method further includes: Based on the style control parameters, determine the reward function for each layout state in the current layout trajectory of the current strategy; Based on the value vectors and reward functions of each layout state in the current layout trajectory of the current strategy, value parameters are generated, which are used to generate the value vectors corresponding to each layout state.

6. The method according to claim 5, characterized in that, Based on the style control parameters, determine the reward function for each layout state in the current layout trajectory of the current strategy, including: Based on the comprehensive advantage function and the value vector of each layout state in the current layout trajectory of the current strategy, determine the reward function of each layout state; or, Based on the style control reward function of each layout state in the current layout trajectory of the current strategy and the discount factor, calculate the accumulated reward from the time corresponding to the layout state to the end time of the current layout trajectory, and use it as the reward function of the layout state.

7. The method according to any one of claims 1-6, characterized in that, The step of generating layout state features based on the current layout state of the first circuit netlist of the chip layout includes: Based on the current layout state of the first circuit netlist of the chip layout, feature extraction is performed to obtain the connection cost features, placed area features, and unplaced area features of the current layout state. The connection cost feature, the placed area feature, and the unplaced area feature are spliced ​​together to obtain the spliced ​​layout state feature; The splicing layout state features are extracted again to obtain the layout state features of the current layout state.

8. The method according to any one of claims 1-6, characterized in that, The style control parameters include at least two of the following: parameter information on chip layout line length, congestion, density, power consumption, performance, area, timing indicators, thermal distribution, and power integrity.

9. A chip layout model training method, characterized in that, include: Graph structure encoding is performed on the second circuit netlist during offline chip layout training to obtain circuit feature vectors; Based on the style control parameters of the second circuit netlist, a style control feature vector is generated; The circuit feature vector, the style control feature vector, and the layout states and chip layout actions of each chip layout trajectory in the preset style control layout trajectory set are input into the chip layout model for model training. The chip layout trajectories in the preset style control layout trajectory set are obtained by the chip layout trajectory generation method as described in any one of claims 1-8.

10. The method according to claim 9, characterized in that, The chip layout model includes a sequence modeling module based on a causal self-attention mechanism; the sequence modeling module is used for: By using a causal masking mechanism, the chip layout process is modeled autoregressively based on the chip layout action sequence prior to the current layout state, limiting the current layout state. The circuit feature vector, the style control feature vector, and the layout states and chip layout actions of each chip layout trajectory in the preset style control layout trajectory set are input into the chip layout model for model training, including: The chip layout model is trained by maximizing the log-likelihood function of the chip layout model in predicting each real action on the chip layout trajectory. When the model training iteration termination condition is met, the chip layout model is obtained.

11. The method according to claim 9, characterized in that, The method further includes: The third circuit netlist to be laid out is graph-structured to obtain circuit feature vectors. Generate a style control feature vector based on the specified style control parameters corresponding to the third circuit netlist; The circuit feature vector and the style control feature vector are input into the chip layout model to obtain the chip layout action sequence; The chip layout action sequence is propagated forward using the chip layout model; and the parameters of the chip layout model are adjusted based on the forward propagation results under a preset loss function.

12. The method according to claim 11, characterized in that, The chip layout action sequence is forward-propagated using the chip layout model, including: Based on the style control parameters, determine the trajectory gain of the chip layout action sequence, and determine the sampling probability of the chip layout action sequence based on the trajectory gain; Trajectory sampling is performed in multiple chip layout action sequences according to the sampling probability, and forward propagation is performed using the chip layout model based on the sampling results.

13. A chip layout method, characterized in that, include: The fourth circuit netlist to be laid out is graph-structured to obtain circuit feature vectors. Generate a style control feature vector based on the specified style control parameters corresponding to the fourth circuit netlist; The circuit feature vector and the style control feature vector are input into the chip layout model, and the chip layout action sequence is output through the chip layout model; The chip layout model is trained using the chip layout model training method as described in any one of claims 9-12.

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