A display screen driving method, display driver and electronic device

Abstract

The application provides a display screen driving method, a display driver and an electronic device, relates to the technical field of display, and aims to improve the stroboscopic problem of the display screen and improve the eye protection performance of the display screen. The display screen driving method comprises the following steps: in a first dimming interval, PWM dimming is adopted, a plurality of groups of anodes are reset during each frame image display period, one set of gamma voltage scheme is adopted to be compatible with a first frame rate and a second frame rate, and the first frame rate and the second frame rate cannot be divided by each other; and in a second dimming interval, DC dimming is adopted, one group of anodes is reset during each frame image display period, and two sets of gamma voltage schemes are adopted to be compatible with the first frame rate and the second frame rate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a method for driving a display screen, a display driver, and an electronic device. Background Technology

[0002] With the increasing prevalence of electronic products such as mobile phones, tablets, and game consoles in people's daily lives, screen flicker and eye protection have become a major concern for users. The industry uses the stroboscopic effect visibility measure (SVM) to measure flicker; for the same device, the lower the SVM value, the weaker the flicker.

[0003] Current displays use different dimming methods when displaying low-brightness and high-brightness images. For example, pulse width modulation (PWM) dimming is used when displaying low brightness, while direct current (DC) dimming is used when displaying high brightness to be compatible with different frame rates. DC dimming has worse flicker than DC dimming and is less eye-friendly. Summary of the Invention

[0004] This application provides a display screen driving method, display driver, and electronic device to improve the flicker problem of the display screen and enhance the eye protection performance of the display screen.

[0005] In a first aspect, a method for driving a display screen is provided, the method comprising: in a first dimming interval, during each frame of image display, multiple sets of anodes are reset, and a single gamma voltage scheme is used to be compatible with a first frame rate and a second frame rate. For example, PWM dimming can be used in the first dimming interval, wherein the first frame rate and the second frame rate are not divisible by each other; in a second dimming interval, during each frame of image display, one set of anodes is reset, and two sets of gamma voltage schemes are used to be compatible with the first frame rate and the second frame rate. For example, DC dimming can be used in the second dimming interval.

[0006] Based on this, in the first dimming interval, multiple resets of the anode of the light-emitting device can be performed during the display of one frame of image, using high-frequency PWM dimming. The higher the frequency, the weaker the flicker. Furthermore, the frame rate can be switched by selecting which reset to write data to, with one gamma voltage scheme compatible with the first and second frame rates that are not divisible. In the second dimming interval, one reset of the anode of the light-emitting device can be performed during the display of one frame of image, using DC dimming. Two gamma voltage schemes are used to be compatible with the first and second frame rates that are not divisible, which improves flicker performance and enables switching between different frame rates.

[0007] In one implementation of the first aspect, the method includes: in a first dimming interval, outputting a reset control signal of a first frequency to the display screen, the reset control signal being used to control the anode reset of the light-emitting device of the pixel circuit; and in a second dimming interval, outputting a reset control signal of a second frequency to the display screen, the first frequency being different from the second frequency.

[0008] In one implementation of the first aspect, the first frequency is an integer multiple of the first frame rate, and the second frequency is an integer multiple of the second frame rate. Using a higher frequency reset control signal in the first dimming interval allows for compatibility with multiple frame rates divisible by the first frequency.

[0009] In one implementation of the first aspect, the method includes: in a first dimming interval, outputting a third frequency light emission control signal to the display screen, the third frequency light emission control signal having multiple pulses during each frame of image display; in a second dimming interval, outputting a fourth frequency light emission control signal to the display screen, the fourth frequency light emission control signal having a single pulse during each frame of image display, wherein in the first dimming interval, the third frequency can be greater than 1000Hz to improve the eye protection capability of the display screen, and in the second dimming interval, the light emission control signal is a single pulse signal, i.e., DC dimming is used. Compared with DC dimming-like dimming, DC dimming can improve flicker and reduce the SVM value of the display screen.

[0010] In one implementation of the first aspect, the width of each pulse of the multiple pulse emission control signal is the same or different.

[0011] In one implementation of the first aspect, the method further includes: the frequency of the light emission control signal output to the display screen is different from the frequency of the reset control signal output to the display screen.

[0012] In one implementation of the first aspect, the method further includes: when controlling the light emission control signal to switch from a third frequency to a fourth frequency, first controlling the frequency of the light emission control signal to switch from a third frequency to a fifth frequency, and then controlling the frequency of the light emission control signal to switch from a fifth frequency to a fourth frequency; or, when controlling the frequency of the light emission control signal to switch from a fourth frequency to a third frequency, first controlling the frequency of the light emission control signal to switch from a fourth frequency to a fifth frequency, and then controlling the frequency of the light emission control signal to switch from a fifth frequency to a third frequency; the fifth frequency is a frequency value between the third frequency and the fourth frequency.

[0013] In one implementation of the first aspect, the method further includes: the timing of the control signal output to the display screen in the first dimming interval is different from that of the control signal output to the display screen in the second dimming interval, and the control signal includes an illumination control signal and a reset control signal.

[0014] In one implementation of the first aspect, the method further includes: the pulse width of the reset control signal output to the display screen in the first dimming interval is different from the pulse width of the reset control signal output to the display screen in the second dimming interval.

[0015] In one implementation of the first aspect, the display screen includes a multi-row pixel circuit, which includes a first row pixel circuit and a second row pixel circuit. The method further includes: the writing time when writing data to the first row pixel circuit and the writing time when writing data to the second row pixel circuit.

[0016] In one implementation of the first aspect, the first row pixel circuit is an odd-numbered row pixel circuit of the display screen, and the second row pixel circuit is an even-numbered row pixel circuit of the display screen.

[0017] In one implementation of the first aspect, the display brightness of the first dimming zone is lower than that of the second dimming zone; or, the brightness level of the first dimming zone is lower than that of the second dimming zone.

[0018] In a second aspect, a display driver is provided for connecting a display screen and for performing the methods provided by the first aspect and any implementation thereof.

[0019] Thirdly, a display module is provided, the display module including a display driver and a display screen, the display driver being connected to the display screen, and the display driver being used to perform the methods provided by the first aspect and any implementation thereof.

[0020] Fourthly, an electronic device is provided, the electronic device including a housing and a display module as provided in the third aspect and any implementation thereof, the display module being mounted on the housing. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the structure of a display module provided in an embodiment of this application;

[0023] Figure 3 This is a timing diagram of the control signals for the pixel circuit provided in an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0026] Figure 6This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0027] Figure 7 A comparative schematic diagram of the light emission control signals for different dimming methods provided in the embodiments of this application;

[0028] Figure 8 This is a schematic diagram of the stripes displayed on the screens of several different devices when captured by a camera at low brightness.

[0029] Figure 9 This is a schematic diagram of the stripes displayed on the screens of several different devices when captured by a camera at high brightness.

[0030] Figure 10 A schematic diagram illustrating two different frame rates provided in the embodiments of this application;

[0031] Figure 11 This application provides a schematic diagram of the control signal timing for a display screen.

[0032] Figure 12 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0033] Figure 13 A schematic diagram of the driving method provided in an embodiment of this application;

[0034] Figure 14 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0035] Figure 15 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0036] Figure 16 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0037] Figure 17 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0038] Figure 18 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0039] Figure 19 This is a schematic diagram of the control signal timing of another display screen provided in an embodiment of this application;

[0040] Figure 20 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0043] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0044] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0045] In the embodiments of this application, the transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a thin-film transistor (TFT). Transistors are classified into two types: N-type and P-type. A transistor includes a source, a drain, and a gate. The transistor's conduction or cutoff can be controlled by controlling the voltage level of the gate. When the transistor is on, the source and drain conduct, generating a conduction current. The magnitude of the conduction current between the source and drain varies depending on the gate voltage level. When the transistor is off, the source and drain do not conduct, and no current is generated. In the embodiments of this application, the transistor's gate is also referred to as the control electrode, the source as the first electrode, and the drain as the second electrode; or, the gate is referred to as the control electrode, the drain as the first electrode, and the source as the second electrode. Furthermore, an N-type transistor conducts when its gate is high, with both its first and second terminals conducting, generating a current between them. When its gate is low, it is cut off, with no current flowing between the first and second terminals. Similarly, a P-type transistor conducts when its gate is low, with both its first and second terminals conducting, generating a current. When its gate is high, it is cut off, with no current flowing between the first and second terminals.

[0046] The technical solutions provided in this application can be applied to various electronic devices including display modules. These electronic devices include, for example, consumer electronics, home electronics, automotive electronics, and financial electronic devices with display functions. Examples include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0047] The following explanation uses a mobile phone as an example. Figure 1 A schematic diagram of the structure of an electronic device provided in this application is shown. Please refer to [link / reference]. Figure 1The electronic device may include: a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor 180, a button 190, a motor 191, an indicator 192, a camera 193, a display module 194, and a subscriber identification module (SIM) card interface 195, etc.

[0048] The aforementioned sensor 180 may include pressure sensors, gyroscope sensors, gravity sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, and bone conduction sensors, etc.

[0049] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0050] Processor 110 may include one or more processing units, such as: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0051] A controller can be the nerve center and command center of an electronic device. Based on the instruction opcode and timing signals, the controller generates operation control signals to control the fetching and execution of instructions.

[0052] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0053] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0054] It is understood that the interface connection relationships between the modules illustrated in this embodiment are merely illustrative and do not constitute a structural limitation on the electronic device. In other embodiments, the electronic device may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0055] The charging management module 140 receives charging input from a charger, which can be a wireless charger or a wired charger. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141.

[0056] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, internal memory 121, external memory, display module 194, camera 193, and wireless communication module 160, etc. In some embodiments, the power management module 141 and the charging management module 140 may also be housed in the same device.

[0057] The wireless communication function of the electronic device can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor, and baseband processor. In some embodiments, antenna 1 of the electronic device is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling the electronic device to communicate with networks and other devices through wireless communication technology.

[0058] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0059] The mobile communication module 150 can provide solutions for wireless communication applications, including 2G / 3G / 4G / 5G, in electronic devices. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation.

[0060] The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via the antenna 1. In some embodiments, at least some functional modules of the mobile communication module 150 can be housed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 can be housed in the same device.

[0061] The wireless communication module 160 can provide solutions for wireless communication applications in electronic devices, including WLAN (such as wireless fidelity, Wi-Fi) networks, Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, and other wireless communication technologies.

[0062] The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signal, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0063] Electronic devices implement display functions through a GPU, a display module 194, and an application processor. The GPU is a microprocessor for image processing, connecting the display module 194 and the application processor. The GPU performs mathematical and geometric calculations and is used for graphics rendering. The processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0064] Display module 194 is used to display images, videos, etc. Display module 194 includes a display screen.

[0065] The electronic device can implement shooting functions through an ISP, camera 193, video codec, GPU, display module 194, and application processor. The ISP is used to process the data fed back by the camera 193. The camera 193 is used to capture still images or videos. In some embodiments, the electronic device may include one or N cameras 193, where N is a positive integer greater than 1.

[0066] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0067] Internal memory 121 can be used to store computer executable program code, which includes instructions. Processor 110 executes various functional applications and data processing of the electronic device by running the instructions stored in internal memory 121. For example, in this embodiment, processor 110 can execute instructions stored in internal memory 121, which may include a program storage area and a data storage area.

[0068] The program storage area can store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.). The data storage area can store data created during the use of the electronic device (such as audio data, phonebook, etc.). Furthermore, the internal memory 121 can include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0069] Electronic devices can implement audio functions such as music playback and recording through audio modules 170, speakers 170A, receivers 170B, microphones 170C, headphone jacks 170D, and application processors.

[0070] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. Motor 191 can generate vibration alerts. Motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. Indicator 192 can be an indicator light, used to indicate charging status, battery level changes, messages, missed calls, notifications, etc. SIM card interface 195 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to achieve contact and separation with the electronic device. The electronic device can support one or N SIM card interfaces, where N is a positive integer greater than 1. SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, etc.

[0071] Figure 2 A schematic diagram of a general display module is shown, which includes a display driver 20 and a display screen 30. The display driver 20 is used to provide control signals, reset signals, and data voltages required for light emission to the pixel circuits in the display screen 30. The display driver can be a display driver integrated circuit (DDIC) chip or a touch and display driver integration (TDDI) chip, etc.

[0072] The display screen can be an organic light-emitting diode (OLED) display screen, a micro organic light-emitting diode (micro OLED) display screen, a quantum dot light-emitting diode (QLED) display screen, or any other display screen capable of self-illumination.

[0073] For any of the above-mentioned display screens, the display screen has a display area AA and a non-display area NAA. The display area AA is provided with multiple rows and columns of pixel circuits. A row of pixel circuits arranged in a row along the horizontal direction X is called a row of pixel circuits, and a column of pixel circuits arranged in a column along the vertical direction Y is called a column of pixel circuits. The display screen also includes multiple scan lines GL extending along the row direction X and arranged along the column direction Y of the pixel circuits, and multiple data lines DL extending along the column direction Y and arranged along the row direction X of the pixel circuits. Pixel circuits located in the same row are connected to the same scan line, and pixel circuits located in the same column are connected to the same data line.

[0074] The display also includes a gate-on-array (GOA) circuit, also known as a driver circuit, located in the non-display area (NAA). The GOA circuit provides control signals to the pixel circuits in the display area to control the pixel circuits in the display area to emit light line by line.

[0075] Figure 3 This is a timing diagram of the control signals for the pixel circuit provided in an embodiment of this application. The operation of the pixel circuit may include... Figure 3 The three stages shown are: reset stage, data voltage writing stage, and light emission stage.

[0076] Furthermore, the pixel circuits in display screen 30 scan and emit light line by line, meaning the pixel circuits are selected line by line. Each pixel circuit can be accessed through, for example... Figure 3 The strobe signal S shown N , Strobe signal S N-1 It is controlled by the light emission control signal EM.

[0077] strobe signal S N-1 Used to control the (N-1)th row pixel circuit to enter the data voltage writing stage and to control the Nth row pixel circuit to enter the reset stage. Strobe signal S N The signal EM is used to control the Nth row of pixel circuits to enter the data voltage writing stage. The EM signal is used to control the Nth row of pixel circuits to enter the light-emitting stage, where N is a positive integer. If the display screen includes M (M is a positive integer) rows of pixel circuits, N is less than or equal to M.

[0078] See Figure 4 , Figure 4 A schematic diagram of a pixel circuit is shown. The pixel circuit includes at least a first reset transistor M1, a data writing transistor M2, a compensation transistor M3, a driving transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second reset transistor M7, a storage capacitor Cst, and a light-emitting device D.

[0079] In the embodiments of this application, the first reset transistor M1, the data writing transistor M2, the compensation transistor M3, the driving transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6, and the second reset transistor M7 are all P-channel transistors, which means that these transistors will be turned on when the voltage of their gate is low and turned off when the voltage of their gate is high.

[0080] The light-emitting device D can be an organic light-emitting diode (OLED), a micro organic light-emitting diode (micro OLED), a mini organic light-emitting diode (mini OLED), a quantum dot light-emitting diode (QLED), or other light-emitting devices.

[0081] The gate of the first reset transistor M1 is used to receive the strobe signal S. N-1 The first terminal (e.g., source) of the first reset transistor M1, the second terminal (e.g., drain) of the compensation transistor M3, the gate of the driving transistor M4, and the first terminal (e.g., [missing information] of the storage capacitor Cst) Figure 4 The lower plate of the storage capacitor Cst is coupled to the first node N1. The second terminal (e.g., the drain) of the first reset transistor M1 is used to receive the first initial voltage Vint1.

[0082] The first terminal (e.g., the source) of the data write transistor M2 is used to receive the data voltage Vdata output from the data voltage output port of the display driver 20. The second terminal (e.g., the drain) of the data write transistor M2 is coupled to the second terminal (e.g., the drain) of the first light-emitting control transistor M5 and the first terminal (e.g., the source) of the driving transistor M4. The gate of the data write transistor M2 is used to receive the strobe signal S. N .

[0083] The first terminal (e.g., the source) of the first light-emitting control transistor M5 is connected to the first power supply voltage input terminal and the second terminal (e.g., the storage capacitor Cst) of the storage capacitor Cst. Figure 4 The upper plate of the storage capacitor Cst is coupled to receive the first power supply voltage ELVDD input at the first power supply voltage input terminal. The gate of the first light-emitting control transistor M5 is used to receive the light-emitting control signal EM.

[0084] The first terminal (e.g., source) of the compensation transistor M3 is coupled to the second terminal (e.g., drain) of the driving transistor M4 and the first terminal (e.g., source) of the second light-emitting control transistor M6. The gate of the compensation transistor M3 is used to receive the strobe signal S. N .

[0085] The second terminal (e.g., drain) of the second light-emitting control transistor M6 is coupled to the anode (a) of the light-emitting device D (e.g., OLED) and the first terminal (e.g., source) of the second reset transistor M7. The second terminal (e.g., drain) of the second reset transistor M7 is used to receive the second initial voltage Vint2. The gate of the second light-emitting control transistor M6 is used to receive the light-emitting control signal EM. The cathode (c) of the light-emitting device D is coupled to the second power supply voltage input terminal (used to output the second power supply voltage ELVSS).

[0086] The gate of the second reset transistor M7 is used to receive the strobe signal S. N-1 .

[0087] The following is combined with, for example Figure 4 The structure of the pixel circuit shown is for example... Figure 3 The three stages shown will be explained in detail.

[0088] Reset phase:

[0089] In the gating signal S N-1 When the voltage is low, the first reset transistor M1 and the second reset transistor M7 are turned on. The first initial voltage Vint1 is transmitted to the gate of the driving transistor M4 through the first reset transistor M1, thereby resetting the gate of the driving transistor M4. In addition, the second initial voltage Vint2 is transmitted to the anode a of the light-emitting device D through the second reset transistor M7, thereby resetting the anode of the light-emitting device D.

[0090] At this time, the voltage of the anode a of the light-emitting device D is the second initial voltage Vint2, and the voltage of the gate of the driving transistor M4 is the first initial voltage Vint1. The first initial voltage Vint1 can be set according to the performance and parameters of the driving transistor M4; the second initial voltage Vint2 can be set according to the parameters of the parasitic capacitance of the light-emitting device D.

[0091] During the reset phase, the voltages of the gate of the driving transistor M4 and the anode a of the light-emitting device D are reset, thus preventing the residual voltages from the previous frame from affecting the next frame. During the reset phase, both the first reset transistor M1 and the second reset transistor M7 are turned on.

[0092] Data voltage writing stage:

[0093] In the gating signal S NWhen the voltage level is low, data writing transistor M2 and compensation transistor M3 are turned on. With data writing transistor M2 on, the first terminal of driving transistor M4 is coupled to the data voltage output port VO of the display driver 20, allowing the driver to receive the data voltage Vdata output from this data voltage output port VO during the data voltage writing phase. That is, the source voltage of driving transistor M4 is Vdata. Therefore, the data voltage writing phase is the phase in which the data voltage Vdata is applied to the first terminal of driving transistor M4.

[0094] When the compensation transistor M3 is turned on, the gate of the driving transistor M4 is coupled to the second electrode, that is, the gate voltage of the driving transistor M4 is the same as the voltage of the second electrode, and the driving transistor M4 is in the on state.

[0095] Luminescence stage:

[0096] When the light emission control signal EM is low, the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.

[0097] The first terminal of the driving transistor M4 is coupled to the first power supply voltage input terminal, so that the first power supply voltage ELVDD output from the first power supply voltage input terminal can be received during the light-emitting stage. The first terminal of the compensation transistor M3 and the second terminal of the driving transistor M4 can be coupled to the anode a of the light-emitting device D. Therefore, the current path between the first power supply voltage ELVDD and the second power supply voltage ELVSS is turned on.

[0098] The driving current generated by the storage capacitor Cst through the driving transistor M4 is transmitted to the light-emitting device D through the aforementioned current path to drive the light-emitting device D to emit light.

[0099] In the example above, the pixel circuit includes 7 transistors and 1 capacitor; such a pixel circuit structure is called a 7T1C structure. The aforementioned transistors can be low-temperature polysilicon thin-film transistors (LTPS TFTs), or simply LTPS transistors. Of course, the aforementioned transistors can also be other types of transistors, and this application does not limit the specific types.

[0100] Figure 4 The pixel circuit with the 7T1C structure shown is only for illustrating the working principle of the pixel circuit. The pixel circuit with the 7T1C structure can also have other structures or signal timing.

[0101] For example, see Figure 5 , Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. Figure 4 In the pixel circuit shown, the first reset transistor M1 and the compensation transistor M3 can also be oxide thin-film transistors, which conduct when the gate voltage is high, thus forming a pixel circuit as shown. Figure 5 The image shows another pixel circuit structure. This technology, which combines low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors, is called low-temperature polycrystalline oxide (LTPO) technology. Its working principle is similar to... Figure 4 The pixel circuits shown operate on roughly the same principle, but it is necessary to distinguish the control signals for N-type transistors and P-type transistors, such as the strobe signal S. N-1 The gating signal S of the N-type transistor N-1 The gating signal S of [N] and P-type transistors N-1 [P], strobe signal S N It is also divided into the strobe signal S of N-type transistors. N The gating signal S of [N] and P-type transistors N [P]

[0102] The aforementioned 7T1C pixel circuit includes two reset transistors. In some other implementations, an additional reset transistor can be added, which can be used to reset the source or drain of the driving transistor.

[0103] For example, see Figure 6 , Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 6 The pixel circuit shown also includes a third reset transistor M8, the gate of which is used to receive a reset control signal Reset. N The reset control signal Reset N Used to control pixel circuit reset, such as the anode reset of the light-emitting device D and the first terminal reset of the driving transistor M4. The first terminal (e.g., the source) of the third reset transistor M8 is used to connect to the third initial voltage Vint3, and the second terminal (e.g., the drain) of the third reset transistor M3 is coupled to the first terminal of the driving transistor M4. When the reset control signal Reset is applied... N When the voltage is low, the third reset transistor M3 is turned on, and the voltage at the first terminal of the driving transistor M4 is the third initial voltage Vint3, thus completing the reset of the driving transistor M4. In some embodiments, the gate of the third reset transistor M3 can be coupled to the gate of the second reset transistor M7 to receive the same reset control signal Reset. N .

[0104] The pixel circuit structure described above includes 8 transistors and 1 capacitor. Such a pixel circuit is called an 8T1C structure pixel circuit. Figure 6 The 8T1C pixel circuit shown is merely an example to illustrate the working principle of a pixel circuit and is not a limitation on the structure of the pixel circuit. The 8T1C pixel circuit can also have other structures or signal timings. In addition, the pixel circuit can also have structures and variations such as 9T1C, 10T3C, 13T3C, and 16T3C, which are not limited in this application.

[0105] With the development of display technology, various screen brightness adjustment technologies have emerged, such as direct current (DC) dimming technology, which adjusts the screen brightness by changing the voltage to regulate the amplitude of the current density; pulse width modulation (PWM) technology, which adjusts the screen brightness by changing the duty cycle of the electrical signal; and quasi-DC dimming technology, which combines the characteristics of DC dimming technology and PWM dimming technology.

[0106] DC dimming controls display brightness by adjusting the screen's voltage or current, i.e., changing the power. For example, it adjusts the display brightness by regulating the data voltage of the pixel circuitry. Figure 6 A brief description of DC dimming in this embodiment is provided. For example... Figure 6 As shown, the first electrode of the data writing transistor M2 receives the data voltage Vdata. When the control data writing transistor M2 is turned on, the data voltage Vdata is transmitted through the data writing transistor M2, the driving transistor M4, and the compensation transistor M3 to the lower electrode of the storage capacitor Cstst. The storage capacitor Cst stores the data voltage signal Vdata, enabling the driving transistor M4 to generate a driving current based on the data voltage Vdata stored in the storage capacitor Cst, thereby controlling the light-emitting device D to emit light. The magnitude of the data voltage Vdata is related to the magnitude of the driving current. In DC dimming mode, the magnitude of the driving current is changed by adjusting the magnitude of the data voltage Vdata, thereby adjusting the brightness of the light-emitting device D and realizing the adjustment of the display brightness of the display device.

[0107] PWM dimming adjusts display brightness by regulating the duty cycle of the effective pulse signal (EM) of the pixel circuit's light-emitting control signal, such as a low-level pulse width duty cycle or a high-level pulse width duty cycle. (Continuing with...) Figure 6 The PWM dimming method in this embodiment will be briefly explained using an example. Figure 6As shown, the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 receive the light-emitting control signal EM. In this embodiment, both the first and second light-emitting control transistors M5 and M6 are P-channel transistors, and the low-level signal in the light-emitting control signal EM is used as an effective signal to control the conduction of the first and second light-emitting control transistors M5 and M6. When the low-level signal in the light-emitting control signal EM arrives, the first and second light-emitting control transistors M5 and M6 are turned on, allowing ELVDD to be transmitted through the first light-emitting control transistor M5 to the first terminal of the driving transistor M4. The second power supply voltage signal VSS is transmitted to the cathode of the light-emitting device D. The first and second power supply voltage signals ELVDD and ELVSS serve as the power source for the driving transistor M4 to generate the driving current, thus driving the light-emitting device D to emit light. The PWM dimming method, by adjusting the duty cycle of the low-level pulse in the light-emitting control signal EM, changes the emission time of the light-emitting device D within one frame, thereby adjusting the brightness of the light-emitting device D and realizing the adjustment of the display brightness. For example, during the display of each frame of an image, if the duty cycle of the PWM signal (referring to the light emission control signal EM) is 100%, that is, a constant DC signal, there is always current flowing through the path where the light emission device D is located, and the light emission device D is the brightest. However, when the PWM signal controls the first light emission control transistor M5 and the second light emission control transistor M6 to turn on and off with a high-frequency signal with a 50% duty cycle, there is current flowing through the path where the light emission device D is located 50% of the time, that is, the light emission device D emits light; while there is no current flowing through the other 50% of the time, that is, the light emission device D does not emit light. Therefore, visually, the brightness of the display is reduced by half.

[0108] DC-like dimming is a dimming method that adjusts both the magnitude of the data voltage and the duty cycle of the effective level of the light emission control signal EM.

[0109] Figure 7 This diagram illustrates a comparison of the light emission control signal EM for different dimming modes provided in this application. When the display screen uses DC dimming mode, the light emission control signal EM has one effective level during the display of one frame of image, meaning the light-emitting device emits light once, also known as a single pulse. When the display screen uses PWM dimming mode, the light emission control signal EM has multiple effective levels during the display of one frame of image, meaning the light-emitting device emits light multiple times, also known as a multi-pulse. When the display screen uses a DC-like dimming mode, the light emission control signal EM has a small number of effective levels during the display of one frame of image, and the light-emitting device also emits light multiple times, but fewer times than in DC dimming mode.

[0110] Because OLED displays lack a backlight, each pixel emits light independently. The power of the light-emitting device is inherently low at low brightness levels. Adjusting brightness by regulating power would result in large fluctuations in luminous power, leading to uneven color distribution and inaccurate color rendering at low brightness. Therefore, PWM dimming is typically used in the low-brightness dimming range. With PWM dimming, the brightness of the light-emitting device remains constant, while the overall display brightness is adjusted by regulating the duty cycle of the luminous control signal (EM). This provides good display performance in the low-brightness dimming range. High-brightness dimming can utilize DC dimming or DC-like dimming. The low-brightness dimming range refers to the dimming range where the display's luminous brightness is below a brightness threshold, while the high-brightness dimming range refers to the dimming range where the display's luminous brightness is above the brightness threshold. The brightness threshold can range from 70 nits to 100 nits; for example, it can be set to 90 nits, or the threshold value can be adjusted according to the specific application scenario.

[0111] The luminous emission control signal (EM) controls the alternation of brightness in light-emitting devices, which inevitably leads to flicker. As OLED displays become increasingly mainstream, flicker sensitivity and eye protection have become major concerns for users. Flicker refers to the perceptible flickering, i.e., the alternation of brightness on the screen. It is usually measured by the stroboscopic effect visibility measure (SVM). A higher SVM value indicates more severe flicker and poorer eye protection; a lower SVM value indicates less flicker and better eye protection. Experiments show that when the SVM value is greater than 0.4, it can easily cause eye discomfort in sensitive users, resulting in symptoms such as dry eyes, eye strain, and difficulty focusing.

[0112] One factor affecting the SVM value is the duty cycle and frequency of the light emission control signal EM of the display screen. In this embodiment, the duty cycle of the light emission control signal EM refers to the duty cycle of the effective signal, that is, the duty cycle of the pulse that controls the light emission of the light-emitting device, for example, combined with... Figure 6 Since the first light-emitting control transistor M5 and the sixth light-emitting control transistor M6 are P-type transistors, the effective pulse of the light-emitting control signal EM is low. With a constant duty cycle, the higher the frequency of the light-emitting control signal EM, the less likely the user is to perceive flicker, and the lower the SVM value.

[0113] The frequency of the luminous emission control signal (EM) of commercially available displays often exceeds the frequency that the human eye can distinguish. Users can roughly determine whether a display is eye-friendly by taking a picture of it with a camera. When the camera's shutter speed (referring to the camera's scanning frequency) is greater than the frequency of the EM signal, alternating bright and dark stripes can be observed on the display screen in the camera's view.

[0114] See Figure 8and Figure 9 , Figure 8 The diagram illustrates stripes displayed on the screens of several different devices when captured by a camera at low brightness. Figure 9 This diagram illustrates the stripes displayed on the screens of several different devices when captured by a camera at high brightness.

[0115] Figure 8 The displays of the devices shown employ PWM dimming when displaying low-brightness images. Devices A and B use high-frequency PWM dimming, resulting in fine, alternating bright and dark stripes when the display is photographed by a camera. The higher the PWM frequency, the finer and denser the stripes. Devices C and D use low-frequency PWM dimming, resulting in wider dark stripes, more noticeable flicker, and higher SVM values.

[0116] Figure 9 The displays of the illustrated devices employ DC dimming or DC-like dimming when showing high-brightness images. Device A uses DC dimming, and only one dark stripe appears when the camera captures the display. Devices B, C, and D use DC-like dimming, and multiple dark stripes appear when the camera captures the display. The number of dark stripes can represent the frequency of the emission control signal EM.

[0117] LTPO technology is now widely used in OLEDs. The off-state current of LTPO transistors is several orders of magnitude smaller than that of LTPS transistors, and the data retention time is longer. Therefore, the frequency of writing data voltage is lower, which can achieve a lower frame rate, such as 1Hz or even lower.

[0118] If the display supports a maximum frame rate of 120Hz, at that maximum frame rate, one frame refresh takes 8.33ms. The frame rate can be changed by inserting hold frames. For example, image frames that write data are used as refresh frames, and image frames that don't write data are used as hold frames. After writing data in the first image frame, the second image frame doesn't write data and serves as a hold frame; data is then written in the third image frame. This is equivalent to inserting a hold frame after each refresh frame, halving the actual frame rate to half the maximum frame rate, i.e., 60Hz. If two hold frames are inserted, the actual frame rate is one-third of the maximum frame rate, achieving a 40Hz frame rate. If three hold frames are inserted, a 30Hz frame rate can be achieved. As you can see, frame rates achievable from 120Hz downwards are 120 / K (where K is a positive integer), such as 120Hz, 60Hz, 40Hz, and 30Hz.

[0119] Similarly, if the highest frame rate supported by the display is 90Hz, it can support frame rates such as 45Hz and 30Hz.

[0120] The above-mentioned method of inserting and holding frames can achieve multiple frame rate switching, but it can only achieve frame rates that are divisible by the highest frame rate. For example, if the highest frame rate is 120Hz, it can support frame rates such as 60Hz and 30Hz. For frame rates such as 90Hz that are not divisible by 120Hz, it cannot be achieved by inserting and holding frames.

[0121] In practical applications, to achieve the switching between 120Hz and 90Hz frame rates, one possible approach is to set up two gamma voltage schemes. That is, the first gamma voltage scheme is used to support 120Hz refresh rate, and the second gamma voltage scheme is used to support 90Hz refresh rate.

[0122] See Figure 10 , Figure 10 This is a schematic diagram illustrating two different frame rates provided in the embodiments of this application. Figure 10 The upper and lower diagrams show the signal timing diagrams for the display screen at refresh rates of 120Hz and 90Hz, respectively. The light emission control signal EM controls whether the light-emitting device emits light or not. When the light emission control signal EM is low, the light-emitting device receives current and emits light. The strobe signal S... N [N] and gating signal S N [P] is used to control data writing; select the strobe signal S. N [N] and gating signal S N [P] When enabled, the data voltage is written to the storage capacitor Cst, completing the data refresh. Strobe signal S N-1 [N] is used to control the gate reset of the driving transistor before data is written. Reset control signal. N Used to control the anode reset of the light-emitting device before each emission of light.

[0123] Taking a 120Hz display as an example, in the low-brightness dimming range, the display uses PWM mode dimming. The light emission control signal EM is a multi-pulse signal per frame, and the reset control signal Reset... N One group per frame. Strobe signal S N-1 [N], strobe signal S N [N] and gating signal S N [P] There is only one pulse in each frame. The frequency of these control signals is the same as the frame rate (120Hz). When the light emission control signal EM is high and the light emission device does not emit light, operations such as reset and data writing are completed. In the high brightness dimming range, a single pulse light emission control signal EM is used per frame, and the timing of the other control signals is the same as the timing of the control signals in the PWM mode.

[0124] Taking a 90Hz display as an example, in the low-brightness dimming range, the display uses PWM mode dimming. The light emission control signal EM is a multi-pulse signal per frame, and the reset control signal Reset... N One group per frame, strobe signal S N-1 [N], strobe signal S N and strobe signal S N [P] There is only one pulse in each frame. The frequency of these control signals is the same as the frame rate (90Hz). When the light emission control signal EM is high and the light emission device does not emit light, operations such as reset and data writing are completed. In the high brightness dimming range, a single pulse light emission control signal EM is used per frame, and the timing of the other control signals is the same as the timing of the control signals in the PWM mode.

[0125] It can be seen that in a gamma voltage scheme, the reset control signal Reset N , Strobe signal S N-1 [N], strobe signal S N and strobe signal S N The frequency of the control signals [P] is constant. Since the pixel circuit needs to be reset before each data write, the maximum frame rate that the display screen can support is also related to the reset control signal Reset. N Frequency-dependent, for example, if the reset control signal Reset... N If the frequency is 120Hz, then the maximum frame rate the display can support is 120Hz, and it can also support frame rates that are divisible by 120Hz, such as 60Hz, 40Hz, and 30Hz. If the reset control signal is Reset... N If the frequency is 90Hz, then the maximum frame rate that the display can support is 90Hz, and it can also support frame rates such as 40Hz and 30Hz that are divisible by 90Hz.

[0126] To achieve frame rate compatibility of 120Hz and 90Hz using a single gamma voltage scheme, a higher frequency reset control signal (Reset) is required. N For example, the reset control signal Reset N The frequency can be set to 360Hz, meaning a reset (group) occurs every 2.778 milliseconds. Writing data every three resets achieves a 120Hz frame rate; writing data every four resets achieves a 90Hz frame rate. Thus, a single gamma voltage scheme can be used to support both 120Hz and 90Hz frame rates. Similarly, to support both 120Hz and 80Hz frame rates, a 240Hz reset control signal (Reset) can be selected. N Alternatively, you can choose a 480Hz reset control signal.

[0127] In other words, the reset control signal ResetN When the frequency and frame rate are the same, that is, when the image is reset once per frame, combined with... Figure 11 , Figure 11 This is a timing diagram of control signals for a display screen provided in an embodiment of this application. For a reset occurring once per frame, multiple sets of compatible, non-divisible frame rates of gamma voltage need to be set, such as 120Hz and 90Hz, or 120Hz and 80Hz, etc. Combined with... Figure 12 , Figure 12 This is a timing diagram of control signals for a display screen provided in an embodiment of this application. To achieve compatibility between two or more frame rates that are not divisible by each other using a single set of gamma voltages, a higher frequency reset control signal needs to be set, resetting multiple times per frame. This allows for the achievement of frame rates divisible by the frequency of the reset control signal. For example, combining... Figure 12 In the reset control signal Reset N At a frequency of 360Hz, a frame rate of 120Hz is achieved by writing data once every 3 resets, and a frame rate of 90Hz is achieved by writing data once every 4 resets.

[0128] Most current LTPO screens use the second approach, which involves multiple resets per frame to achieve a single set of gamma voltage-compatible, non-divisible frame rate schemes. However, resetting the light-emitting device requires it to be done when it is not emitting light, specifically when the luminous control signal (EM) is high. This results in the EM signal being pulled high multiple times during a single frame display, transforming the original DC dimming into a DC-like dimming. DC-like dimming exhibits worse flicker and a higher SVM value compared to DC dimming. Figure 9 When you take a picture of the screen with a camera, multiple dark stripes will appear.

[0129] To improve the flicker problem of displays supporting multiple frame rates in the high-brightness dimming range, and to restore the high-brightness dimming range to DC dimming mode so that only a dark stripe is displayed when the display is photographed, this application also provides a display driving method, see [link to relevant documentation]. Figure 13 The methods include:

[0130] In the first dimming interval, multiple anodes are reset during each frame of image display. PWM dimming is used, and a gamma voltage scheme is used to be compatible with the first frame rate and the second frame rate, wherein the first frame rate and the second frame rate are not divisible by each other.

[0131] In the second dimming interval, an anode is reset once during each frame of image display, DC dimming is used, and two gamma voltage schemes are used to be compatible with the first and second frame rates.

[0132] For example, the first frame rate is 120Hz and the second frame rate is 90Hz. Or, the first frame rate and the second frame rate are 120Hz and 80Hz respectively.

[0133] The reason for grouping anode resets here is that in some cases, the anode can be reset multiple times consecutively, and these multiple resets are considered as a group. In other cases, the anode reset may only occur once, in which case a single reset is considered as a group. Alternatively, multiple consecutive resets may be performed each time the anode is reset.

[0134] In the first dimming interval, the anode can be reset multiple times during one frame of an image. High-frequency PWM dimming can be used; the higher the frequency, the weaker the flicker. During the display of one frame of an image, the light emission control signal includes multiple pulses, meaning the display screen will switch between bright and dark multiple times. When the display screen is not emitting light, the anode of the light-emitting device can be reset. The frame rate can be switched by selecting which reset to write data. A single gamma voltage scheme can be compatible with the first and second frame rates, which are not divisible by each other.

[0135] In the second dimming interval, during the display of one frame of an image, the light emission control signal consists of a single pulse, meaning DC dimming can be used. The anode of the light-emitting device is reset once per frame, and data is written after the reset. Therefore, the frame rate of the display screen is the same as the reset frequency. Typically, one gamma voltage scheme corresponds to one reset frequency. In the second dimming interval, two gamma voltage schemes can be used to achieve a compatible first and second frame rates that are not divisible each other.

[0136] In one possible implementation, the driving method includes:

[0137] In the first dimming interval, a reset control signal of a first frequency is output to the display screen. This reset control signal is used to control the anode reset of the light-emitting devices in the pixel circuit. A light-emitting control signal of a third frequency is output to the display screen, and this third frequency light-emitting control signal appears in multiple pulses during each frame of image display.

[0138] In the second dimming zone, a reset control signal of the second frequency is output to the display screen, and a light emission control signal of the fourth frequency is output to the display screen. The light emission control signal of the fourth frequency appears as a single pulse during each frame of image display. The first frequency is different from the second frequency; the third frequency is different from the fourth frequency.

[0139] See Figure 14 and Figure 15The first dimming zone can be a low-brightness dimming zone, and the second dimming zone can be a high-brightness dimming zone. In the low-brightness dimming zone, high-frequency PWM dimming can be used, for example, frequencies such as 360Hz, 480Hz, 960Hz, 1440Hz, and 3880Hz. Using a light emission control signal (EM) with a frequency greater than 1000Hz in the low-brightness dimming zone can significantly improve the screen's flicker and SVM index. Furthermore, since the light emission control signal (EM) in the low-brightness dimming zone is a multi-pulse signal, the light-emitting device will switch between bright and dark multiple times during the display of one frame of image. Therefore, an anode reset can be performed when the light-emitting device is not emitting light. In other words, in the low-brightness dimming zone, multiple anode resets can be used during the display of one frame of image. By reasonably setting the frequency of the anode reset, compatibility with various refresh rates can be achieved.

[0140] For example, the anode reset frequency can be set to 360Hz, such as Figure 14 As shown, the reset control signal Reset is used to control the anode reset of the light-emitting device. N The refresh rate is set to 360Hz. If data is written every three anode resets, the data writing frequency is 120Hz, resulting in a frame rate of 120Hz. Based on this 120Hz frame rate, more refresh rates such as 60Hz, 40Hz, 30Hz, 20Hz, and 10Hz can be achieved by inserting hold frames. If data is written every four anode resets, the data writing frequency is 90Hz, resulting in a frame rate of 90Hz. Based on this 90Hz frame rate, frame rates such as 45Hz and 30Hz can be achieved by inserting hold frames.

[0141] Alternatively, the reset control signal Reset is used to control the anode reset of the light-emitting device. N The frequency is set to 240Hz. If data is written every two anode resets, the data writing frequency is 120Hz, resulting in a frame rate of 120Hz. Based on this 120Hz, more refresh rates such as 60Hz, 40Hz, 30Hz, 20Hz, and 10Hz can be achieved by inserting hold frames. If data is written every three anode resets, the data writing frequency is 80Hz, resulting in a frame rate of 80Hz. Based on this 80Hz frame rate, frame rates such as 40Hz and 20Hz can be achieved by inserting hold frames.

[0142] In the first dimming zone, PWM mode dimming is used. The frequency of the light emission control signal EM can be the same as or different from the frequency of the anode reset. However, since the anode reset needs to be completed when the light emission control signal is high and the light-emitting device is not emitting light, the frequency of the light emission control signal EM must be greater than or equal to the frequency of the anode reset.

[0143] As can be seen from the timing diagram, with this driving method, the luminous emission control signal EM has multiple pulses and the anode is reset multiple times during the display of one frame of image. A single gamma voltage scheme can achieve various refresh rates; for example, it can be compatible with 120Hz and 90Hz when the anode reset frequency is 360Hz, and with 120Hz and 80Hz when the anode reset frequency is 240Hz. Furthermore, in the first dimming zone, the frequency of the luminous emission control signal EM can be even higher, such as 1440Hz, which can improve the flicker of the display screen in the first dimming zone, resulting in multiple fine, alternating bright and dark stripes when the display screen is photographed.

[0144] In the second dimming zone, for example, the second dimming zone can be a high-brightness dimming zone. In order to improve the flicker of the display screen and reduce the SVM value, a single-pulse light emission control signal is used for dimming, such as... Figure 15 As shown, during the display of one frame of an image, the light-emitting control signal EM has only one low level (or high level), and the light-emitting device switches on and off only once. However, anode reset needs to be performed while the light-emitting device is not emitting light. Therefore, during the display of one frame of an image, the anodes of the light-emitting device are also reset once. After the anode reset, data is written. The frame rate of the display is the same as the anode reset frequency. The display supports a specific refresh rate, as well as other frame rates achieved by inserting hold frames based on that frame rate. For example, if the anode reset frequency is 120Hz, then the maximum frame rate supported by the display is 120Hz, or refresh rates such as 60Hz, 40Hz, 30Hz, and 20Hz can be achieved by inserting hold frames based on 120Hz.

[0145] Alternatively, the anode reset frequency is 90Hz, the maximum frame rate supported by the display is 90Hz, and refresh rates such as 45Hz and 30Hz are achieved by inserting hold frames based on the 90Hz frame rate.

[0146] Since the frequency of control signals, such as the reset control signal, remains constant after the display leaves the factory, two sets of gamma voltage schemes need to be pre-set to support frame rates such as 120Hz and 90Hz, or pre-set two sets of gamma voltage schemes to support frame rates such as 120Hz and 80Hz. In the second dimming zone, for example, the high-brightness dimming zone, the display dims in DC mode and supports multiple frame rates that are not divisible by each other through multiple gamma voltage schemes. During each frame display, the light emission control signal has only one pulse, and the anode of the light-emitting device is reset only once. Compared to DC-like dimming that resets the anode multiple times per frame to accommodate multiple frame rates, this reduces the number of screen brightness switching times, improves the flicker problem in the second dimming zone, reduces the SVM value, and enhances eye protection performance.

[0147] In this embodiment, the first dimming zone can be a low-brightness dimming zone, and the second dimming zone can be a high-brightness dimming zone. The two dimming zones are divided based on the brightness of the display screen. Alternatively, they can be divided using other methods, such as display brightness value (DBV), different gamma bands, or different ELVSS nodes. Alternatively, the first and second dimming zones can be divided based on the overall operating status of the device. For example, the DBV of the first dimming zone is lower than the DBV of the second dimming zone.

[0148] In one implementation, the method provided in this application embodiment further includes:

[0149] The timing of the control signal output to the display screen in the first dimming zone is different from that of the control signal output to the display screen in the second dimming zone.

[0150] Here, the control signals include the light emission control signal EM and the reset control signal, or may include any other control signals.

[0151] In the foregoing Figure 12 In the scheme shown, apart from the timing of the light emission control signal EM, the timing of the other control signals, especially the reset control signal, is the same in the low-brightness dimming range and the high-brightness dimming range. In practical applications, this may result in insufficient darkness during PWM dimming, which is not conducive to full-band flicker optimization. The scheme provided in this application provides different frequencies for the reset control signal in the first dimming range and the second dimming range, which allows for more precise adjustments in different dimming ranges, which is beneficial for flicker optimization and improves the display effect of the screen.

[0152] For example, the pulse width of the reset control signal output to the display screen in the first dimming zone is different from the pulse width of the reset control signal output to the display screen in the second dimming zone. The reset control signal is used to control the reset of the pixel circuit, such as the anode reset of the light-emitting device, or the reset of the driving transistor M4.

[0153] In the foregoing Figure 12 In the example shown, the timing and pulse width of the reset control signal are the same in both the low-brightness dimming range and the high-brightness dimming range. However, the pulse width of the reset control signal is small, and the reset time is short. This may not be enough to fully reset the pixel circuit, potentially leaving residual charge and causing problems such as black pixels appearing shiny or inconsistent light emission. See the embodiments in this application. Figure 16 The frequencies and pulse widths of the reset control signals output to the pixel circuit of the display screen can differ between the first dimming zone and the second dimming zone. For example, the pulse width of the reset control signal can be larger. Figure 16 As shown, the pulse width of the reset control signal selected by the dashed box at mark 1 is different from the pulse width of the reset control signal selected by the dashed box at mark 2 and the pulse width of the reset control signal selected by the dashed box at mark 3. This removes the restriction on the pulse width of the reset control signal. When necessary, the pulse width of the reset control signal can be changed to change the reset time of the pixel circuit, which can improve problems such as inconsistent brightness of black or light.

[0154] Furthermore, the method provided in this application embodiment also includes: when the light emission control signal EM is a multi-pulse control signal, the pulse widths of different pulses can be inconsistent. Here, the pulse refers to the high-level pulse of the light emission control signal EM, that is, the pulse that controls the light-emitting device to not emit light. The pixel circuit reset is performed when the light-emitting device is not emitting light. If the pulse width of the reset control signal can be different, the pulse width of the light emission control signal EM can also be different. For example, if it is necessary to extend the duration of the pixel circuit reset, the high-level duration of the light emission control signal EM can be appropriately extended to ensure that the reset can be completed.

[0155] Furthermore, since the frequencies of the light emission control signals EM in the first dimming zone and the second dimming zone are different—for example, the light emission control signal EM in the first dimming zone is a multi-pulse high-frequency PWM signal, while the light emission control signal EM in the second dimming zone is a single-pulse low-frequency PWM signal—to avoid flickering or other problems caused by switching between these two different signal states, the solution provided in this application embodiment further includes:

[0156] When controlling the light emission control signal to switch from the third frequency to the fourth frequency, first control the light emission control signal frequency to switch from the third frequency to the fifth frequency, and then control the light emission control signal frequency to switch from the fifth frequency to the fourth frequency.

[0157] Alternatively, when switching the frequency of the light emission control signal from the fourth frequency to the third frequency, first switch the frequency of the light emission control signal from the fourth frequency to the fifth frequency, and then switch the frequency of the light emission control signal from the fifth frequency to the third frequency; the fifth frequency is the frequency value between the third frequency and the fourth frequency.

[0158] For example, see Figure 17 Taking the switching of the light emission control signal EM from a single pulse per frame to multiple pulses per frame as an example, at the switching node, the light emission control signal EM can first be switched from a single pulse per frame to three pulses per frame, and this state can be maintained for a transition period of time before switching the light emission control signal EM from three pulses per frame to multiple pulses per frame. The adjustment of the reset control signal can be synchronized with the adjustment of the light emission control signal.

[0159] Or, see Figure 18 The light emission control signal EM can be switched from a single pulse per frame to multiple pulses per frame, while the reset control signal remains unchanged for the time being. After a period of transition with the switched light emission control signal EM, the frequency of the reset control signal can be switched to achieve multiple anode resets per frame.

[0160] The above examples are merely examples of control signal switching provided in the embodiments of this application. Any behavior that involves transition at the switching node is within the scope of protection of this patent.

[0161] In one implementation, the display screen includes multiple rows of pixel circuits. When designing the drivers around the pixel circuits, a strobe signal S is typically used. N [N] represents the 1-to-2 drive configuration, i.e., each strobe signal S N [N] is used to drive the two rows of pixel circuits; while the strobe signal S... N [P] is typically used to drive a row of pixel circuits, which can cause the data write times of adjacent rows to be different, resulting in inconsistent brightness between adjacent rows of pixels and causing fine horizontal lines to appear on the display screen. To improve this problem, the driving method provided in this application embodiment further includes:

[0162] The write time for writing data to the first row of pixel circuits is different from the write time for writing data to the second row of pixel circuits. The first row of pixel circuits and the second row of pixel circuits are two different rows of pixel circuits.

[0163] For example, in the embodiments of this application, combined with Figure 6 strobe signal S N [P] is used to control the conduction state of the data writing transistor M2, in the strobe signal S. NWhen [P] is low, the data writing transistor M2 is turned on, and the data voltage Vdata is written to the pixel circuit through the turned-on data writing transistor M2. The strobe signal S... N [P] The duration of each low-level pulse is the time required for one data write operation.

[0164] The first row of pixel circuits and the second row of pixel circuits are two different rows of pixel circuits. For example, they can be two adjacent rows of pixel circuits, where the first row of pixel circuits is an odd-numbered row and the second row of pixel circuits is an even-numbered row; or the first row of pixel circuits is an even-numbered row and the second row of pixel circuits is an odd-numbered row.

[0165] like Figure 19 As shown, the strobe signal S N [P] is the gating signal that controls the data writing transistor M2 of the first row pixel circuit to turn on. The gating signal S... N-1 [P] is the gating signal for controlling the data writing transistor M2 of the second row pixel circuit to turn on. The solution provided in this application embodiment uses the gating signal S... N [P], strobe signal S N-1 The pulse width of [P] was adjusted from the same to different, and the original gating signal S N [P], strobe signal S N-1 The pulse width of [P] is always a. In the scheme provided by the embodiments of this application, the gating signal S N The pulse width of [P] is b, and the gating signal S N-1 The pulse width of [P] is a, and b can be greater than a, thus controlling the gating signal S output to the first row pixel circuit. N [P] and the gating signal S output to the second row pixel circuit. N-1 By varying the pulse duration of [P], the writing time for writing data to the first row of pixel circuits can be different from the writing time for writing data to the second row of pixel circuits. This allows for adjustment of the data writing duration for both, preventing fine horizontal lines from appearing on the display screen.

[0166] In one implementation, the first row of pixel circuits is an odd-numbered row of pixel circuits on the display screen, and the second row of pixel circuits is an even-numbered row of pixel circuits on the display screen. Alternatively, the first row of pixel circuits and the second row of pixel circuits can be any two different rows of pixel circuits on the display screen.

[0167] This application also provides a display driver, such as the one described above. Figure 2 The display driver shown is used to connect to the display screen and output control signals to the display screen to implement the driving method provided in the foregoing embodiments of this application.

[0168] This application embodiment also provides a display module, such as the aforementioned one. Figure 2The display module shown includes a display driver and a display screen. The display driver is connected to the display screen and is used to provide data voltage, reset signal and control signal to the display screen to implement the driving method provided in the foregoing embodiments of this application.

[0169] This application also provides an electronic device, for example, see [link to relevant documentation]. Figure 20 The electronic device includes a mid-frame 41, a housing 42, and a display module 43 as described in the previous example. Both the display module 43 and the housing 42 are connected to the mid-frame 41. The display module 43 is disposed on one side of the mid-frame 41, and the housing 42 is disposed on the other side of the mid-frame 41. The mid-frame 41 supports and protects the display module 43. In some possible implementations, the mid-frame 41 and the housing 42 can be integrally formed.

[0170] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driving method for a display screen, characterized in that, The method includes: In the first dimming zone, multiple sets of anodes are reset during each frame of image display. A single gamma voltage scheme is used to be compatible with both the first and second frame rates, where the first and second frame rates are not divisible by each other. In the second dimming interval, an anode is reset once during each frame of image display, and two gamma voltage schemes are used to be compatible with the first frame rate and the second frame rate.

2. The method according to claim 1, characterized in that, The method includes: In the first dimming zone, a reset control signal of the first frequency is output to the display screen. The reset control signal is used to control the anode reset of the light-emitting device of the pixel circuit. In the second dimming range, a reset control signal of a second frequency is output to the display screen, the first frequency being different from the second frequency.

3. The method according to claim 2, characterized in that, The first frequency is an integer multiple of the first frame rate, and the first frequency is an integer multiple of the second frame rate.

4. The method according to any one of claims 1 to 3, characterized in that, The method includes: In the first dimming zone, a third frequency light emission control signal is output to the display screen, and the third frequency light emission control signal has multiple pulses during each frame of image display; In the second dimming zone, a fourth frequency light emission control signal is output to the display screen, the fourth frequency light emission control signal having a single pulse during each frame of image display.

5. The method according to claim 4, characterized in that, The width of each pulse in the multiple pulse light emission control signals may be the same or different.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: The frequency of the light control signal output to the display screen is different from the frequency of the reset control signal output to the display screen.

7. The method according to claim 4, characterized in that, The method further includes: When controlling the light emission control signal to switch from the third frequency to the fourth frequency, first control the frequency of the light emission control signal to switch from the third frequency to the fifth frequency, and then control the frequency of the light emission control signal to switch from the fifth frequency to the fourth frequency; or, When controlling the frequency of the light emission control signal to switch from the fourth frequency to the third frequency, first control the frequency of the light emission control signal to switch from the fourth frequency to the fifth frequency, and then control the frequency of the light emission control signal to switch from the fifth frequency to the third frequency; The fifth frequency is the frequency value between the third frequency and the fourth frequency.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: The timing of the control signal output to the display screen in the first dimming zone is different from that of the control signal output to the display screen in the second dimming zone. The control signal includes a light emission control signal and a reset control signal.

9. The method according to claim 8, characterized in that, The method further includes: The pulse width of the reset control signal output to the display screen in the first dimming zone is different from the pulse width of the reset control signal output to the display screen in the second dimming zone.

10. The method according to any one of claims 1 to 9, characterized in that, The display screen includes a multi-row pixel circuit, which includes a first row pixel circuit and a second row pixel circuit. The method further includes: The write time for writing data to the first row of pixel circuits is different from the write time for writing data to the second row of pixel circuits.

11. The method according to claim 10, characterized in that, The first row of pixel circuits is the odd-numbered row of pixel circuits of the display screen, and the second row of pixel circuits is the even-numbered row of pixel circuits of the display screen.

12. The method according to any one of claims 1 to 11, characterized in that, The display brightness of the first dimming zone is lower than that of the second dimming zone; or, the brightness level of the first dimming zone is lower than that of the second dimming zone.

13. A display driver, characterized in that, The display driver is used to connect to a display screen, and the display driver is used to perform the method as described in any one of claims 1 to 12.

14. A display module, characterized in that, The display module includes a display driver and a display screen, the display driver being connected to the display screen, and the display driver being used to perform the method as described in any one of claims 1 to 12.

15. An electronic device, characterized in that, The electronic device includes a housing and a display module as described in claim 14, the display module being mounted on the housing.

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