Display device and driving method thereof

Abstract

The disclosure relates to a display device and a driving method thereof. The display device includes a display panel on which a sub-pixel is formed, each of the sub-pixels including a driving transistor configured to generate a driving current for driving a light emitting element and at least one light emission control transistor configured to apply a high potential voltage to the driving transistor, a gate driver configured to receive a gate high voltage and a gate low voltage and output a gate signal for controlling a transistor included in the sub-pixel, and a power supply configured to provide the gate high voltage set according to a voltage level of the high potential voltage to the gate driver.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, for example, but not limited to, a display apparatus and a driving method thereof. Background Technology

[0002] Electroluminescent display devices have the advantages of fast response speed, high luminous efficiency, and wide viewing angle. Electroluminescent display devices that include multiple sub-pixels can display images by emitting light from the light-emitting element of each sub-pixel.

[0003] The light-emitting element can be based on organic or inorganic materials. The display device may include a display panel having multiple sub-pixels, a driving unit configured to output driving signals for driving the display panel, and a power supply configured to generate power to be supplied to the display panel and the driving unit.

[0004] To reduce power consumption, various technologies have been applied to such display devices. However, since previously proposed methods have room for improvement, research continues on increasing power reduction while maintaining panel performance. Summary of the Invention

[0005] Therefore, this disclosure relates to a display device and a driving method thereof, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0006] Therefore, this disclosure provides a display device and its driving method that can improve or maximize the power consumption reduction effect.

[0007] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims herein and in the accompanying drawings.

[0008] To achieve these objectives and other advantages and in accordance with the purposes of this disclosure, as realized and broadly described herein, a display device includes: a display panel having sub-pixels formed thereon, each of the sub-pixels including a driving transistor and at least one light-emitting control transistor, the driving transistor being configured to generate a driving current for driving a light-emitting element, and the at least one light-emitting control transistor being configured to apply a high-potential voltage to the driving transistor; a gating driver being configured to receive a gating high voltage and a gating low voltage, and to output a gating signal for controlling at least one light-emitting control transistor included in the sub-pixels; and a power supply being configured to provide the gating driver with a gating high voltage set according to the voltage level of the high-potential voltage.

[0009] The difference between the high potential voltage and the gating high voltage can be kept constant based on the offset value.

[0010] The display device may also include a memory configured to store the offset value per brightness of the image data and high-potential voltage setting information.

[0011] The display device may further include a controller configured to generate brightness information of image data; and a data driver configured to receive the brightness information from the controller and control the power supply to output a high-potential voltage corresponding to the brightness information according to high-potential voltage setting information for each brightness stored in a memory.

[0012] The data driver can set the gating high voltage by applying an offset value to a high potential voltage corresponding to the brightness information, and control the power supply to provide the set gating high voltage to the data driver.

[0013] One of the at least one light-emitting control transistors may include a gate electrode configured to receive a gating signal, a first electrode configured to receive a high-potential voltage, and a second electrode connected to the source electrode of the driving transistor.

[0014] At least one light-emitting control transistor may include a P-type thin-film transistor.

[0015] At least one light-emitting control transistor can be turned off by receiving a gating high voltage to select a gating signal.

[0016] The offset value is set based on a positive offset value of the threshold voltage and high potential voltage of at least one light-emitting control transistor.

[0017] In another aspect of this disclosure, a method for driving a display device is provided. The display device includes a display panel having sub-pixels formed thereon. Each sub-pixel includes a driving transistor configured to generate a driving current for driving a light-emitting element and at least one light-emitting control transistor configured to apply a high-potential voltage to the driving transistor. The method includes the steps of: setting a voltage level of the high-potential voltage according to the brightness of an input image; setting a level of a gating high voltage by applying a preset offset value to the voltage level of the high-potential voltage; and generating a light-emitting control signal that oscillates between the gating high voltage and the gating low voltage to output the generated light-emitting control signal to the display panel.

[0018] One of the at least one light-emitting control transistors may include a gate electrode configured to receive a gating signal, a first electrode configured to receive a high-potential voltage, and a second electrode connected to the source electrode of the driving transistor.

[0019] At least one light-emitting control transistor may include a P-type thin-film transistor.

[0020] The step of setting the level of the gating high voltage may include setting the voltage level of the gating high voltage such that the voltage difference between the high potential voltage and the gating high voltage is set to a voltage level that allows a light-emitting control transistor to be turned off.

[0021] The offset value is set based on a positive offset value of the threshold voltage and high potential voltage of at least one light-emitting control transistor.

[0022] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0023] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0024] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Figure 1 This is a schematic block diagram of a display device according to one embodiment of the present disclosure; Figure 2 This is an example of an embodiment of the present disclosure including... Figure 1 The circuit diagram of the sub-pixels in the display device and the diagram of the current flowing in each driving period; Figure 3 This is according to one embodiment of the present disclosure. Figure 2 Waveform diagrams of the scanning signal and the light emission control signal of the sub-pixel; Figure 4 This is a description of an embodiment of the present disclosure for variable control. Figure 2 A diagram showing considerations for high potential voltage EVDD and gating high voltage VGH in sub-pixels; Figure 5 This is a schematic configuration diagram of an optical compensation system applied to a display device according to one embodiment of the present disclosure; Figure 6 This is a diagram illustrating information regarding the setting of the high potential voltage EVDD per luminance according to one embodiment of the present disclosure; Figure 7 This is a flowchart of an optical compensation method applied to a display device according to one embodiment of the present disclosure; Figure 8 This is a diagram illustrating a configuration for controlling the gate high voltage VGH of a display device according to an embodiment of the present disclosure; and Figure 9 This is a flowchart of a method for selecting a high voltage VGH in a control display device according to an embodiment of the present disclosure.

[0025] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals shall be construed as referring to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and depictions of these elements may be exaggerated. Detailed Implementation

[0026] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always refer to the same elements. The names of the corresponding elements used in the following explanation may be chosen solely for the convenience of writing the specification and may therefore differ from those used in actual products.

[0027] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, and can be implemented in various different forms. The embodiments of this disclosure are provided only to make the disclosure complete and to enable those skilled in the art to fully understand the scope of this disclosure.

[0028] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the drawings for illustrative purposes are exemplary, and therefore this disclosure is not limited to the illustrated matters. Throughout the specification, the same reference numerals denote the same components. When terms such as "comprising," "having," and "consisting of" are used in this disclosure, other components may be added unless "only" is used. When a component is expressed in the singular, this includes cases where the components are plural, unless specifically and explicitly described.

[0029] When interpreting a component, it is interpreted as including a range of errors, even without a separate explicit description.

[0030] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", etc., one or more other parts may be located between the two parts unless "immediately" or "directly" is used.

[0031] Although the terms first, second, etc., can be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can be a second component within the technical concept of this disclosure.

[0032] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0033] When describing temporal relationships, when the temporal order is described as such as "after", "following", "next" and "before", discontinuous situations may be included unless more restrictive terms such as "exactly", "immediately" or "directly" are used.

[0034] The expressions "first element," "second element," and " / or" "third element" should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0035] The term “at least one” should be understood to include any and all combinations of one or more associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0037] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0038] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may be interoperable and technically driven differently from each other. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0039] Furthermore, the pixel circuitry and gating driver of the display device described later may include multiple transistors. These transistors may be implemented as oxide thin-film transistors (TFTs) including oxide semiconductors, LTPSTFTs including low-temperature polycrystalline silicon (LTPS), etc. Each of the transistors may be implemented as a p-channel TFT or an n-channel TFT.

[0040] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. Inside the transistor, charge carriers begin to flow out from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0041] The gating signal oscillates between the gate on-state voltage and the gate off-state voltage. The gate on-state voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-state voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage. In an n-channel transistor, the gate on-state voltage can be a high gate voltage (VGH), and the gate off-state voltage can be a low gate voltage (VGL). In a p-channel transistor, the gate on-state voltage can be VGL, and the gate off-state voltage can be VGH.

[0042] Each pixel of an electroluminescent display device includes a light-emitting element and a driving element. The driving element generates a pixel current based on the voltage between the gate and the source to drive the light-emitting element. The light-emitting element includes an anode, a cathode, and an organic compound layer formed between them. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When the pixel current flows through the light-emitting element, holes passing through the HTL and electrons passing through the ETL move to the EML, thereby forming excitons, and thus the EML can emit visible light.

[0043] Throughout this specification, the same reference numerals denote substantially the same components. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In the following description, detailed descriptions of well-known functions or structures relevant to this disclosure are omitted where such unnecessarily detailed descriptions might obscure the gist of the disclosure.

[0044] Figure 1 This is a block diagram schematically illustrating a display device according to one embodiment of the present disclosure.

[0045] Reference Figure 1 The display device 10 includes a display panel 100 having a plurality of sub-pixels SP, a controller 200, a gating driver 300 configured to provide a gating signal to each of the plurality of sub-pixels SP, a data driver 400 configured to provide a data signal to each of the plurality of sub-pixels SP, and a power supply 500 configured to provide power required for driving each of the plurality of sub-pixels SP.

[0046] The display panel 100 has multiple intersecting gate lines GL and multiple intersecting data lines DL, and each of the multiple sub-pixels SP is connected to both the gate lines GL and the data lines DL. Specifically, a sub-pixel SP receives a gate signal from the gate driver 300 via the gate line GL, receives a data signal from the data driver 400 via the data line DL, and receives a high-potential voltage EVDD and a low-potential voltage EVSS from the power supply 500.

[0047] Here, the gating line GL provides the gating signal, and the data line DL provides the data voltage signal Vdata. The gating signal may include a scan signal SC and an illumination control signal EM. Therefore, the gating line GL may include multiple scan lines SCL providing the scan signal SC and an illumination control signal line EML providing the illumination control signal EM. In addition, each of the multiple sub-pixels SP may further include a power line VL for receiving the anode reset voltage VAR, the initialization voltage Vref, etc.

[0048] The controller 200 appropriately processes the RGB image data input from the host system according to the size and resolution of the display panel 100, and provides the image data to the data driver 400. The controller 200 can analyze the brightness of the input RGB image data and provide the corresponding brightness band information of the image to the data driver 400.

[0049] The host system can be one of the following: TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system.

[0050] The controller 200 generates a gating control signal GCS for controlling the operating timing of the gating driver 300 and a data control signal DSC for controlling the operating timing of the data driver 400 based on the timing signals Vsync, Hsync and DE received from the host system.

[0051] The gating driver 300 can be arranged on one or both sides of the display panel 100 in a GIP (Gating in Panel) configuration. The gating driver 300 can sequentially output gating signals to the gating line GL according to the gating control signal GCS provided from the controller 200. In an organic light-emitting display device, the gating signal can include a scan signal SC and a light-emitting control signal EM. Therefore, the gating driver 300 can include a light-emitting control signal driver 310 that outputs the light-emitting control signal EM and a scan driver 320 that outputs the scan signal SC.

[0052] The scan signal SC and the light emission control signal EM output from the gating driver 300 may include pulses that oscillate between a gating low voltage VGL and a gating high voltage VGH. In embodiments of this disclosure, the voltage level of the gating high voltage VGH of each of the scan signal SC and the light emission control signal EM may be set to vary according to the voltage level of the high potential voltage EVDD.

[0053] The data driver 400 can convert image data RGB into a data voltage signal Vdata according to the data control signal DCS provided from the controller 200, and provide the converted data voltage signal Vdata to the sub-pixel SP through the data line DL. The data driver 400 may include multiple integrated circuit ICs and may be arranged in multiple separate sections on one side of the display panel 100.

[0054] The data driver 400 according to embodiments of the present disclosure may include a memory MEM that stores gating high voltage VGH setting information and high potential voltage EVDD setting information based on the brightness of image data RGB. The memory MEM can store the high potential voltage EVDD setting information based on the grayscale of the image data RGB. Additionally, it may store gating high voltage VGH setting information for setting the gating high voltage VGH based on the voltage level of the high potential voltage EVDD. The gating high voltage VGH setting information can be stored as an offset value added to the high potential voltage EVDD. The high potential voltage EVDD setting information and the gating high voltage VGH setting information stored in the memory MEM can be stored during optical compensation of the display device 10. The storage process and application method of the high potential voltage EVDD setting information and the gating high voltage VGH setting information stored in the memory MEM will be described in more detail later.

[0055] The power supply 500 can receive an externally applied DC input voltage to generate a DC voltage (e.g., gating low voltage VGL, gating high voltage VGH, high potential voltage EVDD, and low potential voltage EVSS).

[0056] The power supply 500 uses a DC-DC converter to generate the DC power required to drive the pixel array and display panel driver of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0057] Figure 2 Examples include Figure 1 The circuit diagram of the sub-pixels in the display device and the diagram of the current flowing in each driving period, and Figure 3 yes Figure 2 The waveforms of the scanning signal and the light emission control signal of the sub-pixel.

[0058] Reference Figure 2 A sub-pixel SP can be provided with a high potential voltage EVDD, a low potential voltage EVSS, an initialization voltage Vref, and an anode reset voltage VAR, and can receive a first scan signal SC1 to a third scan signal SC3, a first light emission control signal EM1, a second light emission control signal EM2, and a data voltage signal Vdata.

[0059] A sub-pixel SP may include an organic light-emitting diode (OLED), seven transistors T1 to T7, and two capacitors Cst and CA. Each of the transistors T1 to T7 in the sub-pixel SP can be configured as a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS). In this embodiment, the fifth transistor T5 is implemented as p-type, and each of the remaining transistors T1 to T4 and T6 to T7 is implemented as n-type. Therefore, when a low voltage is applied to the gate electrode, the fifth transistor T5 is turned on, and when a high voltage is applied to the gate electrode, each of the remaining transistors T1 to T4 and T6 to T7 is turned on.

[0060] The OLED emits light through a drive current supplied from the first transistor T1. The anode of the OLED can be connected to the fourth node N4, and the cathode of the OLED can be connected to wiring that provides a low potential voltage EVSS.

[0061] The first transistor T1 can correspond to a driving transistor. The first transistor T1 can have a gate electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The first transistor T1 can generate a driving current supplied to the OLED based on the voltage of the second node N2.

[0062] The second transistor T2 can be turned on in response to the first scan signal SC1. When the first scan signal SC1 is applied at a high level, the second transistor T2 is turned on and applies the data voltage signal Vdata to the second node N2, which serves as the gate electrode of the first transistor T1. The second transistor T2 may include a gate electrode connected to the input line of the first scan signal SC1, a first electrode connected to the data line to which the data voltage signal Vdata is provided, and a second electrode connected to the second node N2. The second transistor T2 may be a data providing transistor.

[0063] The third transistor T3 can be turned on in response to the second scan signal SC2. When the second scan signal SC2 is applied at a high level, the third transistor T3 turns on and applies the initialization voltage Vref to the second node N2 of the first transistor T1. The third transistor T3 may include a gate electrode connected to the input line of the second scan signal SC2, a first electrode connected to the power line of the initialization voltage Vref, and a second electrode connected to the second node N2.

[0064] The fourth transistor T4 can be turned on in response to the first light emission control signal EM1. When the first light emission control signal EM1 is input at a high level, the fourth transistor T4 is turned on and applies the anode reset voltage VAR to the fourth node N4 connected to the anode of the OLED. The fourth transistor T4 may include a gate electrode connected to the input line of the first light emission control signal EM1, a first electrode connected to the power line of the anode reset voltage VAR, and a second electrode connected to the fourth node N4.

[0065] The fifth transistor T5 can be turned on in response to the first light-emitting control signal EM1. When the first light-emitting control signal EM1 is input at a low level, the fifth transistor T5 is turned on and can send a high-potential voltage EVDD to the first node N1 of the first transistor T1. The fifth transistor T5 may include a gate electrode connected to the input line of the first light-emitting control signal EM1, a first electrode connected to the power line of the high-potential voltage EVDD, and a second electrode connected to the first node N1.

[0066] The sixth transistor T6 can be turned on in response to the second light emission control signal EM2. When the second light emission control signal EM2 is input at a high level, the sixth transistor T6 can be turned on and can connect the third node N3 of the first transistor T1 and the fourth node N4 of the OLED. The sixth transistor T6 may include a gate electrode connected to the input line of the second light emission control signal EM2, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0067] The seventh transistor T7 can be turned on in response to the third scan signal SC3. When the third scan signal SC3 is applied at a high level, the seventh transistor T7 is turned on and applies the initialization voltage Vref to the fifth node N5. The seventh transistor T7 may include a gate electrode connected to the input line of the third scan signal SC3, a first electrode connected to the power line of the initialization voltage Vref, and a second electrode connected to the fifth node N5.

[0068] The first capacitor Cst may correspond to the storage capacitor Cst. The first capacitor Cst may be connected between the second node N2 and the third node N3 of the first transistor T1. The first capacitor Cst may include a first electrode corresponding to the second node N2 and a second electrode corresponding to the third node N3.

[0069] The second capacitor CA can be connected between the third node N3 of the first transistor T1 and the fifth node N5 of the seventh transistor T7. The second capacitor CA may include a first electrode corresponding to the third node N3 and a second electrode corresponding to the fifth node N5.

[0070] Figure 3 yes Figure 2 The waveforms of the scanning signal and the emission control signal of the sub-pixel are shown. (Refer to...) Figure 3 The driving period of a subpixel can include an initialization period Ti, a sampling period Ts, a data writing period Tw, and an emission period Te.

[0071] Reference Figure 2 and Figure 3 During the initialization period Ti, the first scan signal SC1 is input at a low level, and the second scan signal SC2, the third scan signal SC3, the first light emission control signal EM1, and the second light emission control signal EM2 are each input at a high level. As a result, the second transistor T2 and the fifth transistor T5 are turned off, and the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on.

[0072] When the third transistor T3 and the seventh transistor T7 are turned on, the second node N2 and the third node N3 of the first transistor T1 can be initialized to the initialization voltage Vref. When the fourth transistor T4 is turned on, the fourth node N4 connected to the anode of the OLED can be reset to the anode reset voltage VAR.

[0073] During the sampling period Ts, the second scan signal SC2 and the third scan signal SC3 are each input at a high level. The first scan signal SC1, the first light emission control signal EM1, and the second light emission control signal EM2 are each input at a low level. As a result, the third transistor T3, the seventh transistor T7, and the fifth transistor T5 are turned on, while the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off.

[0074] When the third transistor T3 is turned on, the initialization voltage Vref is applied to the second node N2 of the first transistor T1, and when the seventh transistor T7 is turned on, the initialization voltage Vref is applied to the fifth node N5.

[0075] When the fifth transistor T5 is turned on, a high-potential voltage EVDD is applied to the first node of the first transistor T1. Since the sixth transistor T6 is turned off, current flows from the first node of the first transistor T1 to the third node, and the voltage at the third node rises to the level of the threshold voltage Vth of the first transistor T1, allowing the threshold voltage Vth to be sampled. After sampling the threshold voltage Vth, the supply of the high-potential voltage EVDD is cut off when the first light-emitting control signal EM1 switches to a high level and the fifth transistor T5 is turned off. When the second scan signal SC2 switches to a low level and the third transistor T3 is turned off, the voltage difference (i.e., the threshold voltage Vth) between the second and third nodes can be sampled in the first capacitor Cst and the second capacitor CA.

[0076] During the data writing period Tw, the second scan signal SC2 and the second light emission control signal EM2 are each input at a low level, while the first scan signal SC1, the third scan signal SC3, and the first light emission control signal EM1 are each input at a high level. As a result, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, while the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0077] When the second transistor T2 is turned on, the data voltage signal Vdata can be applied to the second node N2. The data voltage signal Vdata applied to the second node N2 is compensated by the sampled threshold voltage Vth, and the data voltage compensated by the threshold voltage Vth can be stored in the first capacitor Cst and the second capacitor CA.

[0078] During the light emission period Te, the first scan signal to the third scan signal SC1, SC2, SC3 and the first light emission control signal EM1 are each input at a low level, and the second light emission control signal EM2 is input at a high level.

[0079] When the first light-emitting control signal EM1 is input at a low level, the fifth transistor T5 is turned on, and when the second light-emitting control signal EM2 is input at a high level, the sixth transistor T6 is turned on. The second to fourth transistors T2, T3, and T4, and the seventh transistor T7 are turned off.

[0080] When the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on, the first electrode of the first transistor T1 can be connected to the high potential voltage EVDD, and the third electrode can be connected to the anode of the OLED. Therefore, the first transistor T1 can apply a drive current to the OLED corresponding to the data voltage compensated by the threshold voltage Vth, so that the OLED emits light.

[0081] In a display device including such sub-pixels SP, power consumption can be reduced by variably controlling the voltage level of the high-potential voltage EVDD according to the brightness of the input image. Furthermore, by variably setting the gating high voltage VGH of the gating signal based on the variablely set high-potential voltage EVDD, unnecessary power consumption for driving the sub-pixels can be prevented, thereby maximizing the power consumption reduction effect.

[0082] Figure 4 This is a diagram used to describe the considerations for variably controlling the high-potential voltage EVDD and gating the high-potential voltage VGH.

[0083] For reference Figure 1 As described, strobe driver 300 (refer to) Figure 1The transistor outputs gating signals SC and EM. Gating signals SC and EM consist of scan pulses that oscillate between a gating low voltage VGL and a gating high voltage VGH. The transistor turns on in response to the gate on-state voltage of the gating signal and turns off in response to the gate off-state voltage.

[0084] Since the fifth transistor T5, connected to the variable high-potential voltage EVDD, is a p-channel transistor, its gate turn-on voltage can be the low gate voltage VGL, and its gate turn-off voltage can be the high gate voltage VGH. When adjusting the high gate voltage VGH to reduce power, the voltage level of the high gate voltage VGH needs to be set to a level that turns off the fifth transistor T5, which is a p-channel transistor. Since it can remain in the off state when the voltage difference between the gate electrode g and the source electrode s is below the threshold voltage Vth, the fifth transistor T5, which is a p-channel transistor, can be kept in the off state when the voltage of the gate electrode g is above EVDD+Vth. Therefore, by setting an offset value greater than the threshold voltage Vth and applying the offset value to the variable high-potential voltage EVDD to set the high gate voltage VGH, the fifth transistor T5, which is a p-channel transistor, can be kept in the off state without using an unnecessarily high voltage.

[0085] As described above, the display device according to the embodiment sets an offset value greater than the threshold voltage Vth of the fifth transistor T5, which is a p-channel transistor, and sets the voltage level of the gate high voltage VGH by applying an offset value based on the high potential voltage EVDD, thereby maintaining the voltage level difference between the high potential voltage EVDD and the gate high voltage VGH within a range that keeps the fifth transistor T5 in the off state. As a result, the fifth transistor T5, which is a p-channel transistor, can be kept in the off state without using an excessively high voltage, thereby improving power efficiency.

[0086] The display device according to embodiments of the present disclosure may include a memory MEM (see Figure 1 The memory MEM stores the high-potential voltage EVDD setting information and the gating high-voltage VGH setting information for each brightness level of the image data. This information is stored in the memory MEM (see...). Figure 1 The information in the display device can be acquired and stored during optical compensation.

[0087] Figure 5 This is a schematic configuration diagram of an optical compensation system applied to a display device according to one embodiment of the present disclosure, and Figure 6 This is a graph used to describe information about setting the high potential voltage EVDD per brightness level.

[0088] Reference Figure 5The optical compensation system 500 for optical compensation of the display device 10 may include a measuring device 510 and a compensation device 520.

[0089] The measuring device 510 can measure the brightness, color coordinates, etc. of the test image displayed on the display panel 100.

[0090] The compensation device 520 can display a test image on the display panel 100, generate compensation data for image data compensation based on the measurement results of the brightness, color coordinates, etc. of the image measured by the measuring device 510, and store the compensation data in the memory MEM of the display device 10.

[0091] The compensation device 520 can obtain the optimal level of the high-potential voltage EVDD based on the brightness of the image, and store the obtained level in the memory MEM of the display device 10. For example, refer to... Figure 6 The compensation device 520 can be set with a data voltage for reproducing the target brightness (A nit), reproducing the target brightness on the display panel 100, and as... Figure 6 The brightness is measured while changing the high-potential voltage EVDD under the corresponding data voltage. The compensation device 520 can determine the level of the high-potential voltage EVDD, which can reproduce the corresponding data voltage through the target brightness. When the high-potential voltage EVDD, which is the lowest possible level that can reproduce the target brightness, is set to the optimal level of the high-potential voltage EVDD, the power consumption when reproducing a high-brightness image can be reduced. In addition, the optimal high-potential voltage EVDD can be determined by applying various standards. The compensation device 520 can store the high-potential voltage EVDD setting information for each brightness band in the memory MEM of the display device 10.

[0092] The compensation device 520 can store the gating high voltage VGH setting information in the memory MEM. The gating high voltage VGH setting information can be stored as an offset value of the voltage level applied to the high potential voltage EVDD. The offset value can be set as the voltage level difference between the high potential voltage EVDD, which keeps the fifth transistor T5 in the off state, and the gating high voltage VGH. For example, the offset value can be set as a positive value (positive offset value) that is greater than the threshold voltage Vth of the fifth transistor T5.

[0093] Furthermore, the threshold voltage Vth of the fifth transistor T5 can vary depending on the manufacturing process of the display panel 100. When the compensation device 520 can acquire information about the threshold voltage Vth of the transistor for each display panel 100, the offset value stored in the memory MEM can be stored as a different value based on the information about the threshold voltage Vth of the corresponding display panel 100.

[0094] Figure 7This is a flowchart of an optical compensation method applied to a display device according to one embodiment of the present disclosure.

[0095] Reference Figure 6 and Figure 7 The optical compensation system 500 acquires an EVDD setting value for each brightness band through optical compensation (S100). The optical compensation system 500 sets a data voltage (e.g., 255 grayscale) for reproducing the brightness that can be reproduced on the display panel 100, reproduces it on the display panel 100, and measures the brightness while changing the high-potential voltage EVDD, thereby determining the optimal level of the high-potential voltage EVDD that can reproduce 255 grayscale. The level of the high-potential voltage EVDD for each brightness band can also be set in the same way.

[0096] The compensation device 520 generates high-potential voltage EVDD setting information for the corresponding brightness band and offset value setting information for setting the gating high voltage VGH (S110). The offset value can be a preset value or a value set according to the threshold voltage Vth information for each transistor of the display panel 100. The offset value can be set as the voltage level difference between the gating high voltage VGH and the high-potential voltage EVDD that keeps the fifth transistor T5 in the off state.

[0097] The compensation device 520 can store the high potential voltage EVDD setting information and the gating high voltage VGH setting information per brightness in the memory MEM of the display device 10 (S120).

[0098] Figure 8 This is a diagram illustrating a configuration for controlling the selection high voltage VGH of a display device according to one embodiment of the present disclosure.

[0099] The controller 200 processes externally input image data to a size and resolution suitable for the display panel 100 and provides it to the data driver 400. Here, the controller 200 can provide brightness information of the image data to the data driver 400. The brightness information provided by the controller 200 can be, for example, the average brightness value of the image data for each frame, or the highest brightness value included in the image data for each frame.

[0100] The data driver 400 can receive brightness information of image data from the controller 200. The data driver 400 can refer to the high-potential voltage EVDD setting information per brightness stored in the memory MEM to check the level of the high-potential voltage EVDD corresponding to the brightness information of the received image data. The data driver 400 can control the power control unit PIC to output the high-potential voltage EVDD according to the brightness band of the received image data. Additionally, the data driver 400 can apply an offset value to the high-potential voltage EVDD according to the gating high voltage VGH setting information stored in the memory MEM to set the voltage level of the gating high voltage VGH. The power control unit PIC can provide the gating high voltage VGH and the gating low voltage VGL to the gating driver 300 according to the settings of the data driver 400.

[0101] The gating driver 300 can generate a scan signal SC and a light emission control signal EM that oscillate between a gating high voltage VGH and a gating low voltage VGL, and provide the signals to the sub-pixels of the display panel 100.

[0102] Figure 8 The embodiment illustrates a case where the display device's data driver 400 includes a memory MEM and a power control unit PIC. The memory MEM stores high-level voltage EVDD setting information and gating high voltage VGH setting information per brightness, and the power control unit PIC outputs the drive voltage EVDD, the gating high voltage VGH, and the gating low voltage VGL. However, Figure 8 The control blocks described are merely examples to aid in understanding this disclosure, and each control block can be integrated or separated and configured in various ways. For example, a memory MEM storing high-potential voltage EVDD setting information and gating high-voltage VGH setting information per brightness level can be built into the controller 200 or configured separately in the display device 10. The power control unit PIC can be configured independently of the data driver 400 and can be controlled by either the controller 200 or the data driver 400.

[0103] Figure 9 This is a flowchart of a method for controlling the selection of a high voltage VGH in a display device according to one embodiment of the present disclosure.

[0104] When image data is input to the display device, the brightness of the image data is determined (S200).

[0105] The display device obtains the high potential voltage EVDD setting value for the corresponding brightness band based on pre-stored information (S210).

[0106] The display device sets the voltage level of the gated high voltage VGH by applying a preset offset value to the acquired high potential voltage EVDD (S220).

[0107] The display device provides a gating high voltage VGH and a high potential voltage EVDD for brightness band settings to reproduce image data (S230).

[0108] As described above, the display device according to embodiments of the present disclosure can reduce power consumption when reproducing high-brightness images by variably controlling the voltage level of the high-potential voltage EVDD according to the brightness of the image data. Furthermore, by setting the gate high voltage VGH based on the variably controlled high-potential voltage EVDD, sub-pixels can be controlled without using excessively high voltages, thereby maximizing the power consumption reduction effect.

[0109] The embodiments disclosed herein have the following effects.

[0110] The display device according to embodiments of the present disclosure can reduce power consumption by variably controlling the high potential voltage EVDD according to the brightness of the input image.

[0111] The display device according to embodiments of the present disclosure can variably set the gating high voltage VGH of the gating signal based on the variable setting high potential voltage EVDD to maximize the power consumption reduction effect, thereby preventing unnecessary power consumption for driving sub-pixels.

[0112] The effects of this disclosure are not limited to those shown above, and this disclosure covers a wider range of effects.

[0113] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are not intended to limit the technical concept of the present disclosure, but rather to describe it, and the scope of the technical concept of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of protection of this disclosure should be interpreted by the claims, and all technical concepts within the scope equivalent to those claims should be interpreted as included within the scope of the claims of this disclosure.

[0114] Cross-references to related applications

[0115] This application claims the priority benefit of Korean Patent Application No. 10-2025-0010455, filed on January 23, 2025, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel having sub-pixels formed thereon, each of the sub-pixels including a driving transistor and at least one light-emitting control transistor, the driving transistor being configured to generate a driving current for driving a light-emitting element, and the at least one light-emitting control transistor being configured to apply a high potential voltage to the driving transistor. A gating driver configured to receive a gating high voltage and a gating low voltage, and configured to output a gating signal for controlling the at least one light-emitting control transistor included in the sub-pixel; as well as A power supply configured to provide the gating driver with a gating high voltage set according to the voltage level of the high potential voltage.

2. The display device according to claim 1, wherein, The difference between the high potential voltage and the gating high voltage remains constant based on the offset value.

3. The display device according to claim 2, further comprising a memory configured to store high-potential voltage setting information per brightness of image data and the offset value.

4. The display device according to claim 3, further comprising: A controller configured to generate brightness information for the image data; as well as A data driver configured to receive the brightness information from the controller, and the data driver configured to control the power supply to output a high-potential voltage corresponding to the brightness information according to the high-potential voltage setting information for each brightness stored in the memory.

5. The display device according to claim 4, wherein, The data driver sets the gating high voltage by applying the offset value to the high potential voltage corresponding to the brightness information, and the data driver controls the power supply so that the set gating high voltage is provided to the gating driver.

6. The display device according to claim 1, wherein, One of the at least one light-emitting control transistors includes: A gate electrode configured to receive the gating signal; A first electrode, configured to receive the high potential voltage; and The second electrode is connected to the source electrode of the driving transistor.

7. The display device according to claim 6, wherein, The at least one light-emitting control transistor includes a P-type thin-film transistor.

8. The display device according to claim 6, wherein, The at least one light-emitting control transistor is turned off by receiving the gating high voltage of the gating signal.

9. The display device according to claim 8, wherein, The offset value is set based on a positive offset value greater than the threshold voltage of the at least one light-emitting control transistor and the high potential voltage.

10. A method of driving a display device, the display device comprising a display panel having sub-pixels formed thereon, each of the sub-pixels including a driving transistor and at least one light-emitting control transistor, the driving transistor being configured to generate a driving current for driving a light-emitting element, and the at least one light-emitting control transistor being configured to apply a high-potential voltage to the driving transistor, the method comprising the steps of: The voltage level of the high-potential voltage is set according to the brightness of the input image; The level of the gating high voltage is set by applying an offset value to the voltage level of the high potential voltage; as well as A light emission control signal that oscillates between the high gate voltage and the low gate voltage is generated to output the generated light emission control signal to the display panel.

11. The method according to claim 10, wherein, One of the at least one light-emitting control transistors includes: A gate electrode configured to receive a gating signal; A first electrode, configured to receive the high potential voltage; and The second electrode is connected to the source electrode of the driving transistor.

12. The method according to claim 11, wherein, The at least one light-emitting control transistor includes a P-type thin-film transistor.

13. The method according to claim 11, wherein, The step of setting the level of the gate high voltage includes setting the voltage level of the gate high voltage such that the voltage difference between the high potential voltage and the gate high voltage is set to a voltage level that allows the one light-emitting control transistor to be turned off.

14. The method of claim 10, wherein, The offset value is set based on a positive offset value greater than the threshold voltage of the at least one light-emitting control transistor and the high potential voltage.

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