Variable frequency display device

Abstract

A frequency-variable display device is provided. In the frequency-variable display device, a frame period includes a vertical active period during which a data voltage is input to a sub-pixel and a vertical blank period which follows the vertical active period and during which the data voltage is not input to the sub-pixel. Further, in a frame period in which a frame frequency is lower than a predetermined maximum frame frequency within a variable frame frequency range, a scan signal applied to the sub-pixel has one gate-on period to turn on a first switching transistor connected between a data line and a drive transistor, and a sense signal applied to the sub-pixel has two or more gate-on periods to turn on a second switching transistor connected between the drive transistor and a reference voltage line.

Description

Technical Field

[0001] This disclosure relates to a frequency-variable display device. Background Technology

[0002] Variable frequency display devices change the frame rate of the image displayed on the screen based on the properties of video data received from an external video source. Variable frequency display devices support variable refresh rate (VRR) functionality, which allows the frame rate to be changed within a predetermined frequency range.

[0003] When the frame rate is rapidly changed from a low-speed frame to a high-speed frame or vice versa via VRR operation, users can perceive flickering caused by the perceived brightness deviation. To reduce this deviation, brightness algorithms that adjust the data gain based on the frame rate are known. However, such techniques have limitations in reducing the perceived brightness deviation (i.e., VRR flickering) between the first frame immediately following the rapid frame rate change and the frame immediately preceding it, as the data gain of the current frame is determined based on frequency information about the previous frame. Summary of the Invention

[0004] Therefore, this disclosure relates to a frequency-variable display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0005] To overcome the limitations of the prior art, this disclosure provides a frequency-variable display device that can reduce VRR flicker that occurs when the frame rate changes rapidly.

[0006] Other advantages, aspects, and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon review of the following description, or may be learned from practice of this disclosure. The aspects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims, and in the accompanying drawings.

[0007] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a frequency-variable display device includes: a display panel including a plurality of sub-pixels, each sub-pixel including: a driving transistor including a gate connected to a first node, a drain connected to a high-level source voltage, and a source connected to a second node; a first switching transistor configured to connect the first node to a data line based on a scan signal, the data line being configured to receive a data voltage; a second switching transistor configured to connect the second node to a reference voltage line based on a sensing signal, the reference voltage line being configured to receive an initialization voltage; a storage capacitor connected between the first node and the second node; and a light-emitting element including an anode connected to the second node and a cathode connected to a low-level source voltage; and a gate driver configured to supply a scan signal to a scan gate line connected to the gate of the first switching transistor and a sensing signal to a sensing gate line connected to the gate of the second switching transistor; wherein a frame time period includes a vertical active time period and a vertical blank time period. During the vertical active period, a data voltage is input to a corresponding sub-pixel among the aforementioned sub-pixels. The vertical blank period immediately follows the vertical active period, and during the vertical blank period, a data voltage is not input to a corresponding sub-pixel among the aforementioned sub-pixels. Furthermore, during a frame period in which the display panel is driven at a frame rate lower than a predetermined maximum frame rate within the variable frame rate range, the sensing signal has one or more gate-on periods to turn on the second switching transistor during the vertical blank period.

[0008] In another aspect of this disclosure, a frequency-variable display device includes: a display panel including a plurality of sub-pixels, each sub-pixel including: a driving transistor including a gate connected to a first node, a drain connected to a high-level source voltage, and a source connected to a second node; a first switching transistor configured to connect the first node to a data line based on a scan signal, the data line being configured to receive a data voltage; a second switching transistor configured to connect a second node to a reference voltage line based on a sensing signal, the reference voltage line being configured to receive an initialization voltage; and a storage capacitor connected to... Between the first node and the second node, and a light-emitting element, the light-emitting element including an anode connected to the second node and a cathode connected to a low-level source voltage; and a gate driver, the gate driver being configured to supply a scan signal to a scan gate line connected to the gate of the first switching transistor and to supply a sensing signal to a sensing gate line connected to the gate of the second switching transistor; wherein, during a frame period in which the display panel is driven at a frame rate lower than a predetermined maximum frame rate within a variable frame rate range, the scan signal supplied to one sub-pixel of the sub-pixels has a gate-on period, and the sensing signal supplied to that one sub-pixel of the sub-pixels has two or more gate-on periods.

[0009] In another aspect of this disclosure, a display device includes: a display panel configured to be driven at a variable frame rate within a frequency range, the display panel including sub-pixels, each sub-pixel including: a driving transistor, a first switching transistor, a second switching transistor, and a light-emitting element, wherein the driving transistor has a gate connected to a first node and a first electrode connected to a second node, the first switching transistor has a gate connected to a scan gate line, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the first node, the second switching transistor has a gate connected to a sensing gate line, a first electrode connected to a reference voltage line configured to receive an initialization voltage, and a second electrode connected to the second node, and the light-emitting element is connected to the second node; a data driver configured to provide a data voltage to the data line; and a gate driver configured to provide a scan signal to the scan gate line and a sensing signal to the sensing gate line. During the nth frame (n is a natural number) of driving the display panel at a frame rate lower than a predetermined maximum frame rate within the frequency range, the scan signal may have one gate-on period, and the sensing signal may have two or more gate-on periods.

[0010] It should be understood that the foregoing general description and the following detailed description of this disclosure are examples intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0011] This disclosure includes accompanying drawings to provide a further understanding of the disclosure. The drawings are incorporated in and form part of this application. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the various principles of the disclosure. In the drawings: Figure 1 This is a block diagram illustrating a frequency-variable display device according to an exemplary embodiment of the present disclosure; Figure 2 This is a diagram illustrating the connection structure of a pixel according to an exemplary embodiment of the present disclosure; Figure 3 This is a diagram showing the vertical active time period and the vertical blank time period that constitute an example frame time period; Figure 4 This is a diagram illustrating an example of how the length of the vertical front porch included in the vertical blank period varies with the level of the frame rate; Figure 5 This is a diagram illustrating an example of recognizing level changes in brightness based on frame rate; Figure 6 This is a diagram illustrating VRR flicker that occurs under conditions of rapid frame rate changes; Figure 7 and Figure 8 This is a graph showing an example of how the visibility of VRR flickering is higher at low gray levels compared to high gray levels; Figure 9A This is a diagram illustrating a conventional VRR-driven method in which programming operations are performed only during the vertical active period; Figure 9B This is a diagram illustrating a VRR driving method that performs programming operations during a vertical active period and performs copy programming operations during a vertical idle period, according to an exemplary embodiment of the present disclosure; Figure 10 This is a diagram illustrating an example configuration for supplying scan signals and sensing signals in a VRR driving method according to an example embodiment that differs from conventional VRR driving methods; Figure 11 It is a diagram showing the gate-source voltage difference of a subpixel based on the VRR driving method according to an example embodiment during the vertical active period and vertical blank period included in a frame period; Figure 12A It is shown in Figure 11 A diagram of subpixel operations during the programming period of the vertical active time period; Figure 12B It is shown Figure 11 A diagram of subpixel operations during the emission period of the vertical active phase; Figure 12C It is shown Figure 11A diagram showing the operation of subpixels in the vertical blank period of the programming period; Figure 12D It is shown in Figure 11 A diagram showing the operation of sub-pixels during the luminous phase of the vertical blank period; Figure 13 This is a diagram illustrating an example of brightness flickering in a conventional VRR driving method; Figure 14 A diagram illustrating an example of preventing brightness flicker in a VRR driving method according to an exemplary embodiment of the present disclosure; and Figure 15 This is a diagram illustrating features associated with the intervals between multiple gate-on periods included in the sensing signal in a VRR driving method according to an example embodiment of the present disclosure. Detailed Implementation

[0012] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will more fully convey the scope of this disclosure to those skilled in the art. Furthermore, the scope of protection of this disclosure may be defined by the claims and their equivalents.

[0013] The shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings of various exemplary embodiments of this disclosure are described by way of example, and this disclosure is not limited thereto. The same reference numerals always denote the same elements. Throughout this specification, the same elements are represented by the same reference numerals unless otherwise indicated.

[0014] As used herein, terms such as “comprising,” “having,” and “including” indicate that additional components may be added, unless a more specific term such as “only” is used. As used herein, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise.

[0015] Elements in the various embodiments of this disclosure are to be interpreted as including error margins, even if not explicitly stated otherwise.

[0016] When describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "below," "adjacent," etc., one or more other components may be placed between the two components, unless more specific terms such as "only" or "directly" are used.

[0017] It should be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be construed as being limited by these terms. These terms refer only to one element in isolation from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0018] In the following description, detailed descriptions of known functions or configurations may be omitted where such descriptions might unnecessarily obscure features or aspects of this disclosure.

[0019] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 This is a block diagram illustrating a frequency-variable display device according to an exemplary embodiment of the present disclosure.

[0021] like Figure 1 As shown, the display panel 100 may include a screen (or active area) AA for displaying an input image. The screen AA may include a pixel array for displaying pixel data (hereinafter referred to as "image data") DATA of the input image. The pixel array may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, multiple reference voltage lines, and multiple pixels.

[0022] Pixels can be arranged on the screen AA in a matrix type defined by data lines DL, gate lines GL, and reference voltage lines. Pixels can be arranged on the screen AA in various types, such as stripe type, diamond type, and matrix type.

[0023] A pixel array may include multiple pixel columns and multiple pixel rows L1 to Ln intersecting the pixel columns. Each pixel column may include pixels arranged along the Y-axis. A pixel row may include pixels arranged along the X-axis. A vertical time period may be a frame time period in which image data DATA of one frame is written to all pixels of screen AA. A horizontal time period may be the time obtained by dividing a frame time period by the number of pixel rows L1 to Ln. A horizontal time period may be the time period in which image data DATA of one pixel row sharing a gate line GL is written to the pixels of one pixel row (e.g., one of L1 to Ln).

[0024] Each of the pixels may include a red (R) subpixel 101, a green (G) subpixel 101, a blue (B) subpixel 101, and a white (W) subpixel 101 for implementing the color.

[0025] The frequency-variable display device according to an example embodiment of this disclosure can be implemented as an organic light-emitting display device. In this case, the pixel circuit of the frequency-variable display device may include a light-emitting element, a driving element, one or more switching elements, and a capacitor. The light-emitting element may be implemented as an organic light-emitting diode (OLED). The driving current that allows the light-emitting element to emit light can be adjusted based on the gate-source voltage of the driving element. Each of the driving element and the switching element may be implemented as a transistor. The semiconductor layer of the transistor may include amorphous silicon or polycrystalline silicon. The semiconductor layer of at least some of the transistors may contain oxide. The pixel circuit may be connected to a data line DL and a gate line GL. Figure 1 In the diagram, "D1 to D3" indicated by circles can be data lines, and "Gn-2 to Gn" can be gate lines.

[0026] A touch sensor can be disposed on the display panel 100. The touch sensor can be arranged as an on-cell or add-on type on the screen AA of the display panel 100, or it can be implemented as an in-cell type touch sensor embedded in the pixel array. Touch input can be sensed by the touch sensor, or it can be sensed by pixels alone even without a touch sensor.

[0027] The source driver 110 can generate a data voltage by converting image data DATA received from the timing controller 130 into a gamma-compensated voltage using a digital-to-analog converter (DAC). The source driver 110 can supply the data voltage to the data line DL. The data voltage can be applied to the gate of the driving element through the switching elements of the sub-pixel 101. The source driver 110 can supply an initialization voltage VpreR received from the power supply circuit 200 to a reference voltage line connected to the sub-pixel. The initialization voltage VpreR can be supplied to the reference voltage line and can be applied to the source of the driving element through the switching elements of each sub-pixel 101.

[0028] The source driver 110 can be implemented using one or more source driver integrated circuits (ICs). The source driver IC can be connected to the timing controller 130 via an internal interface circuit. This internal interface circuit can be implemented as an embedded clock point interface (EPI). The source driver IC may also include a touch driver. The touch driver can generate touch sensor drive signals and convert the charge changes of the touch sensor into raw touch data. The touch driver can transmit the raw touch data to the host system (not shown) via a separate interface circuit. This separate interface circuit can be implemented as a serial peripheral interface (SPI).

[0029] Gate driver 120 can be disposed in a bezel area BZ outside the screen AA in the display panel 100. The bezel area BZ can be an area configured not to display images. Gate driver 120 can sequentially supply gate signals synchronized with the data voltage to gate lines GL according to the control of timing controller 130. The gate signals can simultaneously activate pixels in the same pixel row to which the data voltage is charged. Gate driver 120 can output gate signals using one or more shift registers and can shift the gate signals. The gate signals can be referred to as scan signals. Scan signals can include a gate on-voltage VON and a gate off-voltage VOFF received from power supply circuit 200.

[0030] The timing controller 130 can receive video data DATA and timing signals synchronized with the video data DATA from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync can define a vertical time period (i.e., one frame). The horizontal synchronization signal Hsync can define a horizontal time period. The data enable signal DE can define the time during which data voltage is input to a sub-pixel in the vertical time period (i.e., the vertical active time period). Other times in the vertical time period besides the vertical active time period can be vertical blank periods. The data enable signal DE can oscillate during the vertical active time period and may not oscillate during the vertical blank periods.

[0031] The timing controller 130 can generate a source timing control signal DDC for controlling the operating timing of the source driver 110 and a gate timing control signal GDC for controlling the operating timing of the gate driver 120 based on the timing signals Vsync, Hsync and DE received from the host system.

[0032] The host system can be, but is not limited to, a television (TV), set-top box, navigation system, personal computer (PC), home theater, automotive display system, mobile device, and wearable device. In mobile devices and wearable devices, the source driver 110, timing controller 130, and level shifter 140 can be integrated into a single driver IC.

[0033] Level shifter 140 can shift the logic voltage level of the gate timing control signal GDC output from timing controller 130 to either the gate on-voltage VON or the gate off-voltage VOFF to supply the gate driver 120. The low logic voltage of the gate timing control signal GDC can be down-shifted to the gate off-voltage VOFF, and the high logic voltage of the gate timing control signal GDC can be up-shifted to the gate on-voltage VON.

[0034] The power supply circuit 200 can generate various source voltages for panel driving. The power supply circuit 200 can generate a gate on voltage VON and a gate off voltage VOFF for generating scan signals, generate a high-level source voltage EVDD and a low-level source voltage EVSS to be supplied to each sub-pixel 101, and generate an initialization voltage VpreR to be supplied to the reference voltage line.

[0035] Figure 2 This is a diagram illustrating the connection structure of an example pixel PXL according to an exemplary embodiment of the present disclosure.

[0036] like Figure 2 As shown, the example pixel PXL may include four sub-pixels SP1 to SP4 sharing a common reference voltage line RL. The four sub-pixels SP1 to SP4 may be R sub-pixels, G sub-pixels, B sub-pixels, and W sub-pixels used to constitute the same pixel. Each of the sub-pixels SP1 to SP4 may, for example, include a light-emitting element OLED, a driving transistor DT, a first switching transistor ST1 and a second switching transistor ST2, and a storage capacitor Cst.

[0037] An OLED (Optical Display Panel) emits light to achieve brightness by using a drive current supplied from a driving transistor DT. The anode of the OLED can be connected to the second node N2, and the cathode can be connected to the input of a low-level source voltage EVSS.

[0038] The driving transistor DT can be a driving element that generates a driving current based on its gate-source voltage difference to supply driving current to the light-emitting element OLED. The gate of the driving transistor DT can be connected to the first node N1, the drain of the driving transistor DT can be connected to the input terminal of the high-level source voltage EVDD, and the source of the driving transistor DT can be connected to the second node N2.

[0039] The gate of the first switching transistor ST1 can be connected to the scan gate line GLa, the first electrode of the first switching transistor ST1 can be connected to the data line DL, and the second electrode of the first switching transistor ST1 can be connected to the first node N1. The first switching transistor ST1 can connect the first node N1 to the data line DL supplied with the data voltage Vdata based on the scan signal SCAN from the scan gate line GLa.

[0040] The gate of the second switching transistor ST2 can be connected to the sensing gate line GLb. The first electrode of the second switching transistor ST2 can be connected to the reference voltage line RL, and the second electrode of the second switching transistor ST2 can be connected to the second node N2. The second switching transistor ST2 can connect the second node N2 to the reference voltage line RL, which is supplied with the initialization voltage VpreR, based on the sensing signal SEN from the sensing gate line GLb.

[0041] One electrode of the storage capacitor Cst can be connected to the first node N1, and the other electrode of the storage capacitor Cst can be connected to the second node N2.

[0042] The first switch SW1 and the second switch SW2 can be further connected to the reference voltage line RL. The first switch SW1 can connect the input terminal of the initialization voltage VpreR to the reference voltage line RL. The second switch SW2 can connect the reference voltage line RL to the sensing circuit SU used to sense the electrical characteristics (threshold voltage or electron mobility) of the driving transistor DT.

[0043] In the nth frame (where n can be a natural number), the first switch SW1 can be turned on, thus programming the gate-source voltage difference of the driving transistor DT. When the second switch SW2 is turned on, the electrical connection between the input of the initialization voltage VpreR and the reference voltage line RL can be disconnected. When the second switch SW2 is turned on, the sampling operation of the sensing circuit SU can be performed.

[0044] The first switch SW1 and the second switch SW2 may be included in the source driver 110. However, in an example configuration where the sensing function is not used, the second switch SW2 and the sensing circuit SU may be omitted.

[0045] Figure 3 This is a diagram showing the vertical active time period and the vertical blank time period that constitute an example frame time period. Figure 4 This is a diagram illustrating an example of how the length of the vertical leading edge included in a vertical blank period varies horizontally based on the frame rate.

[0046] like Figure 3As shown, a frame time period (vertical time period) can be defined by the vertical synchronization signal Vsync. A frame time period (vertical time period) can be defined as the time interval between adjacent falling (or rising) edges of the vertical synchronization signal Vsync.

[0047] The vertical active period ACT and the vertical blank period BLK in a frame (vertical period) can be defined by the data enable signal DE. The vertical active period ACT can be the period during which the data enable signal DE swings (e.g., between high and low levels), and the vertical blank period BLK can be the period during which the data enable signal DE does not swing.

[0048] A frequency-variable display device according to an exemplary embodiment of this disclosure may have a VRR mode in which the length of a frame varies within a variable frequency range below a predetermined maximum frame rate. In the following, in an exemplary embodiment of this disclosure, the maximum frame rate may be described as 240 Hz, but the inventive concept or disclosure is not limited thereto. In VRR mode, such as Figure 4 As shown, the frame rate can be changed to A Hz, B Hz, and C Hz. When the frame rate changes, the length of a single frame segment can vary accordingly. In VRR mode, the length of the vertical active segment (ACT) can be fixed to a specific value defined relative to the maximum frame rate, and the length of the vertical blank segment (BLK) can vary based on the frame rate. Based on frame rate A Hz, the length of the vertical blank segment can be BLK1; based on frame rate B Hz, it can be BLK2; and based on frame rate C Hz, it can be BLK3. Here, when A>B>C, BLK1... <BLK2<BLK3。

[0049] During a fixed-length vertical active period (ACT), the voltage difference between the data voltage corresponding to the image data (DATA) and the initialization voltage (i.e., the gate-source voltage difference of the driving transistor) in each pixel can be set. This setting operation can be called a programming operation. When the programming operation is complete, while maintaining the gate-source voltage difference of the driving transistor set in the sub-pixel, the source voltage of the driving transistor can be increased to the threshold voltage of the light-emitting element.

[0050] To reduce VRR flicker, copy programming operations can be further performed during the variable-length vertical blanking period (BLK). See below for reference. Figure 9B , Figure 10 , Figure 11 , Figures 12A to 12D , Figure 14 and Figure 15 This will be described in detail.

[0051] Figure 5 This is a diagram illustrating an example of how brightness levels change based on frame rate. Figure 6This is a diagram illustrating VRR flicker that occurs under conditions of rapid frame rate changes. Figure 7 and Figure 8 This is a graph showing an example of how the visibility of VRR flickering is higher at low gray levels compared to high gray levels.

[0052] Figure 5 and Figure 6 The peak low brightness point can be the point where programming operations are performed. The light emission operation of the OLED can be stopped during programming operations, and the light emission operation of the OLED can be performed after programming operations are performed.

[0053] Programming operations and emission operations can be executed continuously within a single frame. The number of programming operations can increase with the number of frames within a predetermined time period, i.e., the frame rate increases. Therefore, the recognition brightness can be reduced. For example, the number of programming operations within a predetermined time period can be twelve at a 240 Hz frame rate, six at a 120 Hz frame rate, and three at a 60 Hz frame rate. As a result, the real-time brightness integral value (i.e., recognition brightness) at a 240 Hz frame rate can be L1, the real-time brightness integral value (i.e., recognition brightness) at a 120 Hz frame rate can be L2 (higher than L1), and the real-time brightness integral value (i.e., recognition brightness) at a 60 Hz frame rate can be L3 (higher than L2).

[0054] As mentioned above, assuming a constant grayscale level for the displayed image, the recognition brightness can be relatively higher at lower frame rates than at higher frame rates. Therefore, when the frame rate changes from high to low, VRR flicker may occur due to the change in recognition brightness.

[0055] like Figure 7 and Figure 8 As shown, the identifiability of VRR flicker can be relatively higher in low grayscale periods than in high grayscale periods. Since the time taken to reach the target brightness saturation level immediately after programming is defined as the brightness transition rate, the brightness transition rate of high grayscale images can be relatively higher than that of low grayscale images. Therefore, VRR flicker caused by frequency variations is not readily identifiable in high grayscale images (and thus is not a serious problem), but it may be clearly identifiable when displaying low grayscale images.

[0056] Figure 9A This is a diagram illustrating a conventional VRR-driven approach that performs programming operations only during the vertical active time period. Figure 9B This is a diagram illustrating a VRR-driven method that performs programming operations during a vertical active period and performs copy programming operations during a vertical idle period, according to an example embodiment of the present disclosure.

[0057] like Figure 9A As shown, in the VRR-driven method that performs programming operations only in the vertical active time period ACT, as referred to Figure 5 As described, the real-time luminance integral value (i.e., the perceived luminance) can increase as the frame rate decreases. Therefore, when the frame rate changes rapidly from a high frequency to a low frequency, VRR flicker may occur due to the change in perceived luminance.

[0058] On the other hand, such as Figure 9B As shown, in the VRR driving method that performs programming operations in the vertical active time period ACT and copy programming operations in the vertical blank time period BLK, the change in recognition brightness caused by frame rate variation can be minimized or reduced, and VRR flicker can be suppressed.

[0059] like Figure 9B As shown, programming operations can be achieved through the sensing signal SEN and the scanning signal SCAN, which are synchronized with the input of the data voltage Vdata and have a gate-on period in the vertical active period ACT.

[0060] The copy programming operation can be implemented using one or more sensing signals SEN that have a gate-on period during the vertical blank period BLK, when there is no data voltage Vdata input. The gate-on period can be defined as the period during which a gate-on voltage is maintained that enables the first switching transistor ST1 and the second switching transistor ST2 of the sub-pixel to conduct. During the vertical blank period BLK, the scan signal SCAN may not have a gate-on period and may maintain a gate-off voltage. The gate-off voltage can be a voltage that enables the first switching transistor ST1 and the second switching transistor ST2 of the sub-pixel to turn off.

[0061] During the vertical blank period BLK, with the gate of the driving transistor DT floating under the scan signal SCAN (gate cutoff voltage), the initialization voltage VpreR can be applied to the source of the driving transistor DT via the sensing signal SEN (gate on-voltage). Therefore, a copy programming operation can be implemented. Based on the initialization voltage VpreR applied to the source of the driving transistor DT, the source voltage of the driving transistor DT can be reduced from the threshold voltage of the OLED to the initialization voltage VpreR. At this time, since the gate of the driving transistor DT is bonded to the source through the storage capacitor Cst, the gate voltage of the driving transistor DT can be reduced. The gate-source voltage difference of the driving transistor DT based on the copy programming operation can be substantially the same as the gate-source voltage difference of the driving transistor DT based on the programming operation.

[0062] Similar to the programming period of the vertical blank period ACT, since the source voltage of the driving transistor DT is lower than the threshold voltage of the OLED during the replication programming period of the vertical blank period BLK, the OLED can not emit light. The number of replication programming periods included in the vertical blank period BLK can increase with the length of the vertical blank period BLK. Therefore, brightness flickering that occurs in long vertical blank periods BLK of low-frequency frames can be suppressed or reduced. As a result, VRR flickering that occurs when the frame rate changes rapidly from high frequency to low frequency can be suppressed or reduced.

[0063] Copy programming periods can be omitted during the vertical blank BLK period of the shortest frame segment corresponding to the maximum frame frequency within the variable frequency range. Copy programming periods can be allocated during the vertical blank BLK period of the frame segment at frame frequencies below the maximum frame frequency.

[0064] A vertical blank period (BLK) may include one or more copy programming periods, and the number of programming periods allocated may be proportional to the length of the vertical blank period (BLK). For example, a vertical blank period (BLK) of a second length that is longer than a first length may include a greater number of copy programming periods than a vertical blank period (BLK) of the first length.

[0065] Figure 10 This is a diagram illustrating an example configuration for supplying scan signals and sensing signals in a VRR driving method according to an example embodiment of this disclosure, which differs from conventional VRR driving methods.

[0066] like Figure 10 As shown, in conventional VRR driving methods, during the vertical active period (ACT), for programming operations, the scan signal (SCAN) and the sensing signal (SEN) can be synchronized with each other and supplied sequentially in pixel rows. In each of the first and second frames at 100 Hz, the length of the vertical active period (ACT) can be defined relative to 240 Hz, which is the maximum frame rate. Furthermore, during the vertical blank period (BLK), the scan signal (SCAN) and the sensing signal (SEN) can be configured not to be supplied to pixel rows.

[0067] On the other hand, in the VRR driving method according to an example embodiment of the present disclosure, during the vertical active period ACT, for programming operations, the scan signal SCAN and the sensing signal SEN can be synchronized with each other and supplied sequentially in pixel rows. Then, for the copy programming operation of the vertical blank period BLK, the sensing signal SEN can be supplied sequentially in pixel rows.

[0068] In each of the first and second frames at 100 Hz, the length of the vertical blank period (BLK) can be greater than the length of the vertical active period (ACT). Within the vertical blank period (BLK) of each of the first and second frames, a copy programming operation can be performed twice for each subpixel.

[0069] The length of the vertical blank period BLK can be a non-integer multiple of the length of the vertical active period ACT. In this case, the supply timing of the sensing signal SEN for the second copy programming operation in the first frame and the supply timing of the sensing signal SEN for the programming operation in the second frame can overlap each other for a specific time OT. Therefore, "SEN Multi Driving" can be performed at the specific overlap time OT. Unlike the programming operation, since no data voltage is supplied in the copy programming operation, no driving problems occur even when performing "SEN Multi Driving".

[0070] Figure 11 This is a diagram illustrating the gate-source voltage difference of a subpixel based on the VRR driving method according to an example embodiment, within the vertical active period ACT and vertical blank period BLK included in a frame time segment. Figures 12A to 12D They are shown separately. Figure 11 The diagram shows the operations of subpixels in the programming period TA of the vertical active period ACT, the emission period TE1 of the vertical active period ACT, the copy programming period TC of the vertical blank period BLK, and the emission period TE2 of the vertical blank period BLK.

[0071] like Figure 11 As shown, for the copy programming operation in the vertical blank period BLK, the sensing signal SEN may have one or more gate-on periods (hereinafter referred to as VON periods) to turn on the second switching transistor ST2 during the vertical blank period BLK.

[0072] like Figure 11 and Figure 12AAs shown, during the programming period TA of the vertical active period ACT, the scan signal SCAN and the sensing signal SEN can remain in the VON period. Therefore, both the first switching transistor ST1 and the second switching transistor ST2 can be turned on. The data voltage Vdata can be applied to the first node N1 connected to the gate of the driving transistor DT through the first switching transistor ST1, and can be the gate voltage Vg of the driving transistor DT. The initialization voltage VpreR can be applied to the second node N2 connected to the source of the driving transistor DT through the second switching transistor ST2, and can be the source voltage Vs of the driving transistor DT. As a result, the gate-source voltage difference "W-Vgs" set in the programming period TA of the vertical active period ACT can be "Vdata-VpreR". The gate-source voltage difference "W-Vgs" can be greater than the threshold voltage of the driving transistor DT.

[0073] During the boost phase TB1 of the vertical active phase ACT, the first switching transistor ST1 and the second switching transistor ST2 can be turned off by the scan signal SCAN and the sensing signal SEN, corresponding to the gate cutoff voltage VOFF. The gate-source voltage difference "W-Vgs" during the programming phase TA can be maintained, and the drive current corresponding to "W-Vgs" can flow through the drive transistor DT. Based on this drive current, the source voltage Vs of the drive transistor DT can be up-boosted up to the turn-on voltage Vf of the light-emitting element OLED. At this time, the gate voltage Vg of the drive transistor DT can increase based on the capacitive boosting of the storage capacitor Cst. However, due to the first capacitor boosting loss, the increase in gate voltage Vg can be less than the increase in source voltage Vs.

[0074] like Figure 11 and Figure 12B As shown, during the light-emitting period TE1 of the vertical active period ACT, due to capacitor boost loss, the gate-source voltage difference "E-Vgs" of the light-emitting period TE1 can be set to be smaller than the gate-source voltage difference "W-Vgs" of the programming period TA. Capacitor boost loss can be defined as "capacitance Cst / (capacitance Cst + parasitic capacitance Cx)". Parasitic capacitance Cx can be defined as the sum of parasitic capacitances affecting the gate of the driving transistor DT. As parasitic capacitance Cx increases, capacitor boost loss increases, and the difference between "W-Vgs" and "E-Vgs" increases. During the light-emitting period TE1 of the vertical active period ACT, a driving current Ids corresponding to the gate-source voltage difference "E-Vgs" can be applied from the driving transistor DT to the light-emitting element OLED. The light-emitting element OLED can emit light through the driving current.

[0075] like Figure 11 and Figure 12C As shown, during the copy programming period TC of the vertical blank period BLK, the sensing signal SEN can remain in the VON period. Therefore, the second switching transistor ST2 can be turned on. At this time, the first switching transistor ST1 can be turned off by the scan signal SCAN of the gate cutoff voltage VOFF. The initialization voltage VpreR can be applied to the second node N2 connected to the source of the driving transistor DT through the second switching transistor ST2. Therefore, the source voltage Vs of the driving transistor DT can be down-boosted from the turn-on voltage Vf of the light-emitting element OLED down to the initialization voltage VpreR. At this time, the gate voltage Vg of the driving transistor DT can also be reduced due to the capacitor boost based on the storage capacitor Cst. However, due to the second capacitor boost loss, the reduction in gate voltage Vg can be less than the reduction in source voltage Vs.

[0076] In the copy programming period TC of the vertical blank period BLK, a gate-source voltage difference "B-Vgs" that is essentially the same as the gate-source voltage difference "W-Vgs" of the programming period TA can be set. In each of "W-Vgs" and "B-Vgs", the gate voltage Vg can be the data voltage Vdata, and the source voltage Vs can be the initialization voltage VpreR.

[0077] The programming period TA of the vertical active period ACT and the copy programming period TC of the vertical blank period BLK can have the same length. Therefore, even if only the second switching transistor ST2 is driven by the sensing signal SEN based on the VON period in the copy programming period TC of the vertical blank period BLK, the same programming effect can be obtained in the programming period TA of the vertical active period ACT, just as if both the first switching transistor ST1 and the second switching transistor ST2 were driven. The gate-source voltage difference "W-Vgs" set in the programming period TA of the vertical active period ACT can be the same as the gate-source voltage difference "B-Vgs" set in the copy programming period TC of the vertical blank period BLK.

[0078] During the copy programming period TC of the vertical blank period BLK, the gate voltage Vg can be varied solely through capacitor boost. Because the second capacitor boost loss acts in the opposite direction to the first capacitor boost loss, the gate voltage Vg of "B-Vgs" can be restored to the data voltage Vdata set at the end of the programming period TA of the vertical active period ACT.

[0079] During the boost phase TB2 of the vertical blank period BLK, the first switching transistor ST1 and the second switching transistor ST2 can be turned off by the scan signal SCAN and the sensing signal SEN, which correspond to the gate cutoff voltage VOFF. The gate-source voltage difference “B-Vgs” during the replication programming period TC can be maintained, and the drive current corresponding to the gate-source voltage difference “B-Vgs” can flow into the drive transistor DT. Based on the drive current, the source voltage Vs of the drive transistor DT can be boosted up to the turn-on voltage Vf of the light-emitting element OLED. At this time, the gate voltage Vg of the drive transistor DT can increase based on the capacitive boost generated by the storage capacitor Cst. However, due to the first capacitive boost loss, the increase in gate voltage Vg can be less than the increase in source voltage Vs.

[0080] like Figure 11 and Figure 12D As shown, during the light-emitting period TE2 of the vertical blank period BLK, the gate-source voltage difference "E-Vgs" of the light-emitting period TE2 can be set to be smaller than the gate-source voltage difference "B-Vgs" of the replication programming period TC by the capacitor boost loss. During the light-emitting period TE2 of the vertical blank period BLK, a driving current corresponding to the gate-source voltage difference "E-Vgs" can be applied from the driving transistor DT to the light-emitting element OLED. The light-emitting element OLED can emit light through the driving current.

[0081] Figure 13 This is a diagram illustrating an example of brightness flickering that occurs in a conventional VRR driving method. Figure 14 This is a diagram illustrating an example of preventing or suppressing brightness flicker in a VRR driving method according to an exemplary embodiment of the present disclosure.

[0082] like Figure 13 As shown, in conventional VRR driving methods that perform programming operations only during the vertical active period, the real-time luminance integral value (i.e., the recognized luminance) can increase in the third and fourth frames, which have a relatively low frame rate at 70 Hz. Therefore, luminance flicker may occur. Thus, when the frame rate changes rapidly from 240 Hz to 70 Hz, VRR flicker caused by changes in recognized luminance may occur.

[0083] On the other hand, such as Figure 14 As shown, in the VRR driving method according to an example embodiment of this disclosure, a copy programming period, which is a non-light-emitting period, can be further set in the third and fourth frames, where the frame rate is relatively low at 70 Hz. Therefore, brightness flickering in the vertical blank period BLK of the third and fourth frames can be prevented or suppressed. According to the example embodiment of this disclosure, because the brightness hardly changes even when the frame rate changes rapidly from 240 Hz to 70 Hz, VRR flickering is not detected.

[0084] Because the third copy programming period of the third frame overlaps with the programming period of the fourth frame, the length of the emission period based on the third copy programming period of the third frame can be reduced. Therefore, the brightness level XY can be lower than the normal length of the emission period.

[0085] Similarly, because the third copy programming period of the fourth frame overlaps with the programming period of the fifth frame, the length of the emission period based on the third copy programming period of the fourth frame can be reduced. Therefore, the brightness level XZ can be lower than the normal length of the emission period.

[0086] However, within a single frame, the time interval for achieving brightness level XY or brightness level XZ can be very short, and brightness levels XY or XZ may overlap with the brightness levels of subsequent frames and may be identified simultaneously. Therefore, there may be almost no identifiable issues.

[0087] Figure 15 This is a diagram illustrating features associated with the intervals between multiple gate-on periods included in the sensing signal in an exemplary embodiment of the VRR driving method according to this disclosure.

[0088] like Figure 15 As shown, for a copy programming operation to reduce VRR flicker, the sensing signal SEN according to an example embodiment of this disclosure may have one or more VON periods to turn on the second switching transistor ST2 during the vertical blank period BLK at a frame frequency of 70 Hz, below the maximum frame frequency of 240 Hz. Furthermore, for a programming operation at a frame frequency of 70 Hz, the scan signal SCAN according to an example embodiment of this disclosure may have a VON period to turn on the first switching transistor ST1 during the vertical active period ACK, and the sensing signal SEN may have a VON period to turn on the second switching transistor ST2 during the vertical active period ACK.

[0089] In other words, at a frame rate of 70 Hz, which is lower than the maximum frame rate of 240 Hz, the scan signal SCAN supplied to a sub-pixel may include one VON period, and the sensing signal SEN supplied to that sub-pixel may include two or more VON periods.

[0090] Here, the first VON period of the sensing signal SEN can overlap with the VON period of the scanning signal SCAN, and the VON period of the sensing signal SEN after the first VON period can overlap with the VOFF period of the scanning signal SCAN.

[0091] like Figure 15As shown, the intervals between multiple VON time periods included in the sensing signal SEN in the nth frame Fn (where n can be a natural number) can have the same first interval INT1. Therefore, luminance distortion can be minimized or effectively reduced in a single programming operation and in multiple copy programming operations.

[0092] like Figure 15 As shown, the interval between the last VON period of the sensing signal SEN set in frame n Fn and the first VON period of the sensing signal SEN set in frame (n+1) Fn+1 can have a second interval INT2 that is smaller than the first interval INT1. Despite this structure, the programming operation based on the data voltage Vdata and performed in frame (n+1) Fn+1 will not cause any problems. This is because the copy programming operation is performed only based on the initialization voltage VpreR, which does not have a data voltage Vdata, during the last VON period of the sensing signal SEN set in frame n Fn.

[0093] As described above in the example embodiments according to this disclosure, the programming period of frame (n+1)Fn+1 can begin before the end of the last copy programming period of frame nFn. Therefore, in terms of programming operations, since there is no output delay relative to the input, it is not necessary to include memory for copying the frame image.

[0094] In the above exemplary embodiments of this disclosure, by using a frequency-variable display device that changes the length of the vertical blank period based on the frame rate, one or more copy programming operations can be performed during the vertical blank period at a frame rate lower than a predetermined maximum frame rate. Therefore, brightness flicker and VRR flicker that occur when the frame rate changes rapidly can be reduced.

[0095] The effects of this disclosure are not limited to the examples described above, and various other effects may be included in the specification or understood from this disclosure, or may be obtained through practice of various embodiments of this disclosure.

[0096] While this disclosure has been specifically shown and described with reference to exemplary embodiments, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A frequency-variable display device, comprising: The display panel includes a plurality of sub-pixels, each sub-pixel including: a driving transistor, the driving transistor including a gate connected to a first node, a drain connected to a high-level source voltage, and a source connected to a second node; a first switching transistor configured to connect the first node to a data line based on a scan signal, the data line being configured to receive a data voltage; a second switching transistor configured to connect the second node to a reference voltage line based on a sensing signal, the reference voltage line being configured to receive an initialization voltage; a storage capacitor connected between the first node and the second node; and a light-emitting element, the light-emitting element including an anode connected to the second node and a cathode connected to a low-level source voltage; and A gate driver configured to supply the scan signal to a scan gate line connected to the gate of the first switching transistor and to a sensing gate line connected to the gate of the second switching transistor; One frame of time includes: A vertical active period, during which the data voltage is input to a corresponding sub-pixel of the sub-pixels; and A vertical blank period, which immediately follows the vertical active period, and during the vertical blank period, the data voltage is not input to the corresponding sub-pixel of the sub-pixel, and In a frame period during which the display panel is driven at a frame rate lower than a predetermined maximum frame rate within the variable frame rate range, the sensing signal has one or more gate-on periods to turn on the second switching transistor during the vertical blank period.

2. The frequency-variable display device according to claim 1, wherein, The length of the vertical active time period is fixed based on the predetermined maximum frame rate, and The length of the vertical blank period is variable, and the lower the frame rate is than the predetermined maximum frame rate, the longer the length of the vertical blank period.

3. The frequency-variable display device according to claim 2, wherein, During the programming period of the vertical active period, the scan signal and the sensing signal maintain the gate-on period, and the first switching transistor and the second switching transistor are turned on. During the copy programming period of the vertical blank period, the scan signal holds the gate off period, the sensing signal holds the gate on period, the first switching transistor is off, and the second switching transistor is on.

4. The frequency-variable display device according to claim 3, wherein, The programming session and the copy programming session have the same length.

5. The frequency-variable display device according to claim 4, wherein, The gate-source voltage difference of the driving transistor during the programming period is equal to the gate-source voltage difference of the driving transistor during the copy programming period.

6. The frequency-variable display device according to claim 3, wherein, When the display panel is driven at a frame rate lower than the predetermined maximum frame rate, the vertical blank period includes one or more of the copy programming periods.

7. The frequency-variable display device according to claim 6, wherein, The number of copy programming periods included in the vertical blank period increases as the length of the vertical blank period increases.

8. The frequency-variable display device according to claim 1, wherein, In the nth frame, each of the intervals between the plurality of gate-on periods of the sensing signal is equal to the first interval, where n is a natural number, and The interval between the last gate-on period of the sensing signal in the nth frame and the first gate-on period of the sensing signal in the (n+1)th frame is equal to a second interval smaller than the first interval.

9. A frequency-variable display device, comprising: The display panel includes a plurality of sub-pixels, each sub-pixel including: a driving transistor, the driving transistor including a gate connected to a first node, a drain connected to a high-level source voltage, and a source connected to a second node; a first switching transistor configured to connect the first node to a data line based on a scan signal, the data line being configured to receive a data voltage; a second switching transistor configured to connect the second node to a reference voltage line based on a sensing signal, the reference voltage line being configured to receive an initialization voltage; a storage capacitor connected between the first node and the second node; and a light-emitting element including an anode connected to the second node and a cathode connected to a low-level source voltage; and A gate driver configured to supply the scan signal to a scan gate line connected to the gate of the first switching transistor and to a sensing gate line connected to the gate of the second switching transistor; In a frame period during which the display panel is driven at a frame rate lower than a predetermined maximum frame rate within the variable frame rate range, the scan signal supplied to one of the sub-pixels has a gate-on period, and the sensing signal supplied to the one of the sub-pixels has two or more gate-on periods.

10. The frequency-variable display device according to claim 9, wherein, During the one-frame period when the display panel is driven at a frame rate lower than the predetermined maximum frame rate: The gate conduction period of the sensing signal overlaps with one of the two or more gate conduction periods of the scanning signal, and The latter gate-on period of the two or more gate-on periods of the sensing signal overlaps with the gate-off period of the scan signal.

11. The frequency-variable display device according to claim 9, wherein, The one-frame time period includes: A vertical active period, during which the data voltage is input to a corresponding sub-pixel of the sub-pixels; and A vertical blank period, which immediately follows the vertical active period, during which the data voltage is not input to the corresponding sub-pixel of the sub-pixel. The length of the vertical active time period is fixed based on the predetermined maximum frame rate, and The length of the vertical blank period is variable, and the lower the frame rate is than the predetermined maximum frame rate, the longer the length of the vertical blank period.

12. The frequency-variable display device according to claim 9, wherein, In the nth frame, each of the intervals between the two or more gate-on periods of the sensing signal is equal to the first interval, where n is a natural number, and The interval between the last gate-on period of the sensing signal in the nth frame and the first gate-on period of the sensing signal in the (n+1)th frame is equal to a second interval that is shorter than the first interval.

13. A display device, comprising: A display panel configured to be driven at a variable frame rate within a frequency range, the display panel including sub-pixels, each sub-pixel including: a driving transistor having a gate connected to a first node and a first electrode connected to a second node; a first switching transistor having a gate connected to a scan gate line, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the first node; a second switching transistor having a gate connected to a sensing gate line, a first electrode connected to a reference voltage line configured to receive an initialization voltage, and a second electrode connected to the second node; and a light-emitting element connected to the second node; A data driver configured to provide the data voltage to the data line; and A gate driver configured to provide a scan signal to the scan gate line and a sensing signal to the sensing gate line. During the nth frame of driving the display panel at a frame rate lower than the predetermined maximum frame rate within the frequency range, the scanning signal has one gate-on period, and the sensing signal has two or more gate-on periods, where n is a natural number.

14. The display device according to claim 13, wherein, The nth frame includes: A vertical active period, during which the data voltage is input to the sub-pixel; and A vertical blank period, which immediately follows the vertical active period and during which the data voltage is not input to the sub-pixel.

15. The display device according to claim 14, wherein: The length of the vertical active time period is fixed based on the predetermined maximum frame rate; and The length of the vertical blank period is variable, and the lower the frame rate is than the predetermined maximum frame rate, the longer the length of the vertical blank period.

16. The display device according to claim 14, wherein: The vertical active period includes a programming period during which the first and second switching transistors are configured to be turned on, and The vertical blank period includes one or more copy programming periods during which the first switching transistor is configured to be off and the second switching transistor is configured to be on.

17. The display device according to claim 16, wherein, Each of the programming session and the one or more copied programming sessions has the same length.

18. The display device according to claim 17, wherein, The number of copy programming periods included in the vertical blank period increases as the length of the vertical blank period increases and the frame rate decreases.

19. The display device according to claim 13, wherein, During the nth frame: The gate-on period of the sensing signal overlaps with one of the two or more gate-on periods of the scanning signal; and The latter gate-on period of the two or more gate-on periods of the sensing signal overlaps with the gate-off period of the scan signal.

20. The display device according to claim 13, wherein: In the nth frame, each of the intervals between the two or more gate-on periods of the sensing signal is equal to the first interval; and The interval between the last gate conduction period of the sensing signal in the nth frame and the first gate conduction period of the gate signal in the (n+1)th frame is equal to a second interval that is shorter than the first interval.

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