High bandwidth memory package structure

By using a package structure with a computing chip surrounding two rings of high-bandwidth memory, where the outer ring of memory is taller than the inner ring, and combining interposer redistribution and bridging chips, the problems of limited memory integration area and poor heat dissipation in existing technologies are solved, achieving high-density integration and flexible expansion of high-bandwidth memory.

CN122455022APending Publication Date: 2026-07-24JCET SEMICON (SHAOXING) CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202610537893.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-04-22
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

Existing 2.5D packaging solutions for high-bandwidth memory and computing chips suffer from problems such as limited integration area, restricted stacking quantity, poor heat dissipation, and complex wiring, making it difficult to increase storage capacity and bandwidth under the condition of fixed chip side length and package size.

Method used

The packaging structure employs a computing chip surrounded by at least two rings of high-bandwidth memory, with the outer ring of memory being taller than the inner ring. The computing chip is connected through a rewiring structure in the intermediary layer, achieving high-density interconnection of signals and power. Combined with a bridging chip and a multi-ring stepped height distribution, the heat dissipation path is optimized.

Benefits of technology

It breaks through the limitation of the number of memory chips on the side length of the computing chip, increases the total capacity and total bandwidth, improves heat dissipation efficiency, reduces packaging complexity and cost, and enhances power and signal integrity.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122455022A_ABST
    Figure CN122455022A_ABST
Patent Text Reader

Abstract

The application relates to a high-bandwidth storage packaging structure. The high-bandwidth storage packaging structure comprises a packaging carrier plate, an interposer arranged on the packaging carrier plate, a rewiring structure arranged in the interposer, a computing chip arranged in a central region of the packaging carrier plate and electrically connected to the packaging carrier plate through the interposer, a plurality of signal interfaces arranged in a circumferential direction of the computing chip, and a plurality of high-bandwidth memories arranged on the interposer, wherein the plurality of high-bandwidth memories are arranged in at least two circles in a peripheral region of the computing chip, the height of the high-bandwidth memories in an outer circle is greater than the height of the high-bandwidth memories in an inner circle, the high-bandwidth memories are connected to the rewiring structure of the interposer, and the high-bandwidth memories are connected to the corresponding signal interfaces of the computing chip through the rewiring structure. The application breaks through the limitation of the side length of the computing chip on the number of high-bandwidth memories, and improves the total capacity and total bandwidth.
Need to check novelty before this filing date? Find Prior Art