Multi-channel power amplifier synchronization driving method and system for RTDS simulation system

Abstract

The application provides a multi-channel power amplifier synchronization driving method and system for an RTDS simulation system, which first receives simulation data streams in real time, identifies a preset frame header to obtain a protocol frame, extracts a start identifier according to a start command field, compares time stamps of each data relative to a frame start time with preset frame synchronization time to obtain a deviation value when the start identifier is matched successfully, performs time domain interpolation adjustment according to the deviation value and a synchronization threshold group to generate a global trigger pulse, then obtains trigger interval jitter based on a current system clock, and makes the jitter value not less than a preset jitter threshold through delay dithering, finally extracts 8-way floating point data in the protocol frame, and splits the 8-way floating point data into 8-way independent digital signal streams according to physical channel mapping for output. The application effectively solves the time delay difference and phase offset problems when multiple power amplifiers are operated in parallel, and significantly improves the synchronization accuracy and timing certainty of multi-channel data output.

Description

Technical Field

[0001] This invention relates to the field of real-time simulation of power systems and power hardware-in-the-loop testing, and more specifically, to a method and system for synchronous drive and control of multi-channel power amplifiers for RTDS simulation systems. Background Technology

[0002] With the continuous development of power system transient simulation technologies such as new energy grid connection, flexible DC transmission, and grid fault reproduction, hardware-in-the-loop testing of power amplifiers based on RTDS simulation systems places increasingly higher demands on the synchronous drive and control accuracy of multi-channel power amplifiers. In practical applications, it is often necessary to operate multiple power amplifiers in parallel to increase output power or simulate complex grid operating conditions. How to ensure data synchronization between channels and achieve low-jitter trigger output has become a pressing technical challenge in this field.

[0003] Existing technologies for synchronous drive and control of multi-channel power amplifiers have the following shortcomings. First, traditional methods typically rely on external synchronization clocks or global trigger cables, using hardware wiring to align the signals of multiple power amplifiers. This approach is not only complex to wire and has poor anti-interference capabilities, but also introduces uncontrollable time delay differences as the number of power amplifiers increases due to clock fan-out and cable length variations. Second, some solutions attempt to use software timestamps or network time synchronization protocols for data alignment, but due to the uncertainty of network protocol stacks and the delay differences in data processing paths for each channel, it is difficult to achieve the microsecond-level synchronization accuracy required for power electromagnetic transient simulation. Especially in transient fault reproduction scenarios, even a phase shift of hundreds of nanoseconds can lead to malfunctions of protection devices. Third, existing technologies often use relatively simple methods to determine data availability, typically setting only a single threshold. If the threshold is too strict, a large number of data frames are discarded, leading to frequent test interruptions; if the threshold is too wide, it tolerates excessive synchronization deviations, causing power amplifier output distortion. Fourth, existing methods struggle to effectively suppress the cumulative jitter of trigger pulses during long-term operation. The instability of the output interval between adjacent frames will gradually amplify the phase difference between channels, seriously affecting the real-time performance and reliability of the closed-loop test.

[0004] Therefore, there is an urgent need for a multi-channel power amplifier synchronous drive and control technology that can autonomously complete data reception, multi-level synchronization verification and time-domain compensation, and jitter suppression. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a method and system for synchronous driving and controlling a multi-channel power amplifier for RTDS simulation systems. Through a series of processes such as start identifier matching, timestamp deviation comparison, synchronization threshold group judgment, time domain interpolation adjustment, trigger interval jitter detection and delay de-jittering, the invention achieves full synchronization and jitter suppression from data reception to pulse output.

[0006] Specifically, firstly, by using fixed frame header detection and dual verification of length and type, the protocol frames entering subsequent processes are ensured to have a complete and valid format. Secondly, by precisely matching the start command field with the reference threshold, the output process is prevented from being mistakenly triggered by non-start frames or interference signals. Thirdly, through a two-stage chain comparison of coarse and fine synchronization thresholds, combined with time-domain interpolation compensation for deviation-over-limit channels, high synchronization accuracy is ensured while avoiding efficiency losses caused by direct frame loss due to minor deviations. Fourthly, by real-time monitoring of trigger interval jitter and performing active delay compensation, accumulated timing jitter over long-term operation is eliminated. Finally, through physical channel mapping and parallel synchronous output, the simultaneous delivery of eight digital signal streams to each power amplifier is ensured, resolving the time delay difference and phase offset issues during parallel operation of multiple power amplifiers, and meeting the requirements of power system transient simulation and power hardware-in-the-loop testing for microsecond-level synchronization and low jitter output.

[0007] The first aspect of this invention provides a method for synchronous driving and controlling a multi-channel power amplifier for an RTDS simulation system, the method comprising:

[0008] The system receives the simulation data stream in real time, identifies the preset frame header, and then obtains the protocol frame.

[0009] Extract the startup identifier from the protocol frame based on the preset startup command field;

[0010] If the start identifier matches the preset start threshold, the timestamp of each data stream relative to the start time of the frame is obtained;

[0011] The deviation value of each channel is obtained by comparing the timestamp of each channel with the preset frame synchronization time.

[0012] Based on the deviation values ​​of each path and the preset synchronization threshold group, a global trigger pulse is generated after adjustment based on the preset time domain interpolation.

[0013] In response to the global trigger pulse, the trigger interval jitter is obtained based on the current system clock and the output trigger pulse time of the previous protocol frame;

[0014] Based on the preset delay debouncing, the trigger interval jitter value is not less than the preset jitter threshold.

[0015] After the global trigger pulse is issued, 8 channels of floating-point data are extracted according to the protocol frame, and then split into 8 independent digital signal streams based on the preset physical channel mapping relationship and output.

[0016] In this scheme, the real-time reception of the simulation data stream, after identifying the preset frame header, and obtaining the protocol frame specifically includes...

[0017] The simulation data stream is received in real time via a full-duplex optical port using an Aurora protocol converter.

[0018] Continuously monitor fixed frame headers in the data stream, and when a field matching a preset frame header is identified, lock the start position of the current frame;

[0019] Based on the predefined frame structure, the length information and type identifier of the current frame are parsed to complete the initial verification of the frame's legality.

[0020] The complete data frame that passes the verification is used as the protocol frame.

[0021] In this solution, the step of extracting the startup identifier from the protocol frame based on the preset startup command field specifically includes:

[0022] The startup command field is read from the specified offset position of the protocol frame to obtain the startup identifier;

[0023] The startup identifier is matched with a preset startup threshold, which is a baseline value for a valid startup command;

[0024] If the startup identifier matches the startup threshold, then a match is determined.

[0025] If the start flag does not match the start threshold, the current protocol frame is discarded and the system returns to receive the next frame.

[0026] In this scheme, the step of generating a global trigger pulse based on a preset time-domain interpolation adjustment after adjusting the deviation values ​​of each path and a preset synchronization threshold group specifically includes:

[0027] Parse the 8 data streams in the protocol frame and obtain the receiving timestamp of each stream relative to the start time of the frame;

[0028] Compare each timestamp with the preset theoretical synchronization time within the frame to calculate the synchronization deviation value for each channel;

[0029] Determine whether the maximum synchronization deviation in the synchronization deviation values ​​is less than the coarse synchronization threshold;

[0030] If not, discard the current protocol frame;

[0031] If so, then the synchronization deviation value of each path is further compared with the fine synchronization threshold one by one;

[0032] A global trigger pulse is generated when all path deviations do not exceed the fine synchronization threshold.

[0033] If any path deviation exceeds the fine synchronization threshold, the data of that path is adjusted by time-domain interpolation until the synchronization deviation falls within the fine synchronization threshold, and then a global trigger pulse is generated.

[0034] In this solution, the step of ensuring that the trigger interval jitter value is not less than a preset jitter threshold based on a preset delay debouncing specifically includes:

[0035] After generating the global trigger pulse, the current system clock is acquired, and the historical moment of the actual output trigger pulse of the previous protocol frame is read. The time difference between the two is calculated as the trigger interval jitter value.

[0036] The trigger interval jitter value is compared with the preset jitter threshold;

[0037] If the jitter value is greater than or equal to the jitter threshold, a trigger pulse is sent directly;

[0038] If the jitter value is less than the jitter threshold, delay debouncing is performed, postponing the issuance time of the trigger pulse until the actual trigger interval is restored to the preset nominal value.

[0039] In this scheme, the step of extracting 8 channels of floating-point data according to the protocol frame and splitting them into 8 independent digital signal streams based on a preset physical channel mapping relationship specifically includes:

[0040] At the moment the trigger pulse is emitted, extract 8 channels of 32-bit floating-point data from the payload of the protocol frame;

[0041] According to the preset mapping relationship between physical channels and data channel numbers, each floating-point data is assigned to the corresponding output channel;

[0042] Perform protocol conversion on each data stream separately to generate an independent digital signal stream;

[0043] The eight digital signal streams are synchronously output to the corresponding eight power amplifiers through a parallel interface.

[0044] A second aspect of the present invention provides a multi-channel power amplifier synchronous drive and control system for an RTDS simulation system, including a multi-channel power amplifier synchronous drive and control method program for an RTDS simulation system. When the multi-channel power amplifier synchronous drive and control method program for an RTDS simulation system is executed by the processor, it performs the following steps:

[0045] The system receives the simulation data stream in real time, identifies the preset frame header, and then obtains the protocol frame.

[0046] Extract the startup identifier from the protocol frame based on the preset startup command field;

[0047] If the start identifier matches the preset start threshold, the timestamp of each data stream relative to the start time of the frame is obtained;

[0048] The deviation value of each channel is obtained by comparing the timestamp of each channel with the preset frame synchronization time.

[0049] Based on the deviation values ​​of each path and the preset synchronization threshold group, a global trigger pulse is generated after adjustment based on the preset time domain interpolation.

[0050] In response to the global trigger pulse, the trigger interval jitter is obtained based on the current system clock and the output trigger pulse time of the previous protocol frame;

[0051] Based on the preset delay debouncing, the trigger interval jitter value is not less than the preset jitter threshold.

[0052] After the global trigger pulse is issued, 8 channels of floating-point data are extracted according to the protocol frame, and then split into 8 independent digital signal streams based on the preset physical channel mapping relationship and output.

[0053] A third aspect of the present invention provides a computer-readable storage medium comprising a program for a multi-channel power amplifier synchronous drive and control method for an RTDS simulation system. When the program for the multi-channel power amplifier synchronous drive and control method for an RTDS simulation system is executed by a processor, it implements the steps of the multi-channel power amplifier synchronous drive and control method for an RTDS simulation system as described in any of the preceding claims.

[0054] This invention provides a method and system for synchronous driving and controlling multi-channel power amplifiers in RTDS simulation systems. First, it receives the simulation data stream in real time and identifies a preset frame header to obtain a protocol frame. A start identifier is extracted from the start command field. Once the start identifier matches successfully, the timestamps of each data channel relative to the frame start time are compared with the preset frame synchronization time to obtain the deviation value. Then, based on the deviation value and a synchronization threshold group, time-domain interpolation adjustment is performed to generate a global trigger pulse. Next, the trigger interval jitter is obtained based on the current system clock, and delay debouncing ensures the jitter value is not less than a preset jitter threshold. Finally, eight floating-point data channels in the protocol frame are extracted and split into eight independent digital signal streams according to physical channel mapping. This invention effectively solves the problems of time delay difference and phase offset when multiple power amplifiers operate in parallel, significantly improving the synchronization accuracy and timing determinism of multi-channel data output. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope.

[0056] Figure 1 A flowchart of a multi-channel power amplifier synchronous drive and control method for an RTDS simulation system is shown below.

[0057] Figure 2 A flowchart illustrating a comparison of synchronization thresholds provided by an embodiment of the present invention is shown;

[0058] Figure 3This invention illustrates a schematic diagram of the system modules of a multi-channel power amplifier synchronous drive and control system for an RTDS simulation system.

[0059] Figure 4 A block diagram of a multi-channel power amplifier synchronous drive and control system for RTDS simulation system is shown. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used in embodiments of this invention shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as being interpreted in an idealized or highly formalized sense, unless expressly defined in this embodiment of the invention.

[0062] The terms "first," "second," and similar words used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "an," "a," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Similarly, terms such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The steps preceding or following the steps in the method of the embodiments of this invention are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0063] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0064] Figure 1 A flowchart of a multi-channel power amplifier synchronous drive and control method for RTDS simulation systems according to the present invention is shown.

[0065] like Figure 1 As shown, the first aspect of this invention discloses a synchronous drive and control method for a multi-channel power amplifier in an RTDS simulation system, the method comprising:

[0066] S102 receives the simulation data stream in real time, and after recognizing the preset frame header, obtains the protocol frame;

[0067] S104, extract the startup identifier according to the protocol frame based on the preset startup command field;

[0068] S106, If the start identifier matches the preset start threshold, obtain the timestamp of each data stream relative to the frame start time;

[0069] S108 compares each time stamp with the preset frame synchronization time to obtain the deviation value of each channel;

[0070] S110, based on the deviation values ​​of each channel and the preset synchronization threshold group, and after adjustment based on the preset time domain interpolation, a global trigger pulse is generated;

[0071] S112, in response to the global trigger pulse, obtains the trigger interval jitter based on the current system clock and the output trigger pulse time of the previous protocol frame;

[0072] S114, based on the preset delay debouncing, ensure that the trigger interval jitter value is not less than the preset jitter threshold;

[0073] S116 After the global trigger pulse is issued, 8 channels of floating-point data are extracted according to the protocol frame, and then split into 8 independent digital signal streams based on the preset physical channel mapping relationship and output.

[0074] It should be noted that in this embodiment, the simulation data stream output by the RTDS simulation system is first received in real time via the full-duplex optical port of the Aurora protocol conversion device, and a preset frame header is continuously detected in the data stream. Once a field matching the preset frame header is detected, the start position of the current frame is locked, and the complete protocol frame is parsed according to the predefined frame structure. Subsequently, according to the preset start command field, the start identifier is extracted from the specified offset position of the protocol frame, and this identifier is compared with the preset start threshold. If they match, the received timestamp of each data channel in the protocol frame relative to the frame start time is obtained, and each timestamp is compared with the preset frame synchronization time to calculate the synchronization deviation value of each channel. Based on the relationship between each deviation value and the preset synchronization threshold group, time-domain interpolation compensation is performed on the channel data with deviation exceeding the limit. After all channels meet the synchronization requirements, a global trigger pulse is generated. In response to this pulse, the current system clock is acquired and subtracted from the historical time of the actual output trigger pulse of the previous protocol frame to obtain the trigger interval jitter value. Then, adjustments are made using a preset delay debouncing mechanism to ensure that the actual trigger interval jitter value is not less than a preset jitter threshold, thereby guaranteeing the stability of the output timing. Finally, after the trigger pulse is validly emitted, eight floating-point data streams are extracted from the payload of the protocol frame, split into eight independent digital signal streams according to a preset physical channel mapping relationship, and synchronously output to eight power amplifiers after protocol conversion. Through the above process, the time delay difference and phase offset problems of multi-channel power amplifiers operating in parallel can be effectively solved.

[0075] According to an embodiment of the present invention, the real-time reception of the simulation data stream, after identifying the preset frame header, and obtaining the protocol frame, specifically includes...

[0076] The simulation data stream is received in real time via a full-duplex optical port using an Aurora protocol converter.

[0077] Continuously monitor fixed frame headers in the data stream, and when a field matching a preset frame header is identified, lock the start position of the current frame;

[0078] Based on the predefined frame structure, the length information and type identifier of the current frame are parsed to complete the initial verification of the frame's legality.

[0079] The complete data frame that passes the verification is used as the protocol frame.

[0080] It should be noted that in this embodiment, the high-speed simulation data stream from the RTDS simulation system is received in real time via the full-duplex optical port of the Aurora protocol conversion device. The device continuously performs fixed frame header detection on the received data bitstream. When a field that perfectly matches the preset frame header is identified, the location of that field is immediately locked as the start boundary of the current frame. Subsequently, according to the system's predefined frame structure, the length information and type identifier of the current frame are parsed sequentially. The length is checked to ensure it is within a reasonable range, and the type identifier is a simulation data type supported by the system, thus completing the initial verification of the current frame's validity. Only after all the above verifications pass is the current complete data frame confirmed as a valid protocol frame suitable for subsequent processing.

[0081] According to an embodiment of the present invention, the step of extracting the startup identifier based on the protocol frame according to the preset startup command field specifically includes:

[0082] The startup command field is read from the specified offset position of the protocol frame to obtain the startup identifier;

[0083] The startup identifier is matched with a preset startup threshold, which is a baseline value for a valid startup command;

[0084] If the startup identifier matches the startup threshold, then a match is determined.

[0085] If the start flag does not match the start threshold, the current protocol frame is discarded and the system returns to receive the next frame.

[0086] It should be noted that in this embodiment, after obtaining a valid protocol frame, the SEND_CS start command field is read from a specified offset position of the protocol frame according to a pre-agreed intra-frame offset. The content of this field is the start identifier for the current received data. A start threshold is pre-stored in the system, corresponding to the command code unique to the normal start of multi-channel output in the RTDS simulation system. The extracted start identifier is compared bit by bit with this start threshold: if they match completely, the match is successful, allowing the subsequent timestamp extraction and synchronization deviation calculation steps to continue; if they do not match, the current protocol frame is determined not to be a valid start frame, the frame is discarded, and the system returns to the received data stream state, waiting for the next frame. This avoids non-start data frames or abnormal interference signals from mistakenly triggering subsequent output processes.

[0087] According to an embodiment of the present invention, the step of generating a global trigger pulse based on a preset time-domain interpolation adjustment after adjusting the deviation values ​​of each path and a preset synchronization threshold group specifically includes:

[0088] Parse the 8 data streams in the protocol frame and obtain the receiving timestamp of each stream relative to the start time of the frame;

[0089] Compare each timestamp with the preset theoretical synchronization time within the frame to calculate the synchronization deviation value for each channel;

[0090] Determine whether the maximum synchronization deviation in the synchronization deviation values ​​is less than the coarse synchronization threshold;

[0091] If not, discard the current protocol frame;

[0092] If so, then the synchronization deviation value of each path is further compared with the fine synchronization threshold one by one;

[0093] A global trigger pulse is generated when all path deviations do not exceed the fine synchronization threshold.

[0094] If any path deviation exceeds the fine synchronization threshold, the data of that path is adjusted by time-domain interpolation until the synchronization deviation falls within the fine synchronization threshold, and then a global trigger pulse is generated.

[0095] It should be noted that, Figure 2 A flowchart illustrating a comparison of synchronization thresholds provided by an embodiment of the present invention is shown. Figure 2 The synchronization threshold comparison process shown in this embodiment involves, after obtaining the received timestamps of each data stream, calculating the timestamp of each stream against the preset theoretical synchronization time within the frame to obtain an independent synchronization deviation value for each stream. Synchronization detection is then initiated: first, the maximum value among all eight deviation values ​​is calculated, and it is determined whether this maximum synchronization deviation is less than or equal to a preset coarse synchronization threshold. If the maximum deviation exceeds the coarse synchronization threshold, it indicates that the overall synchronization of the current frame is severely insufficient, and the protocol frame is discarded and re-received. If the maximum deviation meets the coarse synchronization requirements, the synchronization deviation value of each stream is further compared with a preset fine synchronization threshold. When the deviation values ​​of all eight streams do not exceed the fine synchronization threshold, it indicates that all channels have reached a high-precision synchronization state, and a global trigger pulse is directly generated. If the deviation value of any stream exceeds the fine synchronization threshold, time-domain interpolation adjustment is performed on the corresponding floating-point data, i.e., interpolation or extrapolation compensation is performed on the data points on the time axis according to the direction and magnitude of the deviation, so that the adjusted synchronization deviation falls within the fine synchronization threshold range; after all channels meet the fine synchronization requirements, a global trigger pulse is generated again. By employing a two-stage screening process of coarse and fine synchronization, coupled with targeted temporal interpolation compensation, high synchronization accuracy can be ensured while avoiding efficiency losses caused by direct frame drops due to minor deviations.

[0096] According to an embodiment of the present invention, the step of ensuring that the trigger interval jitter value is not less than a preset jitter threshold based on a preset delay debouncing specifically includes:

[0097] After generating the global trigger pulse, the current system clock is acquired, and the historical moment of the actual output trigger pulse of the previous protocol frame is read. The time difference between the two is calculated as the trigger interval jitter value.

[0098] The trigger interval jitter value is compared with the preset jitter threshold;

[0099] If the jitter value is greater than or equal to the jitter threshold, a trigger pulse is sent directly;

[0100] If the jitter value is less than the jitter threshold, delay debouncing is performed, postponing the issuance time of the trigger pulse until the actual trigger interval is restored to the preset nominal value.

[0101] It should be noted that in this embodiment, after the system generates a global trigger pulse, it does not immediately issue the pulse. Instead, it first enters the trigger jitter detection stage. First, the current system clock value is collected as the preparation time for this trigger. Then, the historical clock record of the actual output trigger pulse of the previous protocol frame is read from the internal register. The current clock value is subtracted from the historical clock value to obtain the time interval between two adjacent triggers, which is used as the actual measurement result of the trigger interval jitter value. Subsequently, this measured jitter value is compared with a preset minimum allowable jitter threshold: if the measured jitter value is greater than or equal to the jitter threshold, it indicates that the current trigger interval stability meets the requirements, and the trigger pulse is directly issued to each output channel; if the measured jitter value is less than the jitter threshold, it indicates that the adjacent trigger intervals are too short, posing a risk of accumulated jitter. In this case, a preset delay de-jitter operation is automatically executed, that is, the issuance time of the trigger pulse is postponed by an appropriate amount of time, restoring the actual trigger interval to the preset nominal interval value, thereby eliminating jitter. By monitoring the trigger interval in real time and actively delaying compensation, trigger timing jitter caused by clock drift or processing fluctuations during long-term operation can be effectively suppressed.

[0102] According to an embodiment of the present invention, the step of extracting 8 channels of floating-point data according to the protocol frame and splitting them into 8 independent digital signal streams based on a preset physical channel mapping relationship specifically includes:

[0103] At the moment the trigger pulse is emitted, extract 8 channels of 32-bit floating-point data from the payload of the protocol frame;

[0104] According to the preset mapping relationship between physical channels and data channel numbers, each floating-point data is assigned to the corresponding output channel;

[0105] Perform protocol conversion on each data stream separately to generate an independent digital signal stream;

[0106] The eight digital signal streams are synchronously output to the corresponding eight power amplifiers through a parallel interface.

[0107] It should be noted that, in this embodiment, at the precise moment the trigger pulse is effectively emitted, eight channels of floating-point format simulation data are extracted from the payload area of ​​the protocol frame according to a predetermined data arrangement order. Each channel of data corresponds to a drive command for one power amplifier. Subsequently, a pre-established and stored physical channel mapping table is invoked. This table records the fixed correspondence between data channel numbers and physical output channels. Based on this table, each channel of floating-point data is accurately allocated to its corresponding output channel. For each allocated channel of data, an independent protocol conversion operation is performed to convert the floating-point data into a high-speed digital signal stream conforming to the SMV digital signal format. Finally, the eight converted digital signal streams are synchronously output to the eight connected power amplifiers at the same time through a parallel interface, thereby driving multiple power amplifiers to work collaboratively. This ensures the simultaneous arrival and consistent driving of each frame of data among multiple power amplifiers.

[0108] It is worth mentioning that it also includes:

[0109] After the trigger pulse is issued, the comparison results of the deviation values ​​of each channel and the jitter of the trigger interval are recorded to form the running status log;

[0110] The number of times temporal interpolation adjustment or delay debouncing actions are triggered during the continuous frame processing of a preset number of times;

[0111] When the number of actions exceeds a preset action frequency threshold, tighten the fine synchronization threshold or the jitter threshold in the synchronization threshold group;

[0112] When the number of actions is lower than the preset stable frequency threshold, the fine synchronization threshold of the synchronization threshold group or the jitter threshold is relaxed.

[0113] It should be noted that in this embodiment, after each successful trigger pulse emission operation, the system automatically records the comparison results between the synchronization deviation value and the trigger interval jitter value during this processing, and writes these records, along with information on whether time-domain interpolation adjustment or delay debouncing actions were performed, into the internal operation status log. Using the number of consecutive frame processing operations as a statistical window, the system accumulates the actual number of times time-domain interpolation adjustment or delay debouncing actions are triggered within this window. When the accumulated number of actions exceeds a preset action frequency threshold, it indicates that the current environment or input signal is fluctuating significantly. The system automatically tightens the fine synchronization threshold or jitter threshold in the synchronization threshold group, making the synchronization and jitter judgment of subsequent frames more stringent to maintain output quality. Conversely, when the accumulated number of actions is lower than a preset stable frequency threshold, it indicates that the current operating state is stable, and the system automatically relaxes the above thresholds to reduce unnecessary computational overhead. Through this dynamic threshold adjustment, the drive control method can adaptively balance synchronization accuracy and processing efficiency.

[0114] It is worth mentioning that it also includes:

[0115] When two or more consecutive protocol frames are discarded in the synchronization threshold group comparison because the maximum synchronization deviation exceeds the coarse synchronization threshold, it is determined to be a data loss synchronization state.

[0116] In response to the data loss synchronization state, the optical port receiving channel of the Aurora protocol conversion device is closed, and the optical port link is re-established after a preset reset time.

[0117] After the link is reset and restored, the detection of the fixed frame header and the reception of subsequent data frames will resume.

[0118] If synchronization cannot be restored after three consecutive resets, switch to the backup optical port channel to receive the simulated data stream.

[0119] It should be noted that in this embodiment, during continuous frame processing, the number of protocol frames discarded due to the maximum synchronization deviation exceeding the coarse synchronization threshold is monitored in real time. When two or more consecutive protocol frames are discarded for the above reasons, it is determined that the currently input data stream has entered a state of out-of-synchronization, that is, the optical link between the Aurora protocol conversion device and the RTDS simulation system may have experienced clock drift or data misalignment. In response to this out-of-synchronization determination, the currently operating optical receiving channel is actively shut down, the data receiving path is cut off, and a preset reset time is waited for the state machines at both ends of the link to return to their initial state. After the wait is completed, the optical receiving channel is restarted and an attempt is made to establish the link. After the link is restored, the detection of fixed frame headers and reception of subsequent data frames resume. If the link synchronization still has not returned to normal after three consecutive reset operations, the system automatically switches to the backup optical channel to continue receiving the simulation data stream. This mechanism effectively improves the system's fault tolerance and continuous operational reliability in the event of link abnormalities.

[0120] It is worth mentioning that it also includes:

[0121] In the joint simulation scenario of power grid fault reproduction or flexible DC transmission, before generating the global trigger pulse, it is verified whether the simulation time stamp carried by the current protocol frame is continuous with the simulation time stamp of the previous successful output frame.

[0122] If the data is determined to be discontinuous, it is identified as a simulation data frame loss event, trigger pulse generation is prohibited, and a data retransmission request is sent to the RTDS simulation system.

[0123] If the sequence is determined to be continuous, the trigger pulse generation step continues.

[0124] It should be noted that in this embodiment, in the joint simulation scenario of power grid fault reproduction or flexible DC transmission, when performing synchronous drive control of multi-channel power amplifiers, an additional verification operation is performed before generating the global trigger pulse: extracting the simulation time stamp field carried in the current protocol frame, and simultaneously reading the simulation time stamp recorded when the previous frame was successfully output, comparing the two to determine whether they are continuous. If the determination result is discontinuous, that is, there is a missing simulation step between the time stamp of the current frame and the time stamp of the previous frame, it is identified as a simulation data frame loss event. At this time, the generation of the trigger pulse of the current frame is prohibited, and a data retransmission request is immediately sent to the RTDS simulation system, requesting the simulation system to retransmit the lost data frame. If the determination result is continuous, it means that the data is complete, and the trigger pulse generation and output continue to be executed according to the normal process. Through the time stamp continuity verification and frame loss retransmission mechanism, power amplifier drive abnormalities caused by simulation data loss can be avoided, thereby ensuring the authenticity and reliability of the test results in the fault reproduction scenario.

[0125] It is worth mentioning that it also includes:

[0126] In the scenario of new energy grid connection or power hardware in the loop test, the 8 floating-point data obtained after the trigger pulse is issued are written into the independent output buffer queues of the corresponding 8 power amplifiers respectively.

[0127] During the reception of the next frame of data, the data backlog depth of each queue is monitored in real time;

[0128] When the backlog depth of any queue exceeds the preset scenario adaptation blocking threshold, it is determined that the power amplifier channel response is lagging.

[0129] In response to channel response lag, extend the jitter threshold or nominal value;

[0130] Once the queue backlog returns to normal levels, restore the jitter threshold and nominal value.

[0131] It should be noted that, in this embodiment, for new energy grid connection or power hardware-in-the-loop testing scenarios, an adaptive adjustment mechanism for trigger parameters based on output queue backlog monitoring is introduced. Specifically, after each trigger pulse is emitted, the obtained eight floating-point data are written into the independent output buffer queues of the corresponding eight power amplifiers. Each queue buffers the drive data to be sent according to the first-in-first-out principle. During the reception and processing of the next frame of data, the backlog depth of data that has not yet been read by the power amplifier in each output buffer queue is monitored in real time. When the backlog depth of any queue exceeds the preset blocking threshold for the current scenario, it is determined that the response speed of the power amplifier corresponding to that channel lags behind the data transmission speed. In response to this determination, the trigger interval jitter threshold or the nominal interval value of the trigger pulse is automatically extended, thereby reducing the data writing rate to the queue and allowing sufficient response time for the power amplifier. After the backlog depth of the monitored queue returns to the normal level, the jitter threshold and the nominal interval value are restored to the original set values. Through queue-aware adaptive trigger adjustment, power amplifier buffer overflow can be effectively prevented, ensuring data continuity and test stability under long-term operation.

[0132] Figure 3 A schematic diagram of the system modules of a multi-channel power amplifier synchronous drive and control system for RTDS simulation system is shown.

[0133] like Figure 3 As shown, the system module includes an RTDS simulation system 31, an Aurora protocol conversion device 32, and a power amplifier device 33.

[0134] The Aurora protocol conversion device 32 includes:

[0135] The optical port receiving module 321 is used to receive the simulated data stream in real time via a full-duplex optical port and to detect the fixed frame header;

[0136] Frame parsing and verification module 322 is used to identify the preset frame header, parse the frame length and type identifier, and extract the protocol frame;

[0137] The startup identifier matching module 323 is used to extract the startup identifier from the protocol frame and match it with a preset startup threshold;

[0138] The timestamp extraction and comparison module 324 is used to obtain the received timestamp of each data channel relative to the frame start time after a successful match, then compare each timestamp with the preset frame synchronization time to obtain the deviation value, and make two-level judgments based on the coarse synchronization threshold and the fine synchronization threshold.

[0139] The time-domain interpolation adjustment module 325 is used to perform time-domain interpolation compensation on channel data whose deviation exceeds the fine synchronization threshold;

[0140] Trigger pulse generation module 326 is used to generate a global trigger pulse after the synchronization requirements are met;

[0141] The jitter detection and delay debouncing module 327 is used to collect the current system clock and the output time of the previous frame, calculate the jitter value of the trigger interval, and perform delay debouncing when the jitter value is less than the preset jitter threshold.

[0142] The data splitting and protocol conversion module 328 is used to extract eight floating-point data from the protocol frame after the trigger pulse is emitted, split it into eight independent digital signal streams according to the physical channel mapping relationship, and convert it into SMV format;

[0143] Parallel output interface 329 is used for synchronous output of eight digital signal streams.

[0144] Figure 4 A block diagram of a multi-channel power amplifier synchronous drive and control system for RTDS simulation system is shown.

[0145] like Figure 4 As shown, the second aspect of the present invention discloses a multi-channel power amplifier synchronous drive and control system 4 for an RTDS simulation system, including a memory 41 and a processor 42. The memory includes a multi-channel power amplifier synchronous drive and control method program for an RTDS simulation system. When the processor executes the multi-channel power amplifier synchronous drive and control method program for an RTDS simulation system, it performs the following steps:

[0146] The system receives the simulation data stream in real time, identifies the preset frame header, and then obtains the protocol frame.

[0147] Extract the startup identifier from the protocol frame based on the preset startup command field;

[0148] If the start identifier matches the preset start threshold, the timestamp of each data stream relative to the start time of the frame is obtained;

[0149] The deviation value of each channel is obtained by comparing the timestamp of each channel with the preset frame synchronization time.

[0150] Based on the deviation values ​​of each path and the preset synchronization threshold group, a global trigger pulse is generated after adjustment based on the preset time domain interpolation.

[0151] In response to the global trigger pulse, the trigger interval jitter is obtained based on the current system clock and the output trigger pulse time of the previous protocol frame;

[0152] Based on the preset delay debouncing, the trigger interval jitter value is not less than the preset jitter threshold.

[0153] After the global trigger pulse is issued, 8 channels of floating-point data are extracted according to the protocol frame, and then split into 8 independent digital signal streams based on the preset physical channel mapping relationship and output.

[0154] It should be noted that in this embodiment, the simulation data stream output by the RTDS simulation system is first received in real time via the full-duplex optical port of the Aurora protocol conversion device, and a preset frame header is continuously detected in the data stream. Once a field matching the preset frame header is detected, the start position of the current frame is locked, and the complete protocol frame is parsed according to the predefined frame structure. Subsequently, according to the preset start command field, the start identifier is extracted from the specified offset position of the protocol frame, and this identifier is compared with the preset start threshold. If they match, the received timestamp of each data channel in the protocol frame relative to the frame start time is obtained, and each timestamp is compared with the preset frame synchronization time to calculate the synchronization deviation value of each channel. Based on the relationship between each deviation value and the preset synchronization threshold group, time-domain interpolation compensation is performed on the channel data with deviation exceeding the limit. After all channels meet the synchronization requirements, a global trigger pulse is generated. In response to this pulse, the current system clock is acquired and subtracted from the historical time of the actual output trigger pulse of the previous protocol frame to obtain the trigger interval jitter value. Then, adjustments are made using a preset delay debouncing mechanism to ensure that the actual trigger interval jitter value is not less than a preset jitter threshold, thereby guaranteeing the stability of the output timing. Finally, after the trigger pulse is validly emitted, eight floating-point data streams are extracted from the payload of the protocol frame, split into eight independent digital signal streams according to a preset physical channel mapping relationship, and synchronously output to eight power amplifiers after protocol conversion. Through the above process, the time delay difference and phase offset problems of multi-channel power amplifiers operating in parallel can be effectively solved.

[0155] According to an embodiment of the present invention, the real-time reception of the simulation data stream, after identifying the preset frame header, and obtaining the protocol frame, specifically includes...

[0156] The simulation data stream is received in real time via a full-duplex optical port using an Aurora protocol converter.

[0157] Continuously monitor fixed frame headers in the data stream, and when a field matching a preset frame header is identified, lock the start position of the current frame;

[0158] Based on the predefined frame structure, the length information and type identifier of the current frame are parsed to complete the initial verification of the frame's legality.

[0159] The complete data frame that passes the verification is used as the protocol frame.

[0160] It should be noted that in this embodiment, the high-speed simulation data stream from the RTDS simulation system is received in real time via the full-duplex optical port of the Aurora protocol conversion device. The device continuously performs fixed frame header detection on the received data bitstream. When a field that perfectly matches the preset frame header is identified, the location of that field is immediately locked as the start boundary of the current frame. Subsequently, according to the system's predefined frame structure, the length information and type identifier of the current frame are parsed sequentially. The length is checked to ensure it is within a reasonable range, and the type identifier is a simulation data type supported by the system, thus completing the initial verification of the current frame's validity. Only after all the above verifications pass is the current complete data frame confirmed as a valid protocol frame suitable for subsequent processing.

[0161] According to an embodiment of the present invention, the step of extracting the startup identifier based on the protocol frame according to the preset startup command field specifically includes:

[0162] The startup command field is read from the specified offset position of the protocol frame to obtain the startup identifier;

[0163] The startup identifier is matched with a preset startup threshold, which is a baseline value for a valid startup command;

[0164] If the startup identifier matches the startup threshold, then a match is determined.

[0165] If the start flag does not match the start threshold, the current protocol frame is discarded and the system returns to receive the next frame.

[0166] It should be noted that in this embodiment, after obtaining a valid protocol frame, the SEND_CS start command field is read from a specified offset position of the protocol frame according to a pre-agreed intra-frame offset. The content of this field is the start identifier for the current received data. A start threshold is pre-stored in the system, corresponding to the command code unique to the normal start of multi-channel output in the RTDS simulation system. The extracted start identifier is compared bit by bit with this start threshold: if they match completely, the match is successful, allowing the subsequent timestamp extraction and synchronization deviation calculation steps to continue; if they do not match, the current protocol frame is determined not to be a valid start frame, the frame is discarded, and the system returns to the received data stream state, waiting for the next frame. This avoids non-start data frames or abnormal interference signals from mistakenly triggering subsequent output processes.

[0167] According to an embodiment of the present invention, the step of generating a global trigger pulse based on a preset time-domain interpolation adjustment after adjusting the deviation values ​​of each path and a preset synchronization threshold group specifically includes:

[0168] Parse the 8 data streams in the protocol frame and obtain the receiving timestamp of each stream relative to the start time of the frame;

[0169] Compare each timestamp with the preset theoretical synchronization time within the frame to calculate the synchronization deviation value for each channel;

[0170] Determine whether the maximum synchronization deviation in the synchronization deviation values ​​is less than the coarse synchronization threshold;

[0171] If not, discard the current protocol frame;

[0172] If so, then the synchronization deviation value of each path is further compared with the fine synchronization threshold one by one;

[0173] A global trigger pulse is generated when all path deviations do not exceed the fine synchronization threshold.

[0174] If any path deviation exceeds the fine synchronization threshold, the data of that path is adjusted by time-domain interpolation until the synchronization deviation falls within the fine synchronization threshold, and then a global trigger pulse is generated.

[0175] It should be noted that in this embodiment, after obtaining the received timestamps of each data channel, the timestamp of each channel is calculated one by one with the preset theoretical synchronization time within the frame to obtain an independent synchronization deviation value for each channel. Then, synchronization detection is initiated: first, the maximum value among all eight deviation values ​​is calculated, and it is determined whether this maximum synchronization deviation is less than or equal to a preset coarse synchronization threshold. If the maximum deviation exceeds the coarse synchronization threshold, it indicates that the overall synchronization of the current frame is severely insufficient, and the protocol frame is directly discarded and re-received. If the maximum deviation meets the coarse synchronization requirements, the synchronization deviation value of each channel is further compared one by one with the preset fine synchronization threshold. When the deviation values ​​of all eight channels do not exceed the fine synchronization threshold, it indicates that all channels have reached a high-precision synchronization state, and a global trigger pulse is directly generated. If the deviation value of any channel exceeds the fine synchronization threshold, time-domain interpolation adjustment is performed on the corresponding floating-point data, that is, interpolation or extrapolation compensation is performed on the data points on the time axis according to the direction and magnitude of the deviation, so that the adjusted synchronization deviation falls within the range of the fine synchronization threshold; after all channels meet the fine synchronization requirements, a global trigger pulse is generated again. By employing a two-stage screening process of coarse and fine synchronization, coupled with targeted temporal interpolation compensation, high synchronization accuracy can be ensured while avoiding efficiency losses caused by direct frame drops due to minor deviations.

[0176] According to an embodiment of the present invention, the step of ensuring that the trigger interval jitter value is not less than a preset jitter threshold based on a preset delay debouncing specifically includes:

[0177] After generating the global trigger pulse, the current system clock is acquired, and the historical moment of the actual output trigger pulse of the previous protocol frame is read. The time difference between the two is calculated as the trigger interval jitter value.

[0178] The trigger interval jitter value is compared with the preset jitter threshold;

[0179] If the jitter value is greater than or equal to the jitter threshold, a trigger pulse is sent directly;

[0180] If the jitter value is less than the jitter threshold, delay debouncing is performed, postponing the issuance time of the trigger pulse until the actual trigger interval is restored to the preset nominal value.

[0181] It should be noted that in this embodiment, after the system generates a global trigger pulse, it does not immediately issue the pulse. Instead, it first enters the trigger jitter detection stage. First, the current system clock value is collected as the preparation time for this trigger. Then, the historical clock record of the actual output trigger pulse of the previous protocol frame is read from the internal register. The current clock value is subtracted from the historical clock value to obtain the time interval between two adjacent triggers, which is used as the actual measurement result of the trigger interval jitter value. Subsequently, this measured jitter value is compared with a preset minimum allowable jitter threshold: if the measured jitter value is greater than or equal to the jitter threshold, it indicates that the current trigger interval stability meets the requirements, and the trigger pulse is directly issued to each output channel; if the measured jitter value is less than the jitter threshold, it indicates that the adjacent trigger intervals are too short, posing a risk of accumulated jitter. In this case, a preset delay de-jitter operation is automatically executed, that is, the issuance time of the trigger pulse is postponed by an appropriate amount of time, restoring the actual trigger interval to the preset nominal interval value, thereby eliminating jitter. By monitoring the trigger interval in real time and actively delaying compensation, trigger timing jitter caused by clock drift or processing fluctuations during long-term operation can be effectively suppressed.

[0182] According to an embodiment of the present invention, the step of extracting 8 channels of floating-point data according to the protocol frame and splitting them into 8 independent digital signal streams based on a preset physical channel mapping relationship specifically includes:

[0183] At the moment the trigger pulse is emitted, extract 8 channels of 32-bit floating-point data from the payload of the protocol frame;

[0184] According to the preset mapping relationship between physical channels and data channel numbers, each floating-point data is assigned to the corresponding output channel;

[0185] Perform protocol conversion on each data stream separately to generate an independent digital signal stream;

[0186] The eight digital signal streams are synchronously output to the corresponding eight power amplifiers through a parallel interface.

[0187] It should be noted that, in this embodiment, at the precise moment the trigger pulse is effectively emitted, eight channels of floating-point format simulation data are extracted from the payload area of ​​the protocol frame according to a predetermined data arrangement order. Each channel of data corresponds to a drive command for one power amplifier. Subsequently, a pre-established and stored physical channel mapping table is invoked. This table records the fixed correspondence between data channel numbers and physical output channels. Based on this table, each channel of floating-point data is accurately allocated to its corresponding output channel. For each allocated channel of data, an independent protocol conversion operation is performed to convert the floating-point data into a high-speed digital signal stream conforming to the SMV digital signal format. Finally, the eight converted digital signal streams are synchronously output to the eight connected power amplifiers at the same time through a parallel interface, thereby driving multiple power amplifiers to work collaboratively. This ensures the simultaneous arrival and consistent driving of each frame of data among multiple power amplifiers.

[0188] It is worth mentioning that it also includes:

[0189] After the trigger pulse is issued, the comparison results of the deviation values ​​of each channel and the jitter of the trigger interval are recorded to form the running status log;

[0190] The number of times temporal interpolation adjustment or delay debouncing actions are triggered during the continuous frame processing of a preset number of times;

[0191] When the number of actions exceeds a preset action frequency threshold, tighten the fine synchronization threshold or the jitter threshold in the synchronization threshold group;

[0192] When the number of actions is lower than the preset stable frequency threshold, the fine synchronization threshold of the synchronization threshold group or the jitter threshold is relaxed.

[0193] It should be noted that in this embodiment, after each successful trigger pulse emission operation, the system automatically records the comparison results between the synchronization deviation value and the trigger interval jitter value during this processing, and writes these records, along with information on whether time-domain interpolation adjustment or delay debouncing actions were performed, into the internal operation status log. Using the number of consecutive frame processing operations as a statistical window, the system accumulates the actual number of times time-domain interpolation adjustment or delay debouncing actions are triggered within this window. When the accumulated number of actions exceeds a preset action frequency threshold, it indicates that the current environment or input signal is fluctuating significantly. The system automatically tightens the fine synchronization threshold or jitter threshold in the synchronization threshold group, making the synchronization and jitter judgment of subsequent frames more stringent to maintain output quality. Conversely, when the accumulated number of actions is lower than a preset stable frequency threshold, it indicates that the current operating state is stable, and the system automatically relaxes the above thresholds to reduce unnecessary computational overhead. Through this dynamic threshold adjustment, the drive control method can adaptively balance synchronization accuracy and processing efficiency.

[0194] It is worth mentioning that it also includes:

[0195] When two or more consecutive protocol frames are discarded in the synchronization threshold group comparison because the maximum synchronization deviation exceeds the coarse synchronization threshold, it is determined to be a data loss synchronization state.

[0196] In response to the data loss synchronization state, the optical port receiving channel of the Aurora protocol conversion device is closed, and the optical port link is re-established after a preset reset time.

[0197] After the link is reset and restored, the detection of the fixed frame header and the reception of subsequent data frames will resume.

[0198] If synchronization cannot be restored after three consecutive resets, switch to the backup optical port channel to receive the simulated data stream.

[0199] It should be noted that in this embodiment, during continuous frame processing, the number of protocol frames discarded due to the maximum synchronization deviation exceeding the coarse synchronization threshold is monitored in real time. When two or more consecutive protocol frames are discarded for the above reasons, it is determined that the currently input data stream has entered a state of out-of-synchronization, that is, the optical link between the Aurora protocol conversion device and the RTDS simulation system may have experienced clock drift or data misalignment. In response to this out-of-synchronization determination, the currently operating optical receiving channel is actively shut down, the data receiving path is cut off, and a preset reset time is waited for the state machines at both ends of the link to return to their initial state. After the wait is completed, the optical receiving channel is restarted and an attempt is made to establish the link. After the link is restored, the detection of fixed frame headers and reception of subsequent data frames resume. If the link synchronization still has not returned to normal after three consecutive reset operations, the system automatically switches to the backup optical channel to continue receiving the simulation data stream. This mechanism effectively improves the system's fault tolerance and continuous operational reliability in the event of link abnormalities.

[0200] It is worth mentioning that it also includes:

[0201] In the joint simulation scenario of power grid fault reproduction or flexible DC transmission, before generating the global trigger pulse, it is verified whether the simulation time stamp carried by the current protocol frame is continuous with the simulation time stamp of the previous successful output frame.

[0202] If the data is determined to be discontinuous, it is identified as a simulation data frame loss event, trigger pulse generation is prohibited, and a data retransmission request is sent to the RTDS simulation system.

[0203] If the sequence is determined to be continuous, the trigger pulse generation step continues.

[0204] It should be noted that in this embodiment, in the joint simulation scenario of power grid fault reproduction or flexible DC transmission, when performing synchronous drive control of multi-channel power amplifiers, an additional verification operation is performed before generating the global trigger pulse: extracting the simulation time stamp field carried in the current protocol frame, and simultaneously reading the simulation time stamp recorded when the previous frame was successfully output, comparing the two to determine whether they are continuous. If the determination result is discontinuous, that is, there is a missing simulation step between the time stamp of the current frame and the time stamp of the previous frame, it is identified as a simulation data frame loss event. At this time, the generation of the trigger pulse of the current frame is prohibited, and a data retransmission request is immediately sent to the RTDS simulation system, requesting the simulation system to retransmit the lost data frame. If the determination result is continuous, it means that the data is complete, and the trigger pulse generation and output continue to be executed according to the normal process. Through the time stamp continuity verification and frame loss retransmission mechanism, power amplifier drive abnormalities caused by simulation data loss can be avoided, thereby ensuring the authenticity and reliability of the test results in the fault reproduction scenario.

[0205] It is worth mentioning that it also includes:

[0206] In the scenario of new energy grid connection or power hardware in the loop test, the 8 floating-point data obtained after the trigger pulse is issued are written into the independent output buffer queues of the corresponding 8 power amplifiers respectively.

[0207] During the reception of the next frame of data, the data backlog depth of each queue is monitored in real time;

[0208] When the backlog depth of any queue exceeds the preset scenario adaptation blocking threshold, it is determined that the power amplifier channel response is lagging.

[0209] In response to channel response lag, extend the jitter threshold or nominal value;

[0210] Once the queue backlog returns to normal levels, restore the jitter threshold and nominal value.

[0211] It should be noted that, in this embodiment, for new energy grid connection or power hardware-in-the-loop testing scenarios, an adaptive adjustment mechanism for trigger parameters based on output queue backlog monitoring is introduced. Specifically, after each trigger pulse is emitted, the obtained eight floating-point data are written into the independent output buffer queues of the corresponding eight power amplifiers. Each queue buffers the drive data to be sent according to the first-in-first-out principle. During the reception and processing of the next frame of data, the backlog depth of data that has not yet been read by the power amplifier in each output buffer queue is monitored in real time. When the backlog depth of any queue exceeds the preset blocking threshold for the current scenario, it is determined that the response speed of the power amplifier corresponding to that channel lags behind the data transmission speed. In response to this determination, the trigger interval jitter threshold or the nominal interval value of the trigger pulse is automatically extended, thereby reducing the data writing rate to the queue and allowing sufficient response time for the power amplifier. After the backlog depth of the monitored queue returns to the normal level, the jitter threshold and the nominal interval value are restored to the original set values. Through queue-aware adaptive trigger adjustment, power amplifier buffer overflow can be effectively prevented, ensuring data continuity and test stability under long-term operation.

[0212] A third aspect of the present invention provides a computer-readable storage medium comprising a program for a multi-channel power amplifier synchronous drive and control method for an RTDS simulation system. When the program for the multi-channel power amplifier synchronous drive and control method for an RTDS simulation system is executed by a processor, it implements the steps of the multi-channel power amplifier synchronous drive and control method for an RTDS simulation system as described in any of the preceding claims.

[0213] In summary, this invention provides a method and system for synchronous driving and controlling multi-channel power amplifiers in RTDS simulation systems. First, it receives the simulation data stream in real time and identifies a preset frame header to obtain a protocol frame. A start identifier is extracted based on the start command field. Once the start identifier matches successfully, the timestamps of each data channel relative to the frame start time are compared with the preset frame synchronization time to obtain the deviation value. Then, based on the deviation value and a synchronization threshold group, time-domain interpolation adjustment is performed to generate a global trigger pulse. Next, the trigger interval jitter is obtained based on the current system clock, and delay debouncing ensures the jitter value is not less than a preset jitter threshold. Finally, eight floating-point data channels in the protocol frame are extracted and split into eight independent digital signal streams according to physical channel mapping. This invention effectively solves the problems of time delay difference and phase offset during parallel operation of multiple power amplifiers, significantly improving the synchronization accuracy and timing determinism of multi-channel data output.

[0214] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0215] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A synchronous drive and control method for a multi-channel power amplifier for an RTDS simulation system, characterized in that, The method includes: The system receives the simulation data stream in real time, identifies the preset frame header, and then obtains the protocol frame. Extract the startup identifier from the protocol frame based on the preset startup command field; If the start identifier matches the preset start threshold, the timestamp of each data stream relative to the start time of the frame is obtained; The deviation value of each channel is obtained by comparing the timestamp of each channel with the preset frame synchronization time. Based on the deviation values ​​of each path and the preset synchronization threshold group, a global trigger pulse is generated after adjustment based on the preset time domain interpolation. In response to the global trigger pulse, the trigger interval jitter value is obtained based on the current system clock and the output trigger pulse time of the previous protocol frame; Based on the preset delay debouncing, the trigger interval jitter value is not less than the preset jitter threshold. After the global trigger pulse is issued, 8 channels of floating-point data are extracted according to the protocol frame, and then split into 8 independent digital signal streams based on the preset physical channel mapping relationship and output.

2. The method for synchronous driving and control of a multi-channel power amplifier for an RTDS simulation system according to claim 1, characterized in that, The real-time received simulation data stream, after identifying the preset frame header, obtains the protocol frame, specifically including... The simulation data stream is received in real time via a full-duplex optical port using an Aurora protocol converter. Continuously monitor fixed frame headers in the data stream, and when a field matching a preset frame header is identified, lock the start position of the current frame; Based on the predefined frame structure, the length information and type identifier of the current frame are parsed to complete the initial verification of the frame's legality. The complete data frame that passes the verification is used as the protocol frame.

3. The method for synchronous driving and control of a multi-channel power amplifier for an RTDS simulation system according to claim 1, characterized in that, The step of extracting the startup identifier from the protocol frame based on the preset startup command field specifically includes: The startup command field is read from the specified offset position of the protocol frame to obtain the startup identifier; The startup identifier is matched with a preset startup threshold, which is a baseline value for a valid startup command; If the startup identifier matches the startup threshold, then a match is determined. If the start flag does not match the start threshold, the current protocol frame is discarded and the system returns to receive the next frame.

4. The method for synchronous driving and control of a multi-channel power amplifier for an RTDS simulation system according to claim 1, characterized in that, The step of generating a global trigger pulse based on a preset time-domain interpolation adjustment after adjusting the deviation values ​​of each path and a preset synchronization threshold group specifically includes: Parse the 8 data streams in the protocol frame and obtain the receiving timestamp of each stream relative to the start time of the frame; Compare each timestamp with the preset theoretical synchronization time within the frame to calculate the synchronization deviation value for each channel; Determine whether the maximum synchronization deviation in the synchronization deviation values ​​is less than the coarse synchronization threshold; If not, discard the current protocol frame; If so, then the synchronization deviation value of each path is further compared with the fine synchronization threshold one by one; A global trigger pulse is generated when all path deviations do not exceed the fine synchronization threshold. If any path deviation exceeds the fine synchronization threshold, the data of that path is adjusted by time-domain interpolation until the synchronization deviation falls within the fine synchronization threshold, and then a global trigger pulse is generated.

5. The method for synchronous driving and control of a multi-channel power amplifier for an RTDS simulation system according to claim 1, characterized in that, The preset delay-based debouncing, ensuring that the trigger interval jitter value is not less than a preset jitter threshold, specifically includes: After generating the global trigger pulse, the current system clock is acquired, and the historical moment of the actual output trigger pulse of the previous protocol frame is read. The time difference between the two is calculated as the trigger interval jitter value. The trigger interval jitter value is compared with the preset jitter threshold; If the jitter value is greater than or equal to the jitter threshold, a trigger pulse is sent directly; If the jitter value is less than the jitter threshold, delay debouncing is performed, postponing the issuance time of the trigger pulse until the actual trigger interval is restored to the preset nominal value.

6. The method for synchronous driving and control of a multi-channel power amplifier for an RTDS simulation system according to claim 1, characterized in that, The step of extracting 8 channels of floating-point data according to the protocol frame and splitting them into 8 independent digital signal streams based on a preset physical channel mapping relationship specifically includes: At the moment the trigger pulse is emitted, extract 8 channels of 32-bit floating-point data from the payload of the protocol frame; According to the preset mapping relationship between physical channels and data channel numbers, each floating-point data is assigned to the corresponding output channel; Perform protocol conversion on each data stream separately to generate an independent digital signal stream; The eight digital signal streams are synchronously output to the corresponding eight power amplifiers through a parallel interface.

7. A synchronous drive and control system for a multi-channel power amplifier for RTDS simulation systems, characterized in that, The system includes a memory and a processor. The memory includes a program for a multi-channel power amplifier synchronous drive and control method for an RTDS simulation system. When the processor executes the program for the multi-channel power amplifier synchronous drive and control method for an RTDS simulation system, it performs the following steps: The system receives the simulation data stream in real time, identifies the preset frame header, and then obtains the protocol frame. Extract the startup identifier from the protocol frame based on the preset startup command field; If the start identifier matches the preset start threshold, the timestamp of each data stream relative to the start time of the frame is obtained; The deviation value of each channel is obtained by comparing the timestamp of each channel with the preset frame synchronization time. Based on the deviation values ​​of each path and the preset synchronization threshold group, a global trigger pulse is generated after adjustment based on the preset time domain interpolation. In response to the global trigger pulse, the trigger interval jitter value is obtained based on the current system clock and the output trigger pulse time of the previous protocol frame; Based on the preset delay debouncing, the trigger interval jitter value is not less than the preset jitter threshold. After the global trigger pulse is issued, 8 channels of floating-point data are extracted according to the protocol frame, and then split into 8 independent digital signal streams based on the preset physical channel mapping relationship and output.

8. A multi-channel power amplifier synchronous drive and control system for RTDS simulation systems according to claim 7, characterized in that, The real-time received simulation data stream, after identifying the preset frame header, obtains the protocol frame, specifically including... The simulation data stream is received in real time via a full-duplex optical port using an Aurora protocol converter. Continuously monitor fixed frame headers in the data stream, and when a field matching a preset frame header is identified, lock the start position of the current frame; Based on the predefined frame structure, the length information and type identifier of the current frame are parsed to complete the initial verification of the frame's legality. The complete data frame that passes the verification is used as the protocol frame.

9. A multi-channel power amplifier synchronous drive and control system for RTDS simulation systems according to claim 7, characterized in that, The step of extracting the startup identifier from the protocol frame based on the preset startup command field specifically includes: The startup command field is read from the specified offset position of the protocol frame to obtain the startup identifier; The startup identifier is matched with a preset startup threshold, which is a baseline value for a valid startup command; If the startup identifier matches the startup threshold, then a match is determined. If the start flag does not match the start threshold, the current protocol frame is discarded and the system returns to receive the next frame.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium includes a program for a multi-channel power amplifier synchronous drive and control method for an RTDS simulation system. When the program is executed by a processor, it implements the steps of the multi-channel power amplifier synchronous drive and control method for an RTDS simulation system as described in any one of claims 1 to 6.

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