Server pcie bandwidth optimization method and system

Abstract

This invention provides a method and system for optimizing PCIe bandwidth in a transaction server. The method includes collecting memory access flows containing process identifiers, page addresses, access core identifiers, and timestamps; generating a heterogeneous latency topology mapping by combining latency data from the access core to the local DRAM node and the CXL region; matching functional weights with the current transaction stage and process identifier, and calculating a memory page urgency score by integrating access frequency, recent access timeliness, and access interval stability; constructing an association graph with pages as nodes and time window co-occurrence strength as edge weights; merging highly associated pages into atomic migration clusters and calculating a comprehensive urgency score; and dynamically determining a threshold based on the global score distribution and remaining DRAM capacity, deploying migration clusters exceeding the threshold to local DRAM nodes with lower weighted latency, and migrating the rest to the bandwidth-available CXL region, thereby optimizing PCIe bandwidth utilization.

Description

Technical Field

[0001] This application belongs to the field of servers, and in particular relates to a method and system for optimizing server PCIe bandwidth. Background Technology

[0002] The rapid development of fintech has placed high demands on the computing performance and real-time processing capabilities of quantitative trading systems. Within short trading cycles, quantitative trading processes generate intensive memory access flows, continuously putting pressure on server memory capacity, memory access latency, and data transfer bandwidth. Traditional local DRAM offers low access latency but has limited capacity and high expansion costs, making it difficult to fully handle the ever-growing large-scale market data, order book data, and strategy calculation data in quantitative trading scenarios. CXL memory pool technology based on the PCIe bus can provide servers with more flexible, large-capacity memory expansion capabilities by decoupling computing resources from memory resources. However, CXL memory pools typically require data access via PCIe links, resulting in higher access latency compared to local DRAM, and can easily consume limited PCIe bandwidth in high-concurrency memory access scenarios. For quantitative trading systems with high responsiveness requirements, if the storage location of data between local DRAM and the CXL area is not properly scheduled, critical data may be frequently accessed across PCIe links, increasing link load and causing long-tail latency, thus affecting the real-time responsiveness of the trading system. To alleviate PCIe bandwidth pressure and improve heterogeneous memory access performance, existing technologies typically employ a heterogeneous memory tiered scheduling approach based on hot and cold data separation. This approach generally relies on characteristics such as data access frequency, keeping high-frequency access data in local DRAM and migrating or placing low-frequency access data in the CXL region, aiming to leverage the complementary advantages of low latency in local DRAM and large capacity in the CXL region. However, existing scheduling schemes do not consider the co-occurrence access relationships of different pages within a time window, easily disrupting data locality and increasing the likelihood of repeated page migrations. Furthermore, traditional scheduling thresholds cannot adaptively adjust based on the global data urgency distribution and the real-time remaining capacity of local DRAM. Under the influence of these factors, existing methods struggle to promptly identify and schedule sets of pages with strong correlations, and some high-urgency data may still be placed in the CXL region, thus increasing PCIe link access pressure and impacting the memory access efficiency and overall performance of the quantitative trading server. Summary of the Invention

[0003] To address the problems in existing technologies that rely solely on access frequency to assess data hotness / coldness, lack page correlation identification, and have static thresholds that are difficult to adapt to changes in DRAM capacity, leading to PCIe bandwidth congestion and increased latency for critical data access, this invention proposes a server PCIe bandwidth optimization method and system.

[0004] In a first aspect, the present invention proposes a server PCIe bandwidth optimization method, comprising the following steps:

[0005] Obtain the memory access flow of the transaction, which includes process identifier, page address, access core identifier and timestamp; generate a heterogeneous latency topology mapping based on the latency data from each access core to the local DRAM node and the CXL region; and obtain the functional weight associated with the process identifier from the preset mapping according to the current transaction stage.

[0006] The data urgency score of each memory page is calculated by weighting the normalized access frequency, the reciprocal of the timestamp decay, the reciprocal of the standard deviation of the time interval, and the functional weight; an association graph is constructed, with the page address as the node and the co-occurrence intensity within the time window as the edge weight; nodes with edge weights exceeding a preset threshold are merged into atomic migration clusters, and the average value of the data urgency score corresponding to each page in the atomic migration cluster is extracted as the comprehensive urgency score.

[0007] A threshold is calculated based on the global score distribution formed by the data urgency scores of all memory pages and the remaining capacity of the local DRAM. If the overall urgency score of the atomic migration cluster exceeds the threshold, the atomic migration cluster is placed in the local DRAM node with the lowest weighted latency in the heterogeneous latency topology mapping according to the access core identifier corresponding to the page in the atomic migration cluster. Otherwise, the atomic migration cluster is placed in the CXL region with available bandwidth.

[0008] Optionally, the acquisition of the transaction's memory access stream, the memory access stream including a process identifier, page address, access kernel identifier, and timestamp, includes:

[0009] The monitoring program is attached to a specific system process through the operating system's performance event counting component, and memory access operations initiated by the specific system process are sampled and detected based on hardware performance counters.

[0010] The process identifier of the initiating process, the page address corresponding to the memory access operation, the currently executing access core identifier, and the microsecond-level timestamp recorded by the clock cycle register are read from the sampling record, synthesized into a memory access action record, and stored in the streaming data cache table according to the occurrence sequence.

[0011] Optionally, generating a heterogeneous latency topology mapping based on latency data from each access core to the local DRAM node and the CXL region includes:

[0012] The operating system allocates test memory pages to each local DRAM node and each CXL region, and each access core sends bypass cached memory read and write test commands to the test memory pages.

[0013] The number of round trip cycles of the memory read / write test instruction is obtained by reading the performance monitoring unit inside the processor, and then converted into a direct nanosecond-level access latency parameter by combining the processor clock frequency.

[0014] A two-dimensional relation matrix is ​​constructed using the access core identifier as the row identifier and the number of the local DRAM node or the CXL region as the column identifier. The converted nanosecond-level access latency parameter is then filled into the corresponding matrix elements to generate the heterogeneous latency topology mapping.

[0015] Optionally, obtaining the functional weight associated with the process identifier from a preset mapping based on the current transaction stage includes:

[0016] A static dictionary table of time intervals for trading phases and weights for trading functions is pre-constructed based on the operating hours of the trading system.

[0017] Obtain the current absolute timestamp of the system and combine it with the process identifier in the memory access stream. Compare the current absolute timestamp of the system with the static dictionary table to locate and determine the current transaction stage.

[0018] The floating-point transaction function weight value corresponding to the current transaction stage and the process identifier is retrieved from the static dictionary table and used as the function weight.

[0019] Optionally, the calculation of the data urgency score for each memory page, weighted by normalized access frequency, reciprocal of timestamp decay, reciprocal of the standard deviation of the time interval, and the functional weight, includes:

[0020] The number of sampled memory access records for the same page address within a fixed time window is counted, and the normalized access frequency is obtained by dividing the number of accesses by the total number of accesses within the fixed time window.

[0021] Extract the time difference between the current system time and the timestamp of the most recent access to the same page address, and take the reciprocal of the sum of the time difference and the first preset small constant as the reciprocal of the timestamp decay;

[0022] The square root of the variance is calculated based on the access time interval sequence of historical access records to obtain the standard deviation of the time interval. When the number of samples in the access time interval sequence is less than the preset number of samples, the reciprocal of the standard deviation of the time interval is set to the preset default value.

[0023] When the number of samples in the access time interval sequence is greater than or equal to the preset number of samples, the reciprocal of the sum of the time interval standard deviation and the second preset small constant is taken to obtain the reciprocal of the time interval standard deviation.

[0024] The normalized access frequency, the reciprocal of the timestamp decay, and the reciprocal of the standard deviation of the time interval are each dimensionless and multiplied by a preset coefficient, then summed and multiplied by the functional weight to obtain the data urgency score of each memory page.

[0025] Optionally, the construction of the association graph, wherein the association graph uses the page address as a node and the co-occurrence intensity within a time window as the edge weight, includes:

[0026] A time-series scan is performed along the memory access stream, using a sliding time window with a fixed width and a sliding step size smaller than the fixed width.

[0027] Within each sliding time window, different page addresses that are both within the same sliding time window are paired up and extracted as node pairs;

[0028] The cumulative frequency of each node pair appearing synchronously across all sliding time windows is counted, and the cumulative frequency is used as the edge weight of the corresponding node connection. The association graph is constructed using the page address as the node connection.

[0029] Optionally, the step of calculating the threshold based on the global score distribution formed by the data urgency scores of all memory pages and the remaining local DRAM capacity includes:

[0030] Arrange the data urgency scores of all memory pages in ascending order to form the global score distribution;

[0031] Obtain the remaining available capacity of the local DRAM node and divide it by the total capacity of the local DRAM node to obtain the local DRAM remaining capacity rate;

[0032] A target percentile is determined based on the remaining local DRAM capacity rate, wherein the target percentile decreases as the remaining local DRAM capacity rate increases and increases as the remaining local DRAM capacity rate decreases.

[0033] The data urgency score corresponding to the target percentile is extracted from the global score distribution and used as the threshold.

[0034] On the other hand, the present invention also proposes a server PCIe bandwidth optimization system, comprising the following modules:

[0035] The generation module is used to obtain the memory access flow of the transaction, which includes process identifier, page address, access core identifier and timestamp; generate heterogeneous latency topology mapping based on the latency data from each access core to the local DRAM node and the CXL region; and obtain the functional weight associated with the process identifier from the preset mapping according to the current transaction stage.

[0036] The calculation module is used to calculate the data urgency score of each memory page by weighting it with normalized access frequency, reciprocal timestamp decay, reciprocal standard deviation of time interval, and the function weight; construct an association graph, with the page address as the node and the co-occurrence intensity within the time window as the edge weight; merge nodes with edge weights exceeding a preset threshold into atomic migration clusters, and extract the average value of the data urgency score corresponding to each page in the atomic migration cluster as the comprehensive urgency score.

[0037] The placement module is used to calculate a threshold based on the global score distribution composed of the data urgency scores of all memory pages and the remaining capacity of the local DRAM. If the overall urgency score of the atomic migration cluster exceeds the threshold, the atomic migration cluster is placed in the local DRAM node with the lowest weighted latency in the heterogeneous latency topology mapping according to the access core identifier corresponding to the page in the atomic migration cluster. Otherwise, the atomic migration cluster is placed in the CXL region with available bandwidth.

[0038] Preferably, the memory access stream for obtaining the transaction includes a process identifier, a page address, an access kernel identifier, and a timestamp, including:

[0039] The monitoring program is attached to a specific system process through the operating system's performance event counting component, and memory access operations initiated by the specific system process are sampled and detected based on hardware performance counters.

[0040] The process identifier of the initiating process, the page address corresponding to the memory access operation, the currently executing access core identifier, and the microsecond-level timestamp recorded by the clock cycle register are read from the sampling record, synthesized into a memory access action record, and stored in the streaming data cache table according to the occurrence sequence.

[0041] Preferably, the step of generating a heterogeneous latency topology mapping based on latency data from each access core to the local DRAM node and the CXL region includes:

[0042] The operating system allocates test memory pages to each local DRAM node and each CXL region, and each access core sends bypass cached memory read and write test commands to the test memory pages.

[0043] The number of round trip cycles of the memory read / write test instruction is obtained by reading the performance monitoring unit inside the processor, and then converted into a direct nanosecond-level access latency parameter by combining the processor clock frequency.

[0044] A two-dimensional relation matrix is ​​constructed using the access core identifier as the row identifier and the number of the local DRAM node or the CXL region as the column identifier. The converted nanosecond-level access latency parameter is then filled into the corresponding matrix elements to generate the heterogeneous latency topology mapping.

[0045] Preferably, obtaining the functional weight associated with the process identifier from a preset mapping based on the current transaction stage includes:

[0046] A static dictionary table of time intervals for trading phases and weights for trading functions is pre-constructed based on the operating hours of the trading system.

[0047] Obtain the current absolute timestamp of the system and combine it with the process identifier in the memory access stream. Compare the current absolute timestamp of the system with the static dictionary table to locate and determine the current transaction stage.

[0048] The floating-point transaction function weight value corresponding to the current transaction stage and the process identifier is retrieved from the static dictionary table and used as the function weight.

[0049] Preferably, the step of calculating the data urgency score for each memory page by weighting the normalized access frequency, the reciprocal of the timestamp decay, the reciprocal of the standard deviation of the time interval, and the functional weight includes:

[0050] The number of sampled memory access records for the same page address within a fixed time window is counted, and the normalized access frequency is obtained by dividing the number of accesses by the total number of accesses within the fixed time window.

[0051] Extract the time difference between the current system time and the timestamp of the most recent access to the same page address, and take the reciprocal of the sum of the time difference and the first preset small constant as the reciprocal of the timestamp decay;

[0052] The square root of the variance is calculated based on the access time interval sequence of historical access records to obtain the standard deviation of the time interval. When the number of samples in the access time interval sequence is less than the preset number of samples, the reciprocal of the standard deviation of the time interval is set to the preset default value.

[0053] When the number of samples in the access time interval sequence is greater than or equal to the preset number of samples, the reciprocal of the sum of the time interval standard deviation and the second preset small constant is taken to obtain the reciprocal of the time interval standard deviation.

[0054] The normalized access frequency, the reciprocal of the timestamp decay, and the reciprocal of the standard deviation of the time interval are each dimensionless and multiplied by a preset coefficient, then summed and multiplied by the functional weight to obtain the data urgency score of each memory page.

[0055] Preferably, the construction of the association graph, wherein the association graph uses the page address as a node and the co-occurrence strength within a time window as the edge weight, includes:

[0056] A time-series scan is performed along the memory access stream, using a sliding time window with a fixed width and a sliding step size smaller than the fixed width.

[0057] Within each sliding time window, different page addresses that are both within the same sliding time window are paired up and extracted as node pairs;

[0058] The cumulative frequency of each node pair appearing synchronously across all sliding time windows is counted, and the cumulative frequency is used as the edge weight of the corresponding node connection. The association graph is constructed using the page address as the node connection.

[0059] Preferably, the step of calculating the threshold based on the global score distribution formed by the data urgency scores of all memory pages and the remaining local DRAM capacity includes:

[0060] Arrange the data urgency scores of all memory pages in ascending order to form the global score distribution;

[0061] Obtain the remaining available capacity of the local DRAM node and divide it by the total capacity of the local DRAM node to obtain the local DRAM remaining capacity rate;

[0062] A target percentile is determined based on the remaining local DRAM capacity rate, wherein the target percentile decreases as the remaining local DRAM capacity rate increases and increases as the remaining local DRAM capacity rate decreases.

[0063] The data urgency score corresponding to the target percentile is extracted from the global score distribution and used as the threshold.

[0064] This invention collects memory access flows from a quantitative trading server and combines them with heterogeneous latency topology mapping to determine the actual memory access costs from different access cores to local DRAM nodes and CXL regions. It introduces functional weights corresponding to the current trading stage to enhance the identification of core trading processes and critical business data. Based on this, it integrates features such as access frequency, recent access timeliness, and access interval stability to calculate the data urgency score of each memory page. A page association graph is constructed based on the co-occurrence strength of time windows, merging highly associated pages into atomic migration clusters to maintain data locality and reduce scattered page migration overhead. A judgment threshold is dynamically set based on the global score distribution and the remaining capacity of local DRAM, placing high-urgency atomic migration clusters on local DRAM nodes with lower weighted latency, and guiding other data to CXL regions with available bandwidth. This alleviates PCIe bandwidth pressure, reduces memory access latency for critical trading data, and improves the overall system operating efficiency. Attached Figure Description

[0065] Figure 1 A flowchart of the first embodiment;

[0066] Figure 2 This is a schematic diagram of a heterogeneous memory access latency topology.

[0067] Figure 3 This is a schematic diagram of the co-occurrence frequency distribution of spatially local node pairs. Detailed Implementation

[0068] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0069] In the first embodiment, the present invention proposes a server PCIe bandwidth optimization method, such as... Figure 1 As shown, it includes the following steps:

[0070] S1, obtain the memory access flow of the transaction, the memory access flow includes process identifier, page address, access core identifier and timestamp; generate heterogeneous latency topology mapping based on the latency data from each access core to the local DRAM node and CXL region; obtain the functional weight associated with the process identifier from the preset mapping according to the current transaction stage.

[0071] By mounting an eBPF probe in the Linux operating system kernel or using the Intel processor performance monitoring unit mechanism to monitor cache miss events, the memory access flow of the quantitative trading program in the system is collected. The extracted process identifier, page address, access core identifier, and timestamp are stored in a circular buffer for user-space reading. System micro-benchmarking tools, such as the Intel memory latency testing tool, are used to extract memory access latency data from each access core to each local DRAM node and CXL region under the non-uniform memory access architecture. A two-dimensional adjacency matrix data structure is constructed to generate a heterogeneous latency topology mapping, where row indices correspond to access core identifiers, column indices correspond to storage node identifiers, and matrix elements are measured latency values. A preset mapping table configured in a JSON format file is read, and the system's trading phase state variables, such as the call auction phase or continuous auction phase, are monitored. The current trading phase and process identifier are combined as a key-value pair to look up the corresponding function weight floating-point number in an unordered mapping hash table.

[0072] In an optional embodiment, the acquisition of the transaction's memory access stream, the memory access stream including a process identifier, page address, access core identifier, and timestamp, includes:

[0073] The monitoring program is attached to a specific system process through the operating system's performance event counting component, and memory access operations initiated by the specific system process are sampled and detected based on hardware performance counters.

[0074] The process identifier of the initiating process, the page address corresponding to the memory access operation, the currently executing access core identifier, and the microsecond-level timestamp recorded by the clock cycle register are read from the sampling record, synthesized into a memory access action record, and stored in the streaming data cache table according to the occurrence sequence.

[0075] By utilizing the `perf_event_open` system call in the Linux operating system, the monitoring program is mounted as a kernel module or eBPF program to the market data receiving process of the quantitative trading system, such as PID=4502, or the strategy calculation process, such as PID=4503. By configuring the processor's built-in hardware performance counters, for example, setting the event type to a specific memory read / write event, and using a fixed sampling frequency, preferably between 1000 and 10000 times per second (example value uses a sampling frequency of 2000Hz), memory access operations triggered by this specific system process are detected. This method reduces the system performance overhead of full tracking and ensures that the detected memory access event stream is representative.

[0076] When a sampling interrupt is triggered, four key data variables are read and extracted from the processor's register context: the process identifier that initiated the memory access operation is obtained through the task_struct structure, for example, PID 4503 is extracted; the page address corresponding to the cache miss caused by the memory access is extracted by consulting the page table translation directory, for example, memory offset 0x1A2B3000; the core identifier of the currently executing instruction is read through the CPUID instruction or system scheduler context, for example, CoreID=5; the processor's internal TSC timestamp counter is read and divided by the processor's operating frequency to convert it into a microsecond-level timestamp.

[0077] After extracting the above data, these four key data variables are packaged and encapsulated into a memory access action record in the form of a fixed memory-aligned length, such as a 24-byte C language structure. Data consistency is ensured using memory barrier instructions. This record is then continuously pushed into a pre-allocated 64MB streaming data buffer in chronological order through a lock-free circular buffer, providing a high-concurrency, low-latency data input source for subsequent correlation graph analysis and page urgency scoring.

[0078] In an optional embodiment, generating a heterogeneous latency topology map based on latency data from each access core to the local DRAM node and the CXL region includes:

[0079] The operating system allocates test memory pages to each local DRAM node and each CXL region, and each access core sends bypass cached memory read and write test commands to the test memory pages.

[0080] The number of round trip cycles of the memory read / write test instruction is obtained by reading the performance monitoring unit inside the processor, and then converted into a direct nanosecond-level access latency parameter by combining the processor clock frequency.

[0081] A two-dimensional relation matrix is ​​constructed using the access core identifier as the row identifier and the number of the local DRAM node or the CXL region as the column identifier. The converted nanosecond-level access latency parameter is then filled into the corresponding matrix elements to generate the heterogeneous latency topology mapping.

[0082] Through the non-uniform memory access management interface, test memory pages of 4KB size with page swapping disabled are explicitly allocated in each local DRAM node configured on the current motherboard (e.g., NUMA nodes 0 and 1) and each CXL memory region connected via the PCIe 5.0 bus (e.g., CXL nodes 2 and 3). A core-binding strategy is employed, causing all cores in the system (e.g., Core 0 to Core 31) to run probe threads. Within each probe thread, each access core uses non-sequential memory instructions to send memory read / write test instructions bypassing various levels of CPU cache to these test memory pages, ensuring that the measured results reflect the response latency of the underlying media and bus transmission. To calculate errors caused by occasional bus congestion, a single read / write test operation for each test page is executed a preset number of times, preferably between 100 and 1000 times; an example value is 500 cycles.

[0083] When acquiring and calculating latency data, memory barrier instructions and timestamp counter instructions are inserted before and after each memory read / write test instruction, respectively. The number of round-trip CPU clock cycles consumed from the issuance of the read / write instruction to the return of data is intercepted from the performance monitoring unit inside the processor, and the arithmetic average of the number of cycles from 500 tests is calculated. This average number of cycles is divided by the processor's operating frequency, for example, a frequency of 2.5 GHz, which is 0.4 nanoseconds per clock cycle, to convert it into direct access latency parameters. For example, the calculated latency from Core0 to local DRAM node 0 is 85.4 nanoseconds, while the latency to CXL node 2 increases to 210.6 nanoseconds.

[0084] Instantiate a static data structure mapping table in the system memory, configure the extracted access core identifiers such as 0 to 31 as the row identifier index of the matrix, configure the logical numbers of local DRAM nodes such as number 0 and 1 and CXL regions such as number 2 and 3 as the column identifier index of the matrix, and open a two-dimensional relation matrix with a dimension of 32 rows and 4 columns in memory. Fill the access delay parameters obtained from the previous conversion into the matrix elements of the corresponding coordinates in turn, for example, assign the value of 205.5 to the matrix element DelayMatrix[5][2]. This two-dimensional matrix constitutes the heterogeneous delay topology mapping table, which allows the system to query the path with lower weighted delay in O(1) time complexity when making atomic migration cluster layout decisions. The heterogeneous memory access delay topology is as follows: Figure 2 As shown.

[0085] In an optional embodiment, obtaining the functional weight associated with the process identifier from a preset mapping based on the current transaction stage includes:

[0086] A static dictionary table of time intervals for trading phases and weights for trading functions is pre-constructed based on the operating hours of the trading system.

[0087] Obtain the current absolute timestamp of the system and combine it with the process identifier in the memory access stream. Compare the current absolute timestamp of the system with the static dictionary table to locate and determine the current transaction stage.

[0088] The floating-point transaction function weight value corresponding to the current transaction stage and the process identifier is retrieved from the static dictionary table and used as the function weight.

[0089] A static dictionary table based on a hash table or B+ tree structure is pre-built in memory. This static dictionary table uses a composite primary key consisting of "trading phase time intervals, such as Unix timestamp start and end intervals or 09:30:00-11:30:00" combined with "specific quantification process identifiers, such as process PID or business alias," and assigns a corresponding preset floating-point trading function weight value as the value of this primary key. For example, the rule can be set as follows: during the opening call auction period from 09:15:00 to 09:25:00, the trading function weight of the process handling market data reception, such as PID4001, is set to a higher priority of 3.0; while during the same call auction period, the trading function weight of the offline process responsible for after-hours data analysis, such as PID4005, is set to 0.2. The preferred range for this floating-point weight setting is generally between 0.1 and 5.0, used to quantify the business importance of each business process in occupying high-speed DRAM memory bandwidth within a specific time period.

[0090] During the system's decision-making phase, the management daemon process retrieves the system's current absolute timestamp by calling the operating system kernel's clock interface, such as the `clock_gettime` function in Linux. This timestamp is then formatted into standard hour, minute, and second values ​​for the current day, e.g., resolving the current time to 09:35:12 AM. The process identifier initiating the memory access flow is extracted from the packet header information of the currently analyzed memory access flow, such as PID 4001. An interval comparison engine is used to perform interval overlap comparisons between the formatted system's current absolute timestamp and the upper and lower boundaries of all trading phase time intervals registered in the static dictionary table. This allows the system to pinpoint and determine the specific trading phase it is currently in, e.g., matching it to the continuous auction morning session.

[0091] A unique query string is generated by combining "continuous auction morning phase" with "process PID 4001". A lookup call with a time complexity of O(1) is initiated to the static dictionary table in memory. The pre-configured floating-point trading function weight value is extracted from the matched table record. For example, the query result is the extracted value 2.5. After extraction, the floating-point value is output as the function weight parameter. This function weight will be used as a multiplier factor in the mathematical formula for the urgency score of data on subsequent pages, so that memory resources are preferentially allocated to the quantitative trading process that is currently in the critical business cycle.

[0092] S2, calculate the data urgency score for each memory page by weighting the normalized access frequency, the reciprocal of the timestamp decay, the reciprocal of the standard deviation of the time interval, and the functional weight; construct an association graph, with the page address as the node and the co-occurrence intensity within the time window as the edge weight; merge nodes with edge weights exceeding a preset threshold into atomic migration clusters, and extract the average value of the data urgency score corresponding to each page in the atomic migration cluster as the comprehensive urgency score.

[0093] The normalized access frequency is obtained by using a sliding window algorithm to count the total number of times a page address appears within a preset time window and dividing by the total number of accesses. The time difference between the current system time and the timestamp of the most recent access to the same page address is extracted, and the reciprocal of the sum of this time difference and a preset constant is taken to obtain the reciprocal of the timestamp decay. The variance of the time difference between two adjacent accesses is calculated and its square root is taken to obtain the standard deviation of the time interval. The reciprocal of the sum of this standard deviation and a preset constant is taken to obtain the reciprocal of the standard deviation of the time interval. Then, the normalized access frequency is multiplied by a first weighting coefficient, the reciprocal of the timestamp decay is multiplied by a second weighting coefficient, and the reciprocal of the standard deviation of the time interval is multiplied by a third weighting coefficient. These three products are then added together to obtain a basic urgency score. Finally, this basic urgency score is multiplied by the functional weight to obtain the data urgency score for each memory page.

[0094] An undirected graph object is instantiated to construct an association graph. Page addresses that have appeared are added as vertices. The Apriori algorithm in association rule mining is used to count the co-occurrence frequency of any two consecutively visited pages within a time window, and this co-occurrence frequency is added as edge weights to the undirected graph object. Using either the connected component algorithm or the Louvain community detection algorithm from graph theory, all edges in the undirected graph object are traversed. If the edge weight value is greater than a preset floating-point threshold, the two page nodes connected by this edge are grouped into the same set, forming an atomic migration cluster. All page nodes in the atomic migration cluster are traversed, and the urgency scores of the page nodes are accumulated and divided by the total number of nodes to obtain the arithmetic mean, which is used as the overall urgency score of the atomic migration cluster.

[0095] In an optional embodiment, the calculation of the data urgency score for each memory page, weighted by normalized access frequency, reciprocal of timestamp decay, reciprocal of the standard deviation of the time interval, and the function weight, includes:

[0096] The number of sampled memory access records for the same page address within a fixed time window is counted, and the normalized access frequency is obtained by dividing the number of accesses by the total number of accesses within the fixed time window.

[0097] Extract the time difference between the current system time and the timestamp of the most recent access to the same page address, and take the reciprocal of the sum of the time difference and the first preset small constant as the reciprocal of the timestamp decay;

[0098] The square root of the variance is calculated based on the access time interval sequence of historical access records to obtain the standard deviation of the time interval. When the number of samples in the access time interval sequence is less than the preset number of samples, the reciprocal of the standard deviation of the time interval is set to the preset default value.

[0099] When the number of samples in the access time interval sequence is greater than or equal to the preset number of samples, the reciprocal of the sum of the time interval standard deviation and the second preset small constant is taken to obtain the reciprocal of the time interval standard deviation.

[0100] The normalized access frequency, the reciprocal of the timestamp decay, and the reciprocal of the standard deviation of the time interval are each dimensionless and multiplied by a preset coefficient, then summed and multiplied by the functional weight to obtain the data urgency score of each memory page.

[0101] When extracting the timing access characteristic parameters of each memory page, a time-series-driven sliding profiler is maintained, and a fixed time window is set. The preferred width of this fixed time window is between 10 milliseconds and 500 milliseconds, for example, set to 100 milliseconds. Within the evaluation period of a specific memory page, the stream data cache table records within the 100-millisecond time window are traversed, and the cumulative frequency of sampled memory access records occurring at a specific page address, such as the page with offset 0x1A2B3000, is counted, for example, 150 times. This frequency is divided by the total number of accesses to all memory pages recorded by the system within the same 100-millisecond fixed time window, for example, 10,000 times, to calculate a floating-point normalized access frequency variable between 0 and 1. For the same specific page, extract the time difference between the current system time and the microsecond-level timestamp of the page's most recent access. Take the reciprocal of the sum of the time difference and a first preset micro constant to obtain the timestamp decay variable representing the timeliness of the most recent access. The larger this value is, the closer the most recent access to the page is to the current time.

[0102] Extract the time intervals of the N most recent consecutive accesses to the page to form a floating-point data sequence. Preferably, N is an integer between 20 and 100, for example, N=50. Calculate the mean of these 50 time interval sequences and obtain the variance. Take the square root of the variance to obtain the standard deviation of the time intervals; for example, the standard deviation is calculated to be 25.0 microseconds. When the number of available access time interval samples is insufficient, the reciprocal of the standard deviation is set to a preset default value. When the sample size is sufficient, the reciprocal of the sum of this standard deviation and a second preset small constant is used as the reciprocal of the standard deviation representing the stability of the memory page access frequency. A higher value indicates a more regular access rhythm. To reduce the order-of-magnitude differences between these three characteristic indicators with different meanings, a maximum-minimum normalization algorithm is used to map and compress the normalized access frequency, timestamp decay reciprocal, and time interval standard deviation into a purely dimensionless range of 0.0 to 1.0.

[0103] After unifying the dimensions, fixed-proportion preset weight coefficients are assigned to each of the three features. A preferred coefficient combination is: access frequency coefficient of 0.4, attenuation reciprocal coefficient of 0.4, and standard deviation reciprocal coefficient of 0.2, summing to 1.0. The dimensionless feature values ​​are multiplied one by one with their corresponding preset coefficients, and the three products are linearly added together to obtain the basic urgency score for that specific page; for example, a result of 0.66. The functional weight variable of the process to which the page belongs in the current transaction stage is extracted; for example, if the previously obtained weight value is 2.5, the obtained basic urgency score is multiplied by this functional weight using a floating-point operation. The resulting product, 1.65, is the data urgency score for that memory page. This score is the evaluation criterion for determining whether the page meets the conditions for migration to high-speed local DRAM.

[0104] In an optional embodiment, the construction of the association graph, which uses the page address as a node and the co-occurrence strength within a time window as the edge weight, includes:

[0105] A time-series scan is performed along the memory access stream, using a sliding time window with a fixed width and a sliding step size smaller than the fixed width.

[0106] Within each sliding time window, different page addresses that are both within the same sliding time window are paired up and extracted as node pairs;

[0107] The cumulative frequency of each node pair appearing synchronously across all sliding time windows is counted, and the cumulative frequency is used as the edge weight of the corresponding node connection. The association graph is constructed using the page address as the node connection.

[0108] Establish an event-stream-based time-series analysis engine. Along the time-series dimension of continuously generated memory access flows, initialize a sliding time window processing mechanism for batch data truncation. In terms of parameter settings, configure a sliding time window with a fixed width, preferably between 5 and 50 milliseconds (e.g., 10 milliseconds). Set a sliding step size variable, numerically smaller than the fixed width, preferably between 1 and 10 milliseconds (e.g., 2 milliseconds). The engine performs overlapping and interleaved sequential scanning operations on the global timeline at 2-millisecond increments. This wide-window, short-step overlapping scanning mechanism reduces the probability of truncation at time window boundaries, ensuring that complex data structures accessed concurrently by quantization strategies at critical time points are completely detected within the same window. Each time the sliding time window advances one step, the engine extracts the independent page address set corresponding to all access behaviors recorded within that time window (e.g., within those 10 milliseconds).

[0109] When processing each extracted single-step sliding time window, duplicate page addresses within the same time window are removed. Assuming page A, page B, and page C are extracted within a window, pairwise combination logic is executed to generate and pair them, extracting and encapsulating them into undirected node pairs, such as [A,B], [A,C], and [B,C]. A globally shared two-dimensional hash table structure is initialized in a pre-allocated memory page for global frequency counting. All sliding time windows generated within an analysis cycle (e.g., 1 second) are traversed, and the total cumulative frequency of each specific node pair appearing synchronously in these hundreds or even thousands of overlapping sliding time windows is calculated by looking up the table and accumulating the results. For example, if the node pair [A,B] is found to have been accessed 320 times simultaneously within a total of 500 time windows, then the cumulative frequency variable for the node pair [A,B] is recorded as the integer 320.

[0110] A standard undirected graph data structure is instantiated, and all unique page addresses detected during the analysis period are registered as vertices of the graph. Undirected connections are instantiated between node pairs that demonstrate non-zero co-occurrence relationships. The cumulative frequency integer value obtained from the global hash table for the corresponding node pairs, such as 320 mentioned above, is assigned and solidified as the edge weight attribute of the undirected connection. Thus, using the page addresses as nodes and the concurrent access frequency as the connection weight, a relational graph quantifying the system's memory layout is constructed in memory. This graph, with its graph-theoretic structure, reveals the data binding and spatial locality relationships of originally discrete pages in the transaction model calculation. The co-occurrence frequency distribution of spatially local node pairs is as follows: Figure 3 As shown.

[0111] S3. Calculate a threshold based on the global score distribution formed by the data urgency scores of all memory pages and the remaining capacity of the local DRAM. If the overall urgency score of the atomic migration cluster exceeds the threshold, then place the atomic migration cluster in the local DRAM node with the lowest weighted latency in the heterogeneous latency topology mapping according to the access core identifier corresponding to the page within the atomic migration cluster; otherwise, place the atomic migration cluster in the CXL region with available bandwidth.

[0112] Calculate the urgency scores of all page data and sort them in ascending order to form a global score distribution. Obtain the remaining available capacity of the local DRAM node by reading the Linux system node memory information interface file and divide it by the total capacity to obtain the local DRAM remaining capacity rate. Determine the target percentile based on the local DRAM remaining capacity rate; lower the target percentile when the local DRAM remaining capacity rate is high and raise it when the local DRAM remaining capacity rate is low. Extract the data urgency score value corresponding to the target percentile from the global score distribution as a threshold. Compare the overall urgency score of the atomic migration cluster with the calculated threshold. If the overall urgency score is greater than the threshold, extract the access core identifier corresponding to all pages in the atomic migration cluster in the historical record, and calculate the access frequency percentage of each access core identifier as the access weight. Traverse each local DRAM node column in the heterogeneous latency topology mapping adjacency matrix, multiply the access weight of each access core identifier by the latency data from the corresponding access core to the local DRAM node, and sum them to obtain the weighted latency for each local DRAM node. The local DRAM node with the lowest weighted latency value is selected, and the pages in the atomic migration cluster are migrated to this local DRAM node by calling the memory migration system call interface provided by the operating system, such as the function move_pages. If the overall urgency score is less than or equal to the threshold, the bandwidth remaining status of each CXL region is determined by querying the PCIe bandwidth monitoring register. CXL regions with bandwidth utilization below 80% are selected, and the atomic migration cluster is moved to the selected CXL region using the same data migration system call. If there are no CXL regions with bandwidth utilization below the preset threshold, the current position of the atomic migration cluster is kept unchanged, or it is added to the delay migration queue for re-determination in subsequent update cycles to alleviate local DRAM space pressure.

[0113] In an optional embodiment, the step of calculating the threshold based on the global score distribution formed by the data urgency scores of all memory pages and the remaining local DRAM capacity includes:

[0114] Arrange the data urgency scores of all memory pages in ascending order to form the global score distribution;

[0115] Obtain the remaining available capacity of the local DRAM node and divide it by the total capacity of the local DRAM node to obtain the local DRAM remaining capacity rate;

[0116] A target percentile is determined based on the remaining local DRAM capacity rate, wherein the target percentile decreases as the remaining local DRAM capacity rate increases and increases as the remaining local DRAM capacity rate decreases.

[0117] The data urgency score corresponding to the target percentile is extracted from the global score distribution and used as the threshold.

[0118] When the set update cycle is triggered, for example, every 100 milliseconds, memory pages in active monitoring status are retrieved from the system kernel's score maintenance table. For example, the data urgency scores of a total of 100,000 4KB pages are extracted. Using a quicksort algorithm with O(NlogN) time complexity, the one-dimensional floating-point score data is queued and sorted in ascending order to form a global score distribution consisting of the data urgency scores of all memory pages.

[0119] By calling the operating system's memory management interface, such as reading the node file / sys / devices / system / node / node0 / meminfo in the Linux system's sysfs directory, the remaining available capacity bytes of a specific low-latency local DRAM node used for optimization can be obtained in real time. For example, the number of bytes of unallocated capacity currently occupied by the local NUMA node 0 can be obtained, for example, if the remaining space is 16GB. This remaining capacity byte number is divided by the total capacity byte number of the local DRAM node's hardwired connections on the motherboard, for example, if the slots are fully filled with a total of 128GB, a floating-point local DRAM remaining capacity rate is calculated, which is always in the range of 0.0 to 1.0. For example, if the calculated value is 0.125.

[0120] The minimum and maximum target percentiles can be preset, for example, the minimum target percentile is the 70th percentile and the maximum target percentile is the 95th percentile. A linear mapping is performed between the two according to the local DRAM remaining capacity rate, so that the higher the local DRAM remaining capacity rate, the closer the target percentile is to the minimum target percentile; the lower the local DRAM remaining capacity rate, the closer the target percentile is to the maximum target percentile.

[0121] The data urgency score corresponding to the target percentile is extracted from the global score distribution and used as the threshold for constraining atomic migration clusters to enter local DRAM within the current update cycle. This calculation logic can generate capacity feedback at runtime: when local DRAM space is abundant, the target percentile decreases, and the threshold decreases relatively, thereby allowing more high-urgency atomic migration clusters to enter local DRAM; when local DRAM space is scarce, the target percentile increases, and the threshold increases relatively, thereby raising the local DRAM entry threshold and reducing the use of low-latency memory resources by minor atomic migration clusters.

[0122] In a second embodiment, the present invention also proposes a server PCIe bandwidth optimization system, comprising the following modules:

[0123] The generation module is used to obtain the memory access flow of the transaction, which includes process identifier, page address, access core identifier and timestamp; generate heterogeneous latency topology mapping based on the latency data from each access core to the local DRAM node and the CXL region; and obtain the functional weight associated with the process identifier from the preset mapping according to the current transaction stage.

[0124] The calculation module is used to calculate the data urgency score of each memory page by weighting it with normalized access frequency, reciprocal timestamp decay, reciprocal standard deviation of time interval, and the function weight; construct an association graph, with the page address as the node and the co-occurrence intensity within the time window as the edge weight; merge nodes with edge weights exceeding a preset threshold into atomic migration clusters, and extract the average value of the data urgency score corresponding to each page in the atomic migration cluster as the comprehensive urgency score.

[0125] The placement module is used to calculate a threshold based on the global score distribution composed of the data urgency scores of all memory pages and the remaining capacity of the local DRAM. If the overall urgency score of the atomic migration cluster exceeds the threshold, the atomic migration cluster is placed in the local DRAM node with the lowest weighted latency in the heterogeneous latency topology mapping according to the access core identifier corresponding to the page in the atomic migration cluster. Otherwise, the atomic migration cluster is placed in the CXL region with available bandwidth.

[0126] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0127] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for optimizing server PCIe bandwidth, characterized in that, Includes the following steps: Obtain the memory access flow of the transaction, which includes process identifier, page address, access core identifier and timestamp; generate a heterogeneous latency topology mapping based on the latency data from each access core to the local DRAM node and the CXL region; and obtain the functional weight associated with the process identifier from the preset mapping according to the current transaction stage. The data urgency score of each memory page is calculated by weighting the normalized access frequency, the reciprocal of the timestamp decay, the reciprocal of the standard deviation of the time interval, and the aforementioned functional weights. Construct an association graph, wherein the association graph uses the page address as a node and the co-occurrence intensity within a time window as the edge weight; Nodes whose edge weights exceed a preset threshold are merged into atomic migration clusters, and the average value of the data urgency score corresponding to each page in the atomic migration cluster is extracted as the comprehensive urgency score. A threshold is calculated based on the global score distribution formed by the data urgency scores of all memory pages and the remaining capacity of the local DRAM. If the overall urgency score of the atomic migration cluster exceeds the threshold, the atomic migration cluster is placed in the local DRAM node with the lowest weighted latency in the heterogeneous latency topology mapping according to the access core identifier corresponding to the page in the atomic migration cluster. Otherwise, the atomic migration cluster is placed in the CXL region with available bandwidth.

2. The method according to claim 1, characterized in that, The memory access stream for obtaining the transaction includes a process identifier, a page address, an access kernel identifier, and a timestamp, including: The monitoring program is attached to a specific system process through the operating system's performance event counting component, and memory access operations initiated by the specific system process are sampled and detected based on hardware performance counters. The process identifier of the initiating process, the page address corresponding to the memory access operation, the currently executing access core identifier, and the microsecond-level timestamp recorded by the clock cycle register are read from the sampling record, synthesized into a memory access action record, and stored in the streaming data cache table according to the occurrence sequence.

3. The method according to claim 1, characterized in that, The generation of heterogeneous latency topology mapping based on latency data from each access core to the local DRAM node and the CXL region includes: The operating system allocates test memory pages to each local DRAM node and each CXL region, and each access core sends bypass cached memory read and write test commands to the test memory pages. The number of round trip cycles of the memory read / write test instruction is obtained by reading the performance monitoring unit inside the processor, and then converted into a direct nanosecond-level access latency parameter by combining the processor clock frequency. A two-dimensional relation matrix is ​​constructed using the access core identifier as the row identifier and the number of the local DRAM node or the CXL region as the column identifier. The converted nanosecond-level access latency parameter is then filled into the corresponding matrix elements to generate the heterogeneous latency topology mapping.

4. The method according to claim 1, characterized in that, The step of obtaining the functional weight associated with the process identifier from the preset mapping based on the current transaction stage includes: A static dictionary table of time intervals for trading phases and weights for trading functions is pre-constructed based on the operating hours of the trading system. Obtain the current absolute timestamp of the system and combine it with the process identifier in the memory access stream. Compare the current absolute timestamp of the system with the static dictionary table to locate and determine the current transaction stage. The floating-point transaction function weight value corresponding to the current transaction stage and the process identifier is retrieved from the static dictionary table and used as the function weight.

5. The method according to claim 2 or 4, characterized in that, The data urgency score for each memory page is calculated by weighting the normalized access frequency, the reciprocal of the timestamp decay, the reciprocal of the standard deviation of the time interval, and the functional weight, including: The number of sampled memory access records for the same page address within a fixed time window is counted, and the normalized access frequency is obtained by dividing the number of accesses by the total number of accesses within the fixed time window. Extract the time difference between the current system time and the timestamp of the most recent access to the same page address, and take the reciprocal of the sum of the time difference and the first preset small constant as the reciprocal of the timestamp decay; The square root of the variance is calculated based on the access time interval sequence of historical access records to obtain the standard deviation of the time interval. When the number of samples in the access time interval sequence is less than the preset number of samples, the reciprocal of the standard deviation of the time interval is set to the preset default value. When the number of samples in the access time interval sequence is greater than or equal to the preset number of samples, the reciprocal of the sum of the time interval standard deviation and the second preset small constant is taken to obtain the reciprocal of the time interval standard deviation. The normalized access frequency, the reciprocal of the timestamp decay, and the reciprocal of the standard deviation of the time interval are each dimensionless and multiplied by a preset coefficient, then summed and multiplied by the functional weight to obtain the data urgency score of each memory page.

6. The method according to claim 1, characterized in that, The construction of the association graph, wherein the association graph uses the page address as a node and the co-occurrence strength within a time window as the edge weight, includes: A time-series scan is performed along the memory access stream, using a sliding time window with a fixed width and a sliding step size smaller than the fixed width. Within each sliding time window, different page addresses that are both within the same sliding time window are paired up and extracted as node pairs; The cumulative frequency of each node pair appearing synchronously across all sliding time windows is counted, and the cumulative frequency is used as the edge weight of the corresponding node connection. The association graph is constructed using the page address as the node connection.

7. The method according to claim 1, characterized in that, The threshold calculation based on the global score distribution formed by the data urgency scores of all memory pages and the remaining local DRAM capacity includes: Arrange the data urgency scores of all memory pages in ascending order to form the global score distribution; Obtain the remaining available capacity of the local DRAM node and divide it by the total capacity of the local DRAM node to obtain the local DRAM remaining capacity rate; A target percentile is determined based on the remaining local DRAM capacity rate, wherein the target percentile decreases as the remaining local DRAM capacity rate increases and increases as the remaining local DRAM capacity rate decreases. The data urgency score corresponding to the target percentile is extracted from the global score distribution and used as the threshold.

8. A server PCIe bandwidth optimization system, characterized in that, Includes the following modules: The generation module is used to obtain the memory access flow of the transaction, which includes process identifier, page address, access core identifier and timestamp; generate heterogeneous latency topology mapping based on the latency data from each access core to the local DRAM node and the CXL region; and obtain the functional weight associated with the process identifier from the preset mapping according to the current transaction stage. The calculation module is used to calculate the data urgency score of each memory page by weighting the normalized access frequency, the reciprocal of the timestamp decay, the reciprocal of the standard deviation of the time interval, and the functional weights. Construct an association graph, wherein the association graph uses the page address as a node and the co-occurrence intensity within a time window as the edge weight; Nodes whose edge weights exceed a preset threshold are merged into atomic migration clusters, and the average value of the data urgency score corresponding to each page in the atomic migration cluster is extracted as the comprehensive urgency score. The placement module is used to calculate a threshold based on the global score distribution composed of the data urgency scores of all memory pages and the remaining capacity of the local DRAM. If the overall urgency score of the atomic migration cluster exceeds the threshold, the atomic migration cluster is placed in the local DRAM node with the lowest weighted latency in the heterogeneous latency topology mapping according to the access core identifier corresponding to the page in the atomic migration cluster. Otherwise, the atomic migration cluster is placed in the CXL region with available bandwidth.

9. The system according to claim 8, characterized in that, The memory access stream for obtaining the transaction includes a process identifier, a page address, an access kernel identifier, and a timestamp, including: The monitoring program is attached to a specific system process through the operating system's performance event counting component, and memory access operations initiated by the specific system process are sampled and detected based on hardware performance counters. The process identifier of the initiating process, the page address corresponding to the memory access operation, the currently executing access core identifier, and the microsecond-level timestamp recorded by the clock cycle register are read from the sampling record, synthesized into a memory access action record, and stored in the streaming data cache table according to the occurrence sequence.

10. The system according to claim 8, characterized in that, The generation of heterogeneous latency topology mapping based on latency data from each access core to the local DRAM node and the CXL region includes: The operating system allocates test memory pages to each local DRAM node and each CXL region, and each access core sends bypass cached memory read and write test commands to the test memory pages. The number of round trip cycles of the memory read / write test instruction is obtained by reading the performance monitoring unit inside the processor, and then converted into a direct nanosecond-level access latency parameter by combining the processor clock frequency. A two-dimensional relation matrix is ​​constructed using the access core identifier as the row identifier and the number of the local DRAM node or the CXL region as the column identifier. The converted nanosecond-level access latency parameter is then filled into the corresponding matrix elements to generate the heterogeneous latency topology mapping.

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