Method for a network-on-chip, system-on-chip, electronic device and program product

Abstract

A method, system-on-a-chip (SoC), electronic device, and program product for an on-chip network are provided. The method includes: in response to receiving a first signal, switching a first unit of the SoC from a first communication state to a second communication state, the first communication state indicating permission to forward communication messages between a second unit of the SoC and at least one third unit of the SoC, the second communication state indicating prohibition to forward communication messages between the second unit and at least one third unit, the first unit being connected to a communication interface of the second unit; acquiring a task processing state of at least one communication task, the at least one communication task being associated with the second unit; and in response to the task processing state satisfying a preset condition, switching the first unit from the second communication state back to the first communication state to resume forwarding communication messages between the second unit and at least one third unit. This improves communication quality.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate generally to the field of computers, and more particularly to methods for networks on a chip, systems on a chip, electronic devices, and computer program products. Background Technology

[0002] In a chip system (such as a system-on-a-chip), multiple interconnected units are often integrated. These units transmit communication messages through a bus or interconnection network to collaboratively complete data processing tasks. During system operation, when one unit malfunctions or requires maintenance, it is usually necessary to reset or isolate that unit without affecting the normal operation of other units.

[0003] However, the reset or isolated unit may still have incomplete communication message transmissions at that moment. How to safely stop and resume the forwarding of communication messages to the unit at the appropriate time without losing these messages or causing transmission deadlock or protocol errors is a problem that needs to be solved. Summary of the Invention

[0004] Some embodiments of this disclosure provide solutions for on-chip networks that are intended to at least partially address one or more of the problems described above and other potential problems.

[0005] In a first aspect of this disclosure, a method for an on-chip network is provided for a system-on-a-chip. The method includes: in response to receiving a first signal, switching a first unit of the system-on-a-chip from a first communication state to a second communication state, the first communication state indicating permission to forward communication messages between a second unit of the system-on-a-chip and at least one third unit of the system-on-a-chip, the second communication state indicating prohibition to forward communication messages between the second unit and at least one third unit, the first unit being independent of the second unit and connected to a communication interface of the second unit for controlling message transmission between the second unit and at least one third unit; acquiring a task processing state of at least one communication task, the at least one communication task being associated with the second unit; and in response to the task processing state of the at least one communication task satisfying a preset condition, switching the first unit from the second communication state back to the first communication state to resume forwarding communication messages between the second unit and at least one third unit.

[0006] In a second aspect of this disclosure, a system-on-a-chip (SoC) is provided. The SoC includes: a first switching module configured to switch a first unit of the SoC from a first communication state to a second communication state in response to receiving a first signal; the first communication state indicating permission to forward communication messages between a second unit of the SoC and at least one third unit of the SoC, and the second communication state indicating prohibition to forward communication messages between the second unit and at least one third unit; the first unit being independent of the second unit and connected to a communication interface of the second unit for controlling message transmission between the second unit and at least one third unit; an acquisition module configured to acquire the task processing status of at least one communication task, the at least one communication task being associated with the second unit; and a second switching module configured to switch the first unit from the second communication state back to the first communication state in response to the task processing status of at least one communication task satisfying a preset condition, thereby resuming the forwarding of communication messages between the second unit and at least one third unit.

[0007] In a third aspect of this disclosure, an electronic device is provided. The device includes at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor. When executed by the at least one processor, the instructions cause the device to perform the method of the first aspect.

[0008] In a fourth aspect of this disclosure, a computer program product is provided, which is tangibly stored in a computer storage medium and includes computer-executable instructions that, when executed by a device, cause the device to perform the method of the first aspect.

[0009] The embodiments of this disclosure can safely suspend and resume the forwarding of communication messages to the second unit at appropriate times by using a first unit set independently of the second unit. This clears and isolates the pending transmissions between the second unit and at least one third unit when the second unit is reset or isolated, reducing the risk of message loss, transmission deadlock or protocol errors, and preventing the abnormal state of the second unit from blocking the communication of other units.

[0010] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The above and other features, advantages, and aspects of the various embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1A schematic diagram of the architecture of a system-on-a-chip capable of implementing several embodiments of the present disclosure is shown; Figure 2 A flowchart illustrating an example process for a network-on-a-chip according to some embodiments of the present disclosure is shown; Figure 3 A schematic structural block diagram of an example scenario according to some embodiments of the present disclosure is shown; Figure 4 A schematic block diagram of a system-on-a-chip according to some embodiments of the present disclosure is shown; Figure 5 A schematic block diagram of an electronic device capable of implementing one or more embodiments of the present disclosure is shown. Detailed Implementation

[0012] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0013] It should be noted that the headings of any section / subsection provided in this disclosure are not limiting. This disclosure describes various embodiments throughout, and any type of embodiment may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0014] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0015] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and related provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing each embodiment of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0016] In this specification and implementation plan, any schemes involving the processing of personal information will be processed only under the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0017] To facilitate understanding of the embodiments described in this disclosure, some of the terminology used in this disclosure will be explained below. It should be understood that the following description is exemplary and is not intended to limit the scope of this disclosure.

[0018] As used in this disclosure, the term "System on Chip" (SoC) refers to a system that integrates multiple functional units onto a single chip, such as a processor core, memory controller, interconnect network, input / output interface, and dedicated hardware accelerator. The second unit and at least one third unit of this disclosure can be integrated into the same SoC.

[0019] As used in this disclosure, the term "first unit" refers to a unit independent of the second unit and connected to the communication interface of the second unit, used to control message transmission (communication) between the second unit and at least one third unit. The first unit may be implemented at least partially in hardware, for example, as a fence module and / or timeout module mounted on the communication interface.

[0020] As used in this disclosure, the term "second unit" refers to a unit whose communication message forwarding is controlled by the first unit and can be reset or isolated, such as a processing unit, storage device, or input / output device in a chip system.

[0021] The term "third unit" as used in this disclosure refers to a unit that transmits messages via the first unit and the second unit, and the number of such units may be at least one.

[0022] As used in this disclosure, the term "communication message" refers to information transmitted between units, which may include, for example, a communication request and response data corresponding to the communication request.

[0023] As used in this disclosure, the term "first communication state" means that the first unit allows communication between the second unit and at least one third unit, such as allowing the communication messages of the second unit to be forwarded to at least one third unit, or allowing the communication messages of at least one third unit to be forwarded to the second unit, etc.

[0024] As used in this disclosure, the term "second communication state" means that the first unit prohibits communication between the second unit and at least one third unit, such as prohibiting the forwarding of communication messages from the second unit to at least one third unit, or prohibiting the forwarding of communication messages from at least one third unit to the second unit, etc.

[0025] As used in this disclosure, the term "first signal" refers to a signal used to trigger a first unit to switch from a first communication state to a second communication state, which may be triggered, for example, based on a reset request for the second unit.

[0026] As used in this disclosure, the term "second signal" refers to a signal used to indicate that the second unit has completed its reset.

[0027] The term "communication task" as used in this disclosure refers to a task related to the second unit that involves the transmission of communication messages, such as an unfinished read task or write task.

[0028] The term "task processing status" as used in this disclosure refers to the progress or completion status of a communication task, which may include, for example, whether the task has been completed, the number of incomplete transactions, etc.

[0029] The term "preset condition" as used in this disclosure refers to the condition used to determine whether to switch the first unit from the second communication state to the first communication state, such as the completion of at least one communication task related to the second unit.

[0030] As used in this disclosure, the term "communication interface" refers to the interface through which the second unit transmits messages with at least one third unit, which may include a first communication interface and / or a second communication interface, etc.

[0031] As used in this disclosure, the term "first communication interface" refers to an interface used to send a communication request to at least one third unit in order to obtain response data corresponding to the communication request from at least one third unit.

[0032] As used in this disclosure, the term "second communication interface" refers to an interface for receiving communication requests from at least one third unit and returning response data corresponding to the communication requests to at least one third unit.

[0033] As used in this disclosure, the term "bus protocol" refers to a protocol that specifies the method of message transmission between units, such as the Advanced eXtensible Interface (AXI) protocol.

[0034] As used in this disclosure, the term "interconnection network" refers to a network that provides connectivity between multiple units and carries message transmission, such as a network on chip (NoC).

[0035] As used in this disclosure, the term "hardware unit" refers to a unit that is at least partially implemented in hardware and can be plugged into a communication interface as a separate module.

[0036] As used in this disclosure, the term "fence module" refers to a module located at the communication interface of the second unit for stopping the forwarding of communication requests from the second unit to at least one third unit during a second communication state, which may, for example, block new communication requests at transaction boundaries.

[0037] As used in this disclosure, the term "timeout module" refers to a module located at the communication interface of the second unit, used to intercept communication requests from at least one third unit during a second communication state, and capable of filling in response messages to at least one third unit.

[0038] As used in this disclosure, the term "response data" refers to data returned in response to a communication request.

[0039] As used in this disclosure, the term "response message" refers to a message sent by the timeout module to at least one third unit as a response to a communication request, which may include preset data.

[0040] As used in this disclosure, the term "preset data" refers to data used to indicate an abnormal response to a communication request, such as an error response or pre-set data (e.g., all zero data).

[0041] As used in this disclosure, the term "first instruction information" refers to information used to instruct the cessation of forwarding new communication messages between the second unit and at least one third unit; correspondingly, "second instruction information" refers to information used to instruct the permission to forward new communication messages between the second unit and at least one third unit.

[0042] As used in this disclosure, the term "reset" refers to an operation that restores a cell to its initial or predetermined state; correspondingly, "reset request" refers to information requesting a reset operation to be performed on the cell.

[0043] As used in this disclosure, the term "transaction boundary" refers to the moment or location in which the forwarding of communication messages can be stopped or resumed during message transmission without compromising the integrity of the initiated transaction.

[0044] As used in this disclosure, the term "master device" refers to a unit that actively initiates a communication request; correspondingly, "slave device" refers to a unit that passively receives a communication request and returns response data. The same unit may act as a master device only, a slave device only, or both.

[0045] As mentioned above, in a chip system, multiple units typically communicate via an interconnect network based on a bus protocol. When a unit is reset or fault-isolated, there may still be unfinished transactions between that unit and other units. Resetting the unit directly may result in the loss of unfinished transactions on the bus, data errors, or even a deadlock. Conversely, when a slave unit malfunctions and fails to respond promptly, the master unit may wait for an extended period, thus blocking communication between other units on the bus.

[0046] This disclosure provides a scheme for a network-on-a-chip (NAT). The scheme includes: in response to receiving a first signal, switching a first unit of the NAT from a first communication state to a second communication state, wherein the first communication state indicates permission to forward communication messages between a second unit of the NAT and at least one third unit of the NAT, and the second communication state indicates prohibition of forwarding communication messages between the second unit and at least one third unit; the first unit being independent of the second unit and connected to the communication interface of the second unit for controlling message transmission between the second unit and at least one third unit; acquiring the task processing state of at least one communication task, the at least one communication task being associated with the second unit; and in response to the task processing state of the at least one communication task satisfying a preset condition, switching the first unit from the second communication state back to the first communication state to resume forwarding communication messages between the second unit and at least one third unit.

[0047] Based on this approach, the embodiments of this disclosure can safely suspend and restore communication permissions for the second unit at appropriate times through an independently configured first unit. This clears and isolates pending transmissions between the second unit and at least one third unit when the second unit is reset or isolated, reducing the risk of message loss, transmission deadlock, or protocol errors, and preventing abnormal states of the second unit from blocking communication with other units.

[0048] The following section provides a detailed description of various example implementations of this scheme, with reference to the accompanying drawings.

[0049] The various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0050] Figure 1 A schematic diagram of an architecture 100 for a system-on-a-chip capable of implementing various embodiments of the present disclosure is shown. (See diagram for reference.) Figure 1 As shown, architecture 100 can be a schematic diagram of the architecture of system-on-chip 400, which may include, for example, units A1 (110), A2 (120), and A3 (130) that communicate with each other. Units A1 (110), A2 (120), and A3 (130) can communicate with each other via an interconnection network (e.g., interconnection network 140).

[0051] As an example, the system-on-a-chip 400 can be any type of chip system, multi-chip module, or any combination of the aforementioned. The system-on-a-chip 400 can integrate multiple communicating units. These units (such as units A1 (110), A2 (120), A3 (130), and the aforementioned units A4 (321), A5 (322), A6 (323), etc.) can include, but are not limited to: processor cores, graphics processors, digital signal processors, neural network processing units, memory controllers, memory units, caches, bus interface units, interconnect network interfaces, power management units, clock management units, input / output interface units, security processing units, and dedicated hardware accelerators. In some embodiments, the multiple units in the system-on-a-chip 400 transmit communication messages through internal buses (such as advanced microcontroller bus architecture buses, advanced scalable interface buses, etc.) and / or interconnect networks (such as on-chip networks, crossbar switch matrices, etc.) to collaboratively complete data processing tasks. Communication connections can be established between the multiple units, forming corresponding communication links. Communication connections can be implemented via wired methods (such as on-chip metal interconnects) or wireless methods (such as on-chip inductive coupling or capacitive coupling), and the embodiments of this disclosure are not limited in this respect. In the embodiments of this disclosure, any two units in the system-on-a-chip 400 can achieve signaling interaction, data sharing, and task collaboration through a communication connection between them. The system-on-a-chip 400 may also include an external communication interface for exchanging data with external devices (such as memory, peripherals, another chip system, or communication devices, etc.). In some embodiments, the system-on-a-chip 400 can support any type of computing scenario, including cloud computing, edge computing, terminal computing, or any combination of the foregoing. The system-on-a-chip 400 can be a standalone chip, a chipset composed of multiple chips, or a distributed chip system, or a chip platform that provides basic capabilities such as computing power services, data storage services, and model inference services.

[0052] It should be understood that the structure and function of the various elements in architecture 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure. For example, the embodiments described in this disclosure can also be applied to other system architectures that include more or fewer units.

[0053] The following description will continue with reference to the accompanying drawings, which will provide some exemplary embodiments of this disclosure.

[0054] Figure 2 A flowchart of an example process 200 for a network-on-a-chip according to some embodiments of the present disclosure is shown. Process 200 can be implemented in architecture 100 and, for example, can be used in system-on-a-chip 400. For ease of discussion, the following is combined with... Figure 1Process 200 is described. For example, the second unit, third unit, etc., mentioned below can be... Figure 1 Any unit from unit A1 (110), unit A2 (120), and unit A3 (130) in the dataset.

[0055] In block 210, in response to receiving a first signal, the system-on-chip 400 switches a first unit of the system-on-chip from a first communication state to a second communication state. The first communication state indicates that forwarding of communication messages is permitted between the second unit of the system-on-chip and at least one third unit of the system-on-chip, and the second communication state indicates that forwarding of communication messages is prohibited between the second unit and at least one third unit. The first unit is independent of the second unit and is connected to the communication interface of the second unit for controlling message transmission between the second unit and at least one third unit.

[0056] As an example, when the second unit is the message sender, the first communication state may indicate that the communication message of the second unit is allowed to be forwarded to at least one third unit, while the second communication state may indicate that the communication message of the second unit is prohibited from being forwarded to at least one third unit. When the second unit is the message receiver, the first communication state may indicate that the communication message of at least one third unit is allowed to be forwarded to the second unit, while the second communication state may indicate that the communication message of at least one third unit is prohibited from being forwarded to the second unit.

[0057] In some implementations, the first signal may be triggered based on a reset request to the second unit. As an example, the second unit may trigger such a first signal when a reset is required. As an example, such a reset request may have various sources, such as being automatically triggered by firmware, triggered by related hardware logic, etc.

[0058] In block 220, the on-chip system 400 acquires the task processing status of at least one communication task, which is related to the second unit. For example, the at least one communication task may be an unfinished read or write task between the second unit and the third unit.

[0059] In block 230, in response to the task processing state of at least one communication task satisfying a preset condition, the on-chip system 400 switches the first unit from the second communication state to the first communication state to resume forwarding communication messages between the second unit and at least one third unit. For example, when at least one communication task related to the second unit has been completed, the task processing state can be considered to satisfy the preset condition.

[0060] In some embodiments, the system-on-chip 400 may output a first indication message in response to the first unit switching to a second communication state, the first indication message indicating that the forwarding of new communication messages between the second unit and at least one third unit should be stopped; and in response to the task processing state of at least one communication task meeting a preset condition, the system-on-chip 400 may output a second indication message, the second indication message indicating that the forwarding of new communication messages between the second unit and at least one third unit should be allowed.

[0061] For example, the first indication information and the second indication information can be implemented as a stop confirmation signal and an exit confirmation signal, respectively. In this way, the system-on-chip 400 can explicitly indicate to external logic whether forwarding communication messages is currently allowed, thereby facilitating the coordination of the reset process for the second unit and improving the controllability and reliability of the reset process.

[0062] In some embodiments, the first signal may be triggered based on a reset request for the second unit, and the second unit is reset while the first unit is in a second communication state. In this way, some embodiments of the present disclosure enable the reset operation of the second unit to be performed after the first unit stops forwarding communication messages between the second unit and at least one third unit, thereby avoiding interference between the reset process and ongoing message transmission and improving the security of the reset.

[0063] In some embodiments, switching the first unit from the second communication state to the first communication state may include: triggering a reset of the second unit in response to the task processing state of at least one communication task meeting a preset condition; and switching the first unit from the second communication state to the first communication state in response to the second unit completing the reset. In this way, some embodiments of this disclosure can ensure that the forwarding of communication messages is only resumed after the second unit has completed the reset and is ready, avoiding transmission errors caused by resuming forwarding before the second unit is ready, and further improving the reliability of the reset process.

[0064] In this way, the system-on-chip 400 can safely stop and resume the forwarding of communication messages to the second unit at an appropriate time when the second unit is reset or isolated, thereby clearing the pending transactions between the second and third units and reducing the risk of message loss, transmission deadlock, or protocol errors. Furthermore, since the first unit operates independently of the second unit, its control over the forwarding of communication messages does not depend on the internal implementation of the second unit. Therefore, some embodiments of this disclosure can also prevent abnormal states of the second unit from blocking communication with other units.

[0065] For ease of understanding, some implementation methods not described in detail in process 200 can be referred to the following in conjunction with the appendix. Figure 3 The example description is not repeated here. The following will be combined with the appendix. Figure 3Some embodiments of this disclosure are described by way of example.

[0066] Figure 3 A schematic structural block diagram of an example scenario 300 according to some embodiments of this disclosure is shown. Figure 3 As shown, the second unit can communicate with at least one third unit (not shown) via the first unit and through an interconnection network 140, which may be, for example, an on-chip network. Figure 3 Three types of second units are shown: unit A4 (321) is a pure master device type, unit A5 (322) is a pure slave device type, and unit A6 (323) is both a master device and a slave device. The first unit can be implemented as a corresponding fence module and / or timeout module for the different types of second units.

[0067] In some implementations, the first unit can be a hardware unit located at the communication interface of the second unit, and the forwarding control of communication messages by the first unit is independent of the second unit. For example, such as Figure 3 As shown, the first unit can be implemented as a fence module C1 (341) mounted on the communication interface B1 (331) of unit A4 (321), or as a timeout module D1 (342) mounted on the communication interface B2 (332) of unit A5 (322).

[0068] In this way, the forwarding control of communication messages by the first unit does not depend on the internal implementation of the second unit, thus making it applicable to different types of second units, reducing modifications to the internal design of the second unit, and improving the adaptability and reusability of the solution.

[0069] In some implementations, the second unit and at least one third unit can transmit communication messages based on a bus protocol, with the first unit performing forwarding control of these messages based on the bus protocol. For example, the bus protocol could be an advanced extensible interface protocol. In this way, the first unit only needs to comply with the bus protocol used by the second unit for external communication, without depending on the specific type or internal architecture of the second unit. As long as the second unit conforms to the corresponding bus protocol, the first unit can be mounted on its communication interface to perform forwarding control, further improving the versatility and reusability of the solution.

[0070] In some implementations, the second unit can communicate with at least one third unit via the first unit through the interconnection network 140, and the first unit's control over the forwarding of communication messages can be independent of the interconnection network 140. In this way, the first unit can stop and resume the forwarding of communication messages without relying on the implementation of the interconnection network 140. Therefore, when resetting or isolating the second unit, it is not necessary to stop or reset the interconnection network 140 along with it, thus achieving independent control of the second unit and avoiding affecting other units communicating via the interconnection network 140, improving the flexibility of isolation and reset operations.

[0071] In some implementations, the first unit may include a fence module, and the communication interface may include a first communication interface, which can be used to send a communication request to at least one third unit to obtain response data corresponding to the communication request from at least one third unit. For example, such as Figure 3 As shown, for unit A4 (321) of pure master device type, the first unit is implemented as fence module C1 (341) mounted on communication interface B1 (331), and communication interface B1 (331) is the first communication interface.

[0072] Alternatively or additionally, the system-on-chip 400 may, during the second communication state, stop forwarding communication requests from the second unit to at least one third unit via the barrier module. For example, the barrier module C1 (341) may, upon receiving a stop request, block new communication requests at the transaction boundary, causing the second unit to stop sending new communication requests to the third unit. In this way, the second unit can stop sending new communication requests at the appropriate transaction boundary and wait for the initiated incomplete transactions to complete naturally, thereby providing conditions for safely resetting or isolating the second unit and reducing the possibility of transmission deadlock or data anomalies caused by the interruption of incomplete transactions.

[0073] In some implementations, the system-on-chip 400 can receive response data from at least one third unit through the fence module while the fence module is in a second communication state; and forward the response data from at least one third unit to the second unit through the fence module. In this way, while ceasing the transmission of new communication requests, response data corresponding to already initiated communication requests is still allowed to return to the second unit, thereby ensuring that unfinished transactions between the second and third units are properly cleared, guaranteeing that the link enters an idle state before reset, and further reducing the risk of data loss and protocol errors.

[0074] In some implementations, the first unit may include a timeout module, and the communication interface may include a second communication interface. The second communication interface can be used to receive communication requests from at least one third unit, and to return response data corresponding to the communication request to at least one third unit. For example, such as... Figure 3 As shown, for unit A5 (322) of pure slave device type, the first unit is implemented as timeout module D1 (342) mounted on communication interface B2 (332), and communication interface B2 (332) is the second communication interface.

[0075] Alternatively or additionally, the system-on-chip 400 may, during the period when the timeout module is in the second communication state, intercept communication requests from at least one third unit to stop forwarding such requests to the second unit. In this manner, some embodiments of this disclosure can intercept communication requests from third units when the second unit, acting as a slave device, is reset or isolated, preventing these requests from being forwarded to the second unit in an abnormal or reset state, thereby achieving independent isolation of the second unit without stopping the third unit, which acts as the master device.

[0076] In some implementations, the system-on-chip 400 can send a response message to at least one third unit during the timeout module's second communication state, as a response to a communication request from at least one third unit. In this way, the timeout module can promptly return a response message to the third unit on behalf of the isolated second unit, preventing the third unit from waiting indefinitely for a response from the second unit and thus avoiding bus hang-ups or prolonged blocking of the third unit.

[0077] In some implementations, the response message may include preset data to indicate an abnormal response to a communication request from at least one third unit. For example, the preset data may be an error response or pre-defined data (such as all zeros). In this way, the third unit can obtain a complete response at the protocol level, while explicitly knowing through the preset data that the current communication request corresponds to an abnormal response, thus facilitating appropriate processing by the upper-layer logic.

[0078] In some implementations, the system-on-chip 400 may, in response to receiving response data from the second unit, delete the response data via a timeout module to stop forwarding the response data to at least one third unit. In this way, during isolation, the timeout module deletes response data generated by the second unit during an error or reset process instead of forwarding it to the third unit, thereby preventing abnormal response data from being propagated to the third unit and further ensuring the correctness of communication.

[0079] In some implementations, before switching the first unit from the second communication state to the first communication state, the on-chip system 400 may receive a second signal via a timeout module, the second signal indicating that the second unit has completed a reset; and in response to the second signal, allow receiving a communication request from at least one third unit via the timeout module.

[0080] For example, upon receiving an exit request, the timeout module can stop accepting new communication requests at the transaction boundary and wait for all responses to the already entered communication requests to be filled in. In this way, it can avoid duplicate responses or protocol errors caused by immediately resuming forwarding when the second unit has just completed its reset, ensuring that the forwarding of communication messages only resumes smoothly after the second unit has completed its reset and the timeout module has completed processing existing transactions.

[0081] In some implementations, the first unit includes a fence module and a timeout module. The communication interface includes a first communication interface connected to the fence module and a second communication interface connected to the timeout module. The fence module and the timeout module independently control the message transmission of the connected communication interfaces. For example, Figure 3 As shown, for unit A6 (323), which is both a master device and a slave device, the first unit is equipped with a fence module C2 (343) via communication interface B3 (333) in the master device direction and a timeout module D3 (344) via communication interface B4 (334) in the slave device direction. Communication interface B3 (333) is the first communication interface and communication interface B4 (334) is the second communication interface.

[0082] In this way, for the second unit that both initiates and responds to communication requests, some embodiments of this disclosure can perform independent isolation and control in the direction of the master device and the slave device, thereby meeting the need for resetting and isolating the second unit in complex scenarios.

[0083] The following is combined Figure 3 The reset procedures for the second unit of three types are described exemplarily below. It should be understood that the signal names mentioned below are merely examples and are not intended to limit the scope of this disclosure.

[0084] In some implementations, for a second unit of a pure master device type (e.g., unit A4 (321), which may be various acceleration engines in the chip, such as graphics processing unit (GPU), video codec, etc., which only initiate external requests), the first unit may be implemented as a fence module (e.g., fence module C1 (341)) mounted on its communication interface.

[0085] Additionally, the reset procedure for a pure master device type second unit (e.g., unit A4 (321)) may include, for example, a stop request (e.g., a stop request signal) initiated by firmware or hardware logic to trigger the barrier module to stop forwarding new communication requests at the transaction boundary. Alternatively or additionally, after the barrier module stops forwarding new communication requests at the transaction boundary, it outputs a stop confirmation message (e.g., a stop confirmation signal); after all unfinished transactions related to the second unit are completed, the barrier module outputs a completion indication message (e.g., a completion indication signal). Alternatively or additionally, the on-chip system 400 may reset the second unit. After the second unit completes the reset, the on-chip system 400 cancels the stop request, and the barrier module accordingly cancels the stop confirmation message and the completion indication message and exits, and communication returns to normal. Since the pure master device type second unit no longer initiates new communication requests after the reset, the barrier module can exit directly after the second unit is reset.

[0086] In some implementations, for a second unit of a purely slave device type (e.g., unit A5 (322), which may be a storage device such as dynamic random access memory or flash memory that passively receives read / write requests and returns response data), the first unit may be implemented as a timeout module (e.g., timeout module D1 (342)) mounted on its communication interface. The reset process of the second unit of the purely slave device type (e.g., unit A5 (322)) may include, for example, entering through hardware detection or being directly triggered by firmware, causing the timeout module to switch to the second communication state; the timeout module automatically fills in response messages for all incomplete communication requests and blocks transactions from the second unit (e.g., deleting response data from the second unit without forwarding it to the third unit). Alternatively or additionally, the system-on-chip 400 may reset the second unit. After the second unit completes the reset, the system-on-chip 400 may send an exit request (e.g., an exit request signal) to the timeout module. In response to the exit request, the timeout module may stop receiving new communication requests at the transaction boundary. Alternatively or additionally, the timeout module can wait for all responses to incoming communication requests to be completed. After confirming that there are no pending transactions, the timeout module can cancel the exit request and exit the second communication state to resume receiving new communication requests, thereby restoring normal communication.

[0087] In some implementations, the timeout module can determine whether to enter the second communication state based on a count. For example, the timeout module can use one or more of the following counting methods: all communication requests share a counter, each type of communication request shares its own counter, each communication request has its own corresponding counter, alternatively or additionally, when any count reaches a preset threshold, the timeout module can enter the second communication state. During the timeout module's second communication state, the timeout module can discard response data from the second unit, automatically reply with an abnormal response to incomplete communication requests (e.g., return all zeros for read requests), and directly reply to newly entering communication requests on-site without forwarding them to the second unit.

[0088] In some implementations, for a second unit that functions as both a master and a slave device (e.g., unit A6 (323, which can be various input / output devices or peripherals supporting high-speed interfaces), the first unit may include a barrier module and a timeout module in each of the two communication directions. For example, as Figure 3 As shown, in one communication direction (e.g., the master device direction), the second unit can be sequentially connected to the fence module C2 (343) and the timeout module D2 (353) via the communication interface B3 (333), and connected to the interconnection network 140 via the timeout module D2 (353). In another communication direction (e.g., the slave device direction), the second unit can be sequentially connected to the timeout module D3 (344) and the fence module C3 (354) via the communication interface B4 (334), and connected to the interconnection network 140 via the fence module C3 (354).

[0089] For a second unit that functions as both a master and a slave (e.g., unit A6 (323)), its reset procedure may include, for example, performing the stop and drain operations described above for a pure master type in the master direction, and performing the intercept and backfill operations described above for a pure slave type in the slave direction. Alternatively or additionally, the on-chip system 400 may reset the second unit after completing the operations in both directions. Alternatively or additionally, the on-chip system 400 may perform the exit procedure described above for a pure slave type in the slave direction and may also perform the exit procedure described above for a pure master type in the master direction, thereby restoring normal communication.

[0090] In some implementations, the isolation and control in the two communication directions can be performed independently without timing alignment. For example, in the master device direction, communication can be resumed directly after the second unit is reset; while in the slave device direction, communication can be resumed after the second unit is reset and the processing of incoming communication requests is completed.

[0091] In some implementations, by means of a timeout module D2 (353) disposed between the barrier module C2 (343) and the interconnect network 140 in the master device direction, and a barrier module C3 (354) disposed between the timeout module D3 (344) and the interconnect network 140 in the slave device direction, it is also possible to independently block and fallback the traffic on the interconnect network 140 side, thereby supporting independent reset and isolation of the second unit and the interconnect network 140 respectively. For example, the system-on-chip 400 may only reset the second unit without resetting the interconnect network 140, or independently reset and isolate the corresponding part of the interconnect network 140 as needed, without resetting unit A6 (323).

[0092] As an example, the fence module C2 (343) and the timeout module D3 (344) can be used for receiving or sending messages to the control unit A6 (323), while the timeout module D2 (353) and the fence module C3 (354) can be used to control the interconnection network 140 to receive or send messages to the outside. In some cases, the first unit for communication of the control unit A6 (323) and the first unit for communication of the interconnection network 140 can exist independently. For example, in the case where the reset unit A6 (323) is required but the interconnection network 140 does not need to be reset, the system-on-chip 400 can be configured with the fence module C2 (343) and the timeout module D3 (344) but without the timeout module D2 (353) and the fence module C3 (354). Alternatively, when the interconnect network 140 needs to be reset but the reset unit A6 (323) is not required, the system-on-chip 400 may be configured with a timeout module D2 (353) and a barrier module C3 (354) instead of a barrier module C2 (343) and a timeout module D3 (344). However, when both the interconnect network 140 and the reset unit A6 (323) need to be reset, the system-on-chip 400 may be configured with both a timeout module D2 (353) and a barrier module C3 (354), or both a barrier module C2 (343) and a timeout module D3 (344).

[0093] In some implementations, the preset data in the response message that the timeout module fills back to the third unit can be abnormal data (e.g., error response or all-zero data). At the hardware level, the timeout module can ensure the integrity of communication at the protocol level, enabling the third unit to complete the corresponding communication process normally. The validity of the abnormal data can be detected and processed by upper-layer logic. For example, when the upper-layer logic of the corresponding data detects abnormal data, the timeout module can re-execute the corresponding communication task or discard the data. In this way, some implementations of this disclosure can ensure the integrity of bus transmission at the protocol level without additional request caching or retransmission processing at the hardware level.

[0094] It should be understood that the above reset procedures for the three types of second units are merely exemplary. In some embodiments, for a second unit that functions as both a master and a slave device, if only the second unit itself needs to be reset, the timeout module D2 (353) in the master device direction and the barrier module C3 (354) in the slave device direction can be omitted. It should be understood that in practical applications, the steps in the above procedures can be added, omitted, replaced, or adjusted according to actual needs.

[0095] Figure 4 A schematic block diagram of a system-on-a-chip 400 according to some embodiments of the present disclosure is shown. The system-on-a-chip 400 may be implemented by architecture 100.

[0096] like Figure 4 As shown, the system-on-a-chip 400 includes: a first switching module 410 configured to switch a first unit of the system-on-a-chip from a first communication state to a second communication state in response to receiving a first signal, wherein the first communication state indicates that forwarding of communication messages is permitted between a second unit of the system-on-a-chip and at least one third unit of the system-on-a-chip, and the second communication state indicates that forwarding of communication messages is prohibited between the second unit and at least one third unit, wherein the first unit is independent of the second unit and is connected to the communication interface of the second unit for controlling message transmission between the second unit and at least one third unit; an acquisition module 420 configured to acquire the task processing status of at least one communication task, wherein the at least one communication task is associated with the second unit; and a second switching module 430 configured to switch the first unit from the second communication state to the first communication state in response to the task processing status of at least one communication task satisfying a preset condition, so as to resume forwarding of communication messages between the second unit and at least one third unit.

[0097] In some implementations, the first unit is a hardware unit located at the communication interface of the second unit, and the forwarding control of communication messages by the first unit is independent of the second unit.

[0098] In some implementations, the second unit and at least one third unit transmit communication messages based on a bus protocol, and the first unit performs forwarding control of the communication messages based on the bus protocol.

[0099] In some implementations, the second unit communicates with at least one third unit via the first unit through the interconnection network 140, and the first unit controls the forwarding of communication messages independently of the interconnection network 140.

[0100] In some embodiments, the first switching module 410 is further configured to: output first indication information in response to the first unit switching to the second communication state, the first indication information indicating that the forwarding of new communication messages between the second unit and at least one third unit is stopped; the second switching module 430 is further configured to: output second indication information in response to the task processing state of at least one communication task meeting a preset condition, the second indication information indicating that the forwarding of new communication messages between the second unit and at least one third unit is allowed.

[0101] In some implementations, the first signal is triggered based on a reset request for the second unit, and the second unit is reset while the first unit is in a second communication state.

[0102] In some implementations, the second switching module 430 is configured to: trigger a reset of the second unit in response to the task processing state of at least one communication task meeting a preset condition; and switch the first unit from the second communication state to the first communication state in response to the second unit completing the reset.

[0103] In some implementations, the first unit includes a fence module, and the communication interface includes a first communication interface for sending a communication request to at least one third unit to obtain response data corresponding to the communication request from at least one third unit; the system-on-chip 400 is also configured to: while the fence module is in a second communication state, stop forwarding the communication request of the second unit to at least one third unit through the fence module.

[0104] In some embodiments, the system-on-chip 400 is further configured to: receive response data from at least one third unit via the fence module while the fence module is in a second communication state; and forward the response data from at least one third unit to the second unit via the fence module.

[0105] In some implementations, the first unit includes a timeout module, and the communication interface includes a second communication interface for receiving communication requests from at least one third unit to return response data corresponding to the communication request to at least one third unit; the system-on-chip 400 is also configured to: while the timeout module is in the second communication state, intercept the communication request from at least one third unit through the timeout module to stop forwarding the communication request from at least one third unit to the second unit.

[0106] In some implementations, the system-on-chip 400 is also configured to send a response message to at least one third unit via the timeout module during the second communication state, as a response to a communication request from at least one third unit.

[0107] In some implementations, the response message includes preset data to indicate an abnormal response to a communication request from at least one third unit.

[0108] In some implementations, the system-on-chip 400 is also configured to: in response to receiving response data from a second unit, delete the response data via a timeout module to stop forwarding the response data to at least one third unit.

[0109] In some embodiments, the system-on-chip 400 is also configured to: receive a second signal via a timeout module, the second signal indicating that the second unit has completed a reset, before switching the first unit from a second communication state to a first communication state; and in response to the second signal, allow receiving a communication request from at least one third unit via the timeout module.

[0110] In some implementations, the first unit includes a fence module and a timeout module, and the communication interface includes a first communication interface connected to the fence module and a second communication interface connected to the timeout module. The fence module and the timeout module independently control the message transmission of the connected communication interfaces.

[0111] The modules included in the System-on-Chip 400 can be implemented in various ways, including software, hardware, firmware, or any combination thereof. In some implementations, one or more units may be implemented using software and / or firmware, such as machine-executable instructions stored on a storage medium. In addition to or as an alternative to machine-executable instructions, some or all of the modules in the System-on-Chip 400 may be implemented at least partially by one or more hardware logic components. By way of example and not limitation, exemplary types of hardware logic components that may be used include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), Systems-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0112] Figure 5 A block diagram of an electronic device 500 in which one or more embodiments of the present disclosure may be implemented is shown. It should be understood that... Figure 5 The electronic device 500 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described in this disclosure. Figure 5 The electronic device 500 shown can be used to achieve Figure 1 or Figure 4 The System-on-Chip 400.

[0113] like Figure 5As shown, electronic device 500 is in the form of a general-purpose electronic device. Components of electronic device 500 may include, but are not limited to, at least one processor 510 or processing unit, memory 520, storage device 530, one or more communication units 540, one or more input devices 550, and one or more output devices 560. Processor 510 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 520. In a multiprocessor system, multiple processors execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 500.

[0114] Electronic device 500 typically includes multiple computer storage media. Such media can be any accessible media that is accessible to electronic device 500, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 520 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 530 can be removable or non-removable media and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data and can be accessed within electronic device 500.

[0115] Electronic device 500 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 5 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 520 may include computer program product 525 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0116] Communication unit 540 enables communication with other electronic devices via a communication medium. Additionally, the functionality of components of electronic device 500 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, electronic device 500 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0117] Input device 550 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 560 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 500 can also communicate with one or more external devices (not shown) via communication unit 540 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 500, or with any device that enables electronic device 500 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0118] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the methods described above. According to an exemplary implementation of this disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, which are executed by a processor to implement the methods described above.

[0119] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, apparatuses, and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0120] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0121] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0122] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0123] Various implementations of this disclosure have been described above. The foregoing description is exemplary and not exhaustive, nor is it limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used in this disclosure is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A method for on-chip networks, used in on-chip systems, characterized in that, include: In response to receiving a first signal, the first unit of the system-on-a-chip is switched from a first communication state to a second communication state. The first communication state indicates that forwarding of communication messages between the second unit of the system-on-a-chip and at least one third unit of the system-on-a-chip is permitted, and the second communication state indicates that forwarding of communication messages between the second unit and the at least one third unit is prohibited. The first unit is independent of the second unit and is connected to the communication interface of the second unit for controlling message transmission between the second unit and the at least one third unit. Obtain the task processing status of at least one communication task, wherein the at least one communication task is related to the second unit; as well as In response to the task processing state of the at least one communication task meeting a preset condition, the first unit is switched from the second communication state to the first communication state to resume forwarding communication messages between the second unit and the at least one third unit.

2. The method according to claim 1, characterized in that, The first unit is a hardware unit located at the communication interface of the second unit, and the forwarding control of communication messages by the first unit is independent of the second unit.

3. The method according to claim 2, characterized in that, The second unit and the at least one third unit transmit communication messages based on a bus protocol, and the first unit performs forwarding control of the communication messages based on the bus protocol.

4. The method according to claim 2, characterized in that, The second unit communicates with the at least one third unit via the first unit through an interconnection network, wherein the first unit controls the forwarding of communication messages independently of the interconnection network.

5. The method according to claim 1, characterized in that, The method further includes: In response to the first unit switching to the second communication state, a first indication message is output, indicating that the forwarding of new communication messages between the second unit and the at least one third unit should be stopped; and In response to the task processing status of the at least one communication task meeting a preset condition, a second indication information is output, which indicates that it is permissible to forward a new communication message between the second unit and the at least one third unit.

6. The method according to claim 1, characterized in that, The first signal is triggered based on a reset request for the second unit, and the second unit is reset while the first unit is in the second communication state.

7. The method according to claim 6, characterized in that, The step of switching the first unit from the second communication state to the first communication state in response to the task processing state of the at least one communication task satisfying a preset condition includes: In response to the task processing state of the at least one communication task satisfying a preset condition, a reset of the second unit is triggered; and In response to the second unit completing a reset, the first unit is switched from the second communication state to the first communication state.

8. The method according to claim 1, characterized in that, The first unit includes a fence module, and the communication interface includes a first communication interface, which is used to send a communication request to the at least one third unit to obtain response data corresponding to the communication request from the at least one third unit. The method further includes: While the fence module is in the second communication state, the forwarding of communication requests from the second unit to the at least one third unit is stopped through the fence module.

9. The method according to claim 8, characterized in that, The method further includes: While the fence module is in the second communication state, the response data from the at least one third unit is received via the fence module; and The fence module forwards response data from at least one third unit to the second unit.

10. The method according to claim 1, characterized in that, The first unit includes a timeout module, the communication interface includes a second communication interface, the second communication interface is used to receive communication requests from the at least one third unit, and to return response data corresponding to the communication request to the at least one third unit, and the method further includes: While the timeout module is in the second communication state, the timeout module intercepts communication requests from the at least one third unit to stop forwarding communication requests from the at least one third unit to the second unit.

11. The method according to claim 10, characterized in that, The method further includes: While the timeout module is in the second communication state, a response message is sent to the at least one third unit via the timeout module as a response to a communication request from the at least one third unit.

12. The method according to claim 11, characterized in that, The response message includes preset data to indicate an abnormal response to a communication request from the at least one third unit.

13. The method according to claim 10, characterized in that, The method further includes: In response to receiving the response data from the second unit, the response data is deleted by the timeout module to stop forwarding the response data to the at least one third unit.

14. The method according to claim 10, characterized in that, Before switching the first unit from the second communication state to the first communication state, the method further includes: The timeout module receives a second signal, which indicates that the second unit has completed its reset; and In response to the second signal, the communication request from the at least one third unit is allowed to be received via the timeout module.

15. The method according to claim 1, characterized in that, The first unit includes a fence module and a timeout module. The communication interface includes a first communication interface connected to the fence module and a second communication interface connected to the timeout module. The fence module and the timeout module independently control the message transmission of the connected communication interfaces.

16. A system-on-a-chip, characterized in that, The on-chip system includes: A first switching module is configured to switch a first unit of the system-on-a-chip from a first communication state to a second communication state in response to receiving a first signal. The first communication state indicates that forwarding of communication messages is permitted between the second unit of the system-on-a-chip and at least one third unit of the system-on-a-chip, and the second communication state indicates that forwarding of communication messages is prohibited between the second unit and the at least one third unit. The first unit is independent of the second unit and is connected to the communication interface of the second unit for controlling message transmission between the second unit and the at least one third unit. The acquisition module is configured to acquire the task processing status of at least one communication task, said at least one communication task being related to the second unit; and The second switching module is configured to switch the first unit from the second communication state to the first communication state in response to the task processing state of the at least one communication task meeting a preset condition, so as to resume the forwarding of communication messages between the second unit and the at least one third unit.

17. An electronic device, characterized in that, The electronic device includes: At least one processor; and At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions causing the electronic device to perform the method according to any one of claims 1 to 15 when executed by the at least one processor.

18. A computer program product, said computer program product being tangibly stored in a computer storage medium and comprising computer-executable instructions, characterized in that, The computer-executable instructions, when executed by the device, cause the device to perform the method according to any one of claims 1 to 15.

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