On-chip self-test method and system for power amplifiers

Abstract

The application discloses an on-chip self-test method and system for a power amplifier, comprising initializing parameters of a chip to be tested, then reading a jumper state of an external board card, constructing a board card node identifier NID and saving the same; receiving a test instruction issued by an ATE host computer and a node identifier of the chip to be tested; obtaining LNA gain configuration parameters from a preset LNA gain table according to the test instruction; setting all phases to an idle state first, then setting a phase to be tested to a TXRX loopback; injecting a test single-tone signal and the LNA gain configuration parameters, then performing FFT triggering; after the FFT triggering is completed, reading CSI data stored in a buffer address; normalizing the CSI data to obtain power amplifier indexes; and returning the power amplifier indexes to the ATE host computer through a CLI message. The application replaces external measuring equipment with demodulation path multiplexing, realizes self-test of the power amplifier, and significantly reduces the cost of production line test equipment and the complexity of a work station.

Description

Technical Field

[0001] This invention relates to the field of communication testing technology, and in particular to an on-chip self-test method and system for power amplifiers. Background Technology

[0002] Existing PLC (Power Line Carrier) chips or HPLC (High Power Line Carrier) chips require testing of parameters such as the transmit power and SNR (Signal-to-Noise Ratio) of the power amplifier (PA) before leaving the factory.

[0003] Existing technologies typically employ the following methods when testing the parameters of power amplifiers: 1. Reliance on expensive off-chip RF instruments: Traditional PA testing requires the use of external equipment such as vector network analyzers, spectrum analyzers, and envelope detectors to measure transmit power, EVM, and SNR. These external devices cost hundreds of thousands of yuan per unit and significantly lengthen production line cycle time and increase the complexity of the testing station.

[0004] 2. Existing "loopback self-test" solutions: There are patents in the industry for using loopback for PA self-test, but these measurements mostly rely on envelope detectors / square wave limiters to measure power, or EVM symbol comparison to measure transmit quality. These methods either require additional analog test circuitry or can only measure a single parameter.

[0005] 3. Noise floor calculation does not consider PLC harmonic interference: Existing solutions usually sum the subcarriers across the entire frequency band as the noise floor when calculating SNR. However, when the PLC chip transmits a single tone for testing, it will generate harmonic and spurious tone signals (such as integer multiples of the single tone signal). If these harmonic-related subcarriers are included in the noise floor, it will lead to distortion in the SNR calculation.

[0006] 4. Lack of production line automation communication mechanism: The existing on-chip self-test solution lacks a standardized communication interface with the ATE (Automatic Test Equipment) host computer, and cannot realize the necessary functions of the production line such as test parameter distribution, result feedback, and device identity verification.

[0007] 5. Inflexible gain configuration: Existing solutions typically use fixed gain configurations for PA testing, which cannot cover the PA characterization requirements under different LNA gain levels, affecting test coverage and accuracy. Summary of the Invention

[0008] To address the technical problem of power amplifiers being unable to perform self-testing in existing technologies, this invention proposes an on-chip self-testing method and system for power amplifiers. It reuses the demodulation path of a communication chip originally used for channel estimation, treating it as a "built-in digital measurement instrument" for PA testing. Through phase forced loopback, injection of a single-tone signal (i.e., a single-tone signal containing only one frequency component), elimination of harmonic-related subcarriers in noise window calculation, and combination of normalized amplitude conversion, shared memory ATE communication, and hardware identification, on-chip automated testing of the power amplifier is achieved.

[0009] To achieve the above objectives, the present invention provides the following technical solution: An on-chip self-test method for power amplifiers specifically includes the following steps: S1: Initialize the parameters of the chip under test, then read the jumper status of the external board, construct the board node identifier NID and save it; S2: Receive the test command and the node identifier of the chip under test issued by the ATE host computer; S3: Obtain the LNA gain configuration parameters from the preset LNA gain table according to the test command; S4: First set all phases to the idle state, then set the phase to be tested to TXRX loopback; S5: Inject the test single-tone signal and LNA gain configuration parameters, and then perform FFT triggering; S6: After the FFT is triggered, read the CSI data stored in the buffer address; S7: Normalize the CSI data to obtain the power amplifier specifications; S8: Send the power amplifier specifications back to the ATE host computer via CLI message.

[0010] Preferably, in step S1, the parameters of the chip under test include UART, RTC, timer, GPIO matrix, and data packet module.

[0011] Preferably, in step S1, the high and low levels of the external board are read by switching 6 GPIO pins, the high and low levels are combined into binary values, and then converted into decimal numbers, which are the board node identifiers.

[0012] Preferably, in step S2, the path for issuing the test command includes a first path and a second path: The first path is: chip transmitter output → board-level attenuation network → PA LNA input → PA LNA amplification → PALNA output → chip receiver input; The second path is: chip transmitter output → PA input → PA output → board-level attenuation network → LNA input → PA LNA input coupled to PA LNA output → chip receiver input.

[0013] Preferably, step S2 further includes NID verification: After receiving the test command, it determines whether the node identifier of the chip to be tested is consistent with the node identifier of the constructed board. If they are consistent, it proceeds to the next step; otherwise, it returns an NID error and refuses to execute the test.

[0014] Preferably, S5 includes: S5-1: First, configure the TX gain and RX gain of the test single-tone signal according to the LNA gain configuration parameters; S5-2: After configuration, start the FFT trigger mechanism and check in real time whether it is completed. If not, continue to wait; if yes, proceed to S6.

[0015] Preferably, step S5-2 further includes a retry mechanism: If the waiting time for polling the FFT completion flag exceeds the preset time, an FFT TIMEOUT error flag will be returned, and the FFT will be triggered again.

[0016] Preferably, S6 further includes: traversing subcarriers within a preset frequency band and removing harmonics of the test single-tone signal to obtain a noise floor.

[0017] Preferably, S7 includes: S7-1: Calculate csi_amp based on the normalized amplitude of the ADC:

[0018] in, The value represents the overall amplitude after the full path is completed; ATE_ADC_FULL_SCALE_REF represents the ADC full-scale reference value; ATE_AMP_DB_OFFSET represents the CSI normalized reference value. This represents the sum of the digital signal power of a single-tone signal; S7-2: The noise ratio csi_snr is calculated using tone_data and noise_data.

[0019] Where csi_snr represents the noise ratio; noise_data represents the noise floor; S7-3: Read RSSI value directly from register.

[0020] The present invention also provides an on-chip self-test system for a power amplifier, comprising: The NID identification module is used to read external hardware jumpers to generate board node identifiers. The data receiving module can use shared memory to receive test commands from the ATE host computer and the node identifier of the chip under test; The loopback control module is used to force the target phase into the TXRX loopback mode by phase forcing. The gain configuration module is used to obtain LNA gain configuration parameters from the preset LNA gain table according to the test command, and to configure the LNA gain for the test single-tone signal. The measurement module is used to read CSI data of the test single-tone signal subcarrier from the buffer address in the demodulation path; The noise calculation module is used to traverse subcarriers within a preset frequency band and remove harmonics from the test single-tone signal to obtain the noise floor. The index conversion module is used to calculate the power amplifier index based on the ADC normalized index, CSI data, and noise floor. The result feedback module is used to send the power amplifier parameters back to the ATE host computer via CLI messages.

[0021] In summary, by adopting the above technical solution, the present invention has at least the following beneficial effects compared with the prior art: 1. This invention achieves self-testing of power amplifiers by replacing external measurement equipment with demodulation path multiplexing, significantly reducing the cost of production line testing equipment and the complexity of workstations.

[0022] 2. Harmonic Removal Improves SNR Accuracy: Harmonic-related subcarriers of the test signal (corresponding to the fundamental and harmonics of the 3MHz test single-tone signal) are removed during noise window calculation to avoid harmonic energy being included in the noise floor, which would lead to a falsely low SNR and improve the consistency between on-chip measurements and off-chip instruments.

[0023] 3. ADC Normalized Amplitude Conversion: A normalization factor is introduced to map the original I / Q amplitude of CSI to the full-scale scale of the ADC, so that the amplitude reading is directly aligned with the actual sampling range of the hardware ADC, eliminating the CSI scaling differences between different individual chips.

[0024] 4. Adaptable to PLC multi-phase architecture: Through phase forced loopback, any phase A / B / C can be flexibly selected for PA self-test, and the multi-phase topology can be reused to complete single-channel characterization.

[0025] 5. NID Hardware Anti-Crosstalk: The NID is generated by reading external jumpers through a switch and then verified, which effectively prevents instruction crosstalk during parallel testing of multiple DUTs.

[0026] 6. Multi-level gain coverage: 7 preset LNA gain tables cover PA characterization under different receive gain scenarios, improving test coverage and accuracy.

[0027] 7. FFT Retry Fault Tolerance: Introduce an FFT timeout retry mechanism to improve the robustness and yield of production line testing. Attached Figure Description Figure 1 This is a schematic diagram of an on-chip self-test method for a power amplifier according to an exemplary embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of an ATE on-chip self-test system for a power amplifier according to an exemplary embodiment of the present invention. Detailed Implementation

[0029] The present invention will be further described in detail below with reference to embodiments and specific implementation methods. However, this should not be construed as limiting the scope of the above-described subject matter of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0030] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0031] like Figure 1 As shown, this invention provides an on-chip self-test method for power amplifiers, specifically including the following steps: S1: Initialize system parameters, then read the jumper status of the external board, construct the board node identifier NID and save it.

[0032] In this embodiment, the system (PLC chip system or HPLC chip system) parameters include UART (Universal Asynchronous Receiver / Transmitter), RTC (Real-Time Clock), timer, GPIO matrix, data packet module, etc.

[0033] In this embodiment, the board has multiple solder points or DIP switches. Inserting a jumper cap indicates "on" (0), removing it indicates "off" (1), or connecting it to a high level / ground. Each switch corresponds to a binary number. The system's CPU reads the high and low levels of each switch, combines them into a binary value, and then converts it into a decimal number, which is the board's node identifier (NID). The main control software can read this NID to determine which functional daughter card is currently inserted, or to assign unique addresses to different devices on the bus to prevent conflicts.

[0034] Furthermore, the board has six GPIO pin switches, each corresponding to a 6-bit binary number (each bit represents 1 bit). Since 2^6 = 64, the combination of these six switches can represent the 64 numbers from 0 to 63. The CPU reads the high / low level of each switch through the six GPIO pins, combining them into a 6-bit binary value 101001, which is then converted to the decimal number 41, serving as the board's node identifier. The main control software reads this ID to determine which functional daughter card is currently inserted, or to assign unique addresses to different devices on the bus to prevent conflicts.

[0035] The biggest advantage of this approach is that it's plug-and-play, requiring no programming software; the address can be changed simply by removing or inserting jumper caps, thus improving detection speed.

[0036] Furthermore, the board node identifier is stored in shared memory for the ATE host computer to verify the device identity; In this embodiment, the method also includes initializing the shared memory flag; registering the CLI (Command Line Interface) message processing callback; and waiting for instructions from the ATE host computer.

[0037] S2: The system receives the test command and the node identifier of the chip under test from the ATE host computer.

[0038] S2-1: In this embodiment, the ATE host computer can send test commands to the system chip via UART, that is, the ATR host computer communicates with the system via UART.

[0039] The test commands include tone0_att (tone attenuation value) and td_pwr (transmit power). ana_pwr (analog power setting), tone_switch (GPIO level control, used to control the path of test command delivery), the node identifier to be tested, and rx_lna_gain (LNA gain level index).

[0040] In this embodiment, the test command sending path includes a first path and / or a second path. The ATE host computer can send test commands to the chip through the first path, and the ATE host computer can send test commands to the chip through the second path. The ATE host computer can send test commands to the chip sequentially through the first path and the second path. Currently, R&D testing will test both paths for comparison, but actual factory testing only tests one path.

[0041] The first path is the internal return path of the chip: chip transmitter output → board-level attenuation network → PA LNA input → PALNA amplification → PA LNA output → chip receiver input; In the first path, the signal bypasses the external independent power amplifier (PA) and low noise amplifier (LNA), and only passes through the on-board attenuation network and possibly integrated RF front-end module. This is used to quickly verify the chip's digital-to-analog conversion, modulation and demodulation, and whether the RF traces on the board are connected. It does not involve high-power devices, has low risk, and is suitable for quick judgment during power-on initialization.

[0042] The second path is a full board loopback: chip transmitter output → PA input → PA output → board-level attenuation network → LNA input → PA LNA input coupled to PA LNA output → chip receiver input.

[0043] In the second path, the signal passes through an external independent power amplifier (PA) and low noise amplifier (LNA) in its entirety. (The transmitted signal has extremely high power after passing through the PA and must pass through a high-power attenuation network (such as a coupler or π-type attenuator) before entering the sensitive LNA; otherwise, the receiving channel will be burned out.) This is used to test whether the actual transmit power meets the standard, whether the receive sensitivity is normal, and whether the gain and linearity of the PA and LNA meet the specifications. It is usually used during production line calibration or high-precision diagnostics.

[0044] S2-2: After receiving the test command, determine whether the node identifier of the chip under test matches the node identifier of the constructed board. If they match, proceed to S3; otherwise, return an NID error and refuse to execute the test. This mechanism prevents instruction crosstalk during parallel testing of multiple DUTs (Device Under Test).

[0045] S3: Obtain the LNA gain configuration parameters from the preset LNA gain table according to the test command.

[0046] In this embodiment, the test instruction contains the rx_lna_gain (LNA gain level index) corresponding to the node identifier to be tested. Then, the corresponding LNA gain configuration parameters can be obtained from the LNA gain table according to the index, so as to achieve a comprehensive characterization of PA under different receiving gain levels and improve test coverage and accuracy, as shown in Table 1.

[0047] Table 1. LNA Gain Table

[0048] In this embodiment, the chip transmitter controls the power consistency of the transmitted signal by controlling the parameters of three TX-related registers (tx_tone_att, tx_factor, and tx_pga_gain); tx_tone_att represents the transmit single-tone attenuation, tx_factor represents the transmit multiplier, and tx_pga_gain represents the transmit programmable gain.

[0049] The chip receiver controls the parameters of four RX-related registers (rx_pgf_gain, rx_bq_gain, rx_pga_gain, rx_gain_shift) and the PA register (pa_pgf_gain) to ensure the consistency of the final received signal power when traversing the LNA gain table. rx_pgf_gain represents the received analog programmable gain, rx_bq_gain represents the equalization filter amplification gain, rx_pga_gain represents the digital domain gain shift compensation (digital correction after analog amplification), rx_gain_shift represents the received gain offset, and pa_pgf_gain represents the level, with each level increasing the gain by 6dB.

[0050] In this embodiment, the external power supply of the power amplifier is controlled by a GPIO pin switch, which is turned on before testing and turned off after testing to prevent hot-plugging.

[0051] S4: First, set all phases to the idle state, and then set the phase to be tested (target phase, such as phase A) to TX-RX loopback (this is to configure the working mode of the main control chip: the normal working mode is half-duplex, with TX and RX states working alternately; the TX-RX loopback mode is full-duplex, and RX can also be performed in TX state), so that the transmitted signal loops back directly to the receiver without external coupling, eliminating phase / frequency abrupt changes.

[0052] In this embodiment, if two phases simultaneously switch from the idle state to the active state, the internal PLL (phase-locked loop) phase transition will generate an extremely narrow pulse spike. Although the energy is small, when the internal loop returns directly, this spike will directly feed into the receiver front end, potentially causing bit errors or occasional LNA saturation. Activating one phase at a time ensures a smooth transition of the waveform from "DC silence" to "sine wave".

[0053] Meanwhile, by bypassing all external circuits (attenuation network, PA, LNA, PCB traces), the test results completely eliminated external variables such as poor soldering, attenuator accuracy deviation, and PA nonlinear distortion.

[0054] S5: Inject a test single-tone signal and LNA gain configuration parameters into the phase to be tested, and then perform FFT triggering.

[0055] S5-1: First, configure the TX gain and RX gain of the test single-tone signal according to the LNA gain configuration parameters.

[0056] In this embodiment, the frequency of the single-tone signal being tested is 3MHz.

[0057] In this embodiment, an RX front-end filter is also configured: a 500kHz high-pass filter + a 26MHz low-pass filter.

[0058] S5-2: After configuration, start the FFT trigger mechanism and check in real time whether it is completed. If not, continue to wait; if yes, proceed to S6.

[0059] In this embodiment, the FFT triggering mechanism is as follows: 1. ADC time-domain sampling: The analog I and Q differential signals after being amplified by various gain stages in the RX path are sent to the ADC. The ADC samples and outputs I and Q data. The hardware buffers a continuous time-domain data as input data for FFT operation.

[0060] 2. The internal hardware of the digital front-end (DEF) will process the data to remove the DC component, eliminate the ADC zero-point drift, and output the processed time-domain complex sequence to the FFT module for calculation.

[0061] 3. The FFT module performs FFT calculations, outputs the complex number of the frequency point after the calculation is completed, and then stores the data in the CSI buffer.

[0062] 4. After caching is complete, set FFT_DONE high.

[0063] In this embodiment, the FFT completion flag (LOOP_FFT_DONE) can be polled. If the completion flag is found, it means that the FFT trigger is completed and proceed to S6; otherwise, polling continues.

[0064] This embodiment also includes a retry mechanism: If the waiting time for polling the FFT completion flag exceeds the preset time (100ms), an FFT TIMEOUT error flag will be returned, and the FFT will be triggered again.

[0065] S6: After the FFT is triggered, read the I / Q value of CSI (Channel State Information) and the CSI data tone_data of the subcarrier where the single tone signal is located, which are stored in the buffer address, i.e. the sum of digital signal power after FFT calculation.

[0066] In this embodiment, the chip data test uses the demodulation path originally used for channel estimation as the "built-in digital measurement instrument". Therefore, it is only necessary to read the I / Q value of CSI stored in the buffer address and then process it to obtain the measurement result. There is no need to design a separate analog test circuit (envelope detector / limiter, etc.).

[0067] Furthermore, the I / Q value of CSI includes the quadrature amplitude components: In-phase (I) data csi_i and Quadrature (Q) data csi_q.

[0068] The I / Q value is a basic unit of complex sampling, representing a pair of in-phase and quadrature components obtained by the ADC from sampling the RF analog quadrature signal. The data in the buffer address is the I / Q data set for all frequency points. tone_data is the frequency point data of the transmitted test tone.

[0069] S7: Traverse the subcarriers and remove harmonics of single-tone signals to obtain the noise floor.

[0070] In this embodiment, the subcarriers are traversed within the 2-26MHz frequency band (subcarrier indices 82-1021), and the second harmonic of the 3MHz test single-tone signal is removed to ensure that the noise floor only reflects the real thermal noise and noise floor, thereby obtaining the noise floor noise_data through existing technology.

[0071] S8: Normalize and convert the CSI I / Q values ​​and CSI data tone_data into power amplifier specifications, so that the original CSI readings are directly aligned with the actual sampling range of the power amplifier, eliminating the CSI scaling differences between different individual chips.

[0072] S8-1: Calculate csi_amp based on the normalized amplitude of the ADC;

[0073] in, This represents the overall amplitude after the complete path is completed, which is ultimately used to evaluate whether the PA is qualified; ATE_ADC_FULL_SCALE_REF represents the ADC full-scale reference value, which is 70 here; ATE_AMP_DB_OFFSET represents the CSI normalized reference value, which is the maximum value of uint16, 65535; This represents the CSI data of the subcarrier where a single-tone signal is located, i.e., the power of the digital signal at that single-tone location.

[0074] S8-2: The noise ratio csi_snr is calculated using tone_data and noise_data.

[0075] Wherein, tone_data is the sum of digital signal power of a single tone signal, representing the effective energy of a single tone target signal, and noise_data is the sum of digital signal power of the remaining frequency points in the 2MHz-26MHz band, which is the total spurious noise power of the entire frequency band after removing signal harmonics within the working bandwidth.

[0076] S8-3: Reads RSSI (Received Signal Strength Indication) values ​​directly from the register, which are then calculated in real time by the PHY RXTX module inside the main chip.

[0077] S9: Send the power amplifier specifications back to the ATE host computer via CLI message.

[0078] In this embodiment, after obtaining the power amplifier specifications, the following steps are also included: 1. Disable software CSI buffer access and exit loopback mode; 2. Restore hardware TX / RX control; 3. Turn off the external power supply (3V / 12V) to the PA; 4. Send the power amplifier specifications back to the ATE host computer via CLI message; 5. Update the shared memory flag, that is, realize the status synchronization between the chip and the ATE host computer through fixed address shared memory, support polling of key fields such as result / status / nid / sw_ver, and adapt to the production line automated test cycle.

[0079] In this embodiment, the shared memory is located at a fixed physical address and includes the test result (result), current status (status), board node identifier (nid), and software version number (sw_ver) fields; the ATE host computer determines the test progress by polling the result and status fields.

[0080] like Figure 2 As shown, based on the above-described on-chip self-test method for power amplifiers, the present invention also provides an on-chip self-test system for power amplifiers, specifically including an NID identification module, a data receiving module, a loopback control module, a gain configuration module, a measurement module, a noise calculation module, an index conversion module, and a result feedback module.

[0081] In this embodiment, the output of the NID identification module is connected to the input of the data receiving module, the output of the data receiving module is connected to the input of the gain configuration module, the output of the gain configuration module and the output of the loopback control module are connected in parallel and then connected to the input of the measurement module, the output of the measurement module is connected to the input of the noise calculation module, the output of the noise calculation module is connected to the input of the index conversion module, the output of the index conversion module is connected to the input of the result feedback module, and the output of the result feedback module is connected to the ATE host computer.

[0082] The NID identification module is used to read external hardware jumpers to generate board node identifiers. The data receiving module can use shared memory to receive test commands from the ATE host computer and the node identifier of the chip under test; The loopback control module is used to force the target phase into the TXRX loopback mode by phase forcing. The gain configuration module is used to obtain LNA gain configuration parameters from the preset LNA gain table according to the test command, and to configure the test single-tone signal. The measurement module is used to read the I / Q amplitude of the test single-tone signal subcarrier from the buffer address in the demodulation path; The noise calculation module is used to traverse subcarriers within a preset frequency band and remove harmonics from the test single-tone signal to obtain the noise floor. The index conversion module is used to calculate the power amplifier indexes based on the ADC normalized indexes, I / Q amplitude, and noise floor, including the power amplifier amplitude, noise ratio (SNR), and received signal strength index (RSSI). The result feedback module is used to send the power amplifier parameters back to the ATE host computer via CLI messages.

[0083] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention. In practical applications of persistent media (such as server disks, NAS, and object storage), various changes in form and detail can be made without departing from the spirit and scope of the present invention.

Claims

1. An on-chip self-test method for power amplifiers, characterized in that, Specifically, the following steps are included: S1: Initialize the parameters of the chip under test, then read the jumper status of the external board, construct the board node identifier NID and save it; S2: Receive the test command and the node identifier of the chip under test issued by the ATE host computer; S3: Obtain the LNA gain configuration parameters from the preset LNA gain table according to the test command; S4: First set all phases to the idle state, then set the phase to be tested to TXRX loopback; S5: Inject the test single-tone signal and LNA gain configuration parameters, and then perform FFT triggering; S6: After the FFT is triggered, read the CSI data stored in the buffer address; S7: Normalize the CSI data to obtain the power amplifier specifications; S8: Send the power amplifier specifications back to the ATE host computer via CLI message.

2. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, In S1, the parameters of the chip under test include UART, RTC, timer, GPIO matrix and data packet module.

3. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, In S1, the high and low levels of the external board are read through 6 GPIO pin switches, the high and low levels are combined into binary values, and then converted into decimal numbers, which are the board node identifiers.

4. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, In step S2, the path for issuing the test command includes a first path and a second path: The first path is: chip transmitter output → board-level attenuation network → PA LNA input → PA LNA amplification → PA LNA output → chip receiver input; The second path is: chip transmitter output → PA input → PA output → board-level attenuation network → LNA input → PALNA input coupled to PA LNA output → chip receiver input.

5. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, S2 also includes NID verification: After receiving the test command, it determines whether the node identifier of the chip to be tested is consistent with the node identifier of the constructed board. If they are consistent, it proceeds to the next step; otherwise, it returns an NID error and refuses to execute the test.

6. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, S5 includes: S5-1: First, configure the TX gain and RX gain of the test single-tone signal according to the LNA gain configuration parameters; S5-2: After configuration, start the FFT trigger mechanism and check in real time whether it is completed. If not, continue to wait; if yes, proceed to S6.

7. The on-chip self-test method for a power amplifier as described in claim 6, characterized in that, S5-2 also includes a retry mechanism: If the waiting time for polling the FFT completion flag exceeds the preset time, an FFT TIMEOUT error flag will be returned, and the FFT will be triggered again.

8. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, S6 further includes: traversing subcarriers within a preset frequency band and removing harmonics of the test single-tone signal to obtain a noise floor.

9. The on-chip self-test method for a power amplifier as described in claim 1, characterized in that, S7 includes: S7-1: Calculate csi_amp based on the normalized amplitude of the ADC: in, The value represents the overall amplitude after the full path is completed; ATE_ADC_FULL_SCALE_REF represents the ADC full-scale reference value; ATE_AMP_DB_OFFSET represents the CSI normalized reference value. This represents the sum of the digital signal power of a single-tone signal; S7-2: The noise ratio csi_snr is calculated using tone_data and noise_data. Where csi_snr represents the noise ratio; noise_data represents the noise floor; S7-3: Read RSSI value directly from register.

10. An on-chip self-test system for a power amplifier based on the method of any one of claims 1-9, characterized in that, include: The NID identification module is used to read external hardware jumpers to generate board node identifiers. The data receiving module can use shared memory to receive test commands from the ATE host computer and the node identifier of the chip under test; The loopback control module is used to force the target phase into the TXRX loopback mode by phase forcing. The gain configuration module is used to obtain LNA gain configuration parameters from the preset LNA gain table according to the test command, and to configure the LNA gain for the test single-tone signal. The measurement module is used to read CSI data of the test single-tone signal subcarrier from the buffer address in the demodulation path; The noise calculation module is used to traverse subcarriers within a preset frequency band and remove harmonics from the test single-tone signal to obtain the noise floor. The index conversion module is used to calculate the power amplifier index based on the ADC normalized index, CSI data, and noise floor. The result feedback module is used to send the power amplifier parameters back to the ATE host computer via CLI messages.

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