Storage server mainboard

Abstract

The utility model provides a main board of a storage server. The main board comprises a first processor, a second processor, a nest plate, a CPLD (Complex Programmable Logic Device) chip, a gigabit network controller, a first memory slot unit, a second memory slot unit, a first PCIE (Peripheral Component Interface Express) slot unit, a second PCIE slot unit, a first connector unit, a second connector unit, a third connector unit and a fourth connector unit, the first processor is respectively connected with the first memory slot unit, the first PCIE slot unit, the first connector unit, the second processor, the nest plate and the CPLD chip, the second memory slot unit, the second PCIE slot unit and the second connector unit are all connected with the second processor, and the gigabit network controller is respectively connected with the nest plate and the third connector unit. And the fourth connector unit is connected with the sleeve sheet. The double S5000C-32 processor architecture provided by the scheme of the utility model has higher computing power resources, and provides a plurality of PCIE (Peripheral Component Interconnect Express) buses and a plurality of memory slots, so that the requirements of high-speed data storage and large-capacity data storage can be met.

Description

Technical Field

[0001] The utility model relates to the technical field of storage servers, in particular to a storage server mainboard. Background Art

[0002] A storage server motherboard is a motherboard used to support storage servers. Storage server motherboards usually have multiple storage device interfaces, such as SATA, SAS or NVMe, in order to connect hard disk drives, solid-state drives and other storage devices. They are usually also equipped with network interfaces, memory slots and other expansion slots to support corresponding additional functions and expansion functions. In the related art, storage servers often use a single processor. With the development of science and technology, society has entered the era of data interconnection. The data traffic of various industries has grown rapidly, and the amount of data for various applications has also increased year by year. However, a single processor has limited processing power and cannot meet the needs of large-capacity data storage and high-speed data access. Therefore, it is necessary to design a storage server that can meet the needs of large-capacity data storage and high-speed data access. Utility Model Content

[0003] The utility model provides a storage server mainboard, aiming to solve the problem in the related art that the storage system cannot meet the requirements of large-capacity data storage and high-speed data access.

[0004] In order to solve the above technical problems, the first aspect of the utility model provides a storage server motherboard, including: a first S5000C-32 processor, a second S5000C-32 processor, a chip set, a CPLD chip, a gigabit network controller, a first memory slot unit, a second memory slot unit, a first PCIE slot unit, a second PCIE slot unit, a first connector unit, a second connector unit, a third connector unit and a fourth connector unit; the first S5000C-32 processor is electrically connected to the first memory slot unit, the first PCIE slot unit, the first connector unit, the second S5000C-32 processor, the chip set and the CPLD chip, the second memory slot unit, the second PCIE slot unit and the second connector unit are all electrically connected to the second S5000C-32 processor, the gigabit network controller is electrically connected to the chip set and the third connector unit, and the fourth connector unit is electrically connected to the chip set.

[0005] Furthermore, the first memory slot unit and the second memory slot unit both include a first DDR5 memory slot, a second DDR5 memory slot, a third DDR5 memory slot and a fourth DDR5 memory slot; the first PCIE slot unit and the second PCIE slot unit both include a first PCIE5.0 slot, a second PCIE5.0 slot and a third PCIE5.0 slot; the first connector unit includes a first MCIO connector and a runBMC daughter card connector, and the second connector unit includes a first M.2 connector and a second MCIO connector, a third MCIO connector and a fourth MCIO connector; the third connector unit includes a first double-layer RJ45 connector and a second double-layer RJ45 connector; the fourth connector unit includes a first SATA connector, a second SATA connector, a third SATA connector, a fourth SATA connector, a panel USB connector, a second M.2 connector, an RJ45 connector and a double-layer USB3.0 connector.

[0006] Furthermore, it also includes a video memory chip, and the video memory chip is electrically connected to the set of chips.

[0007] Furthermore, it also includes a DB15 connector and a DB9 connector, and the DB15 connector and the DB9 connector are both electrically connected to the runBMC daughter card connector.

[0008] Furthermore, it also includes a serial port level conversion chip, and the serial port level conversion chip is electrically connected to the CPLD chip, the DB15 connector and the DB9 connector respectively.

[0009] Furthermore, it also includes a panel control connector, and the panel control connector is electrically connected to the CPLD chip.

[0010] From the above description, it can be seen that the utility model adopts dual processors, chip sets, CPLD chips, memory slot units, PCIE slot units and multiple connector units to form a storage server motherboard. The dual processors adopt Tengyun S5000C-64 processors. The high-performance dual processors can provide higher computing resources, and connect multiple PCIE slots and connectors to provide high-speed data transmission, which can effectively meet the needs of high-speed data access; and the dual processors are both domestic devices, which is conducive to ensuring data processing security. At the same time, by building a dual processor architecture and connecting multiple memory slots, more memory space can be expanded to meet the needs of large-capacity data storage. By connecting the CPLD chip, more controllable functions are provided for the system. By setting the chip set and the gigabit network controller, reliable network communication functions are provided for the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1It is a structural schematic diagram of a storage server mainboard according to an embodiment of the utility model;

[0012] Figure 2 It is a structural schematic diagram of another storage server motherboard according to an embodiment of the utility model;

[0013] Figure 3 This is a circuit schematic diagram of a power supply module according to an embodiment of the utility model. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical scheme and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model. In addition, the technical features involved in the various embodiments of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0015] Before describing in detail the radar signal processing system provided in the embodiment of the present application, the abbreviations or custom terms appearing below are explained as follows:

[0016] PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard); SATA (Serial ATA, serial ATA bus); MDI (Media Dependent Interface, uplink port); CPLD (Complex Programmable Logic Device, complex programmable logic device); LPDDR4 (LowPower Double Data Rate 4); UART (Universal Asynchronous Receiver / Transmitter, universal serial data bus).

[0017] In the related art, since there is a problem that the storage system cannot meet the data security requirements well, for this reason, an embodiment of the utility model provides a storage server motherboard.

[0018] like Figure 1The figure shows a schematic diagram of the structure of a storage server motherboard provided by an embodiment of the utility model, the storage server motherboard comprises: a first S5000C-32 processor 10, a second S5000C-32 processor 20, a chip set 30, a CPLD chip 40, a Gigabit network controller 50, a first memory slot unit 60, a second memory slot unit 70, a first PCIE slot unit 80, a second PCIE slot unit 90, a first connector unit 100, a second connector unit 110, a third connector unit 120 and a fourth connector unit 130; ... second S5000C-32 processor 20, a first S5000C-32 processor 20, a second S5000C-32 processor 20, a An S5000C-32 processor 10 is electrically connected to the first memory slot unit 60, the first PCIE slot unit 80, the first connector unit 100, the second S5000C-32 processor 20, the chip set 30 and the CPLD chip 40 respectively; the second memory slot unit 70, the second PCIE slot unit 90 and the second connector unit 110 are all electrically connected to the second S5000C-32 processor 20; the Gigabit network controller 50 is electrically connected to the chip set 30 and the third connector unit 120 respectively; and the fourth connector unit 130 is electrically connected to the chip set 30.

[0019] Specifically, the storage server motherboard provided adopts a dual processor structure, the first S5000C-32 processor 10 and the second S5000C-32 processor 20 both adopt Tengyun S5000C-32 processors, and data access processing is performed based on two high-performance Tengyun S5000C-64 processors, which can better meet the needs of large-capacity storage data and high access speed. The storage server motherboard is composed of dual processors, chip sets, CPLD chips, memory slot units, PCIE slot units and multiple connector units. Each device can adopt domestic devices, so that the storage server motherboard can be domestically produced, can replace foreign similar products, realize the high degree of autonomy and controllability of the storage system, and effectively ensure data security. Among them, the first high-speed PCIE3.0x8 bus of the first S5000C-32 processor 10 is connected to the set 30 of the computing motherboard, which is used to provide USB3.0, USB2.0 interfaces, and SATA3.0, PCIE3.0 buses to the outside; the second, third, and fourth high-speed PCIE3.0 buses of the first S5000C-32 processor 10 are connected to the first PCIE slot unit 80, which is used to provide PCIE5.0 buses to the outside; the fifth, sixth, and seventh high-speed PCIE buses of the first S5000C-32 processor 10 are connected to the first connection The device unit 100 is used to provide a PCIE5.0 bus to the outside; the 1st, 2nd, 3rd, and 4th C2Cx8 buses of the first S5000C-32 processor 10 are connected to the second S5000C-32 processor 20, which can be used to expand the memory and provide PCIE5.0 and PCIE3.0 buses to the outside; the memory bus of the first S5000C-32 processor 10 is connected to the first memory slot unit 60 for external memory sticks; the UART serial port and GPIO port of the first S5000C-32 processor 10 are connected to the CPLD chip 40 for signal control. The 1st, 5th, 6th, 7th, 8th, 9th and 10th high-speed PCIE buses of the second S5000C-32 processor 20 are connected to the second connector unit 110, the 2nd, 3rd and 4th high-speed PCIE buses are connected to the second PCIE slot unit 90, the 1st, 2nd, 3rd and 4th C2Cx8 buses of the second S5000C-32 processor 20 are connected to the first S5000C-32 processor 10, and the memory bus of the second S5000C-32 processor 20 is connected to the second memory slot unit 70. The chip set 30 in this embodiment can be a Feiteng X100 chip set, the gigabit network controller 50 can be a Netxon WX1860AL4 gigabit network controller, and the CPLD chip 40 can be an Anlu EF3L90CG400B CPLD.

[0020] like Figure 2 FIG. 1 is a schematic diagram of the structure of another storage server motherboard provided by an embodiment of the utility model, see Figure 2, the first memory slot unit 60 and the second memory slot unit 70 both include a first DDR5 memory slot C / G, a second DDR5 memory slot D / H, a third DDR5 memory slot E / I and a fourth DDR5 memory slot F / J. The first PCIE slot unit 80 and the second PCIE slot unit 90 both include a first PCIE5.0 slot AH / AK, a second PCIE5.0 slot AI / AL and a third PCIE5.0 slot AJ / AM. The first connector unit 100 includes a first MCIO connector Y and a runBMC daughter card connector U, and the second connector unit 110 includes a first M.2 connector V and a second MCIO connector Z, a third MCIO connector AB and a fourth MCIO connector AC. The third connector unit 120 includes a first double-layer RJ45 connector M and a second double-layer RJ45 connector N. The fourth connector unit 130 includes a first SATA connector S, a second SATA connector P, a third SATA connector Q, a fourth SATA connector R, a panel USB connector AG, a second M.2 connector W, an RJ45 connector and a double-layer USB3.0 connector AE; in addition, the storage server motherboard also includes a video memory chip AO, and the video memory chip AO is electrically connected to the set chip K (30).

[0021] Specifically, in this embodiment, the second high-speed PCIE5.0x8 bus of the first S5000C-32 processor A (10) is connected to the PCIE5.0x8 slot AH, the third high-speed PCIE5.0x8 bus is connected to the PCIE5.0x8 slot AI, and the fourth high-speed PCIE5.0x16 bus is connected to the PCIE5.0x16 slot AJ, so as to provide PCIE5.0 bus to the outside; the fifth and sixth high-speed PCIE5.0x4 buses are connected to the MCIO connector Y, so as to provide two PCIE5.0x4 buses to the outside; the sixth PCIE3.0x high-speed bus is connected to the runBMC daughter card connector (slot) U; the DDR5 memory bus 1 is connected to the DDR5 memory slot C, the DDR5 memory bus 2 is connected to the DDR5 memory slot D, the DDR5 memory bus 3 is connected to the DDR5 memory slot E, and the DDR5 memory bus 4 is connected to the DDR5 memory slot F, so as to provide four memory channels.

[0022] The first high-speed PCIE3.0x4 bus of the second S5000C-32 processor B (20) is connected to the M.2 connector V to provide an M.2 hard disk interface to the outside; the second high-speed PCIE5.0x8 bus is used to connect the PCIE5.0x8 slot AK, the third high-speed PCIE5.0x8 bus is used to connect the PCIE5.0x8 slot AL, and the fourth high-speed PCIE5.0x8 bus is connected to the PCIE5.0x8 slot AM to provide a PCIE5.0 bus to the outside; the fifth and sixth high-speed PCIE5.0x4 buses are used to connect the MCIO connector Z, the seventh and eighth high-speed PC The IE5.0x4 bus is used to connect the MCIO connector AB, the 8th and 9th high-speed PCIE5.0x4 buses are used to connect the MCIO connector AC (the PCIE5.0x2 in the figure is another schematic diagram) to provide 6 PCIE5.0x4 buses to the outside; the DDR5 memory bus 1 is connected to the DDR5 memory slot G, the DDR5 memory bus 2 is connected to the DDR5 memory slot H, the DDR5 memory bus 3 is connected to the DDR5 memory slot I, and the DDR5 memory bus 4 is connected to the DDR5 memory slot J, which are used to connect external memory sticks and provide 4 memory channels; the GPIO is connected to the CPLD chip AD (40) (not shown in the figure).

[0023] The 1-way PCIE3.0x2 bus of the set K (30) is connected to the M.2 connector W, providing an M.2 hard disk interface to the outside; the 4-way high-speed SATA3.0 bus is connected to the SATA connector P, SATA connector Q, SATA connector R, and SATA connector S, providing 4 SATA hard disk interfaces to the outside; it is connected to a double-layer USB3.0+RJ45 connector AE, each layer of the USB3.0 connector is respectively connected to 2 USB3.0 and 2 USB2.0 buses, providing USB3.0 / USB2.0 interfaces to the outside; it is connected to a panel USB connector AG, providing 2 USB3.0 and 2 USB2.0 interfaces to the outside; it is connected to the Changxin CXDB3ABAM-MK-A video memory chip AO, providing 1 LPDDR4 channel; the 1-way high-speed PCIE3.0x2 is connected to the Netxun WX1860AL4 Gigabit Network Controller L (50), providing 4 Gigabit Network interfaces to the outside; the 2-way USB3.0 and 2-way USB2.0 buses are connected to the panel USB connector AG.

[0024] The Netxon WX1860AL4 Gigabit Network Controller L is connected to the double-layer RJ45 connector M and the double-layer RJ45 connector N. Each double-layer RJ45 connector is connected to 2 MDI buses to provide 4 Gigabit Network interfaces to the outside.

[0025] Further, see Figure 2The storage server mainboard further includes a DB15 connector and a DB9 connector O, both of which are electrically connected to the runBMC daughter card connector U. The storage server mainboard further includes a serial port level conversion chip T, which is electrically connected to the CPLD chip AD (40), the DB15 connector and the DB9 connector O, respectively. The storage server mainboard further includes a panel control connector AF, which is electrically connected to the CPLD chip AD.

[0026] Specifically, in this embodiment, the N-way GPIO of the Anlu EF3L90CG400B CPLD is connected to the BMC controller (not shown in the figure); the 8-way GPIO is connected to the panel control connector AF to provide 8-way GPIO; the AT3243EEAI serial port level conversion chip T is connected to provide 1 RS232 interface. The double-layer DB15+DB9 connector O is connected to the rumBMC daughter card connector U through 1 RGB bus; and the AT3243EEAI serial port conversion chip T is connected through 1 RS232 bus. The double-layer USB3.0+RJ45 connector AE is also connected to the runBMC daughter card connector U (not shown in the figure) to provide 1 BMC Gigabit network port, the runBMC daughter card connector U is connected to the double-layer DB15+DB9 connector O through 1 RGB bus and 1 MDI bus (not shown in the figure), and the runBMC daughter card connector U is connected to the Anlu EF3L90CG400B CPLD (not shown in the figure) through N-way GPIO.

[0027] In addition, the storage server motherboard also includes a power module X, which is used to supply power to various devices and connectors, such as Figure 3 The circuit schematic diagram of the power supply module shown in the figure shows that the CPLD chip M (40) can control the power-on timing of each power supply level, and the runBMC daughter card connector U can detect the voltage value of each level.

[0028] The storage server motherboard provided by the embodiment of the utility model adopts dual processors, chips, CPLD chips, memory slot units, PCIE slot units and multiple connector units to form the storage server motherboard. Each device can adopt domestic devices. For example, the main processor adopts the Tengyun S5000C-64 processor, the chip set adopts the X100 chip set, etc., so that the storage server motherboard can be domestically produced, effectively ensuring data security. At the same time, based on two high-performance processors such as the Tengyun S5000C-64 for data access processing, it can better meet the needs of large-capacity storage data and high access speed.

[0029] It should be noted that the various embodiments in the present invention are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0030] It should also be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0031] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present invention, but will conform to the widest range consistent with the principles and novel features disclosed in the present invention.

Claims

1. A storage server motherboard, characterized in that: include: A first S5000C-32 processor, a second S5000C-32 processor, a chip set, a CPLD chip, a Gigabit network controller, a first memory slot unit, a second memory slot unit, a first PCIE slot unit, a second PCIE slot unit, a first connector unit, a second connector unit, a third connector unit and a fourth connector unit; The first S5000C-32 processor is electrically connected to the first memory slot unit, the first PCIE slot unit, the first connector unit, the second S5000C-32 processor, the chip set and the CPLD chip respectively; the second memory slot unit, the second PCIE slot unit and the second connector unit are all electrically connected to the second S5000C-32 processor; the Gigabit network controller is electrically connected to the chip set and the third connector unit respectively; and the fourth connector unit is electrically connected to the chip set.

2. The storage server motherboard according to claim 1, characterized in that: The first memory slot unit and the second memory slot unit both include a first DDR5 memory slot, a second DDR5 memory slot, a third DDR5 memory slot and a fourth DDR5 memory slot.

3. The storage server motherboard according to claim 1, characterized in that: The first PCIE slot unit and the second PCIE slot unit both include a first PCIE 5.0 slot, a second PCIE 5.0 slot and a third PCIE 5.0 slot.

4. The storage server motherboard according to claim 1, characterized in that: The first connector unit includes a first MCIO connector and a runBMC daughter card connector, and the second connector unit includes a first M.2 connector and a second MCIO connector, a third MCIO connector and a fourth MCIO connector.

5. The storage server motherboard according to claim 1, characterized in that: The third connector unit includes a first double-layer RJ45 connector and a second double-layer RJ45 connector.

6. The storage server motherboard according to claim 1, characterized in that: The fourth connector unit includes a first SATA connector, a second SATA connector, a third SATA connector, a fourth SATA connector, a panel USB connector, a second M.2 connector, an RJ45 connector and a double-layer USB3.0 connector.

7. The storage server motherboard according to claim 1, characterized in that: It also includes a video memory chip, which is electrically connected to the set of chips.

8. The storage server motherboard according to claim 4, characterized in that: It also includes a DB15 connector and a DB9 connector, and both the DB15 connector and the DB9 connector are electrically connected to the runBMC daughter card connector.

9. The storage server motherboard according to claim 8, characterized in that: It also includes a serial port level conversion chip, which is electrically connected to the CPLD chip, the DB15 connector and the DB9 connector respectively.

10. The storage server motherboard according to any one of claims 1 to 9, characterized in that: It also includes a panel control connector, which is electrically connected to the CPLD chip.

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