Bypass circuit for avoiding overcurrent protection at reset starting moment

Abstract

The utility model belongs to the field of circuit protection, and relates to a bypass circuit capable of avoiding reset starting instant overcurrent protection, which comprises a charging circuit, a switching circuit, a bypass protection circuit, a power utilization circuit and a power supply circuit, the bypass protection circuit comprises a first MOS tube, a diode, a charging capacitor and a third resistor. The grid electrode of the first MOS tube is connected with the output end of the switching circuit, and the first MOS tube is an N-type MOS tube; the positive electrode of one end of the diode is connected with the output end of the reset key, and the negative electrode is connected with the grid electrode of the first MOS tube; one end of the charging capacitor is connected with the grid electrode of the first MOS tube, and the other end is grounded; the third resistor is connected between the grid electrode of the first MOS tube and the ground; after the charging capacitor is charged to a certain pressure value, the first MOS tube is conducted; when instant large current occurs in the charging circuit, rapid charging and discharging are realized through the time-delay power-on circuit and the first MOS tube, so that the problem of'inrush current 'or'surge current' is simply and efficiently solved.

Description

Technical Field

[0001] The present application belongs to the field of circuit protection, and in particular relates to a bypass circuit for preventing overcurrent protection during reset startup. Background Art

[0002] In the power management system of electronic devices, the power management chip (PMIC) is a critical component responsible for converting the input power into a stable output suitable for different parts of the electronic device. During the device startup process, energy storage through capacitors is usually required to smooth the power supply voltage and ensure that the device can obtain a continuous and stable current supply. However, when capacitors start to charge from a fully discharged state, they absorb a large amount of current in a short period of time. This phenomenon is called "inrush current" or "surge current". If this current exceeds the design limit of the PMIC, it may trigger the overcurrent protection mechanism, causing the PMIC to disconnect or reduce the output, thereby affecting the normal startup of the device.

[0003] For example, if the overcurrent protection voltage of a certain chip is 5A, at the moment of machine reset and startup, due to charging the capacitor, the voltage instantly exceeds 5A, causing the chip to be protected and no current to be output, resulting in the machine being unable to boot normally or repeatedly restarting. The waveform of the voltage tested by the oscilloscope is shown in the following figure. The original voltage V_SYS of Y1 and the voltage VBAT of Y2 are the same as 3.45V, but due to the triggering of the overcurrent protection, the output is instantly turned off, causing the chip to turn off the output, and the voltage instantly drops to 2.49V, and the electronic product cannot be turned on, or repeatedly restarts.

[0004] To solve this problem, the industry has developed a variety of different solutions, such as thermistors (PTCs), negative temperature coefficient (NTC) resistors, or electronic switches. These components add a series impedance to limit the inrush current during cold start, and allow normal current to flow after the capacitor is fully charged. However, these methods increase system complexity, cost, and power consumption, and may not completely eliminate the overcurrent problem, especially under extreme temperature conditions or when the power supply is unstable.

[0005] Therefore, how to solve "inrush current" or "surge current" more effectively is a problem. Summary of the invention

[0006] The purpose of the present application is to provide a bypass circuit for preventing overcurrent protection during reset startup, so as to solve the problem in the prior art that the "inrush current" cannot be completely eliminated or the elimination method is too complicated.

[0007] The technical solution of the present application is: a bypass circuit for avoiding instantaneous overcurrent protection during reset startup, comprising a charging circuit, a switch circuit, a bypass protection circuit, a power circuit and a power supply circuit; the charging circuit is provided with a first output terminal VBAT and a second output terminal V-SYS; the output terminals of the bypass protection circuit and the charging circuit are both connected to the input terminal of the power supply circuit, and the output terminal of the power supply circuit is connected to the input terminal of the power circuit; the output terminal of the switch circuit is connected to the bypass protection circuit, and the bypass protection circuit comprises a first MOS tube, a diode, a charging capacitor and a third resistor; the first MOS tube is an N-type MOS tube; the positive electrode of the diode is connected to the output terminal of the switch circuit, and the negative electrode is connected to the gate of the first MOS tube; one end of the charging capacitor is connected to the gate of the first MOS tube, and the other end is grounded; the third resistor is connected between the gate of the first MOS tube and the ground; when the diode receives a high level, the charging capacitor will continue to charge, and after the charging capacitor is charged to a certain pressure value, the first MOS tube is turned on.

[0008] Preferably, the bypass protection circuit further includes a second MOS tube, a second resistor and a third MOS tube; the second MOS tube, the second resistor and the third MOS tube are all arranged in parallel and one end of the second resistor is connected to the source of the second MOS tube and the third MOS tube, the second MOS tube is connected to the first output terminal VBAT of the charging circuit, the drain of the third MOS tube is connected to the second output terminal V-SYS of the charging circuit, and the second MOS tube and the third MOS tube are both P-type MOS tubes.

[0009] Preferably, the charging circuit includes a charging chip, interface No. 7 of the charging chip is connected to a 5V power supply, interfaces No. 13 and No. 14 of the charging chip are the first output terminal VBAT; interfaces No. 4 and No. 5 of the charging chip are the second output terminal V-SYS.

[0010] Preferably, the switching circuit includes a reset button and a first resistor; interface No. 1 of the reset button is connected to the power supply, interface No. 2 is the output end, and interfaces No. 3, 4 and 5 are all grounded; the first resistor is connected between the power supply and interface No. 1 of the reset button.

[0011] Preferably, the power supply circuit includes a power supply chip, a first capacitor group, a fourth MOS tube and a second capacitor group; the A1 interface of the power supply chip is connected to the second output terminal V-SYS of the charging chip, the first capacitor group has a total of four capacitors, the first capacitor group is arranged between the second output terminal V-SYS and the A1 interface of the power supply chip, and the capacitors in the first capacitor group are all grounded at one end away from the A1 interface of the power supply chip; the gate of the fourth MOS tube is connected to the No. 2 interface of the switching circuit, the drain is grounded, and the source is connected to the B5 interface of the power supply chip, and the B5 interface is the EN port; a fourth resistor is arranged between the source of the fourth MOS tube and the second output terminal V-SYS; the E1 interface of the power supply chip is connected to the power circuit, the E1-E4 interfaces are connected in parallel, and the E5 interface is grounded; there are three groups of the second capacitor groups, one end of the second capacitor group is connected to the E1 interface of the power supply chip, and the other end is connected to the E5 interface of the power supply chip.

[0012] The bypass circuit of the present application for avoiding instantaneous overcurrent protection at reset startup, when the reset button is released, the output end of the reset button becomes a low level, and then the diode is not conducting, the fourth resistor pulls up the voltage of the B5 interface of the power chip, the power chip is powered on, the capacitors on the various power circuits behind the power chip begin to charge, and a large current passes instantaneously between interfaces 13 and 14 of the charging chip and interfaces 4 and 5 of the charging chip, thereby triggering the overcurrent protection, that is, fast charging and discharging is achieved through the delayed power-on circuit and the first MOS tube, so as to simply and efficiently solve the "inrush current" or "surge current" problem.

[0013] However, when the reset button is released, the voltage on the charging capacitor cannot be released immediately because it is connected to the cathode of the diode. It needs to be maintained for tens of milliseconds to maintain the continued conduction of the first MOS tube, the second MOS tube, and the third MOS tube, so as to achieve the output from the first output terminal VBAT to the second output terminal V-SYS, so as to share the large current passing through instantly with the charging chip and avoid overcurrent protection of the charging chip. When the capacitors of the various power circuits are charged, no large current is generated, and the voltage on the charging capacitor is slowly released. The first MOS tube, the second MOS tube, and the third MOS tube are not turned on, and the bypass protection current function is exited. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solution provided by the present application, the following is a brief introduction to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present application.

[0015] Figure 1 This is a schematic diagram of the overall structure of this application;

[0016] Figure 2 This is a schematic diagram of the switch circuit for this application;

[0017] Figure 3 This is a schematic diagram of the bypass protection circuit for this application;

[0018] Figure 4 This is a schematic diagram of the charging circuit for this application;

[0019] Figure 5 This is a schematic diagram of the power supply circuit for this application.

[0020] 1. Charging circuit; 2. Switching circuit; 3. Bypass protection circuit; 4. Power circuit; 5. Power supply circuit; 6. Reset button; 7. First resistor; 8. First MOS tube; 9. Second MOS tube; 10. Third MOS tube; 11. Second resistor; 12. Diode; 13. Charging capacitor; 14. Third resistor; 15. Charging chip; 16. Power supply chip; 17. First capacitor group; 18. Fourth MOS tube; 19. Second capacitor group; 20. Fourth resistor. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] A bypass circuit to avoid overcurrent protection during reset startup, such as Figure 1 , including a charging circuit 1, a switch circuit 2, a bypass protection circuit 3, a power circuit 4 and a power supply circuit 5. The charging circuit 1 is provided with a first output terminal VBAT and a second output terminal V-SYS. The output terminals of the bypass protection circuit 3 and the charging circuit 1 are both connected to the input terminal of the power supply circuit 5, and the output terminal of the power supply circuit 5 is connected to the input terminal of the power circuit 4.

[0023] Combination Figure 2 The switch circuit 2 includes a reset button 6 and a first resistor 7. Interface 1 of the reset button 6 is connected to the power supply, interface 2 is the output end, and interfaces 3, 4 and 5 are all grounded. The first resistor 7 is connected between the power supply and interface 1 of the reset button 6 for reducing the voltage.

[0024] Combination Figure 3, the output end of the switch circuit 2 is connected to the bypass protection circuit 3, and the bypass protection circuit 3 includes a first MOS tube 8, a second MOS tube 9, a third MOS tube 10, a second resistor 11 and a delay power-on circuit. The gate of the first MOS tube 8 is connected to the output end of the switch circuit 2, that is, the No. 2 interface of the reset button 6, the drain of the first MOS tube 8 is grounded, and the source is connected to the gates of the second MOS tube 9 and the third MOS tube 10. The second MOS tube 9, the second resistor 11 and the third MOS tube 10 are all arranged in parallel, and one end of the second resistor 11 is connected to the source of the second MOS tube 9 and the third MOS tube 10, the second MOS tube 9 is connected to the first output end VBAT of the charging circuit 1, the drain of the third MOS tube 10 is connected to the second output end V-SYS of the charging circuit 1, the first MOS tube 8 is an N-type MOS tube, and the second MOS tube 9 and the third MOS tube 10 are both P-type MOS tubes.

[0025] When the switch circuit 2 outputs a high level, the first MOS transistor 8 is turned on, and the source outputs a low level, thereby turning on the second MOS transistor 9 and the third MOS transistor 10; when the switch circuit 2 outputs a low level, the first MOS transistor 8 is not turned on, and the source outputs a high level, thereby turning off the second MOS transistor 9 and the third MOS transistor 10. The second resistor 11 is used to realize the shunting and protection functions.

[0026] A delay power-on circuit is provided at the front end of the first MOS tube 8, and the delay power-on circuit includes a diode 12, a charging capacitor 13 and a third resistor 14. The positive electrode of the diode 12 is connected to the output end of the reset button 6, and the negative electrode is connected to the gate of the first MOS tube 8; one end of the charging capacitor 13 is connected to the gate of the first MOS tube 8, and the other end is grounded; the third resistor 14 is connected between the gate of the first MOS tube 8 and the ground. When the diode 12 receives the high level of the reset button 6, the first MOS tube 8 will not be turned on immediately, and the charging capacitor 13 will continue to charge at this time. After the charging capacitor 13 is charged to a certain pressure value, the first MOS tube 8 is turned on.

[0027] Combination Figure 4 The charging circuit 1 includes a charging chip 15, the model of the charging chip 15 is CS5181E, the interface No. 7 of the charging chip 15 is connected to a 5V power supply, the interfaces No. 13 and No. 14 of the charging chip 15 are the first output terminal VBAT; the interfaces No. 4 and No. 5 of the charging chip 15 are the second output terminal V-SYS.

[0028] Combination Figure 5The power circuit 5 includes a power chip 16, a first capacitor group 17, a fourth MOS tube 18 and a second capacitor group 19. The model of the power chip 16 is RT6158HWSC. The A1 interface of the power chip 16 is connected to the second output terminal V-SYS of the charging chip 15. The first capacitor group 17 has four capacitors. The first capacitor group 17 is arranged between the second output terminal V-SYS and the A1 interface of the power chip 16. The capacitors in the first capacitor group 17 are all grounded at one end away from the A1 interface of the power chip 16. The gate of the fourth MOS tube 18 is connected to the No. 2 interface of the switch circuit 2, the drain is grounded, and the source is connected to the B5 interface of the power chip 16. The B5 interface is the EN interface; a fourth resistor 20 is arranged between the source of the fourth MOS tube 18 and the second output terminal V-SYS. The fourth resistor 20 is used for boosting. The E1 interface of the power chip 16 is connected to the power circuit 4, the E1-E4 interfaces are connected in parallel, and the E5 interface is grounded. There are three second capacitor groups 19 . One end of the second capacitor group 19 is connected to the E1 interface of the power chip 16 , and the other end is connected to the E5 interface of the power chip 16 .

[0029] The various power circuits 4 specifically include 0.8 / 1.5 / 1.8 / 3 / 3V DC-DC circuits.

[0030] When the reset button 6 is pressed, the output end of the reset button 6 becomes a high level, and the fourth MOS tube 18 is turned on after receiving the high level, the B5 interface of the power chip 16 is grounded, the power chip 16 does not work, and the subsequent voltage output is turned off. The power supply circuit 5 and the power circuit 4 are not powered, there is no load and no need to draw power, and no large current passes between the interfaces 13 and 14 of the charging chip 15 and the interfaces 4 and 5 of the charging chip 15, and the capacitive charge on the 0.8 / 1.5 / 1.8 / 3 / 3V DC-DC circuit is released.

[0031] At the same time, since the output end of the reset button 6 becomes a high level, the charging capacitor 13 is charged through the diode 12 until the first MOS tube 8 is turned on.

[0032] After the first MOS tube 8 is turned on, its drain is grounded; after being grounded, the capacitance of the first MOS tube 8 is released again, and due to the existence of the diode 12, the sources of the second MOS tube 9 and the third MOS tube 10 are at a low level, and the second MOS tube 9 and the third MOS tube 10 are turned on, thereby realizing the conduction of the first output terminal VBAT and the second output terminal V-SYS.

[0033] When the reset button 6 is released, the output end of the reset button 6 becomes a low level, and then the diode 12 is not conducting, the fourth resistor 20 pulls up the voltage of the B5 interface of the power chip 16, the power chip 16 is powered on, and the capacitors on the various power circuits 4 behind the power chip 16 begin to charge. A large current passes between the interfaces 13 and 14 of the charging chip 15 and the interfaces 4 and 5 of the charging chip 15 for a moment, thereby triggering the overcurrent protection, that is, fast charging and discharging is achieved through the delayed power-on circuit and the first MOS tube 8, so as to simply and efficiently solve the "inrush current" or "surge current" problem.

[0034] However, when the reset button 6 is released, the voltage charged on the charging capacitor 13 cannot be released immediately because it is connected to the negative electrode of the diode 12. It needs to be maintained for tens of milliseconds to maintain the continued conduction of the first MOS tube 8, the second MOS tube 9 and the third MOS tube 10, so as to achieve the output from the first output terminal VBAT to the second output terminal V-SYS, so as to share the large current passing through instantly with the charging chip 15, and avoid the overcurrent protection of the charging chip 15. When the capacitors of the various power circuits 4 are charged, no large current is generated, and the voltage on the charging capacitor 13 is slowly released. The first MOS tube 8, the second MOS tube 9 and the third MOS tube 10 are not turned on, and the bypass protection current function is exited.

[0035] Finally, it should be noted that: the drawings of the embodiments disclosed in the present invention only involve structures related to the embodiments disclosed in the present invention, and other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

[0036] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A bypass circuit for preventing overcurrent protection during reset startup, characterized in that: The invention comprises a charging circuit (1), a switch circuit (2), a bypass protection circuit (3), a power circuit (4) and a power supply circuit (5); the charging circuit (1) is provided with a first output terminal VBAT and a second output terminal V-SYS; the output terminals of the bypass protection circuit (3) and the charging circuit (1) are both connected to the input terminal of the power supply circuit (5), and the output terminal of the power supply circuit (5) is connected to the input terminal of the power circuit (4); the output terminal of the switch circuit (2) is connected to the bypass protection circuit (3), and the bypass protection circuit (3) comprises a first MOS tube (8), a diode (12), a charging circuit (4) and a charging circuit (5). The invention relates to a circuit comprising a charging capacitor (13) and a third resistor (14); the first MOS tube (8) is an N-type MOS tube; the positive electrode of the diode (12) is connected to the output end of the switch circuit (2), and the negative electrode is connected to the gate of the first MOS tube (8); one end of the charging capacitor (13) is connected to the gate of the first MOS tube (8), and the other end is grounded; the third resistor (14) is connected between the gate of the first MOS tube (8) and the ground; when the diode (12) receives a high level, the charging capacitor (13) will continue to charge, and when the charging capacitor (13) is charged to a certain pressure value, the first MOS tube (8) is turned on.

2. The bypass circuit for preventing overcurrent protection during reset startup as claimed in claim 1, characterized in that: The bypass protection circuit (3) further comprises a second MOS transistor (9), a second resistor (11) and a third MOS transistor (10); the second MOS transistor (9), the second resistor (11) and the third MOS transistor (10) are all arranged in parallel and one end of the second resistor (11) is connected to the source electrodes of the second MOS transistor (9) and the third MOS transistor (10); the second MOS transistor (9) is connected to the first output terminal VBAT of the charging circuit (1); the drain electrode of the third MOS transistor (10) is connected to the second output terminal V-SYS of the charging circuit (1); and the second MOS transistor (9) and the third MOS transistor (10) are both P-type MOS transistors.

3. The bypass circuit for preventing overcurrent protection during reset startup as claimed in claim 2, characterized in that: The charging circuit (1) comprises a charging chip (15), interface No. 7 of the charging chip (15) is connected to a 5V power supply, interfaces No. 13 and No. 14 of the charging chip (15) are a first output terminal VBAT; interfaces No. 4 and No. 5 of the charging chip (15) are a second output terminal V-SYS.

4. The bypass circuit for preventing overcurrent protection during reset startup as claimed in claim 1, characterized in that: The switch circuit (2) comprises a reset button (6) and a first resistor (7); interface No. 1 of the reset button (6) is connected to a power supply, interface No. 2 is an output end, and interfaces No. 3, 4 and 5 are all grounded; the first resistor (7) is connected between the power supply and interface No. 1 of the reset button (6).

5. The bypass circuit for preventing overcurrent protection during reset startup as claimed in claim 1, characterized in that: The power supply circuit (5) comprises a power supply chip (16), a first capacitor group (17), a fourth MOS transistor (18) and a second capacitor group (19); the A1 interface of the power supply chip (16) is connected to the second output end V-SYS of the charging chip (15); the first capacitor group (17) has four capacitors in total; the first capacitor group (17) is arranged between the second output end V-SYS and the A1 interface of the power supply chip (16); the capacitors in the first capacitor group (17) are all grounded at one end away from the A1 interface of the power supply chip (16); the gate electrode of the fourth MOS transistor (18) is connected to the ground; The electrode is connected to the No. 2 interface of the switch circuit (2), the drain is grounded, and the source is connected to the B5 interface of the power chip (16), and the B5 interface is an EN interface; a fourth resistor (20) is provided between the source of the fourth MOS tube (18) and the second output end V-SYS; the E1 interface of the power chip (16) is connected to the power circuit (4), the E1-E4 interfaces are connected in parallel, and the E5 interface is grounded; the second capacitor group (19) has three groups in total, one end of the second capacitor group (19) is connected to the E1 interface of the power chip (16), and the other end is connected to the E5 interface of the power chip (16).

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