Display device and electronic device including the same

Abstract

The utility model relates to a display device and an electronic device comprising the display device, and the display device comprises a plurality of pixels which are connected with a plurality of scanning lines and a plurality of data lines; and a data driving unit for supplying a data signal to the plurality of data lines via a plurality of output lines, the data driving unit being provided with: a signal generation unit for generating the data signal and supplying the data signal to a plurality of channel lines; and first and second amplifiers connected in parallel between each of the channel lines and each of the output lines.

Description

Technical Field

[0001] The utility model relates to a display device and an electronic device comprising the display device. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become increasingly prominent. In response, the use of display devices such as liquid crystal display devices (Liquid Crystal Display Device) and organic light emitting display devices (Organic Light Emitting Display Device) is increasing.

[0003] The display device may include pixels, and the pixels may display a predetermined image corresponding to a data signal. To this end, the display device may include a data driving unit for supplying data signals to data lines connected to the pixels via output lines. The data driving unit may include amplifiers connected to each output line, and the amplifiers may be precharged before outputting the data signals.

[0004] An electronic device (for example, a portable electronic device) including a display device has an antenna for short-range and / or long-range wireless communication. During the period when the amplifier of the data driving unit is precharged, the output line can be set to a floating state. When the output line is periodically floated, intermodulation noise may be generated in the communication frequency band of the antenna. Utility Model Content

[0005] An object of the present utility model is to provide a display device capable of minimizing intermodulation noise, a driving method thereof, and an electronic device comprising the display device.

[0006] The display device involved in the utility model comprises: a plurality of pixels, which are arranged to be connected to a plurality of scanning lines and a plurality of data lines; and a data driving unit, which is used to supply data signals to the plurality of data lines via a plurality of output lines, and the data driving unit has: a signal generating unit, which is used to generate the data signals to supply to a plurality of channel lines; and a first amplifier and a second amplifier, which are connected in parallel between each of the channel lines and each of the output lines.

[0007] According to an embodiment, the first amplifier and the second amplifier located at an i-th (i is an integer greater than or equal to 0) channel are alternately connected to an i-th output line.

[0008] According to an embodiment, the data driving unit further includes: a first transistor connected between the first amplifier and the i-th output line; a second transistor connected between the first amplifier and the i-th channel line; a third transistor connected between the second amplifier and the i-th output line; and a fourth transistor connected between the second amplifier and the i-th channel line.

[0009] According to an embodiment, the first transistor and the third transistor are alternately turned on, and the second transistor and the fourth transistor are alternately turned on.

[0010] According to an embodiment, the second transistor is turned on earlier than the first transistor and a turn-on period of the second transistor partially overlaps with a turn-on period of the first transistor.

[0011] According to an embodiment, the fourth transistor is turned on earlier than the third transistor and a turn-on period of the fourth transistor partially overlaps with a turn-on period of the third transistor.

[0012] According to an embodiment, the data driving unit further includes: a third amplifier connected in parallel with the first amplifier and the second amplifier between each of the channel lines and each of the output lines.

[0013] According to an embodiment, the first amplifier, the second amplifier, and the third amplifier located at an i-th (i is an integer greater than or equal to 0) channel are alternately connected to an i-th output line.

[0014] According to an embodiment, the data driving unit further includes: a first transistor connected between the first amplifier and the i-th output line; a second transistor connected between the first amplifier and the i-th channel line; a third transistor connected between the second amplifier and the i-th output line; a fourth transistor connected between the second amplifier and the i-th channel line; a fifth transistor connected between the third amplifier and the i-th output line; and a sixth transistor connected between the third amplifier and the i-th channel line.

[0015] According to an embodiment, the first transistor, the third transistor, and the fifth transistor are alternately turned on, and the second transistor, the fourth transistor, and the sixth transistor are alternately turned on.

[0016] According to an embodiment, the second transistor is turned on before the first transistor and its turn-on period partially overlaps with the turn-on period of the first transistor, the fourth transistor is turned on before the third transistor and its turn-on period partially overlaps with the turn-on period of the third transistor, and the sixth transistor is turned on before the fifth transistor and its turn-on period partially overlaps with the turn-on period of the fifth transistor.

[0017] The display device involved in the utility model comprises: a plurality of pixels, which are arranged to be connected to a plurality of scanning lines and a plurality of data lines; and a data driving unit, which is used to supply data signals to the plurality of data lines via a plurality of output lines, and the data driving unit has: a signal generating unit, which is used to generate the data signals to supply to a plurality of channel lines; and a first amplifier and an auxiliary amplifier, which are connected in series between each of the channel lines and each of the output lines.

[0018] According to an embodiment, the input terminal of the first amplifier located in the i-th (i is an integer greater than 0) channel is connected to the i-th channel line, and the output terminal of the auxiliary amplifier is connected to the i-th output line.

[0019] According to an embodiment, the display device further includes: a first transistor located in the i-th channel, connected between the output terminal of the first amplifier and the input terminal of the auxiliary amplifier, and turned on during a part of a horizontal period.

[0020] The driving method of the display device involved in an embodiment of the utility model includes: a step of generating a data signal corresponding to the grayscale of the data by a signal generating unit that receives data; and a step of supplying the data signal to a plurality of data lines via a plurality of output lines from an output unit connected to the signal generating unit, wherein the i-th (i is an integer greater than 0) channel of the output unit has a plurality of amplifiers, and the plurality of amplifiers are alternately connected to the i-th output line.

[0021] According to an embodiment, the plurality of amplifiers are connected to the i-th output line alternately based on a horizontal period.

[0022] According to an embodiment, each of the amplifiers is electrically connected to the i-th output line after being precharged according to the data signal supplied from the signal generating unit.

[0023] The electronic device involved in the utility model comprises: a display module for displaying a predetermined image; and a processor for supplying data corresponding to the image to the display module, and the display module comprises: a display panel for displaying the image; a gate driver for supplying a scanning signal to the display panel; and a source driver for supplying a data signal to the display panel, and each channel of the source driver that outputs the data signal comprises a plurality of amplifiers.

[0024] According to an embodiment, the plurality of amplifiers output the data signals alternately.

[0025] According to an embodiment, the plurality of amplifiers output the data signals alternately based on a horizontal period.

[0026] The subject of the present invention is not limited to the above-mentioned subject. Through the following description, those skilled in the art should be able to understand other technical subjects not mentioned.

[0027] (Effect of utility model)

[0028] According to the display device and the electronic device including the display device of the present invention, a plurality of output lines of the data driving unit can be always connected to the amplifier, thereby minimizing intermodulation noise.

[0029] However, the effects of the present invention are not limited to the above effects, and various extensions can be made without departing from the scope of the idea and field of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a diagram showing a display device according to an embodiment of the present invention.

[0031] Figure 2 is a diagram schematically showing an electronic device including a display device.

[0032] Figure 3 It is a diagram showing an embodiment of a data driving unit according to an embodiment of the present invention.

[0033] Figure 4 Yes means Figure 3 A diagram of an embodiment of an output unit is shown.

[0034] Figure 5 Yes means Figure 4 FIG. 1 is a waveform diagram of an embodiment of an output part driving method shown in FIG.

[0035] Figure 6 is a waveform diagram showing a driving method of a comparative example.

[0036] Figure 7 It is a graph showing the intermodulation noise according to the comparative example and the embodiment of the present invention.

[0037] Figure 8 Yes means Figure 3 A diagram of an embodiment of an output unit is shown.

[0038] Fig. 9 Yes means Figure 3 A diagram of an embodiment of an output unit is shown.

[0039] Fig.10 Yes means Fig. 9 FIG. 1 is a diagram showing an embodiment of an output unit driving method.

[0040] Fig.11 This is a diagram for explaining a pixel according to an embodiment of the present invention.

[0041] Fig.12 It is used to illustrate Fig.11 A diagram of an exemplary driving method for a pixel is shown.

[0042] Fig.13 It is a diagram showing an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0044] In order to clearly explain the present invention, the parts not related to the explanation are omitted, and the same or similar components are given the same symbols throughout the specification. Therefore, the symbols explained above can also be used in other drawings.

[0045] In addition, the size and thickness of each structure shown in the figure are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to the case shown in the figure. In the drawings, in order to clearly show each layer and region, the thickness is exaggerated.

[0046] Furthermore, the expression "same" in the description may mean "substantially the same". That is, it may mean the sameness to a degree that can be recognized by a person skilled in the art. Other expressions may be expressions in which "substantially" is omitted.

[0047] Some embodiments are described in the accompanying drawings attached in association with functional blocks, units and / or modules. Those skilled in the art should be able to understand that such blocks, units and / or modules can be physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, wiring connections and other electronic circuits. It can be formed using semiconductor substrate manufacturing technology or other manufacturing technologies. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, software can be used to program or control, so as to perform the various functions discussed in the utility model, and optionally, it can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or it can be implemented by a combination of dedicated hardware that performs some functions and processors that perform other functions (for example, one or more programmed microprocessors and related circuits). In addition, in some embodiments, blocks, units and / or modules can also be physically separated into two or more separate blocks, units and / or modules that act on each other without exceeding the scope of the concept of the utility model. Furthermore, in some embodiments, blocks, units and / or modules may also be physically combined into more complex blocks, units and / or modules without departing from the scope of the concept of the present invention.

[0048] The "connection" between two components may represent both electrical connection and physical connection, but is not necessarily limited thereto. For example, the "connection" used based on a circuit diagram may represent an electrical connection, and the "connection" used based on a cross-sectional view or a plan view may represent a physical connection.

[0049] Although the terms "first", "second" and the like can be used to describe various components, the components are not limited to the terms. The terms are used only to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0050] On the other hand, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms. In addition, each embodiment disclosed below can be implemented alone, or can be combined with at least one other embodiment to implement in a complex manner.

[0051] Figure 1 It is a diagram showing a display device according to an embodiment of the present invention.

[0052] Reference Figure 1 The display device 100 according to an embodiment of the present invention may include a pixel unit 110, a timing control unit 120, a scan driver 130, a data driver 140, a light driver 150, and a power supply unit 160. The above-mentioned structures may be implemented by a separate integrated circuit, and two or more of the above-mentioned structures may be unified into one integrated circuit. In addition, the scan driver 130 and / or the light driver 150 may be formed in the pixel unit 110.

[0053] The pixel portion 110 may include a plurality of pixels PX (here, n, m, o are integers greater than 0) connected to scanning lines SL0, SL1, SL2, ..., SLn, data lines DL1, DL2, ..., DLm, light emitting control lines EL1, EL2, ..., ELo and power lines PL1, PL2, PL3.

[0054] When a scan signal is supplied to the scan lines SL0 to SLn, the pixel PX can be selected in units of horizontal lines (for example, the pixels PX connected to the same scan line can be classified into one horizontal line (or pixel row)), and the pixel PX selected according to the scan signal can receive a data signal from the data line (any one of DL1 to DLm) connected to itself. The pixel PX that receives the data signal can generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0055] The scan driving unit 130 may receive a scan driving signal SCS from the timing control unit 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required for driving the scan driving unit 130. The scan driving unit 130 may generate a scan signal while shifting the scan start signal corresponding to the clock signal. The scan signal may be set to a gate-on voltage so that the transistor included in the pixel PX can be turned on.

[0056] As an example, a low-level scan signal can be supplied to a P-type transistor, and a high-level scan signal can be supplied to an N-type transistor. The transistor that receives the scan signal can be turned on corresponding to the scan signal. Hereinafter, "supplying a scan signal" can mean supplying a gate-on voltage to the scan line SL. In addition, "not supplying a scan signal" can mean supplying a gate-off voltage to the scan line SL.

[0057] The data driving unit 140 may receive the output data Dout and the data driving signal DCS from the timing control unit 120. The data driving signal DCS may include a sampling signal and / or a timing signal required for driving the data driving unit 140. The data driving unit 140 may generate a data signal based on the data driving signal DCS and the output data Dout. As an example, the data driving unit 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driving unit 140 may supply the data signal in units of horizontal periods.

[0058] The light emitting driving unit 150 may receive a light emitting driving signal ECS from the timing control unit 120. The light emitting driving signal ECS may include a light emitting start signal and a clock signal required for driving the light emitting driving unit 150. The light emitting driving unit 150 may shift the light emitting start signal corresponding to the clock signal and generate a light emitting control signal. The light emitting control signal may be set to a gate-off voltage so that the transistor included in the pixel PX can be turned off.

[0059] As an example, the light emitting control signal supplied to the P-type transistor may be set to a high level, and the light emitting control signal supplied to the N-type transistor may be set to a low level. The transistor receiving the light emitting control signal may be turned off corresponding to the light emitting control signal. Hereinafter, "supplying a light emitting control signal" may mean supplying a gate-off voltage to the light emitting control line EL. In addition, "not supplying a light emitting control signal" may mean supplying a gate-on voltage to the light emitting control line EL.

[0060] The timing control unit 120 may receive input data Din and control signal CS from the host system through an interface. As an example, the timing control unit 120 may receive input data Din and control signal CS from at least one of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and an AP (Application Processor) included in the host system. The control signal CS may include various signals including a clock signal.

[0061] The timing control unit 120 may generate a scan drive signal SCS, a data drive signal DCS, and a light emitting drive signal ECS based on the control signal CS. The scan drive signal SCS may be supplied to the scan drive unit 130, the data drive signal DCS may be supplied to the data drive unit 140, and the light emitting drive signal ECS may be supplied to the light emitting drive unit 150.

[0062] The timing control unit 120 may realign the input data Din in accordance with the specification of the display device 100. In addition, the timing control unit 120 may correct the input data Din to generate output data Dout, and supply the output data Dout to the data driving unit 140. In an embodiment, the timing control unit 120 may correct the input data Din corresponding to the optical measurement result measured during the process.

[0063] The power supply unit 160 may generate various power sources required for driving the display device 100. As an example, the power supply unit 160 may generate a first driving power source VDD, a second driving power source VSS, and an initialization power source Vint.

[0064] The first driving power supply VDD may be a power supply for supplying a driving current to the pixel PX. The second driving power supply VSS may be a power supply for receiving a driving current from the pixel PX. The initialization power supply Vint may be a power supply for initializing a gate electrode of a driving transistor included in each pixel PX. During a period in which the pixel PX is set to a light emitting state, the first driving power supply VDD may be set to a voltage higher than the second driving power supply VSS.

[0065] The first driving power VDD generated by the power supply unit 160 may be supplied to the first power line PL1, the second driving power VSS generated by the power supply unit 160 may be supplied to the second power line PL2, and the initialization power Vint generated by the power supply unit 160 may be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the pixel PX, but the embodiment of the utility model is not limited thereto.

[0066] In an embodiment, the first power line PL1 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in an embodiment of the present utility model, the pixel PX may be connected to any one of the first power line PL1, any one of the second power line PL2, and any one of the third power line PL3.

[0067] Figure 2 is a diagram schematically showing an electronic device including a display device.

[0068] Reference Figure 2 The electronic device 1000 may include a housing 1002 , a window portion 190 , a panel 170 , a first flexible circuit substrate 172 , a second flexible circuit substrate 1004 , an antenna module 1006 , a driver integrated circuit (IC) 180 , a first connection portion 182 , and a second connection portion 1003 .

[0069] The housing 1002 may provide a predetermined storage space for configuring various configurations. The housing 1002 may be combined with the window portion 190. The window portion 190 may be configured on the front surface of the housing 1002. The housing 1002 may be combined with the window portion 190 to provide a predetermined storage space.

[0070] The housing 1002 may include a relatively rigid material. For example, the housing 1002 may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed of a combination of these materials. The housing 1002 may stably protect the components stored in the internal space from external impacts.

[0071] The window portion 190 may cover the entire outer side of the panel 170 of the electronic device 1000. The window portion 190 may have a shape corresponding to the panel 170. The window portion 190 may include an optically transparent insulating material. As an example, the window portion 190 may be a glass substrate or a polymer substrate. For example, the window portion 190 may be a tempered glass substrate.

[0072] Panel 170 may include Figure 1 The pixel unit 110, the scanning driving unit 130 and the light emitting driving unit 150 are shown. The panel 170 can generate an image and can further include a structure for sensing input applied from the outside. To this end, the panel 170 can include a display layer, a sensor layer, and the like.

[0073] The first flexible circuit substrate 172 may be electrically connected to the driver IC 180. As an example, the driver IC 180 may be mounted on the first flexible circuit substrate 172. In this case, the first flexible circuit substrate 172 may be referred to as a chip on film (CoF).

[0074] The driving IC 180 may supply various signals required for driving the panel 170. As an example, the driving IC 180 may generate a data signal and supply it to the panel 170. In this case, the driving IC 180 may include a data driving unit 140. The driving IC 180 may further include a timing control unit 120. The driving IC 180 may include Figure 1 The one or more structures shown supply various signals (for example, SCS and ECS) including data signals to the panel 170 .

[0075] The driving IC 180 may be electrically connected to the panel 170 through the first connection portion 182. The first connection portion 182 may include a bending region, and electrically connects the driving IC 180 to the panel 170 via the bending region. The first connection portion 182 may be a flexible circuit substrate.

[0076] The second flexible circuit substrate 1004 may include various components included in the host system. As an example, the second flexible circuit substrate 1004 may include at least one of a GPU, a CPU, and an AP. The second flexible circuit substrate 1004 may be electrically connected to the first flexible circuit substrate 172 via the second connection portion 1003. The second flexible circuit substrate 1004 may supply input data Din and a control signal CS to the driver IC 180 via the first flexible circuit substrate 172.

[0077] The antenna module 1006 can perform wireless communication of the electronic device 1000, and can perform short-range and / or long-range wireless communication as an example. As an example, the antenna module 1006 can perform wireless communication using a predetermined transmission frequency band and a reception frequency band. Such an antenna module 1006 can be attached to the housing 1002 and can be arranged adjacent to the driver IC 180.

[0078] On the other hand, since the antenna module 1006 is disposed adjacent to the driving IC 180 , when the output line of the data driving part 140 is periodically floated, intermodulation noise may be generated in the communication frequency band of the antenna.

[0079] Figure 3 It is a diagram showing an embodiment of a data driving unit according to an embodiment of the present invention.

[0080] Reference Figure 3The data driving unit 140 according to the embodiment of the present invention may include a signal generating unit 142 and an output unit 144 .

[0081] The signal generating unit 142 may receive the output data Dout and the data driving signal DCS from the timing control unit 120. The signal generating unit 142 may sequentially store the output data Dout corresponding to the data driving signal DCS, and generate the data signal using the stored output data Dout. To this end, the signal generating unit 142 may include a plurality of latches and a plurality of digital-to-analog converters. As an example, the signal generating unit 142 may include a plurality of channels, each of which may include a latch and a digital-to-analog converter.

[0082] The signal generating section 142 may be connected to the output section 144 via channel lines CL1, CL2, ..., CLm. The data signal generated by the signal generating section 142 may be supplied to the output section 144 via the channel lines CL1 to CLm.

[0083] The output unit 144 can supply data signals to the output lines OL1, OL2, ..., OLm located in each of the channels. To this end, the output unit 144 can include at least one amplifier located in each of the channels. Each amplifier can be precharged when supplying a data signal to a channel line (any one of CL1 to CLm) connected to itself, and supply the voltage of the precharged data signal to the output line (any one of OL1 to OLm) connected to itself. As an example, each amplifier can amplify the data signal supplied from the channel line (any one of CL1 to CLm) and supply it to the output line (any one of OL1 to OLm).

[0084] The output lines OL1 to OLm may be electrically connected to the data lines DL1, DL2, ..., DLm in the junctions 1461, 1462, ..., 146m. As an example, the first output line OL1 may be electrically connected to the first data line DL1 in the first junction 1461. As an example, the m-th output line OLm may be electrically connected to the m-th data line DLm in the m-th junction 146m. As an example, the junctions 1461 to 146m may be formed of pads or the like.

[0085] Figure 4 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of an output unit shown in FIG. Figure 4 2 shows the i-th (i is an integer greater than or equal to 0) channel of the output unit 144. The configurations of the other channels included in the output unit 144 may be substantially the same as that of the i-th channel.

[0086] Reference Figure 4The i-th channel of the output unit 144 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first amplifier Amp1, and a second amplifier Amp2.

[0087] The first transistor M1 to the fourth transistor M4 may be turned on when the control signals CS1, CS2, CS3, and CS4 are supplied, and may be turned off when the control signals CS1, CS2, CS3, and CS4 are not supplied. Here, supplying the control signals CS1 to CS4 may indicate supplying a gate-on voltage to the gate electrodes of the first transistor M1 to the fourth transistor M4, and not supplying the control signals CS1 to CS4 may indicate supplying a gate-off voltage to the gate electrodes of the first transistor M1 to the fourth transistor M4.

[0088] The first transistor M1 may be connected between the i-th output line OLi and the first amplifier Amp1. The first transistor M1 as described above may be turned on when the first control signal CS1 is supplied, and may be turned off when the first control signal CS1 is not supplied.

[0089] The second transistor M2 may be connected between the i-th channel line CLi and the first amplifier Amp1. The second transistor M2 as described above may be turned on when the second control signal CS2 is supplied, and may be turned off when the second control signal CS2 is not supplied.

[0090] An input terminal of the first amplifier Amp1 may be connected to the second transistor M2, and an output terminal of the first amplifier Amp1 may be connected to the first transistor M1. The first amplifier Amp1 may supply a data signal to the i-th data line DLi (or the i-th output line OLi).

[0091] The third transistor M3 may be connected between the i-th output line OLi and the second amplifier Amp2. The third transistor M3 as described above may be turned on when the third control signal CS3 is supplied, and may be turned off when the third control signal CS3 is not supplied.

[0092] The fourth transistor M4 may be connected between the i-th channel line CLi and the second amplifier Amp2. The fourth transistor M4 as described above may be turned on when the fourth control signal CS4 is supplied, and may be turned off when the fourth control signal CS4 is not supplied.

[0093] An input terminal of the second amplifier Amp2 may be connected to the fourth transistor M4, and an output terminal of the second amplifier Amp2 may be connected to the third transistor M3. The second amplifier Amp2 may supply a data signal to the i-th data line DLi (or the i-th output line OLi).

[0094] A first transistor M1, a first amplifier Amp1, and a second transistor M2 may be connected in series between the i-th channel line CLi and the i-th output line OLi. A third transistor M3, a second amplifier Amp2, and a fourth transistor M4 may be connected in series between the i-th channel line CLi and the i-th output line OLi. In this case, the third transistor M3, the second amplifier Amp2, and the fourth transistor M4 may be connected in parallel with the first transistor M1, the first amplifier Amp1, and the second transistor M2 between the i-th channel line CLi and the i-th output line OLi.

[0095] In an embodiment, the first amplifier Amp1 and the second amplifier Amp2 may alternately supply data signals to the i-th data line DLi (or the i-th output line OLi). In an embodiment, the first amplifier Amp1 and the second amplifier Amp2 may alternately supply data signals to the i-th data line DLi every horizontal period.

[0096] Figure 5 Yes means Figure 4 FIG. 1 is a waveform diagram of an embodiment of an output part driving method shown in FIG.

[0097] Reference Figure 5 In two adjacent horizontal periods 1H and 2H, a data signal is supplied from the first amplifier Amp1 to the i-th data line DLi in the first horizontal period 1H, and a data signal is supplied from the second amplifier Amp2 to the i-th data line DLi in the second horizontal period 2H.

[0098] The second control signal CS2 is supplied in the first period T1 of the first horizontal period 1H, and the second transistor M2 is turned on. The second transistor M2 may also remain turned on in the horizontal period before the first horizontal period 1H. If the second transistor M2 is turned on, the first amplifier Amp1 may be precharged.

[0099] In the first period T1 and the second period T2 of the first horizontal period 1H, the first control signal CS1 is supplied so that the first transistor M1 can be turned on. If the first transistor M1 is turned on, the first amplifier Amp1 can be electrically connected to the i-th data line DLi via the first transistor M1, the i-th output line OLi and the i-th junction 146i. At this time, the first amplifier Amp1 can supply a data signal to the i-th data line DLi.

[0100] On the other hand, in the second period T2, the fourth control signal CS4 is supplied, so that the fourth transistor M4 can be turned on. If the fourth transistor M4 is turned on, the second amplifier Amp2 can be precharged by the voltage from the i-th channel line CLi. That is, the second amplifier Amp2 can be precharged before supplying the data signal to the i-th data line DLi, thereby stably outputting the data signal voltage. The fourth transistor M4 can maintain a conductive state in the third period T3 of the second horizontal period 2H by the fourth control signal CS4.

[0101] In the third period T3 and the fourth period T4 of the second horizontal period 2H, the third control signal CS3 is supplied so that the third transistor M3 can be turned on. If the third transistor M3 is turned on, the second amplifier Amp2 can be electrically connected to the i-th data line DLi via the third transistor M3, the i-th output line OLi and the i-th junction 146i. At this time, the second amplifier Amp2 can supply a data signal to the i-th data line DLi.

[0102] In the fourth period T4 of the second horizontal period 2H, the second control signal CS2 is supplied, so that the second transistor M2 is turned on. If the second transistor M2 is turned on, the first amplifier Amp1 can be precharged by the voltage from the i-th channel line CLi. That is, the first amplifier Amp1 can be precharged before supplying the data signal to the i-th data line DLi, thereby stably outputting the data signal voltage.

[0103] In practice, the first amplifier Amp1 and the second amplifier Amp2 included in each channel of the output unit 144 may alternately supply data signals to the data lines (any one of DL1 to DLm) every horizontal period while repeating the above-mentioned process.

[0104] The first transistor M1 and the third transistor M3 may be turned on and off alternately with each other. To this end, the third control signal CS3 may have a phase opposite to that of the first control signal CS1 while having the same cycle. When the first transistor M1 and the third transistor M3 are turned on and off alternately with each other, the i-th output line OLi may be alternately connected to the first amplifier Amp1 or the second amplifier Amp2.

[0105] The second transistor M2 and the fourth transistor M4 may be turned on and off alternately with each other. To this end, the fourth control signal CS4 may have a phase opposite to that of the second control signal CS2 while having the same cycle. When the second transistor M2 and the fourth transistor M4 are turned on and off alternately with each other, the i-th channel line CLi may be alternately connected to the first amplifier Amp1 or the second amplifier Amp2.

[0106] The second transistor M2 may be turned on before the first transistor M1, and its on period may partially overlap with the on period of the first transistor M1. The fourth transistor M4 may be turned on before the third transistor M3, and its on period may partially overlap with the on period of the third transistor M3.

[0107] On the other hand, as described above, during the driving process of the display device 100, the i-th output line OLi maintains the state of being connected to the first amplifier Amp1 or the second amplifier Amp2. That is, during the driving process of the display device 100, the i-th output line OLi is not set to a floating state. In the case where the i-th output line OLi is not set to a floating state as described above, intermodulation noise can be minimized in the communication frequency band of the antenna module 1006.

[0108] On the other hand, Figure 5 In FIG. 1 , the outputs of the first amplifier Amp1 and the second amplifier Amp2 do not consider the voltage of the i-th data line DLi, and only the voltages outputted from the first amplifier Amp1 and the second amplifier Amp2 are shown. As an example, the output voltages of the first amplifier Amp1 and the second amplifier Amp2 may not drop sharply due to the voltage of the i-th data line DLi.

[0109] Figure 6 is a waveform diagram showing a driving method of a comparative example. Figure 6 In the comparative example, Figure 4 The circuit of FIG. 1 removes the second transistor M2, the third transistor M3, the fourth transistor M4 and the second amplifier Amp2.

[0110] Reference Figure 6 First, the horizontal period H can be divided into an 11th period T11 and a 12th period T12 for driving.

[0111] In the 12th period T12 before the specific horizontal period, the first amplifier Amp1 may be precharged by the voltage supplied from the i-th channel line CLi. After the first amplifier Amp1 is precharged, the first control signal CS1 is supplied in the 11th period T11 of the specific horizontal period, so that the first transistor M1 may be turned on. If the first transistor M1 is turned on, the data signal is supplied from the first amplifier Amp1 to the i-th data line DLi via the i-th output line OLi.

[0112] In the 12th period T12 of the specific horizontal period, the supply of the first control signal CS1 is interrupted, so that the first transistor M1 is turned off. If the first transistor M1 is turned off, the i-th output line OLi and the first amplifier Amp1 are disconnected. In the 12th period T12 of the specific horizontal period, the first amplifier Amp1 can be precharged by the voltage supplied from the i-th channel line CLi. In the case of the comparative example, the data signal can be supplied to the i-th data line DLi while repeating the above process.

[0113] On the other hand, in the comparative example, the i-th output line OLi may be set to a floating state periodically (for example, in the 12th period T12). When the i-th output line OLi is periodically set to a floating state, intermodulation noise may be generated in the communication frequency band of the antenna module 1006.

[0114] Figure 7 : is a graph showing the intermodulation noise involved in the comparative example and the embodiment of the present utility model. Figure 7 In the diagram, the X-axis represents frequency and the Y-axis represents decibel milliwatt (dBm).

[0115] Reference Figure 7 , when the i-th output line OLi is periodically floated as in the comparative example, intermodulation noise is generated in the communication frequency band of the antenna module 1006. In contrast, in the embodiment ( Figure 4 and Figure 5 ), the i-th output line OLi is always connected to the amplifier (Amp1 or Amp2), thereby minimizing intermodulation noise in the communication frequency band of the antenna module 1006.

[0116] Figure 8 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of an output unit shown in FIG. Figure 8 , the i-th (i is an integer greater than or equal to 0) channel of the output unit 144 is shown. The configurations of the other channels included in the output unit 144 may be substantially the same as that of the i-th channel.

[0117] Reference Figure 8 The channel of the output unit 144 may include a first amplifier Amp1a, a first transistor M1a, and an auxiliary amplifier aAmp. The first amplifier Amp1a, the first transistor M1a, and the auxiliary amplifier aAmp may be connected in series between the i-th channel line CLi and the i-th output line OLi.

[0118] In an embodiment, an input terminal of the first amplifier Amp1a may be connected to the i-th channel line CLi. In an embodiment, an output terminal of the auxiliary amplifier aAmp may be connected to the i-th output line OLi. The first transistor M1a may be connected between the output terminal of the first amplifier Amp1a and the input terminal of the auxiliary amplifier aAmp. The first transistor M1a may be turned on when the first control signal CS1 is supplied, and turned off when the first control signal CS1 is not supplied.

[0119] As an example, the first transistor M1a may be Figure 6 The first amplifier Amp1a may output a data signal during the 11th period T11 and be precharged during the 12th period T12. The auxiliary amplifier aAmp may receive a data signal from the first amplifier Amp1a during the 11th period T11 and output the received data signal to the i-th output line OLi.

[0120] In the above-described embodiment of the present invention, the output line OLi can be always electrically connected to the auxiliary amplifier aAmp. As described above, when the i-th output line OLi is always electrically connected to the auxiliary amplifier aAmp, the intermodulation noise can be minimized in the communication frequency band of the antenna module 1006.

[0121] On the other hand, Figure 8 In the embodiment of FIG. 1 , the auxiliary amplifier aAmp outputs a data signal without precharging. In this case, when the display device 100 is driven at a high driving frequency (or when the horizontal period H is shortened), a data signal of a desired voltage cannot be supplied to the pixel PX.

[0122] therefore, Figure 8 The embodiment of the present invention may be applicable to the case where the display device 100 is driven at a low driving frequency and a data signal with a sufficient voltage is supplied to the pixel PX via the auxiliary amplifier aAmp. Figure 8 The output unit 144 of the display device 100 according to the embodiment can be determined through experiments.

[0123] Fig. 9 Yes means Figure 3 FIG. 1 is a diagram of an embodiment of an output unit shown in FIG. Fig. 9 2 shows the i-th (i is an integer greater than or equal to 0) channel of the output unit 144. The configurations of the other channels included in the output unit 144 may be substantially the same as that of the i-th channel.

[0124] Reference Fig. 9The output unit 144 may include a first transistor M1b, a second transistor M2b, a third transistor M3b, a fourth transistor M4b, a fifth transistor M5, a sixth transistor M6, a first amplifier Amp1b, a second amplifier Amp2b, and a third amplifier Amp3.

[0125] The first transistor M1b to the sixth transistor M6 may be turned on when the control signals CS1b, CS2b, CS3b, CS4b, CS5, and CS6 are supplied, and may be turned off when the control signals CS1b, CS2b, CS3b, CS4b, CS5, and CS6 are not supplied. Here, supplying the control signals CS1b to CS6 may indicate supplying a gate-on voltage to the gate electrodes of the first transistor M1b to the sixth transistor M6, and not supplying the control signals CS1b to CS6 may indicate supplying a gate-off voltage to the gate electrodes of the first transistor M1b to the sixth transistor M6.

[0126] The first transistor M1b may be connected between the i-th output line OLi and the first amplifier Amp1b. The first transistor M1b as described above may be turned on when the first control signal CS1b is supplied, and may be turned off when the first control signal CS1b is not supplied.

[0127] The second transistor M2b may be connected between the i-th channel line CLi and the first amplifier Amp1b. The second transistor M2b as described above may be turned on when the second control signal CS2b is supplied, and may be turned off when the second control signal CS2b is not supplied.

[0128] An input terminal of the first amplifier Amp1b may be connected to the second transistor M2b, and an output terminal of the first amplifier Amp1b may be connected to the first transistor M1b. The first amplifier Amp1b may supply a data signal to the i-th data line DLi (or the i-th output line OLi).

[0129] The third transistor M3b may be connected between the i-th output line OLi and the second amplifier Amp2b. The third transistor M3b as described above may be turned on when the third control signal CS3b is supplied, and may be turned off when the third control signal CS3b is not supplied.

[0130] The fourth transistor M4b may be connected between the i-th channel line CLi and the second amplifier Amp2b. The fourth transistor M4b as described above may be turned on when the fourth control signal CS4b is supplied, and may be turned off when the fourth control signal CS4b is not supplied.

[0131] An input terminal of the second amplifier Amp2b may be connected to the fourth transistor M4b, and an output terminal thereof may be connected to the third transistor M3b. The second amplifier Amp2b may supply a data signal to the i-th data line DLi (or the i-th output line OLi).

[0132] The fifth transistor M5 may be connected between the i-th output line OLi and the third amplifier Amp3. The fifth transistor M5 as described above may be turned on when the fifth control signal CS5 is supplied, and may be turned off when the fifth control signal CS5 is not supplied.

[0133] The sixth transistor M6 may be connected between the i-th channel line CLi and the third amplifier Amp3. The sixth transistor M6 as described above may be turned on when the sixth control signal CS6 is supplied, and may be turned off when the sixth control signal CS6 is not supplied.

[0134] An input terminal of the third amplifier Amp3 may be connected to the sixth transistor M6, and an output terminal thereof may be connected to the fifth transistor M5. The third amplifier Amp3 may supply a data signal to the i-th data line DLi (or the i-th output line OLi).

[0135] Between the i-th channel line CLi and the i-th output line OLi, a first transistor M1b, a first amplifier Amp1b, and a second transistor M2b may be connected in series. Between the i-th channel line CLi and the i-th output line OLi, a third transistor M3b, a second amplifier Amp2b, and a fourth transistor M4b may be connected in series. Between the i-th channel line CLi and the i-th output line OLi, a fifth transistor M5, a third amplifier Amp3, and a sixth transistor M6 may be connected in series.

[0136] Between the i-th channel line CLi and the i-th output line OLi, the third transistor M3b, the second amplifier Amp2b, and the fourth transistor M4b may be connected in parallel with the first transistor M1b, the first amplifier Amp1b, and the second transistor M2b. Between the i-th channel line CLi and the i-th output line OLi, the fifth transistor M5, the third amplifier Amp3, and the sixth transistor M6 may be connected in parallel with the first transistor M1b, the first amplifier Amp1b, and the second transistor M2b.

[0137] In an embodiment, the first amplifier Amp1b, the second amplifier Amp2b, and the third amplifier Amp3 may alternately supply data signals to the i-th data line DLi. As an example, the first amplifier Amp1b, the second amplifier Amp2b, and the third amplifier Amp3 electrically connected to the i-th output line OLi may be set differently in each horizontal period. In an embodiment, the first amplifier Amp1b, the second amplifier Amp2b, and the third amplifier Amp3 may be electrically connected to the i-th output line OLi in sequence.

[0138] Fig.10 Yes means Fig. 9 FIG. 1 is a diagram showing an embodiment of an output unit driving method.

[0139] Reference Fig.10 During the three adjacent horizontal periods 1H, 2H, and 3H, a data signal is supplied from the first amplifier Amp1b to the i-th data line DLi during the first horizontal period 1H, a data signal is supplied from the second amplifier Amp2b to the i-th data line DLi during the second horizontal period 2H, and a data signal is supplied from the third amplifier Amp3 to the i-th data line DLi during the third horizontal period 3H.

[0140] In the first period T1b of the first horizontal period 1H, the second control signal CS2b is supplied so that the second transistor M2b can be turned on. The second transistor M2b can also be kept turned on in the horizontal period before the first horizontal period 1H. If the second transistor M2b is turned on, the first amplifier Amp1b can be precharged.

[0141] In the first period T1b and the second period T2b of the first horizontal period 1H, the first control signal CS1b is supplied so that the first transistor M1b can be turned on. If the first transistor M1b is turned on, the first amplifier Amp1b is electrically connected to the i-th data line DLi via the first transistor M1b, the i-th output line OLi and the i-th junction 146i. At this time, the first amplifier Amp1b can supply a data signal to the i-th data line DLi.

[0142] On the other hand, in the second period T2b, the fourth control signal CS4b is supplied, so that the fourth transistor M4b can be turned on. If the fourth transistor M4b is turned on, the second amplifier Amp2b can be precharged by the voltage from the i-th channel line CLi. That is, the second amplifier Amp2b can be precharged before supplying the data signal to the i-th data line DLi, thereby stably outputting the data signal voltage.

[0143] In the third period T3b and the fourth period T4b of the second horizontal period 2H, the third control signal CS3b is supplied so that the third transistor M3b can be turned on. If the third transistor M3b is turned on, the second amplifier Amp2b can be electrically connected to the i-th data line DLi via the third transistor M3b, the i-th output line OLi and the i-th junction 146i. At this time, the second amplifier Amp2b can supply a data signal to the i-th data line DLi.

[0144] In the fourth period T4b of the second horizontal period 2H, the sixth control signal CS6 is supplied, so that the sixth transistor M6 is turned on. If the sixth transistor M6 is turned on, the third amplifier Amp3 can be precharged by the voltage from the i-th channel line CLi. That is, the third amplifier Amp3 can be precharged before supplying the data signal to the i-th data line DLi, thereby stably outputting the data signal voltage.

[0145] During the fifth period T5 and the sixth period T6 of the third horizontal period 3H, the fifth control signal CS5 is supplied so that the fifth transistor M5 can be turned on. If the fifth transistor M5 is turned on, the third amplifier Amp3 can be electrically connected to the i-th data line DLi via the fifth transistor M5, the i-th output line OLi and the i-th junction 146i. At this time, the third amplifier Amp3 can supply a data signal to the i-th data line DLi.

[0146] In the sixth period T6 of the third horizontal period 3H, the second control signal CS2b is supplied, so that the second transistor M2b is turned on. If the second transistor M2b is turned on, the first amplifier Amp1b can be precharged by the voltage from the i-th channel line CLi. That is, the first amplifier Amp1b can be precharged before supplying the data signal to the i-th data line DLi, thereby stably outputting the data signal voltage.

[0147] In practice, the first amplifier Amp1 b , the second amplifier Amp2 b , and the third amplifier Amp3 included in each channel of the output unit 144 may supply a data signal to the data line (any one of DL1 to DLm) while repeatedly performing the above process.

[0148] The conduction periods of the first transistor M1b, the third transistor M3b, and the fifth transistor M5 do not overlap. As an example, the first transistor M1b, the third transistor M3b, and the fifth transistor M5 can be turned on during different horizontal periods. As an example, the first transistor M1b can be turned on during the first horizontal period of 1H, the third transistor M3b can be turned on during the second horizontal period of 2H, and the fifth transistor M5 can be turned on during the third horizontal period of 3H.

[0149] The conduction periods of the second transistor M2b, the fourth transistor M4b, and the sixth transistor M6 do not overlap. The second transistor M2b may be turned on before the first transistor M1b, and the conduction period may partially overlap with the conduction period of the first transistor M1b. The fourth transistor M4b may be turned on before the third transistor M3b, and the conduction period may partially overlap with the conduction period of the third transistor M3b. The sixth transistor M6 may be turned on before the fifth transistor M5, and the conduction period may partially overlap with the conduction period of the fifth transistor M5.

[0150] Fig.11 1 is a diagram for explaining a pixel according to an embodiment of the present invention. Fig.11 In FIG. 1 , a pixel PXij connected to an i-th scanning line and a j-th data line (j is an integer greater than or equal to 0) is shown.

[0151] Reference Fig.11A pixel PXij according to an embodiment of the present invention includes transistors M11, M12, M13, M14, M15, M16, M17, a storage capacitor Cst, and a light emitting element LD.

[0152] In the following, a circuit composed of P-type transistors is used as an example for explanation. However, a person skilled in the art should be able to design a circuit composed of N-type transistors by making the polarity of the voltage applied to the gate terminal different. Similarly, a person skilled in the art should be able to design a circuit composed of a combination of P-type transistors and N-type transistors. Transistors can be constructed in various forms such as TFT (thin film transistor), FET (field effect transistor), BJT (bipolar junction transistor), etc.

[0153] The first transistor M11 may have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor M11 may be named a driving transistor.

[0154] The second transistor M12 may have a gate electrode connected to the scan line SLi1 , a first electrode connected to the data line DLj, and a second electrode connected to the second node N2 .

[0155] The third transistor M13 may have a gate electrode connected to the scan line SLi2 , a first electrode connected to the third node N3 , and a second electrode connected to the first node N1 .

[0156] The fourth transistor M14 may have a gate electrode connected to the scan line SLi3 , a first electrode connected to the first node N1 , and a second electrode connected to the third power line PL3 .

[0157] The fifth transistor M15 may have a gate electrode connected to the i-th light emitting control line ELi, a first electrode connected to the first power line PL1, and a second electrode connected to the second node N2. The fifth transistor M15 may be named a light emitting transistor.

[0158] The sixth transistor M16 may have a gate electrode connected to the i-th light emitting control line ELi, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light emitting element LD. The sixth transistor M16 may be named a light emitting transistor. In other embodiments, the gate electrode of the sixth transistor M16 may also be connected to a light emitting control line different from the gate electrode of the fifth transistor M15.

[0159] The seventh transistor M17 may have a gate electrode connected to the scan line SLi4 , a first electrode connected to the third power line PL3 , and a second electrode connected to the anode of the light emitting element LD.

[0160] A first electrode of the storage capacitor Cst may be connected to the first power line PL1 , and a second electrode of the storage capacitor Cst may be connected to the first node N1 .

[0161] The light emitting element LD may be an anode connected to the second electrode of the sixth transistor M16 and a cathode connected to the second power line PL2. The light emitting element LD may be a light emitting diode. The light emitting element LD may be composed of an organic light emitting diode, an inorganic light emitting diode, a quantum dot / quantum well light emitting diode, etc. In addition, in the present embodiment, the pixel PXij has only one light emitting element LD, but in other embodiments, the pixel PXij may also have multiple light emitting elements. At this time, the multiple light emitting elements may be connected in series, in parallel, in series and in parallel, etc.

[0162] The voltage of the first driving power supply VDD may be applied to the first power line PL1, the voltage of the second driving power supply VSS may be applied to the second power line PL2, and the voltage of the initialization power supply Vint may be applied to the third power line PL3. For example, the first driving power supply VDD may have a higher voltage than the second driving power supply VSS. For example, the initialization power supply Vint may have a voltage that is the same as or higher than the second driving power supply VSS. For example, the initialization power supply Vint may have a voltage lower than the voltage of the data signal.

[0163] Fig.12 It is used to illustrate Fig.11 A diagram of an exemplary driving method for a pixel is shown.

[0164] In the following, for the sake of convenience, it is assumed that the scan lines SLi1, SLi2, and SLi4 are the i-th scan line SLi and the scan line SLi3 is the i-1th scan line SL(i-1). However, the connection relationship between the scan lines SLi1, SLi2, SLi3, and SLi4 may be different according to the embodiment. For example, the scan line SLi4 may also be the i-1th scan line SL(i-1) or the i+1th scan line.

[0165] First, a light emitting control signal of a cut-off level (logic high level) is applied to the i-th light emitting control line ELi, a data signal DATA(i-1)j for the i-1-th pixel is applied to the data line DLj, and a scanning signal of a conduction level (logic low level) is applied to the scanning line SLi3. The high / low of the logic level may be different depending on whether the transistor is a P-type or an N-type.

[0166] At this time, a scan signal of an off level is applied to the scan lines SLi1 and SLi2, so the second transistor M12 is in an off state, preventing the data signal DATA(i-1)j for the i-1th pixel from being introduced into the pixel PXij.

[0167] At this time, the fourth transistor M14 is in the on state, so the first node N1 is connected to the third power line PL3, so that the voltage of the first node N1 is initialized. Since the light emitting control signal of the off level is applied to the i-th light emitting control line ELi, the fifth transistor M15 and the sixth transistor M16 are in the off state, preventing unnecessary light emission of the light emitting element LD caused by the application process of the initialization voltage.

[0168] Next, a data signal DATAij for the i-th pixel PXij is applied to the data line DLj, and a scanning signal of a conduction level is applied to the scanning lines SLi1 and SLi2. As a result, the second transistor M12, the first transistor M11, and the third transistor M13 are in a conducting state, and the data line DLj is electrically connected to the first node N1. Therefore, a compensation voltage obtained by subtracting the threshold voltage of the first transistor M11 from the data signal DATAij is applied to the second electrode (i.e., the first node N1) of the energy storage capacitor Cst, and the energy storage capacitor Cst maintains a voltage equivalent to the difference between the voltage of the first driving power supply VDD and the compensation voltage. This period can be named a threshold voltage compensation period or a data writing period.

[0169] In addition, when the scan line SLi4 is the i-th scan line SLi, since the seventh transistor M17 is in the on state, the anode of the light-emitting element LD is connected to the third power line PL3, and the light-emitting element LD is initialized with a charge amount equivalent to the difference between the voltage of the initialization power supply Vint and the voltage of the second driving power supply VSS.

[0170] Next, a light emitting control signal of a turn-on level is applied to the i-th light emitting control line ELi, so that the fifth transistor M15 and the sixth transistor M16 can be turned on. Thus, a current path connecting the first power line PL1, the fifth transistor M15, the first transistor M11, the sixth transistor M16, the light emitting element LD and the second power line PL2 is formed.

[0171] According to the voltage maintained by the energy storage capacitor Cst, the amount of driving current flowing to the first electrode and the second electrode of the first transistor M11 is adjusted. The light emitting element LD emits light at a brightness corresponding to the amount of driving current. The light emitting element LD emits light until a light emitting control signal of a cutoff level is applied to the i-th light emitting control line ELi.

[0172] When the light-emitting control signal is at the on level, the pixel PX receiving the corresponding light-emitting control signal may be in a display state. Therefore, the period during which the light-emitting control signal is at the on level may be referred to as a light-emitting period (or light-emitting permission period) EP. In addition, when the light-emitting control signal is at the off level, the pixel PX receiving the corresponding light-emitting control signal may be in a non-display state. Therefore, the period during which the light-emitting control signal is at the off level may be referred to as a non-light-emitting period (or light-emitting non-permitted period) NEP.

[0173] exist Fig.12 The non-light emitting period NEP described in is a period for preventing the pixel PXij from emitting light with an undesired brightness during the time between the initialization period and the data writing period.

[0174] During the period when the data signal written into the pixel PXij is maintained (for example, one frame period), one or more non-luminous periods NEP may be provided additionally to reduce the luminous period EP of the pixel PXij to effectively express low grayscale or to perform soft blur processing on the motion of the image.

[0175] Fig.13 It is a diagram showing an electronic device according to an embodiment of the present invention.

[0176] Reference Fig.13 The electronic device 1000 according to the embodiment of the present invention outputs various information via the display module 1140. If the processor 1110 executes an application stored in the memory 1120, the display module 1140 provides the application information to the user via the display panel 1141.

[0177] The processor 1110 obtains external input through the input module 1130 or the sensor module 1161, and executes an application corresponding to the external input. For example, when the user selects the camera icon (or camera application icon) displayed in the display panel 1141, the processor 1110 obtains the user input through the input sensor 1161-2 and activates the camera module 1171. The processor 1110 transmits image data corresponding to the captured image obtained by the camera module 1171 to the display module 1140. The display module 1140 can display an image corresponding to the captured image through the display panel 1141.

[0178] As another example, in the case where personal information authentication is performed in the display module 1140, the fingerprint sensor 1161-1 obtains input data as the input fingerprint information. The processor 1110 compares the input data obtained by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120, and executes the application according to the comparison result. The display module 1140 can display information executed according to the logic of the application through the display panel 1141. The fingerprint sensor 1161-1 can be configured to be able to obtain fingerprint information in the entire area of ​​the display module 1140 (or the display panel 1141).

[0179] As another example, when the music streaming icon displayed on the display module 1140 is selected, the processor 1110 obtains user input through the input sensor 1161-2 and activates the music streaming application stored in the memory 1120. If a music execution command is input to the music streaming application, the processor 1110 activates the audio output module 1163 to provide the user with audio information that complies with the music execution command.

[0180] The above briefly describes the operation of the electronic device 1000. The following describes in detail the configuration of the electronic device 1000. Part of the configuration of the electronic device 1000 described below may be integrated into one configuration, or one configuration may be divided into two or more configurations.

[0181] The electronic device 1000 can communicate with the external electronic device 2000 through the Internet (for example, a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, a built-in module 1160, and an external module 1170. According to one embodiment, the electronic device 1000 may omit at least one of the above-mentioned components or add one or more other components. According to one embodiment, a part of the above-mentioned components (for example, a sensor module 1161, an antenna module 1162, or an audio output module 1163) may be combined into another component (for example, a display module 1140).

[0182] The processor 1110 may execute software to control at least one other component (e.g., a hardware component or a software component) of the electronic device 1000 connected to the processor 1110, and may perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operation, the processor 1110 may store commands or data received from other components (e.g., the input module 1130, the sensor module 1161, or the communication module 1173) in the volatile memory 1121, process the commands or data stored in the volatile memory 1121, and store the result data in the non-volatile memory 1122.

[0183] The processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include one or more of a central processing unit (CPU) 1111-1 or an application processor (AP: application processor). The main processor 1111 may also include one or more of a graphics processing unit (GPU) 1111-2, a communication processor (CP: communication processor) and an image signal processor (ISP: image signal processor). The main processor 1111 may further include a neural processing unit (neural processing unit) NPU 1111-3. The neural network processing unit NPU 1111-3 is a processor specialized for processing artificial intelligence models, which can be generated by machine learning. The artificial intelligence model may include multiple artificial neural network arrays. The artificial neural network can be a deep neural network (DNN), a CNN (convolutional neural network), an RNN (recurrent neural network), an RBM (restricted Boltzmann machine), a DBN (deep belief network), a BRDNN (bidirectional recurrent deep neural network), a deep Q-network or a combination of two or more of the above networks, and is not limited to the above examples. In addition to the hardware structure, the artificial intelligence model may additionally or alternatively include a software structure. At least two of the above-mentioned processing unit and processor can be implemented by a unified structure (for example, a single chip), and can be implemented by separate independent structures (for example, multiple chips).

[0184] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. As an example, the controller 1112-1 may include Figure 1The timing control unit 120 is shown. The controller 1112-1 receives the image signal from the main processor 1111, converts the data format of the image signal into an interface specification that conforms to the display module 1140, and outputs the image data. The controller 1112-1 can output various control signals required for driving the display module 1140.

[0185] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, and a touch control circuit (not shown). The data conversion circuit 1112-2 may receive image data from the controller 1112-1, compensate the image data so as to display an image at a desired brightness according to the characteristics of the electronic device 1000 or the user's settings, or convert the image data in order to reduce power consumption or compensate for afterimages.

[0186] The gamma correction circuit 1112-3 may transform image data or gamma reference voltage so that an image displayed in the electronic device 1000 has a desired gamma characteristic. The rendering circuit 1112-4 may receive image data from the controller 1112-1 and render the image data in consideration of the pixel configuration of the display panel 1141 of the electronic device 1000.

[0187] The touch control circuit may supply a touch signal to the input sensor 1161 - 2 , and receive a sensing signal from the input sensor 1161 - 2 corresponding to the touch signal.

[0188] At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, the rendering circuit 1112-4, and the touch control circuit may be combined into other components (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, and the rendering circuit 1112-4 may also be combined into the source driver 1143 described later.

[0189] The memory 1120 may store various data used by at least one component of the electronic device 1000 (e.g., the processor 1110 or the sensor module 1161) and input data or output data for commands related thereto. In addition, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include at least one of a volatile memory 1121 and a nonvolatile memory 1122.

[0190] The input module 1130 may receive commands or data to be used in components of the electronic device 1000 (eg, the processor 1110 , the sensor module 1161 , or the audio output module 1163 ) from outside the electronic device 1000 (eg, a user or an external electronic device 2000 ).

[0191] The input module 1130 may include a first input module 1131 into which a user inputs a command or data and a second input module 1132 into which an external electronic device 2000 inputs a command or data. The first input module 1131 may include a microphone, a mouse, a keyboard, a button (e.g., a key) or a pen (e.g., a passive pen or an active pen). The second input module 1132 may support a specified protocol that can be connected to the external electronic device 2000 in a wired or wireless manner. According to one embodiment, the second input module 1132 may include an HDMI (high definition multimedia interface), a USB (universalserial bus) interface, an SD card interface, or an audio interface. The second input module 1132 may include a connector that can be physically connected to the external electronic device 2000 (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)).

[0192] The display module 1140 provides visual information to the user. The display module 1140 may include a display panel 1141, a gate driver 1142, and a source driver 1143. The display module 1140 may also include a window portion 190 (see FIG. 1141 ) for protecting the display panel 1141. Figure 2 ), a base and a bracket. The display module 1140 as described above may include Figure 1 The display device 100 is shown.

[0193] The display panel (or display) 1141 may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel. The type of the display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type, or may be a flexible type that is rollable or foldable. The display module 1140 may also include a support, a bracket, or a heat dissipation component that supports the display panel 1141. The display panel 1141 may include Figure 1 The pixel portion 110 and / or Figure 2 Panel 170 is shown.

[0194] The gate driver 1142 is a driving chip that can be installed in the display panel 1141. In addition, the gate driver 1142 can be integrated into the display panel 1141. For example, the gate driver 1142 may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) built into the display panel 1141. The gate driver 1142 receives a control signal from the controller 1112-1 and outputs a scan signal to the display panel 1141 in response to the control signal. The gate driver 1142 may include, for example, Figure 1 The scan driving unit 130 is shown.

[0195] The display module 1140 may further include a light emitting driver. The light emitting driver outputs a light emitting control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The light emitting driver may be formed separately from the gate driver 1142 or combined into the gate driver 1142. The light emitting driver may include, for example, Figure 1 The light-emitting driving unit 150 is shown.

[0196] The source driver 1143 receives a control signal from the controller 1112-1, converts the image data into an analog voltage (eg, a data signal) in response to the control signal, and then outputs the data signal to the display panel 1141. The source driver 1143 may include: Figure 1 The data driving unit 140 is shown.

[0197] That is, the source driver 1143 may include Figure 3 The signal generating unit 142 and the output unit 144 are shown. Each channel of the output unit 144 included in the source driver 1143 may include Figure 4 , Figure 8 or Fig. 9 Each channel of the output unit 144 can output a data signal.

[0198] The source driver 1143 may be integrated into other components (eg, the controller 1112 - 1 ). The functions of the interface conversion circuit and the timing control circuit of the controller 1112 - 1 may also be integrated into the source driver 1143 .

[0199] The display module 1140 may further include a voltage generating circuit 1144. The voltage generating circuit 1144 may output various voltages required for driving the display panel 1141. As an example, the voltage generating circuit 1144 may include Figure 1 The power supply unit 160 is shown.

[0200] In an embodiment, the display panel 1141 may include a plurality of pixel columns respectively including a plurality of pixels.

[0201] In an embodiment, the source driver 1143 may convert data corresponding to red (R), green (G), and blue (B) included in the image data received from the processor 1110 into red data signals (or data voltages), green data signals (or data voltages), and blue data signals (or data voltages), and provide them to a plurality of pixel columns included in the display panel 1141 within one horizontal period.

[0202] The power module 1150 supplies power to the components of the electronic device 1000. The power module 1150 may include a battery for charging the power supply voltage. The battery may include a primary battery that cannot be recharged, a secondary battery that can be recharged, or a fuel cell. The power module 1150 may include a PMIC (power management integrated circuit). The PMIC supplies optimized power to the above-mentioned modules and the modules described later, respectively. The power module 1150 may include a radio transceiver component electrically connected to the battery. The radio transceiver component may include a plurality of antenna radiators in the form of coils.

[0203] The electronic device 1000 may further include a built-in module 1160 and an external module 1170. The built-in module 1160 may include a sensor module 1161, an antenna module 1162, and an audio output module 1163. The external module 1170 may include a camera module 1171, a light module 1172, and a communication module 1173.

[0204] The sensor module 1161 can sense input caused by the user's body or input caused by the pen in the first input module 1131, and generate an electrical signal or data value corresponding to the input. The sensor module 1161 can include any one or more of a fingerprint sensor 1161-1, an input sensor 1161-2, and a digitizer 1161-3.

[0205] The fingerprint sensor 1161-1 may generate a data value corresponding to the fingerprint of the user. The fingerprint sensor 1161-1 may include an optical fingerprint sensor or a capacitive fingerprint sensor.

[0206] The input sensor 1161-2 may generate a data value corresponding to the coordinate information of the input caused by the user's body or the input caused by the pen. The input sensor 1161-2 generates the capacitance change caused by the input as a data value. The input sensor 1161-2 may sense the input caused by the passive pen or transmit and receive data with the active pen.

[0207] The input sensor 1161-2 may also measure biological signals such as blood pressure, water content, or body fat. For example, when a user places a part of the body in contact with the sensor layer or the sensing panel and does not move for a certain period of time, the input sensor 1161-2 may sense the biological signal based on the electric field change caused by the part of the body to output the information desired by the user to the display module 1140.

[0208] The digitizer 1161-3 may generate a data value corresponding to the coordinate information of the input caused by the pen. The digitizer 1161-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 1161-3 may sense the input caused by the passive pen or transmit and receive data with the active pen.

[0209] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may also be implemented as a sensor layer formed on the display panel 1141 through a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be configured on the upper side of the display panel 1141, and any one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (for example, the digitizer 1161-3) may be configured on the lower side of the display panel 1141.

[0210] Two or more of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be integrated into one sensing panel through the same process. When integrated into one sensing panel, the sensing panel may be disposed between the display panel 1141 and a window portion disposed on the upper side of the display panel 1141. According to one embodiment, the sensing panel may also be disposed on the window portion, and the position of the sensing panel is not particularly limited.

[0211] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be built in the display panel 1141. That is, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be simultaneously formed through the process of forming elements (e.g., light emitting elements, transistors, etc.) included in the display panel 1141.

[0212] In addition, the sensor module 1161 can generate an electrical signal or data value corresponding to the internal state or external state of the electronic device 1000. The sensor module 1161 may also include, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip force sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0213] The antenna module 1162 may include one or more antennas for transmitting signals or power to the outside or receiving signals or power from the outside. According to one embodiment, the communication module 1173 may transmit signals to the external electronic device 2000 or receive signals from the external electronic device 2000 through an antenna that complies with the communication method. The antenna pattern of the antenna module 1162 may also be integrated with a component of the display module 1140 (for example, the display panel 1141) or the input sensor 1161-2. The antenna module 1162 may be Figure 2 Antenna module 1006 is shown.

[0214] The audio output module 1163 is a device for outputting an audio signal to the outside of the electronic device 1000, and may include, for example, a speaker for general use such as multimedia playback or recording playback and a receiver for making and receiving calls. According to one embodiment, the receiver may be formed integrally with the speaker or formed separately. The audio output pattern of the audio output module 1163 may also be formed integrally with the display module 1140.

[0215] The camera module 1171 can capture still images or dynamic images. According to one embodiment, the camera module 1171 may include one or more lenses, image sensors, or image signal processors. The camera module 1171 may also include an infrared camera capable of measuring the presence of a user, the position of a user, the line of sight of a user, etc.

[0216] The light module 1172 may provide light. The light module 1172 may include a light emitting diode or a xenon lamp. The light module 1172 may operate in conjunction with the camera module 1171 or independently.

[0217] The communication module 1173 can support the establishment of a wired or wireless communication channel between the electronic device 1000 and the external electronic device 2000 and the execution of communication based on the established communication channel. The communication module 1173 may include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module or a GNSS (global navigation satellite system) communication module and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module 1173 can communicate with the external electronic device 2000 through a short-range communication network such as Bluetooth, WiFi direct connection or IrDA (infrared data association) or a long-range communication network such as a cellular network, the Internet or a computer network (for example, LAN or WAN). The above-mentioned various types of communication modules 1173 can be implemented by one chip or by separate chips.

[0218] The input module 1130 , the sensor module 1161 , the camera module 1171 , and the like may be linked with the processor 1110 and effectively utilized in controlling the operation of the display module 1140 .

[0219] The processor 1110 outputs a command or data to the display module 1140, the audio output module 1163, the camera module 1171, or the light module 1172 based on the input data received from the input module 1130. For example, the processor 1110 may generate image data corresponding to input data applied through a mouse or an active pen, etc., and output it to the display module 1140, or generate command data corresponding to the input data and output it to the camera module 1171 or the light module 1172. The processor 1110 may convert the operation mode of the electronic device 1000 to a low power mode or a sleep mode when no input data is received from the input module 1130, thereby reducing the power consumed in the electronic device 1000.

[0220] The processor 1110 outputs a command or data to the display module 1140, the audio output module 1163, the camera module 1171, or the light module 1172 based on the sensing data received from the sensor module 1161. For example, the processor 1110 may execute an application according to the comparison result after comparing the authentication data applied by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120. The processor 1110 may execute a command or output corresponding image data to the display module 1140 based on the sensing data sensed by the input sensor 1161-2 or the digitizer 1161-3. In the case where the sensor module 1161 includes a temperature sensor, the processor 1110 may receive temperature data for the temperature measured by the sensor module 1161, and further perform brightness correction for the image data based on the temperature data.

[0221] The processor 1110 may receive measurement data on the presence or absence of a user, the position of the user, the line of sight of the user, etc. from the camera module 1171. The processor 1110 may further perform brightness correction on the image data based on the measurement data. For example, the processor 1110, which has determined the presence or absence of a user through the input from the camera module 1171, may output image data whose brightness has been corrected through the data conversion circuit 1112-2 or the gamma correction circuit 1112-3 to the display module 1140.

[0222] Some of the components described can be connected to each other through a communication method between peripheral devices (for example, a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface) or UPI (Ultrapath interconnect) link), so as to exchange signals (for example, commands or data) with each other. The processor 1110 can communicate with the display module 1140 through an interface agreed upon by each other, for example, any one of the above-mentioned communication methods can be used, but it is not limited to the above-mentioned communication methods.

[0223] The above description has been made with reference to the embodiments of the present invention, but those skilled in the art should be aware that various modifications and changes may be made to the present invention without departing from the scope of the idea and field of the present invention described in the claims.

Claims

1. A display device, characterized in that: include: A plurality of pixels are arranged to be connected to a plurality of scanning lines and a plurality of data lines; as well as a data driving unit for supplying data signals to the plurality of data lines via the plurality of output lines, The data driving unit comprises: a signal generating unit, configured to generate the data signal to supply to a plurality of channel lines; and The first amplifier and the second amplifier are connected in parallel between each of the channel lines and each of the output lines.

2. The display device according to claim 1, characterized in that The first amplifier and the second amplifier located in the i-th channel are alternately connected to the i-th output line, where i is an integer greater than 0.

3. The display device according to claim 2, characterized in that: The data driving unit further comprises: a first transistor connected between the first amplifier and the i-th output line; a second transistor connected between the first amplifier and the i-th channel line; a third transistor connected between the second amplifier and the i-th output line; as well as A fourth transistor is connected between the second amplifier and the i-th channel line.

4. The display device according to claim 3, characterized in that: The first transistor and the third transistor are turned on alternately, and the second transistor and the fourth transistor are turned on alternately.

5. The display device according to claim 3, characterized in that: The second transistor is turned on earlier than the first transistor and a turn-on period of the second transistor partially overlaps with a turn-on period of the first transistor.

6. The display device according to claim 3, characterized in that: The fourth transistor is turned on earlier than the third transistor and a turn-on period of the fourth transistor partially overlaps with a turn-on period of the third transistor.

7. The display device according to claim 1, characterized in that The data driving unit further includes a third amplifier connected in parallel with the first amplifier and the second amplifier between each of the channel lines and each of the output lines.

8. The display device according to claim 7, characterized in that: The first amplifier, the second amplifier and the third amplifier located in the i-th channel are alternately connected to the i-th output line, where i is an integer greater than 0.

9. The display device according to claim 8, characterized in that: The data driving unit further comprises: a first transistor connected between the first amplifier and the i-th output line; a second transistor connected between the first amplifier and the i-th channel line; a third transistor connected between the second amplifier and the i-th output line; a fourth transistor connected between the second amplifier and the i-th channel line; a fifth transistor connected between the third amplifier and the i-th output line; as well as A sixth transistor is connected between the third amplifier and the i-th channel line.

10. The display device according to claim 9, characterized in that: The first transistor, the third transistor and the fifth transistor are alternately turned on, The second transistor, the fourth transistor, and the sixth transistor are alternately turned on.

11. The display device according to claim 9, characterized in that The second transistor is turned on earlier than the first transistor and its on period partially overlaps with the on period of the first transistor. The fourth transistor is turned on earlier than the third transistor and its on period partially overlaps with the on period of the third transistor. The sixth transistor is turned on earlier than the fifth transistor and a turn-on period of the sixth transistor partially overlaps with a turn-on period of the fifth transistor.

12. A display device, characterized in that: include: A plurality of pixels are arranged to be connected to a plurality of scanning lines and a plurality of data lines; as well as a data driving unit for supplying data signals to the plurality of data lines via the plurality of output lines, The data driving unit comprises: a signal generating unit, configured to generate the data signal to supply to a plurality of channel lines; and The first amplifier and the auxiliary amplifier are connected in series between each of the channel lines and each of the output lines.

13. The display device according to claim 12, characterized in that: An input terminal of the first amplifier located in the i-th channel is connected to the i-th channel line, and an output terminal of the auxiliary amplifier is connected to the i-th output line, wherein i is an integer greater than 0.

14. The display device according to claim 13, characterized in that: Also available: The first transistor is located in the i-th channel, connected between the output terminal of the first amplifier and the input terminal of the auxiliary amplifier, and is turned on during a part of the horizontal period.

15. An electronic device, characterized in that: have: A display module, configured to display a predetermined image; and a processor, configured to supply data corresponding to the image to the display module, The display module has: A display panel, displaying the image; a gate driver, configured to supply a scanning signal to the display panel; and A source driver, used for supplying a data signal to the display panel, Each channel of the source driver that outputs the data signal includes a plurality of amplifiers.

16. The electronic device according to claim 15, characterized in that: The plurality of amplifiers output the data signals alternately.

17. The electronic device according to claim 16, characterized in that: The plurality of amplifiers output the data signal alternately based on a horizontal period.

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