Display device and tiled display device

Abstract

The utility model provides a display device and a tiled display device. The display device includes: a substrate having a lower surface on which a recess is formed; a conductive pattern disposed in the recess of the substrate; a bridge pattern disposed on the substrate and electrically connected to the conductive pattern through a contact hole passing through the substrate; a first insulating layer disposed on the substrate and covering the bridge pattern; a transistor disposed on the first insulating layer; a second insulating layer disposed on the substrate and covering the transistor; and a light emitting element disposed on the second insulating layer. The bridge pattern is electrically connected to the transistor or the light emitting element. The first valley is further formed on the lower surface of the substrate, and the first valley and the recess are different from each other, and the conductive pattern is not disposed in the first valley. In the display device, since a transistor or a light emitting element may be electrically connected to a circuit board through a conductive pattern in a groove formed on a lower surface of a substrate and a contact hole through the substrate, the display device has improved reliability.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0058512 filed on May 4, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to a display device and a spliced ​​display device. Background Art

[0003] The spliced ​​display device may be implemented by splicing a plurality of display panels, and in the case where there is an invalid space in each display panel, a boundary between the display panels may be visually recognized and the display quality of an image displayed on the spliced ​​display device may be deteriorated.

[0004] Therefore, in order to reduce the dead space of the display panel, a pad (also referred to as a "pad") is formed on the rear surface of the display panel.

[0005] The pads on the rear surface of the display panel are electrically connected to a circuit inside the display panel through a connection line (or side line) formed on a side surface of the display panel.

[0006] For example, by adding a rear surface process for forming a pad on the rear surface of the display panel and a side surface process for forming a connection line on the side surface of the display panel, the manufacturing process of the display device becomes complicated. In the case where the connection line on the side surface of the display panel is exposed, the reliability of the display panel may be deteriorated. Utility Model Content

[0007] The utility model aims to provide a display device and a spliced ​​display device which can be manufactured by a simpler process and have high reliability.

[0008] According to a disclosed embodiment, a display device may include: a substrate including a groove on a lower surface; a conductive pattern disposed in the groove of the substrate; a bridge pattern disposed on the substrate and electrically connected to the conductive pattern through a contact hole passing through the substrate; a first insulating layer disposed on the substrate and covering the bridge pattern; a transistor disposed on the first insulating layer; a second insulating layer disposed on the substrate and covering the transistor; and a light emitting element disposed on the second insulating layer. The bridge pattern may be electrically connected to the transistor or the light emitting element, a first valley different from the groove may be further formed on the lower surface of the substrate, and the conductive pattern may not be disposed in the first valley.

[0009] The substrate may be a flexible substrate.

[0010] In a cross-sectional view, the shape of the first valley and the shape of the groove may be different from each other.

[0011] In a cross-sectional view, the groove may have a semicircular shape, and the first valley may have a triangular shape.

[0012] In a plan view, the first valleys may extend in a first direction, and may be repeatedly arranged at a pitch corresponding to the light emitting elements in a second direction crossing the first direction.

[0013] The first valleys may be arranged in a mesh structure over the entire area of ​​the substrate in a plan view.

[0014] The display device may further include: a pixel defining layer disposed on the second insulating layer. An opening for disposing the light emitting element and a second valley different from the opening may be formed in the pixel defining layer, and the first valley may overlap the second valley in a plan view.

[0015] The display device may further include: a circuit board disposed under the substrate and electrically connected to the conductive pattern through the groove of the substrate.

[0016] The groove may include a curved surface, and the conductive pattern may include a curved surface corresponding to the groove.

[0017] At least a portion of the groove may be defined by a lower surface of the conductive pattern.

[0018] The light emitting element may be included in a plurality of sub-pixels, and the grooves may be repeatedly arranged in the first direction at a pitch corresponding to at least one of the sub-pixels.

[0019] The groove may have a size corresponding to the plurality of sub-pixels, and a plurality of conductive patterns may be disposed in the groove.

[0020] According to the disclosed embodiment, a method for manufacturing a display device may include: forming a first mold pattern on a carrier substrate; forming a conductive pattern on the first mold pattern; forming a base layer on the carrier substrate to cover the first mold pattern and the conductive pattern; forming a transistor on the base layer; separating the carrier substrate and the first mold pattern from the base layer; and mounting a light emitting element on the base layer. A groove corresponding to the first mold pattern may be formed on the lower surface of the base layer.

[0021] The step of forming the first molding pattern may include: forming a sacrificial layer on the carrier substrate; and punching the sacrificial layer using a mold including a second groove corresponding to the first molding pattern. The sacrificial layer may include silica sol-gel (Si sol-gel) or a polymer organic material.

[0022] The forming of the first mold pattern may further include forming a second mold pattern together with the first mold pattern. In a cross-sectional view, the second mold pattern and the first mold pattern may have different shapes from each other, and a first valley corresponding to the second mold pattern may be formed on the lower surface of the base layer.

[0023] The step of forming the transistor may include forming a pixel defining layer on the base layer. An opening for disposing the light emitting element and a second valley different from the opening may be formed in the pixel defining layer, and the first valley may overlap the second valley in a plan view.

[0024] According to the disclosed embodiments, a spliced ​​display device may include: a plurality of display devices, each including pixels. The display devices may be arranged adjacent to each other at a spacing corresponding to the spacing between the pixels. At least one of the display devices may include: a substrate including a groove on a lower surface; a conductive pattern arranged in the groove of the substrate; a bridge pattern arranged on the substrate and electrically connected to the conductive pattern through a contact hole passing through the substrate; a first insulating layer arranged on the substrate and covering the bridge pattern; a transistor arranged on the first insulating layer; a second insulating layer arranged on the substrate and covering the transistor; and a light-emitting element arranged on the second insulating layer. The bridge pattern may be electrically connected to the transistor or the light-emitting element. A first valley different from the groove may be further formed on the lower surface of the substrate.

[0025] At least some of the display devices may have different sizes or different shapes.

[0026] At least some of the display devices may have different resolutions.

[0027] The substrate may be a flexible substrate.

[0028] In the display device according to the disclosed embodiment, the transistor or the light emitting element can be electrically connected to the circuit board through the conductive pattern formed in the groove on the lower surface of the substrate and the contact hole passing through the substrate. Therefore, it is not necessary to set the connecting wire on the side surface of the display device, the reliability degradation caused by the connecting wire can be prevented, and the invalid space of the display device can be reduced or eliminated.

[0029] The method of manufacturing a display device according to the disclosed embodiment can manufacture a display device only through a front surface process of sequentially forming a conductive pattern, a base layer, a transistor, etc. on a carrier substrate. Therefore, a rear surface process for forming a conductive pattern under the base layer or a side surface process for forming a connection line on the side surface of the display device can be excluded, and a display device without an invalid space can be manufactured through a simpler process.

[0030] The effects according to the disclosed embodiments are not limited to the contents described above as examples, and more various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the disclosure will become more apparent by describing the disclosed embodiments in more detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0033] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of pixels;

[0034] Figure 3 is a diagram showing a method according to another embodiment Figure 1 Schematic diagram of pixels;

[0035] Figure 4 is a diagram showing the embodiment including Figure 2 and Figure 3 A schematic diagram of an equivalent circuit of a sub-pixel in a pixel;

[0036] Figure 5 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic plan view of a display device;

[0037] Figure 6 It is shown that the Figure 5 A schematic diagram of a connection relationship between a pixel circuit and a stage in a display device;

[0038] Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic cross-sectional view of a display device;

[0039] Figure 8 and Fig. 9 is a display device shown included in Figure 7 A schematic bottom view of a groove in a display device of FIG.

[0040] Fig.10 and Fig.11 It shows the manufacturing Figure 7 A schematic cross-sectional view of a method for displaying a device;

[0041] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic cross-sectional view of a display device;

[0042] Fig.13 It shows the manufacturing Fig.12 A schematic cross-sectional view of a method for displaying a device;

[0043] Fig.14 is a diagram showing a method according to an embodiment of the present invention. Fig.12 A schematic plan view of a display device;

[0044] Fig.15 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic diagram of a display device;

[0045] Fig.16 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic cross-sectional view of a display device;

[0046] Fig.17 is a display device shown included in Fig.16 A schematic bottom view of a valley in a display device of FIG.

[0047] Fig.18 and Fig.19 It shows the manufacturing Fig.16 A schematic cross-sectional view of a method for displaying a device;

[0048] Fig. 20 and Fig.21 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic cross-sectional view of a display device;

[0049] Fig. 22 is a display device shown included in Fig. 20 and Fig.21 A schematic bottom view of a groove in a display device of FIG.

[0050] Fig.23 is a schematic plan view showing a spliced ​​display device including a plurality of display devices according to an embodiment;

[0051] Fig.24 yes Fig.23 A schematic enlarged plan view of area AA of FIG. 1 ; and

[0052] Fig.25 is a schematic block diagram showing a spliced ​​display device according to an embodiment. DETAILED DESCRIPTION

[0053] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments or implementations disclosed. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor need they be limited to disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0054] The advantages and features of the disclosure and methods for achieving them will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. The embodiments are provided so that the disclosure will be thorough and complete, and those skilled in the art to which the disclosure belongs can fully understand the scope of the disclosure. The disclosure is limited only by the scope of the claims.

[0055] The terms used herein are for the purpose of describing a particular embodiment, and are not intended to be limiting. As used herein, unless the context clearly states otherwise, the singular forms "one", "one (kind / person)" and "the (described)" are also intended to include plural forms. In addition, when the terms "include", "comprise", "have" and / or and variations thereof are used in this specification, the stated features, integral bodies, steps, operations, elements, components and / or groups thereof are specified to exist, but one or more other features, integral bodies, steps, operations, elements, components and / or groups thereof are not excluded from existence or addition. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, so as to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0056] The case where an element or layer is referred to as being "on" another element or layer includes the case where the layer or element is directly disposed on the other element or layer or the case where another layer or element is located therebetween. However, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or intervening layers. Throughout the specification, the same reference numerals indicate the same components. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings used to describe the embodiments are exemplary, and therefore, the disclosure is not limited thereto.

[0057] The term "connection" between two structures can be used to include both electrical connection and physical connection, but is not limited thereto. For example, "connection" used based on a circuit diagram can represent electrical connection, and "connection" used based on a cross-sectional view and a plan view can represent physical connection.

[0058] When a component is described herein as "connecting" another component to or being "connected to" another component, the components may be connected to each other as separate elements, or the components may be integral with each other. In addition, throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element or "electrically connected" to the other element with one or more intervening elements interposed therebetween.

[0059] Although "first" and "second" etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the disclosed technical spirit, the first component mentioned below may be the second component.

[0060] Each of the features of the various disclosed embodiments can be combined or combined with each other in part or in whole, and various interlocks and drives are technically feasible. Each embodiment can be implemented independently of each other, and their associations can be implemented together.

[0061] For the purpose of this disclosure, the phrase "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. In addition, "at least two of X, Y, and Z" may be interpreted as two or more of X, Y, and Z, such as both of X and Y, both of X and Z, both of Y and Z, and all of X, Y, and Z.

[0062] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0063] For descriptive purposes, spatially relative terms such as "below," "below," "above," "upper," "on," and "side" may be used herein to describe the relationship of one element to another element (or elements) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, then the elements described as "below" or "below" other elements or features will subsequently be oriented to be "above" the other elements or features. Therefore, the example term "below" can cover both the above and below orientations. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0064] According to the convention in the art, some embodiments are described and shown in the accompanying drawings according to functional blocks, units, components and / or modules. It will be understood by those skilled in the art that these blocks, units, components and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case where blocks, units, components and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed here, and can be optionally driven by firmware and / or software. It is also envisioned that each block, unit, component and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and related circuits) for performing other functions. In addition, without departing from the scope of the disclosure, each block, unit, component and / or module of some example embodiments can be physically divided into two or more interactive and discrete blocks, units, components and / or modules. Furthermore, the blocks, units, components and / or modules of some example embodiments may be physically combined into more complex blocks, units, components and / or modules without departing from the scope of the disclosure.

[0065] Unless otherwise noted, the illustrated embodiments should be understood to provide example features of the disclosure. Therefore, without departing from the disclosure, unless otherwise noted, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged.

[0066] Cross hatching and / or shading used in the drawings are usually provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the shown elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0067] Various embodiments are described herein with reference to cross-sections and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes caused by, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated regional shapes, but rather include shape deviations caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore are not necessarily intended to be limiting.

[0068] The first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of the rectangular coordinate system (such as the x, y, and z axes), and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0069] The display surface may be parallel to a surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface (i.e., the thickness direction of the display device) may indicate a third direction DR3. In this specification, the expression "when viewed from the top or in a plan view" may indicate the situation when viewed in the third direction DR3. In the following, the front surface (or top surface) and the rear surface (or bottom surface) of each of the layers or units may be distinguished by the third direction DR3. However, the directions indicated by the first direction to the third directions DR1, DR2, and DR3 may be relative concepts and converted relative to each other (e.g., converted to opposite directions).

[0070] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0071] Hereinafter, embodiments are described with reference to the accompanying drawings.

[0072] Figure 1 is a schematic plan view showing a display device according to an embodiment. Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of pixels. Figure 3 is a diagram showing a method according to another embodiment Figure 1 Schematic diagram of pixels.

[0073] Reference Figure 1The display device 10 (or display panel) can be a device that displays images and can be used as a display screen for various products (not only portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs)), but also televisions, notebook computers, monitors, billboards, and Internet of Things (IOT) devices, etc.).

[0074] The display device 10 may have a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1 in a plan view. In a plan view, the corner where the long side of the first direction DR1 and the short side of the second direction DR2 meet may be rounded to have a curvature (e.g., a predetermined or selectable curvature), or have a right angle. However, the shape of the display device 10 is not limited to a quadrilateral, and in another embodiment, in a plan view, the shape of the display device 10 may be other polygons, a circle, an ellipse, etc. The display device 10 may be flat, but the disclosure is not limited thereto. In a plan view, the display device 10 may have an irregular shape. For example, the display device 10 may include a curved portion formed at the left and right ends having a curvature (e.g., a constant or selectable curvature or a variable curvature). The display device 10 may be flexibly formed to be twisted, bent, bent, folded, or curled.

[0075] The display device 10 may include pixels PX. The pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2, but the disclosure is not limited thereto. The display device 10 may further include gate lines (or scan lines) extending in the first direction DR1 (see, for example, Figure 4 GL) and a data line extending in a second direction DR2.

[0076] like Figure 2 and Figure 3 As shown in FIG, each of the pixels PX may include sub-pixels SPX1, SPX2, and SPX3. Figure 2 and Figure 3 It is illustrated that each of the pixels PX includes three sub-pixels SPX1 to SPX3 (eg, a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 ), but the disclosure is not limited thereto.

[0077] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be electrically connected to a data line (see, e.g., Figure 4 DL) and at least one of the gate lines.

[0078] Reference Figure 2In a plan view, each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a rectangular, square, or diamond shape, etc. For example, Figure 2 As shown in FIG. 1 , in a plan view, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. Figure 3 As shown in FIG. 1 , each of the first to third subpixels SPX1 , SPX2 , and SPX3 may have a square or diamond shape including sides having the same length in the first and second directions DR1 and DR2 in a plan view.

[0079] Reference Figure 2 , the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be arranged in the first direction DR1. In another embodiment, one of the second sub-pixel SPX2 and the third sub-pixel SPX3 and the first sub-pixel SPX1 may be arranged in the first direction DR1, and the other of the second sub-pixel SPX2 and the third sub-pixel SPX3 and the first sub-pixel SPX1 may be arranged in the second direction DR2. For example, referring to Figure 3 , the first sub-pixel SPX1 and the second sub-pixel SPX2 may be arranged in the first direction DR1, and the first sub-pixel SPX1 and the third sub-pixel SPX3 may be arranged in the second direction DR2.

[0080] In another embodiment, one of the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 may be arranged in the first direction DR1, and the other of the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 may be arranged in the second direction DR2. In another embodiment, one of the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 may be arranged in the first direction DR1, and the other of the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 may be arranged in the second direction DR2.

[0081] The first sub-pixel SPX1 may emit a first light, the second sub-pixel SPX2 may emit a second light, and the third sub-pixel SPX3 may emit a third light. The first light may be light in a red band, the second light may be light in a green band, and the third light may be light in a blue band. The red band may be a band in the range of about 600 nm to about 750 nm, the green band may be a band in the range of about 480 nm to about 560 nm, and the blue band may be a band in the range of about 370 nm to about 460 nm, but the disclosure is not limited thereto.

[0082] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may include an inorganic light emitting element including an inorganic semiconductor as a light emitting element emitting light. For example, the inorganic light emitting element may be a flip chip type micro light emitting diode (LED), but the disclosure is not limited thereto.

[0083] Reference Figure 2 and Figure 3 , in a plan view, the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be substantially the same, but the disclosure is not limited thereto. At least one of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from the other of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3. In another embodiment, at least two of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be substantially the same, and the other of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from the at least two areas. In another embodiment, the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from each other.

[0084] Figure 4 is a diagram showing the embodiment including Figure 2 and Figure 3 Schematic diagram of the equivalent circuit of a sub-pixel in a pixel. Figure 4 The sub-pixel SPX shown in FIG. 1 may be included in Figure 2 and Figure 3 The sub-pixels SPX1 to SPX3 may have structures (or circuits) substantially the same as or similar to each other.

[0085] Reference Figure 4 The subpixel SPX may be electrically connected to the gate line GL, the data line DL, the first power line PL1, and the second power line PL2. The subpixel SPX may also be electrically connected to at least another power line (not shown) and / or a signal line (not shown).

[0086] A gate signal (or scan signal) may be supplied to the gate line GL, a data signal may be supplied to the data line DL, a voltage of the first power VDD may be applied to the first power line PL11, and a voltage of the second power VSS may be applied to the second power line PL2. The first power VDD and the second power VSS may have different potentials.

[0087] The sub-pixel SPX may include a light emitting element ED for generating light of brightness corresponding to each data signal. The sub-pixel SPX may further include a pixel circuit PC for driving the light emitting element ED.

[0088] The pixel circuit PC may be electrically connected to the gate line GL and the data line DL, and may be electrically connected between the first power line PL1 and the light emitting element ED.

[0089] The pixel circuit PC may include at least one transistor and a capacitor Cst. For example, the pixel circuit PC may include a first transistor M1, a second transistor M2, and a capacitor Cst.

[0090] The first transistor M1 may be electrically connected between the first power line PL1 and the second node N2. The second node N2 may be a node at which the pixel circuit PC and the light emitting element ED are electrically connected. For example, the second node N2 may be a node at which an electrode (e.g., a source electrode) of the first transistor M1 and the light emitting element ED are electrically connected to each other. The gate electrode of the first transistor M1 may be electrically connected to the first node N1. The first transistor M1 may control a driving current supplied to the light emitting element ED in response to a voltage of the first node N1. For example, the first transistor M1 may be a driving transistor of the sub-pixel SPX.

[0091] The second transistor M2 may be electrically connected between the data line DL and the first node N1. A gate electrode of the second transistor M2 may be electrically connected to the gate line GL. When a gate signal having a gate-on voltage (e.g., a logic high voltage or a high-level voltage) is supplied from the gate line GL, the second transistor M2 may be turned on to connect the data line DL and the first node N1.

[0092] A data signal of a corresponding frame may be supplied to the data line DL in each frame period, and the data signal may be transmitted to the first node N1 through the second transistor M2 during a period in which a gate signal having a gate-on voltage is supplied. For example, the second transistor M2 may be a switching transistor for transmitting each data signal to the inside of the subpixel SPX.

[0093] A first electrode of the capacitor Cst may be connected to the first node N1, and a second electrode of the capacitor Cst may be connected to the second node N2. The capacitor Cst may be charged with a voltage corresponding to a data signal supplied to the first node N1 during each frame period.

[0094] exist Figure 4In the embodiment, both the first transistor M1 and the second transistor M2 included in the pixel circuit PC may be n-type transistors, but the disclosure is not limited thereto. In another embodiment, at least one of the first transistor M1 and the second transistor M2 may be a p-type transistor. According to embodiments, the structure and driving method of the sub-pixel SPX may be variously changed.

[0095] The pixel circuit PC may further include other circuit elements, such as an initialization transistor (or a sensing transistor) for initializing the anode electrode of the light emitting element ED, a compensation transistor for compensating for the threshold voltage of the first transistor M1, an initialization transistor for initializing the voltage of the first node N1, an emission control transistor for controlling the period in which a driving current is supplied to the light emitting element ED, a boost capacitor for increasing the voltage of the first node N1, etc., or a combination thereof.

[0096] The light emitting element ED may emit light having a brightness corresponding to the driving current supplied by the pixel circuit PC. The light emitting element ED may be electrically connected between the first transistor M1 and the second power line PL2. The first electrode of the light emitting element ED may be electrically connected to the electrode (or the second node N2) of the first transistor M1, and the second electrode of the light emitting element ED may be electrically connected to the second power line PL2. The first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element ED may be a micro light emitting diode (LED) formed of an inorganic semiconductor, but the disclosure is not limited thereto.

[0097] exist Figure 4 In the embodiment, the sub-pixel SPX may include only one light-emitting element ED, but the disclosure is not limited thereto. In another embodiment, the sub-pixel SPX may also include at least one light-emitting element electrically connected in parallel to the light-emitting element ED. In another embodiment, the sub-pixel SPX may also include at least one light-emitting element connected in series to the light-emitting element ED. According to the embodiment, the number, type and / or structure of the light-emitting elements ED constituting the effective light source of the sub-pixel SPX may be changed.

[0098] Figure 5 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic plan view of a display device. Figure 6 It is shown that the Figure 5 Schematic diagram of the connection relationship between the pixel circuit and the stage in the display device of FIG. A plurality of stages may constitute at least one gate driver (or scan driver).

[0099] Reference Figures 1 to 6, the display device 10 may include a pixel PX, and the pixel PX may include first to third sub-pixels SPX1 to SPX3.

[0100] The first sub-pixel SPX1 may include a first light emitting element ED1 and a first pixel circuit PC1, and the first pixel circuit PC1 may supply a driving current to the first light emitting element ED1. The first pixel circuit PC1 may be positioned in the second direction DR2 relative to the first light emitting element ED1, and the first pixel circuit PC1 may be electrically connected to the first light emitting element ED1. The second sub-pixel SPX2 may include a second light emitting element ED2 and a second pixel circuit PC2, and the second pixel circuit PC2 may supply a driving current to the second light emitting element ED2. The second pixel circuit PC2 may be positioned in the second direction DR2 relative to the second light emitting element ED2, and the second pixel circuit PC2 may be electrically connected to the second light emitting element ED2. The third sub-pixel SPX3 may include a third light emitting element ED3 and a third pixel circuit PC3, and the third pixel circuit PC3 may supply a driving current to the third light emitting element ED3. The third pixel circuit PC3 may be positioned in the second direction DR2 relative to the third light emitting element ED3, and the third pixel circuit PC3 may be electrically connected to the third light emitting element ED3.

[0101] According to an embodiment, each of the first to third sub-pixels SPX1 to SPX3 may include two light-emitting elements. For example, each of the first to third sub-pixels SPX1 to SPX3 may include a light-emitting element (e.g., a main light-emitting element) and another light-emitting element (e.g., a repair light-emitting element), but the disclosure is not limited thereto. In another embodiment, each of the first to third sub-pixels SPX1 to SPX3 may include three or more light-emitting elements. Figure 5 The first to third light emitting elements ED1 to ED3 shown in FIG. 1 may be electrodes (eg, anode electrodes and cathode electrodes) of each of the first to third light emitting elements ED1 to ED3, and will be referred to below. Figure 7 An electrode of each of the first to third light emitting elements ED1 to ED3 will be described.

[0102] Based on the light-emitting elements ED1 to ED3, the pixels PX can be arranged to have a uniform pixel spacing. The light-emitting elements ED1 to ED3 can be arranged in a plurality of pixel rows. For example, the light-emitting elements ED1 to ED3 can be arranged in the kth pixel row to the k+5th pixel row PROWk, PROWk+1, PROWk+2, PROWk+3, PROWk+4 and PROWk+5 (wherein k is a positive integer). The pixel circuits PC1 to PC3 can be arranged in a plurality of circuit rows. The pixel circuits PC1 to PC3 can be arranged in the kth circuit row to the k+5th circuit row CROWk, CROWk+1, CROWk+2, CROWk+3, CROWk+4 and CROWk+5.

[0103] The kth pixel row PROWk may be arranged to be adjacent to the kth circuit row CROWk in a direction opposite to the second direction DR2, and the k+1th pixel row PROWk+1 may be arranged to be adjacent to the k+1th circuit row CROWk+1 in the second direction DR2. The kth circuit row CROWk and the k+1th circuit row CROWk+1 may be arranged between the kth pixel row PROWk and the k+1th pixel row PROWk+1. Similarly, the k+2th pixel row PROWk+2 may be arranged to be adjacent to the k+2th circuit row CROWk+2 in a direction opposite to the second direction DR2, and the k+3th pixel row PROWk+3 may be arranged to be adjacent to the k+3th circuit row CROWk+3 in the second direction DR2. The k+2th circuit row CROWk+2 and the k+3th circuit row CROWk+3 may be arranged between the k+2th pixel row PROWk+2 and the k+3th pixel row PROWk+3. Similarly, the k+4th pixel row PROWk+4 may be disposed adjacent to the k+4th circuit row CROWk+4 in a direction opposite to the second direction DR2, and the k+5th pixel row PROWk+5 may be disposed adjacent to the k+5th circuit row CROWk+5 in the second direction DR2. The k+4th circuit row CROWk+4 and the k+5th circuit row CROWk+5 may be disposed between the k+4th pixel row PROWk+4 and the k+5th pixel row PROWk+5.

[0104] The k-th stage STGk may be disposed at an upper side of the k-th circuit row CROWk and the k-th pixel row PROWk. The k-th stage STGk may supply a gate signal to the k-th gate line GLk electrically connected to the pixel circuits PC1, PC2, PC3 of the k-th circuit row CROWk. The k-th stage STGk may be electrically connected to the k-th gate line GLk through a connection line CL. For example, the k-th stage STGk may be electrically connected to the k-th gate line GLk through a first connection line CL1 extending in a first direction DR1 and a second connection line CL2 extending in a second direction DR2.

[0105] The k+1th stage STGk+1 and the k+2th stage STGk+2 may be disposed between the k+1th pixel row PROWk+1 and the k+2th pixel row PROWk+2. The k+1th stage STGk+1 may be disposed at the lower side of the k+1th circuit row CROWk+1 and the k+1th pixel row PROWk+1. The k+1th stage STGk+1 may supply a gate signal to the k+1th gate line GLk+1 of the pixel circuit PC electrically connected to the k+1th circuit row CROWk+1. The k+1th stage STGk+1 may be electrically connected to the k+1th gate line GLk+1 through a connection line CL.

[0106] The k+2 stage STGk+2 may be disposed at the upper side of the k+2 circuit row CROWk+2 and the k+2 pixel row PROWk+2. The k+2 stage STGk+2 may supply a gate signal to the k+2 gate line GLk+2 electrically connected to the pixel circuit PC of the k+2 circuit row CROWk+2. The k+2 stage STGk+2 may be electrically connected to the k+1 gate line GLk+2 through a connection line CL.

[0107] The k+3rd stage STGk+3 and the k+4th stage STGk+4 may be disposed between the k+3rd pixel row PROWk+3 and the k+4th pixel row PROWk+4. The k+3rd stage STGk+3 may be disposed at the lower side of the k+3rd circuit row CROWk+3 and the k+3rd pixel row PROWk+3. The k+3rd stage STGk+3 may supply a gate signal to the k+3rd gate line GLk+3 of the pixel circuit PC electrically connected to the k+3rd circuit row CROWk+3. The k+3rd stage STGk+3 may be electrically connected to the k+3rd gate line GLk+3 through a connection line CL.

[0108] The k+4th stage STGk+4 may be disposed at an upper side of the k+4th circuit row CROWk+4 and the k+4th pixel row PROWk+4. The k+4th stage STGk+4 may supply a gate signal to the k+4th gate line GLk+4 electrically connected to the pixel circuit PC of the k+4th circuit row CROWk+4. The k+4th stage STGk+4 may be electrically connected to the k+4th gate line GLk+4 through a connection line CL.

[0109] The k+5th stage STGk+5 may be disposed at the lower side of the k+5th circuit row CROWk+5 and the k+5th pixel row PROWk+5. The k+5th stage STGk+5 may supply a gate signal to the k+5th gate line GLk+5 electrically connected to the pixel circuit PC of the k+5th circuit row CROWk+5. The k+5th stage STGk+5 may be electrically connected to the k+5th gate line GLk+5 through a connection line CL.

[0110] The data lines DL may include first to third data lines DL1 to DL3. The first data line DL1 may supply a data voltage to a plurality of first pixel circuits PC1 disposed in the same column. The second data line DL2 may supply a data voltage to a plurality of second pixel circuits PC2 disposed in the same column. The third data line DL3 may supply a data voltage to a plurality of third pixel circuits PC3 disposed in the same column.

[0111] Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic cross-sectional view of a display device. Figure 7 A simplified cross-sectional view of the display device 10 based on a sub-pixel SPX is shown. Figure 8 and Fig. 9 is a display device shown included in Figure 7 Schematic bottom view of a groove in a display device.

[0112] Reference Figures 1 to 7 The sub-pixel SPX (or the display device 10 or the display panel) may include a substrate SUB (or a base layer), a lower electrode layer BML, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first source metal layer SDL1, a first via layer VIA1, a first protective layer PVX1, a second source metal layer SDL2, a second via layer VIA2, a second protective layer PVX2, a third source metal layer SDL3, a third via layer VIA3, a third protective layer PVX3, a pixel electrode layer PEL, a fourth via layer VIA4 and a fourth protective layer PVX4.

[0113] The substrate SUB may be a base substrate or a base member for supporting the display device 10. The substrate SUB may be a flexible substrate that is bendable, foldable, or rollable, etc., and the substrate SUB may include an insulating material such as a polymer resin including polyimide (PI), etc. The substrate SUB may have a single-layer structure or a multi-layer structure.

[0114] In an embodiment, the groove GRV may be formed on the lower surface of the substrate SUB. For example, the groove GRV may have a shape in which the lower surface of the substrate SUB is concave in the third direction DR3.

[0115] In an embodiment, the groove GRV may include a curved surface. For example, at least a portion of the groove GRV may be a curved surface. Figure 7 In the cross-sectional view, the groove GRV may have a semicircular or semi-elliptical shape. However, the disclosure is not limited thereto, and in another embodiment, in the cross-sectional view, the groove GRV may have a rectangular or polygonal shape.

[0116] In the embodiments, reference Figure 8and Fig. 9 In a plan view, the groove GRV may have a circular shape. However, the disclosure is not limited thereto, and in another embodiment, in a plan view, the groove GRV may have an elliptical shape or a quadrilateral whose corners are rounded, or the like.

[0117] In an embodiment, the grooves GRV may be repeatedly arranged in the first direction DR1 or the second direction DR2 at an interval INTV corresponding to at least one sub-pixel SPX For example, the interval INTV may be in the range of about 10 μm to about 100 μm.

[0118] In an embodiment, the groove GRV may be arranged corresponding to the arrangement of the line connected to the sub-pixel SPX. Mutually independent signals may be applied to the line, and for example, the line may include a data line DL. However, the disclosure is not limited thereto, and in another embodiment, the line may include a line commonly electrically connected to the sub-pixel SPX, such as a second power line PL2, etc. For example, referring to Figure 8 In the case where the data line DL (or the second power line PL2) electrically connected to the sub-pixel SPX is arranged in the first direction DR1, the groove GRV may be repeatedly arranged in the first direction DR1 corresponding to each data line DL (or each second power line PL2). However, the position of the groove GRV in the second direction DR2 is not particularly limited thereto.

[0119] Reference Figure 8 , the groove GRV may be provided corresponding to a line (eg, a data line DL), but the disclosure is not limited thereto. Fig. 9 , a plurality of grooves GRV may be arranged corresponding to a line (e.g., a data line DL), or the grooves GRV corresponding to the line may be repeatedly arranged in the second direction DR2. In another embodiment, in the case where the grooves GRV are arranged in multiple rows, only the grooves GRV corresponding to a portion of the line (e.g., odd grooves GRV_ODD corresponding to odd lines) may be arranged in one row (e.g., a specific row), and only the grooves GRV corresponding to another line (e.g., even grooves GRV_EVEN corresponding to even lines) may be arranged in another row. However, the disclosure is not limited thereto, and for example, based on the line (or sub-pixel SPX), the number of corresponding grooves GRV and the position in the plan view, etc. may be freely changed.

[0120] Refer again Figure 7 , the width W of the groove GRV in the first direction DR1 or the second direction DR2 may be smaller than the interval INTV. For example, the width W of the groove GRV may be in the range of about 5 μm to about 50 μm. However, the disclosure is not limited thereto. The width W of the groove GRV may be where the conductive pattern CP and the circuit board (see, for example, Fig.12 FPCB) can be made by anisotropic conductive film (see for example Fig.12 ACF) or bumps (see e.g. Fig.12 The width W of the groove GRV may be variously changed according to the number of the conductive patterns CP provided in the groove GRV.

[0121] The conductive pattern CP (or connection pattern) may be disposed in the groove GRV. The conductive pattern CP may include a conductive material. For example, the conductive pattern CP may include a conductive material such as copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), etc. and alloys thereof. The conductive pattern CP may have a single layer or multiple layers. For example, the conductive pattern CP may have a stacked structure of aluminum and titanium (Ti / Al / Ti) or a stacked structure of copper and titanium (Ti / Cu), etc.

[0122] In an embodiment, one conductive pattern CP may be disposed corresponding to one groove GRV, but the disclosure is not limited thereto. In another embodiment, a plurality of conductive patterns may be disposed in one groove GRV, and will be referred to below. Fig. 22 Give a description.

[0123] In an embodiment, the conductive pattern CP may include a curved surface corresponding to the groove GRV. At least a portion of the groove GRV may be defined by a lower surface of the conductive pattern CP. Figure 7 , the conductive pattern CP may define a portion of the groove GRV, and a portion of the substrate SUB may define the remaining portion of the groove GRV.

[0124] An independent conductive pattern CP (or each conductive pattern CP) may be disposed in each groove GRV. For example, a first conductive pattern CP1 may be disposed in a groove GRV, a second conductive pattern CP2 may be disposed in another groove GRV, and the first conductive pattern CP1 and the second conductive pattern CP2 may be electrically separated or insulated (or disconnected).

[0125] The lower electrode layer BML may be disposed on the substrate SUB and may include a conductive material or the like.

[0126] The lower electrode layer BML may include a first bridge pattern BPR1 and a second bridge pattern BRP2. The first bridge pattern BRP1 may be electrically connected to the first conductive pattern CP1 through a contact hole passing through the substrate SUB (or extending from the upper surface of the substrate SUB to the groove GRV). Similarly, the second bridge pattern BRP2 may be electrically connected to the second conductive pattern CP2 through a contact hole passing through the substrate SUB.

[0127] The buffer layer BF (also referred to as the first insulating layer) may be disposed on the surface of the substrate SUB and cover the lower electrode layer BML. The buffer layer BF may prevent the penetration of air or moisture. The buffer layer BF may be an insulating layer including an inorganic material. For example, the buffer layer BF may include an inorganic material including silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x In another embodiment, the buffer layer BF may be omitted according to the material or process conditions of the substrate SUB.

[0128] The active layer ACTL may be disposed on the buffer layer BF. In an embodiment, the active layer ACTL may include a silicon semiconductor such as polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, etc., or a combination thereof. In another embodiment, the active layer ACTL may include an oxide semiconductor, etc.

[0129] The active layer ACTL may include a channel CH of the transistor TFT, a first electrode SE, and a second electrode DE. The transistor TFT may be included in the pixel circuit (see, for example, Figure 4 PC), and for example, the transistor TFT may be a first transistor (see for example Figure 4 M1). The channel CH of the transistor TFT may be a region overlapping with the gate electrode GE of the transistor TFT in a third direction DR3 (or in a plan view), and the third direction DR3 is a thickness direction of the substrate SUB. The first electrode SE of the transistor TFT may be disposed on one side of the channel CH, and the second electrode DE may be disposed on the other side of the channel CH. The first electrode SE and the second electrode DE of the transistor TFT may be a region not overlapping with the gate electrode GE in the third direction DR3 (or in a plan view). The channel CH of the transistor TFT may be a semiconductor pattern in which impurities are not doped, and may be an intrinsic semiconductor. The first electrode SE and the second electrode DE of the transistor TFT may be a semiconductor pattern in which impurities are doped.

[0130] A gate insulating layer GI (also referred to as one of the second insulating layers) may be disposed on the active layer ACTL. The gate insulating layer GI may be an insulating layer including an inorganic material.

[0131] The gate layer GTL may be disposed on the gate insulating layer GI. The gate layer GTL may include a conductive material, and may have a single layer or a multi-layer.

[0132] The gate layer GTL may include (in addition to other electrodes GAT (or other lines)) a gate electrode GE of the transistor TFT and a first capacitor electrode CE1. For example, the other electrodes GAT may include a data line DL and a second power line PL2, or may be electrically connected to the data line DL and the second power line PL2. The other electrodes GAT may be electrically connected to the first bridge pattern BRP1 through a contact hole passing through the gate insulating layer GI and the buffer layer BF. The other electrodes GAT may be electrically connected to the first conductive pattern CP1 through the first bridge pattern BRP1.

[0133] An interlayer insulating layer ILD (also referred to as another one of the second insulating layers) may be disposed on the gate layer GTL. The interlayer insulating layer ILD may be an insulating layer including an inorganic material.

[0134] The first source metal layer SDL1 may be disposed on the interlayer insulating layer ILD. The first source metal layer SDL1 may include a conductive material, and may have a single layer or a multi-layer.

[0135] The first source metal layer SDL1 may include a connection electrode CCE and a second capacitor electrode CE2. The connection electrode CCE may be electrically connected to the first electrode SE (or the second electrode DE) of the transistor TFT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI. The second capacitor electrode CE2 may form a capacitor with the first capacitor electrode CE1 (see, for example, Figure 4 Cst).

[0136] The first via layer VIA1 (or the first planarization layer) may be disposed on the first source metal layer SDL1. The first via layer VIA1 may planarize the step difference caused by the active layer ACTL, the gate layer GTL, and the first source metal layer SDL1. The first via layer VIA1 may be an insulating layer including an organic material. For example, the first via layer VIA1 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc., or a combination thereof.

[0137] The first protective layer PVX1 may be disposed on the first via layer VIA1. The first protective layer PVX1 may be an insulating layer including an inorganic material.

[0138] The second source metal layer SDL2 may be disposed on the first protection layer PVX1. The second source metal layer SDL2 may include a conductive material, and may have a single layer or a multi-layer.

[0139] The second source metal layer SDL2 may include an anode connection line ACL The anode connection line ACL may be electrically connected to the connection electrode CCE through a contact hole passing through the first protection layer PVX1 and the first via layer VIA1 .

[0140] In another embodiment, the first via layer VIA1 and the first protection layer PSV1 may be omitted, and the connection electrode CCE may be included in the anode connection line ACL, but the disclosure is not limited thereto. In another embodiment, the first via layer VIA1 may be omitted. For example, the anode connection line ACL may be electrically connected to the first electrode SE of the transistor TFT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0141] The second via layer VIA2 may be disposed on the second source metal layer SDL2. The second via layer VIA2 may be an insulating layer including an organic material.

[0142] The second protective layer PVX2 may be disposed on the second via layer VIA2. The second protective layer PVX2 may be an insulating layer including an inorganic material.

[0143] The third source metal layer SDL3 may be disposed on the second protection layer PVX2. The third source metal layer SDL3 may include a conductive material, and may have a single layer or a multi-layer.

[0144] The third source metal layer SDL3 may include an anode connection electrode ACE (or a bridge electrode). The anode connection electrode ACE may be electrically connected to the anode connection line ACL through a contact hole passing through the second protection layer PVX2 and the second via layer VIA2.

[0145] The third via layer VIA3 may be disposed on the third source metal layer SDL3. The third via layer VIA3 may be an insulating layer including an organic material.

[0146] The third protection layer PVX3 may be disposed on the third via layer VIA3. The third protection layer PVX3 may be an insulating layer including an inorganic material.

[0147] The pixel electrode layer PEL may be disposed on the third protective layer PVX3. The pixel electrode layer PEL may include a pixel electrode AND (or a first pixel electrode) and a common electrode COM (or a second pixel electrode). The pixel electrode AND may be referred to as an anode electrode, and the common electrode COM may be referred to as a cathode electrode.

[0148] The pixel electrode AND may be electrically connected to the anode connection electrode ACE through a contact hole passing through the third protection layer PVX3 and the third via layer VIA3. The pixel electrode AND may be electrically connected to the first electrode SE of the transistor TFT through the anode connection electrode ACE, the anode connection line ACL, and the connection electrode CCE. Therefore, the pixel voltage (or driving current) controlled by the transistor TFT may be applied to the pixel electrode AND.

[0149] Similar to the pixel electrode AND, the common electrode COM may be electrically connected to a power line (eg, second power line PL2 ) through a contact hole passing through the third protective layer PVX3 and the third via layer VIA3 . The power voltage of the power line may be applied to the common electrode COM through the third protective layer PVX3 and the third via layer VIA3 .

[0150] The pixel electrode AND and the common electrode COM may include a metal material having high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), etc. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0151] The fourth via layer VIA4 (or bank or pixel defining layer) may be disposed on the third protective layer PVX3. The fourth via layer VIA4 may be an insulating layer including an organic material. The fourth via layer VIA4 may include an opening, and at least a portion of the pixel electrode AND and the common electrode COM may be exposed through the opening of the fourth via layer VIA4.

[0152] The fourth protective layer PVX4 may be disposed on the third protective layer PVX3 (and the fourth via layer VIA4). The fourth protective layer PVX4 may cover the edge of the pixel electrode AND and the edge of the common electrode COM. The fourth protective layer PVX4 may be an insulating layer including an inorganic material.

[0153] The light emitting element ED may be disposed in the opening of the fourth via layer VIA4 (and the fourth protective layer PVX4 ). The light emitting element ED may be disposed on the pixel electrode AND and the common electrode COM that are not covered by the fourth protective layer PVX4 (or exposed by the fourth protective layer PVX4 ).

[0154] For example, the light emitting element ED may be a flip chip type micro LED. The light emitting element ED may be formed of an inorganic material such as GaN. Each of the lengths of the light emitting element ED in the first direction DR1, the second direction DR2, and the third direction DR3 may be in the range of several micrometers (μm) to several hundred micrometers (μm). For example, each of the lengths of the light emitting element ED in the first direction DR1, the second direction DR2, and the third direction DR3 may be less than or equal to about 100 μm.

[0155] exist Figure 7In the embodiment, the data line DL, the second power line PL2, or a line connected to the data line DL and the second power line PL2 may be disposed on the gate layer GTL, but the disclosure is not limited thereto. For example, a line including the data line DL and the second power line PL2 may be disposed on at least one of the first source metal layer SDL1, the second source metal layer SDL2, and the third source metal layer SDL3.

[0156] Fig.10 and Fig.11 It shows the manufacturing Figure 7 A schematic cross-sectional view of a method of displaying a device.

[0157] Reference Figure 7 , Fig.10 and Fig.11 , a carrier substrate SUB0 may be prepared. The carrier substrate SUB0 may be a rigid substrate including a glass material, but the disclosure is not limited thereto.

[0158] A sacrificial layer SSG may be formed on the carrier substrate SUB 0. The sacrificial layer SSG may include silicon dioxide sol-gel (Si sol-gel) or a polymer organic material, or the like.

[0159] The first mold pattern MP1 may be formed by the sacrificial layer SSG. For example, the first mold pattern MP1 may be formed by stamping the sacrificial layer SSG using a mold having a groove corresponding to the first mold pattern MP1. The shape, pitch, size, position, and arrangement of the first mold pattern MP1 may correspond to the reference pattern MP1, respectively. Figures 7 to 9 The shape, spacing, size, position and arrangement of the grooves GRV described.

[0160] A conductive layer CLL may be formed on the carrier substrate SUB0 to cover the first mold pattern MP1.

[0161] A photoresist PR may be formed on the conductive layer CLL. The photoresist PR may be disposed to correspond to the conductive pattern CP.

[0162] The conductive pattern CP may be formed from the conductive layer CLL by etching a portion of the conductive layer CLL exposed by the photoresist PR. After the conductive pattern CP is formed, the photoresist PR may be removed.

[0163] A substrate SUB (or base layer) may be formed on the carrier substrate SUB0 to cover the conductive patterns CP.

[0164] After forming the substrate SUB, refer to Fig.11, a lower electrode layer BML, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first source metal layer SDL1, a first via layer VIA1, a first protective layer PVX1, a second source metal layer SDL2, a second via layer VIA2, a second protective layer PVX2, a third source metal layer SDL3, a third via layer VIA3, a third protective layer PVX3, a pixel electrode layer PEL, a fourth via layer VIA4 and a fourth protective layer PVX4 can be sequentially formed on the substrate SUB.

[0165] The carrier substrate SUB0 may be removed or separated from the display device 10 (or substrate SUB). For example, the carrier substrate SUB0 may be removed from the display device 10 using a laser separation device. The first mold pattern MP1 may be removed or separated from the display device 10 (or substrate SUB) together with the carrier substrate SUB0. The groove corresponding to the first mold pattern MP1 (see, for example, Figure 7 A GRV) may be formed on a lower surface of the substrate SUB.

[0166] After the groove GRV is formed, a light emitting element may be disposed or mounted on the pixel electrode layer PEL (eg, on the pixel electrode AND and the common electrode COM) exposed by the fourth via layer VIA4 and the fourth protective layer PVX4 (eg, Figure 7 ED). For example, the light emitting element ED can be formed by growing on a semiconductor substrate such as a silicon wafer. The light emitting element ED can be transferred from the silicon wafer to the pixel electrode AND and the common electrode COM of the display device 10. In another embodiment, the light emitting element ED can be transferred to the pixel electrode AND and the common electrode COM of the display device 10 by an electrostatic method using an electrostatic head, a stamping method using an elastic polymer material (such as PDMS or silicon, etc.).

[0167] As described above, the display device 10 can be manufactured only by sequentially forming the front surface processes from the substrate SUB to the pixel electrode layer PEL on the carrier substrate SUB0. For example, it is not necessary to form a conductive pattern (for example, for connecting to a circuit board (see, for example)) on the lower portion of a conventional substrate. Fig.12 The display device 10 including the conductive pattern CP exposed under the substrate SUB can be manufactured by a simpler process. Since the connecting line (and the insulating layer) are not disposed on the side surface of the display device 10, the invalid space of the display device 10 (for example, the area at the edge of the display device 10 where the sub-pixel SPX is not disposed) can be reduced, and the invalid space can be substantially absent in the display device 10.

[0168] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic cross-sectional view of a display device. Fig.13 It shows the manufacturing Fig.12 A schematic cross-sectional view of a method of displaying a device. Fig.14 is a diagram showing a method according to an embodiment of the present invention. Fig.12 A schematic plan view of a display device. Fig.15 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of a display device.

[0169] Reference Figure 1 , Figure 7 , Fig.12 , Fig.13 and Fig.14 , the display device 10 may further include a circuit board FPCB (or a circuit film).

[0170] The circuit board FPCB may be disposed under the substrate SUB and may be connected to the conductive pattern CP through an anisotropic conductive film ACF or a bump BUMP, etc. For example, the circuit board FPCB may include a wire and a pad electrically connected to a driving circuit (e.g., a data driver mounted on the circuit board FPCB), and the wire may be electrically connected to the conductive pattern CP through the pad and the anisotropic conductive film ACF (or the bump BUMP).

[0171] For example, refer to Fig.13 and Fig.14 The display device 10 may be implemented as a spliced ​​display device including a plurality of display panels 11, 12, 13, 14, 15, and 16. The display panels 11 to 16 (e.g., the first display panel 11 and the second display panel 12) may be mounted on a substrate having an anisotropic conductive film (see, e.g., Fig.13 ACF) (or bump (see e.g. Fig.13 The display device 10 is manufactured on a circuit board FPCB with a BUMP)).

[0172] As reference Fig.10 and Fig.11As described, since there is basically no invalid space in the display device 10 (or display panels 11 to 16), even if the display panels 11 to 16 with different sizes and shapes are spliced ​​like a mosaic, there may be no misalignment (or staggering) between the display panels 11 to 16, and the display device 10 may have a perfect shape (e.g., a desired shape). For example, the length of the display device 10 in the first direction DR1 may be the same as the following parts: the first part connected to the first display panel 11 and the second display panel 12; the second part connected to the first display panel 11, the third display panel 13 and the fourth display panel 14; the third part connected to the first display panel 11, the third display panel 13 and the fifth display panel 15; and the fourth part connected to the first display panel 11, the third display panel 13 and the fifth display panel 15 and the sixth display panel 16. Therefore, the size or shape of the display panels 11 to 16 constituting the display device 10 may not need to be the same, and the shape of each of the display panels 11 to 16 may not need to be limited to a quadrilateral. For example, the shapes of the display panels 11 to 16 may be irregular. Since the mother panel (or motherboard) including the display panels 11 to 16 can be used substantially 100% (for example, compared to a case where the mother panel is not used 100%), the manufacturing cost of the display device 10 can be reduced. In the case where a defect exists in a part of the mother panel, most of the mother panel can be used to manufacture the display device 10 except for the corresponding area (for example, the smallest area) where the defect exists, and the manufacturing cost can be reduced.

[0173] In an embodiment, the resolution (e.g., pixels per inch (PPI)) of at least two of the display panels 11 to 16 may be different. Depending on the purpose of the display device 10, the resolution of a portion of the display device 10 and the resolution of another portion of the display device 10 may be different from each other. For example, the resolution of the third display panel 13 may be larger than the resolution of the first display panel 11, and the resolution of the fifth display panel 15 may be lower than the resolution of the first display panel 11. Since the size and shape of the display panels 11 to 16 do not need to be the same, only a portion (e.g., a desired portion) of the display device 10 may have different resolutions.

[0174] Reference Fig.15 , the mother panel 1 can be stored in a rollable form.

[0175] The display panels 11_1, 12_1, and 13_1 may be obtained by cutting only a portion (eg, a specific portion) of the mother panel 1. As described above, since the substrate SUB is a flexible substrate including an insulating material such as a polymer resin including polyimide (PI), each of the display panels 11_1, 12_1, and 13_1 may be bent or rolled.

[0176] For example, the display device 10_1 may be manufactured by attaching the first display panel 11_1 to a cylinder (or a column having a curved surface).

[0177] The display device 10_1 may further include a fourth display panel 14, and the fourth display panel 14 and the first display panel 11_1 may have different sizes or different shapes. The fourth display panel 14 and the first display panel 11_1 may have different resolutions.

[0178] Fig.16 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic cross-sectional view of a display device. Fig.16 A simplified cross-sectional view of the display device 10 based on some of the light emitting elements ED1 to ED3 is shown. Fig.17 is a display device shown included in Fig.16 Schematic bottom view of a valley in a display device.

[0179] Reference Figure 1 , Figure 7 , Fig.16 and Fig.17 , each of the light emitting elements ED1 to ED3 (or a stacked structure including the light emitting elements ED1 to ED3) may correspond to a sub-pixel SPX (see, for example Figure 7 ). Figure 5 As described above, the first light emitting element ED1 may correspond to the first sub-pixel SPX1, the second light emitting element ED2 may correspond to the second sub-pixel SPX2, and the third light emitting element ED3 may correspond to the third sub-pixel SPX3. The first light emitting element ED1 to the third light emitting element ED3 (or the first sub-pixel SPX1 to the third sub-pixel SPX3) may be included in one pixel PX. Figure 7 and Fig.12 The structure of the sub-pixel SPX is described, and thus the description of the structure of the sub-pixel SPX is omitted, and the description is similar to Figure 7 and Fig.12 The differences in embodiments. Figure 7 and Fig.12 The embodiments can be applied to Fig.16 Embodiment of the invention.

[0180] On the lower surface of the substrate SUB, (in addition to the groove GRV), a first valley LVAL (or lower valley) may be formed. For example, similar to the groove GRV, the first valley LVAL may have a shape in which the lower surface of the substrate SUB is concave in the third direction DR3. The conductive pattern may not be provided in the first valley LVAL.

[0181] In an embodiment, in a cross-sectional view, the shape of the first valley LVAL and the shape of the groove GRV may be different from each other. Fig.16 In the cross-sectional view, the first valley LVAL may have a triangular shape (eg, an isosceles triangle, a right triangle, or an equilateral triangle, etc.). However, the disclosure is not limited thereto, and in another embodiment, in the cross-sectional view, the groove GRV may have a trapezoidal or semicircular shape, etc.

[0182] In the embodiments, reference Fig.17 In a bottom view, the first valley LVAL may extend in the first direction DR1 and / or the second direction DR2, and the first valley LVAL may extend in a direction parallel to at least one pixel PX (or at least one light emitting element (see, for example Figure 7 The corresponding spacings of ED)) are arranged repeatedly.

[0183] For example, the first valley LVAL may include a first horizontal valley LVAL_H extending in the first direction DR1 and arranged in the second direction DR2. The first valley LVAL may include a first vertical valley LVAL_V extending in the second direction DR2 and arranged in the first direction DR1. The first horizontal valley LVAL_H and the first vertical valley LVAL_V may cross each other, and the first valley LVAL may have a mesh structure throughout the display device 10 (or the mother panel 1).

[0184] According to an embodiment, the first valley LVAL (or the first horizontal valley LVAL_H and the first vertical valley LVAL_V) may be repeatedly arranged at a pitch corresponding to a block BLK (eg, a block including a plurality of pixels PX) or a sub-pixel SPX.

[0185] As described above, in the case where the display device 10 (or the mother panel 1) is bendable or rollable, the first valley LVAL can reduce the stress caused by the bending or rolling of the display device 10 (or the mother panel 1), and can facilitate the bending or rolling of the display device 10 (or the mother panel 1).

[0186] As described above, in the case where the display device 10 (or display panel) is obtained by cutting the mother panel 1, the first valley LVAL and the second valley UVAL can together contribute to cutting the mother panel 1 (or the display device 10). Since the first valley LVAL is arranged at a pitch corresponding to at least one pixel PX and the mother panel 1 can be arbitrarily cut based on the first valley LVAL (or the arrangement pitch of the first valley LVAL), the display device 10 having an irregular shape (for example, a polygon other than a quadrilateral) in a plan view can be easily manufactured.

[0187] Refer again Fig.16 A second valley UVAL exposing a pixel electrode (eg, an anode or cathode electrode contacting the light emitting elements ED1 to ED3 ) may be further formed on the fourth via layer VIA4 (and the fourth protective layer PVX4 ).

[0188] For example, refer to Fig.16 In the cross-sectional view, the second valley UVAL may have a quadrilateral shape, but the disclosure is not limited thereto. For example, in the cross-sectional view, the second valley UVAL may have an inverted trapezoid, an inverted triangle, or a semicircle.

[0189] In the embodiments, reference Fig.17 , the second valley UVAL may extend in the first direction DR1 or the second direction DR2, and the second valley UVAL may be repeatedly arranged at a pitch corresponding to at least one pixel PX. For example, the second valley UVAL may correspond to the first valley LVAL. For example, the first valley LVAL and the second valley UVAL may overlap each other in the third direction DR3 (or in a plan view), or the first valley LVAL and the second valley UVAL may be located on the same virtual line extending in the third direction DR3. However, the disclosure is not limited thereto.

[0190] For example, the second valley UVAL may include a second horizontal valley UVAL_H extending in the first direction DR1 and arranged in the second direction DR2. The second valley UVAL may include a second vertical valley UVAL_V extending in the second direction DR2 and arranged in the first direction DR1. The second valley UVAL may have a mesh structure throughout the display device 10 (or the mother panel 1).

[0191] According to an embodiment, the second valley UVAL (or the second horizontal valley UVAL_H and the second vertical valley UVAL_V) may be repeatedly arranged at a pitch corresponding to a block BLK (eg, a block including the pixel PX) or a sub-pixel SPX.

[0192] Fig.18 and Fig.19 It shows the manufacturing Fig.16 A schematic cross-sectional view of a method of displaying a device. Fig.18 Shown with Fig.10 The cross section corresponding to the embodiment, Fig.19 Shown with Fig.16 The cross section corresponding to area AA.

[0193] Reference Fig.10 , Fig.16 , Fig.18 and Fig.19 , a carrier substrate SUB0 can be prepared.

[0194] A sacrificial layer SSG may be formed on the carrier substrate SUB0.

[0195] The first mold pattern MP1 and the second mold pattern MP2 may be formed by the sacrificial layer SSG. For example, the first mold pattern MP1 and the second mold pattern MP2 may be formed by stamping the sacrificial layer SSG using a mold including grooves corresponding to the first mold pattern MP1 and the second mold pattern MP2. The shape, arrangement, spacing, size, and position of the second mold pattern MP2 may correspond to the reference pattern MP1, MP2, and the like. Fig.16 and Fig.17 The shape, arrangement, spacing, size and position of the first valley LVAL are described.

[0196] A conductive layer CLL may be formed on the carrier substrate SUB0 to cover the first and second mold patterns MP1 and MP2 .

[0197] A photoresist PR may be formed on the conductive layer CLL. The photoresist PR may be disposed to correspond to the conductive pattern CP. The photoresist PR may not be disposed on the second mold pattern MP2, or may be removed.

[0198] The conductive pattern CP may be formed from the conductive layer CLL by etching a portion of the conductive layer CLL exposed by the photoresist PR. After the conductive pattern CP is formed, the photoresist PR may be removed.

[0199] A substrate SUB (or base layer) may be formed on the carrier substrate SUB0 to cover the conductive patterns CP and the second mold patterns MP2.

[0200] After forming the substrate SUB, refer to Fig.19 , a buffer layer BF, a gate insulating layer GI, an interlayer insulating layer ILD, a first via layer VIA1, a first protective layer PVX1, a second via layer VIA2, a second protective layer PVX2, a third via layer VIA3, a third protective layer PVX3, a fourth via layer VIA4 and a fourth protective layer PVX4 may be sequentially formed on the substrate SUB. As described above, a second valley UVAL corresponding to the first valley LVAL of the substrate SUB may be formed on the fourth via layer VIA4 (and the fourth protective layer PVX4).

[0201] The carrier substrate SUB0 may be removed or separated from the display device 10 (or substrate SUB). The first mold pattern MP1 and the second mold pattern MP2 may be removed or separated from the display device 10 (or substrate SUB) together with the carrier substrate SUB0. A groove corresponding to the first mold pattern MP1 may be formed on the lower surface of the substrate SUB (see, for example, Fig.16 GRV) and a first valley LVAL corresponding to the second molding pattern MP2.

[0202] After forming the groove and the first valley LVAL, the pixel electrode layer (see, for example, Figure 7 A light emitting element is arranged or mounted on a PEL (see for example Fig.16 ED1 to ED3).

[0203] As described above, the first valley LVAL may be formed together with the groove GRV.

[0204] Fig. 20 and Fig.21 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic cross-sectional view of a display device. Fig. 20 and Fig.21 A simplified cross-sectional view of the display device 10 based on some of the light emitting elements ED1 to ED3 is shown. Fig. 22 is a display device shown included in Fig. 20 and Fig.21 Schematic bottom view of a groove in a display device.

[0205] Reference Figure 1 , Figure 7 , Fig.12 , Fig. 20 , Fig.21 and Fig. 22 , each of the light emitting elements ED1 to ED3 (or a stacked structure including the light emitting elements ED1 to ED3) may correspond to a sub-pixel SPX (see, for example Figure 7 and Fig.12 ). Figure 5 As described above, the first light emitting element ED1 may correspond to the first sub-pixel SPX1, the second light emitting element ED2 may correspond to the second sub-pixel SPX2, and the third light emitting element ED3 may correspond to the third sub-pixel SPX3. The first light emitting element ED1 to the third light emitting element ED3 (or the first sub-pixel SPX1 to the third sub-pixel SPX3) may be included in one pixel PX. Figure 7 and Fig.12 The structure of the sub-pixel SPX is described, so the description of the structure of the sub-pixel SPX is omitted, and the description is similar to Figure 7 Embodiments (except Fig.12 and Fig.16 (except for the differences). Figure 7 Embodiments (except Fig.12 and Fig.16 In addition) can be applied to Fig. 20 and Fig.21 Embodiment of the invention.

[0206] In an embodiment, the groove GRV_1 may be formed on the lower surface of the substrate SUB. For example, the groove GRV_1 may have a shape in which the lower surface of the substrate SUB is concave in the third direction DR3.

[0207] In an embodiment, the groove GRV_1 may include a curved surface. Figure 7 , in a cross-sectional view, the groove GRV_1 may have a quadrilateral shape whose corners are rounded. However, the disclosure is not limited thereto, and in another embodiment, in a cross-sectional view, the groove GRV_1 may have a quadrilateral shape.

[0208] In the embodiments, reference Fig. 22 , in a plan view, the groove GRV_1 may have a quadrilateral shape whose corners are rounded. However, the disclosure is not limited thereto, and in another embodiment, in a plan view, the groove GRV_1 may have a circular shape.

[0209] In an embodiment, the grooves GRV_1 may be repeatedly arranged in the first direction DR1 (and / or the second direction DR2) corresponding to at least one pixel (for example, a pixel including the first to third light emitting elements ED1 to ED3). For example, in the case where the size of the sub-pixel is small, since only the first to third light emitting elements ED1 to ED3 are used, the grooves GRV_1 may be repeatedly arranged in the first direction DR1 (and / or the second direction DR2) corresponding to at least one pixel (for example, a pixel including the first to third light emitting elements ED1 to ED3). Figure 7 The groove GRV may fail to ensure a stable connection between the conductive pattern CP and the circuit board FPCB, and thus the groove GRV_1 may be arranged corresponding to at least one pixel.

[0210] The conductive pattern CP_1 (or the connection pattern) may be disposed in the groove GRV_1. The conductive pattern CP_1 may include a first conductive pattern CP1 and a second conductive pattern CP2. For example, both the first conductive pattern CP1 and the second conductive pattern CP2 may be disposed in each groove GRV_1.

[0211] In an embodiment, the first conductive pattern CP1 may be connected to a plurality of first bridge patterns BRP1 extending in the second direction DR2. Fig. 22 , the first conductive pattern CP1 may be connected to three first bridge patterns BRP1 extending in the second direction DR2. The first bridge patterns BPR1 may be connected to each other by a line (or portion) extending in the first direction DR1. The first bridge pattern BRP1 may be connected to a plurality of first bridge patterns BRP1 in an adjacent groove GRV_1 by a line, but the disclosure is not limited thereto. For example, the first bridge patterns BPR1 corresponding to only one groove GRV_1 may be connected to each other and may be electrically separated or insulated from the first bridge pattern BRP1 in the adjacent groove GRV_1.

[0212] Similar to the first conductive pattern CP1, the second conductive pattern CP2 may be connected to a plurality of second bridge patterns BRP2 extending in the second direction DR2.

[0213] In an embodiment, each of the first conductive pattern CP1 and the second conductive pattern CP2 may include at least one of the protrusions PRT1 and PRT2. Fig. 22 , the first conductive pattern CP1 may include a first protrusion PRT1 protruding in a direction opposite to the second direction DR2, and the second conductive pattern CP2 may include a second protrusion PRT2 protruding in the second direction DR2. Each of the first protrusion PRT1 and the second protrusion PRT2 may ensure a contact area between the anisotropic conductive film ACF (or bump BUMP) and each of the first conductive pattern CP1 and the second conductive pattern CP2. The first protrusion PRT1 and the second protrusion PRT2 may not be aligned with each other or may be alternately arranged in the first direction DR1, and a short circuit between the first conductive pattern CP1 and the second conductive pattern CP2 may be prevented.

[0214] As described above, the groove GRV_1 may be positioned corresponding to at least one pixel, and a plurality of conductive patterns CP_1 may be disposed in the groove GRV_1 .

[0215] Fig.23 is a schematic plan view showing a spliced ​​display device including a plurality of display devices according to an embodiment.

[0216] Reference Fig.23 , the spliced ​​display device TD may include a plurality of display devices 10_1, 10_2, 10_3, and 10_4. For example, the spliced ​​display device TD may include a first display device 10_1, a second display device 10_2, a third display device 10_3, and a fourth display device 10_4.

[0217] Each of the display devices 10_1 to 10_4 may include pixels, and the display devices 10_1 to 10_4 may be disposed adjacent to each other at intervals corresponding to or equal to intervals between pixels.

[0218] The display devices 10_1 to 10_4 may have the same size and may be arranged in a grid shape, but the disclosure is not limited thereto. Fig.14 The display panels 11 to 16 described, at least some of the display devices 10_1 to 10_4 may have different sizes (or different shapes, for example, irregular shapes), and the display devices 10_1 to 10_4 may be arbitrarily arranged. At least some of the display devices 10_1 to 10_4 may have different resolutions.

[0219] In an embodiment, the spliced ​​display device TD may further include a seam SM. The seam SM may include a bonding member or an adhesive member, etc. The display devices 10_1 to 10_4 may be connected to each other by a bonding member or an adhesive member of the seam SM. The seam SM may be provided between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4. However, the disclosure is not limited thereto, and similarly Fig.13 and Fig.14 In the embodiment, there may be no seam SM between the display devices 10_1 to 10_4.

[0220] Fig.24 yes Fig.23 Schematic enlarged plan view of area AA.

[0221] Reference Fig.24 , the first display device 10_1 may include first pixels PX1 arranged in a matrix form in a first direction DR1 and a second direction DR2 to display an image. The second display device 10_2 may include second pixels PX2 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The third display device 10_3 may include third pixels PX3 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 10_4 may include fourth pixels PX4 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. Each of the first pixel PX1 to the fourth pixel PX4 may be a pixel (see, for example Figures 1 to 3 of PX).

[0222] A distance (e.g., a minimum distance) between first pixels PX1 disposed adjacent to each other in the first direction DR1 may be defined as a first horizontal spacing distance GH1, and a distance (e.g., a minimum distance) between second pixels PX2 disposed adjacent to each other in the first direction DR1 may be defined as a second horizontal spacing distance GH2. The first horizontal spacing distance GH1 and the second horizontal spacing distance GH2 may be substantially the same.

[0223] The seam SM may be disposed between the first pixel PX1 and the second pixel PX2 disposed adjacent to each other in the first direction DR1. The distance (e.g., minimum distance) GG1 between the first pixel PX1 and the second pixel PX2 disposed adjacent to each other in the first direction DR1 may be the sum of the distance (e.g., minimum distance) GHS1 between the first pixel PX1 and the seam SM in the first direction DR1, the distance (e.g., minimum distance) GHS2 between the second pixel PX2 and the seam SM in the first direction DR1, and the width GSM1 of the seam SM in the first direction DR1.

[0224] The distance (e.g., minimum distance) GG1 between the first pixel PX1 and the second pixel PX2 that are adjacent in the first direction DR1, the first horizontal spacing distance GH1, and the second horizontal spacing distance GH2 may be the same. For example, the distance GHS1 between the first pixel PX1 and the seam SM in the first direction DR1 may be smaller than the first horizontal spacing distance GH1, and the distance GHS2 between the second pixel PX2 and the seam SM in the first direction DR1 may be smaller than the second horizontal spacing distance GH2. The width GSM1 of the seam SM in the first direction DR1 may be smaller than the first horizontal spacing distance GH1 or the second horizontal spacing distance GH2.

[0225] A distance (e.g., a minimum distance) between third pixels PX3 disposed adjacent to each other in the first direction DR1 may be defined as a third horizontal spacing distance GH3, and a distance (e.g., a minimum distance) between fourth pixels PX4 disposed adjacent to each other in the first direction DR1 may be defined as a fourth horizontal spacing distance GH4. The third horizontal spacing distance GH3 and the fourth horizontal spacing distance GH4 may be substantially the same.

[0226] The seam SM may be disposed between the third pixel PX3 and the fourth pixel PX4 disposed adjacent to each other in the first direction DR1. The distance (e.g., minimum distance) GG4 between the third pixel PX3 and the fourth pixel PX4 disposed adjacent to each other in the first direction DR1 may be the sum of the distance (e.g., minimum distance) GHS3 between the third pixel PX3 and the seam SM in the first direction DR1, the distance (e.g., minimum distance) GHS4 between the fourth pixel PX4 and the seam SM in the first direction DR1, and the width GSM1 of the seam SM in the first direction DR1.

[0227] The distance GG4 between the third pixel PX3 and the fourth pixel PX4, which are adjacent to each other in the first direction DR1, the third horizontal spacing distance GH3, and the fourth horizontal spacing distance GH4 may be substantially the same. For example, the distance GHS3 between the third pixel PX3 and the seam SM in the first direction DR1 may be smaller than the third horizontal spacing distance GH3, and the distance GHS4 between the fourth pixel PX4 and the seam SM in the first direction DR1 may be smaller than the fourth horizontal spacing distance GH4. The width GSM1 of the seam SM in the first direction DR1 may be smaller than the third horizontal spacing distance GH3 or the fourth horizontal spacing distance GH4.

[0228] A distance (e.g., a minimum distance) between first pixels PX1 disposed adjacent to each other in the second direction DR2 may be defined as a first vertical spacing distance GV1, and a distance (e.g., a minimum distance) between third pixels PX3 disposed adjacent to each other in the second direction DR2 may be defined as a third vertical spacing distance GV3. The first vertical spacing distance GV1 and the third vertical spacing distance GV3 may be substantially the same.

[0229] The seam SM may be disposed between the first pixel PX1 and the third pixel PX3 disposed adjacent to each other in the second direction DR2. The distance (e.g., minimum distance) GG2 between the first pixel PX1 and the third pixel PX3 disposed adjacent to each other in the second direction DR2 may be the sum of the distance (e.g., minimum distance) GVS1 between the first pixel PX1 and the seam SM in the second direction DR2, the distance (e.g., minimum distance) GVS3 between the third pixel PX3 and the seam SM in the second direction DR2, and the width GSM2 of the seam SM in the second direction DR2.

[0230] The distance GG2, the first vertical spacing distance GV1, and the third vertical spacing distance GV3 between the first pixel PX1 and the third pixel PX3, which are adjacent to each other in the second direction DR2, may be substantially the same. For example, the distance GVS1 between the first pixel PX1 and the seam SM in the second direction DR2 may be smaller than the first vertical spacing distance GV1, and the distance GVS3 between the third pixel PX3 and the seam SM in the second direction DR2 may be smaller than the third vertical spacing distance GV3. The width GSM2 of the seam SM in the second direction DR2 may be smaller than the first vertical spacing distance GV1 or the third vertical spacing distance GV3.

[0231] A distance (e.g., a minimum distance) between second pixels PX2 disposed adjacent to each other in the second direction DR2 may be defined as a second vertical spacing distance GV2, and a distance (e.g., a minimum distance) between fourth pixels PX4 disposed adjacent to each other in the second direction DR2 may be defined as a fourth vertical spacing distance GV4. The second vertical spacing distance GV2 and the fourth vertical spacing distance GV4 may be substantially the same.

[0232] The seam SM may be disposed between the second pixel PX2 and the fourth pixel PX4 disposed adjacent to each other in the second direction DR2. The distance (e.g., minimum distance) GG3 between the second pixel PX2 and the fourth pixel PX4 disposed adjacent to each other in the second direction DR2 may be the sum of the distance (e.g., minimum distance) GVS2 between the second pixel PX2 and the seam SM in the second direction DR2, the distance (e.g., minimum distance) GVS4 between the fourth pixel PX4 and the seam SM in the second direction DR2, and the width GSM2 of the seam SM in the second direction DR2.

[0233] The distance GG3, the second vertical spacing distance GV2, and the fourth vertical spacing distance GV4 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2 may be substantially the same. For example, the distance GVS2 between the second pixel PX2 and the seam SM in the second direction DR2 may be smaller than the second vertical spacing distance GV2, and the distance GVS4 between the fourth pixel PX4 and the seam SM in the second direction DR2 may be smaller than the fourth vertical spacing distance GV4. The width GSM2 of the seam SM in the second direction DR2 may be smaller than the second vertical spacing distance GV2 or the fourth vertical spacing distance GV4.

[0234] Reference Fig.24 , the distance between pixels of the display devices arranged to be adjacent to each other and the distance between pixels of each of the display devices may be substantially the same, so that a seam SM is not visually recognized between images displayed by the display devices 10_1 to 10_4.

[0235] Fig.25 is a schematic block diagram showing a spliced ​​display device according to an embodiment. For ease of explanation, Fig.25 A first display device 10_1 and a host system HOST are shown.

[0236] Reference Fig.23 and Fig.25 According to the embodiment, the splicing display device TD may include a host system HOST, a broadcast tuning part (unit) 210, a signal processing part (unit) 220, a display part (unit) 230, a speaker 240, a user input part (unit) 250, an HDD 260, a network communication part 270 (unit), a UI generation part (unit) 280 and a control part (unit) 290.

[0237] The host system HOST may be implemented as one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer, a mobile phone system, a tablet computer, and the like.

[0238] The user's instructions can be input to the host system HOST in various formats. For example, the instructions input by the user's touch can be input to the host system HOST. In another embodiment, the user's instructions can be input to the host system HOST through keyboard input or button input of a remote controller.

[0239] The host system HOST may receive raw video data corresponding to the raw image from the outside. The host system HOST may divide the raw video data according to the number of display devices. For example, in response to the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4, the host system HOST may divide the raw video data into first video data corresponding to the first image, second video data corresponding to the second image, third video data corresponding to the third image, and fourth video data corresponding to the fourth image. The host system HOST may transmit the first video data to the first display device 10_1, the second video data to the second display device 10_2, the third video data to the third display device 10_3, and the fourth video data to the fourth display device 10_4.

[0240] The first display device 10_1 can display the first image according to the first video data, the second display device 10_2 can display the second image according to the second video data, the third display device 10_3 can display the third image according to the third video data, and the fourth display device 10_4 can display the fourth image according to the fourth video data. Therefore, the user can view the original image in which the first to fourth images displayed on the first to fourth display devices 10_1 to 10_4 are combined.

[0241] The first display device 10_1 may include a broadcast tuner 210 , a signal processing part 220 , a display part 230 , a speaker 240 , a user input part 250 , an HDD 260 , a network communication part 270 , a UI generation part 280 , and a control part 290 .

[0242] The broadcast tuner 210 can tune a channel frequency (e.g., a predetermined or selectable channel frequency) under the control of the control unit 290 and receive a broadcast signal of a corresponding channel through an antenna. The broadcast tuner 210 may include a channel detection module (not shown) and an RF demodulation module (not shown).

[0243] The broadcast signal demodulated by the broadcast tuner 210 may be processed by the signal processor 220 and output to the display 230 and the speaker 240. The signal processor 220 may include a demultiplexer 221, a video decoder 222, a video processor (unit) 223, an audio decoder 224, and an additional data processor (unit) 225.

[0244] The demultiplexer 221 may divide the demodulated broadcast signal into a video signal, an audio signal, and additional data. The divided video signal, audio signal, and additional data may be restored by the video decoder 222, the audio decoder 224, and the additional data processing unit 225, respectively. In the case of transmitting a broadcast signal, the video decoder 222, the audio decoder 224, and the additional data processing unit 225 may restore the divided video signal, audio signal, and additional data to a decoding format corresponding to the encoding format.

[0245] The decoded video signal may be converted by the video processing part 223 to match the vertical frequency, resolution, aspect ratio, etc. of an image corresponding to the output standard of the display part 230 , and the decoded audio signal may be output to the speaker 240 .

[0246] The display part 230 may include a display panel (not shown) on which an image is displayed and a panel driver (not shown) that controls driving of the display panel.

[0247] The user input unit 250 may receive a signal transmitted from the host system HOST. The user input unit 250 may receive data for selecting and inputting commands related to communication with other display devices of a user and data related to selection and manipulation of a channel transmitted by the host system HOST and a user interface (UI) menu.

[0248] The HDD 260 may store various software programs including an OS program, recorded broadcast programs, moving pictures, photos, and other data, and may be formed of a storage medium such as a hard disk or a nonvolatile memory.

[0249] The network communication unit 270 may be used for short-range communication with the host system HOST and other display devices, and may be implemented using a communication module including an antenna pattern for implementing mobile communication, data communication, Bluetooth, RF, Ethernet, and the like.

[0250] The network communication unit 270 can send and receive wireless signals with at least one of a base station, an external terminal and a server on a mobile communication network constructed according to a technical standard or communication method for mobile communication (for example, Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA2000), Enhanced Voice Data Optimization or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Advanced Long Term Evolution (LTE-A) or 5G, etc.) through the antenna mode to be described below.

[0251] The network communication unit 270 can send and receive wireless signals in a communication network according to wireless Internet technology through an antenna mode to be described below. The wireless Internet technology may include, for example, wireless LAN (WLAN), wireless fidelity (Wi-Fi), wireless fidelity (Wi-Fi) direct connection, digital living network alliance (DLNA), wireless broadband (WiBro), world microwave access interoperability (WiMAX), high-speed downlink packet access (HSDPA), high-speed uplink packet access (HSUPA), long-term evolution (LTE) and advanced long-term evolution (LTE-A), etc., and the antenna mode can send and receive data according to at least one wireless Internet technology within the range including Internet technologies not listed above.

[0252] The UI generation unit 280 may generate a UI menu for communicating with the host system HOST and other display devices, and may be implemented by an algorithm code and an OSD IC. The UI menu for communicating with the host system HOST and other display devices may be a menu for specifying a corresponding digital TV for communication and selecting a function (e.g., a desired function).

[0253] The control unit 290 can be responsible for the overall control of the first display device 10_1, and is responsible for the communication control of the host system HOST and the second display device to the fourth display device 10_2, 10_3 and 10_4, and can store the corresponding algorithm code for control, and the control unit 290 can be implemented by a microcontroller unit (MCU) that executes the stored algorithm code.

[0254] The control unit 290 may control to transmit corresponding control instructions and data to the host system HOST and the second to fourth display devices 10_2, 10_3, and 10_4 through the network communication unit 270 according to the input and selection of the user input unit 250. Of course, in the case where control instructions and data (e.g., predetermined or selectable control instructions and data) are input from the host system HOST and the second to fourth display devices 10_2, 10_3, and 10_4, operations may be performed according to the corresponding control instructions.

[0255] Due to the combination Fig.25 The block diagram of the second display device 10_2, the block diagram of the third display device 10_3, and the block diagram of the fourth display device 10_4 are substantially the same as the block diagram of the first display device 10_1, and thus descriptions of the block diagrams of the second to fourth display devices 10_2, 10_3, and 10_4 are omitted.

[0256] The above description is an example of the disclosed technical features, and those skilled in the art will be able to make various modifications and changes.Therefore, the above disclosed embodiments can be implemented individually or in combination with each other.

[0257] Therefore, the embodiments disclosed in the disclosure are not intended to limit the disclosed technical spirit, but to describe the disclosed technical spirit, and the scope of the disclosed technical spirit is not limited by these embodiments. The disclosed protection scope should be interpreted by the claims, and it should be interpreted that all technical spirits within the equivalent scope are within the disclosed scope.

Claims

1. A display device, characterized in that: The display device comprises: a base including a groove on a lower surface; A conductive pattern, disposed in the groove of the substrate; a bridge pattern disposed on the substrate and electrically connected to the conductive pattern through a contact hole passing through the substrate; A first insulating layer, disposed on the substrate and covering the bridge pattern; A transistor, disposed on the first insulating layer; a second insulating layer, disposed on the substrate and covering the transistor; and A light emitting element is disposed on the second insulating layer, wherein the bridge pattern is electrically connected to the transistor or the light emitting element, A first valley different from the groove is further formed on the lower surface of the substrate, and The conductive pattern is not disposed in the first valley.

2. The display device according to claim 1, characterized in that The substrate is a flexible substrate.

3. The display device according to claim 1, characterized in that In cross section, the shape of the first valley and the shape of the groove are different from each other, and Wherein, in cross section, the groove has a semicircular shape, and the first valley has a triangular shape.

4. The display device according to claim 1, characterized in that In a plane, the first valleys extend in a first direction and are repeatedly arranged in a second direction intersecting the first direction at a pitch corresponding to the light emitting elements, and Wherein, in a plane, the first valleys are arranged in a mesh structure throughout the entire area of ​​the substrate.

5. The display device according to claim 1, characterized in that The display device further includes: A pixel defining layer is disposed on the second insulating layer, wherein an opening for arranging the light emitting element and a second valley different from the opening are formed in the pixel defining layer, and In a plane, the first valley overlaps with the second valley.

6. The display device according to claim 1, characterized in that: The display device further includes: A circuit board is disposed under the substrate and is electrically connected to the conductive pattern through the groove of the substrate.

7. The display device according to claim 1, characterized in that The groove comprises a curved surface, The conductive pattern includes a curved surface corresponding to the groove, and At least a portion of the groove is defined by a lower surface of the conductive pattern.

8. The display device according to claim 1, characterized in that: The light emitting element is included in a plurality of sub-pixels, and The grooves are repeatedly arranged in a first direction at a pitch corresponding to at least one sub-pixel among the plurality of sub-pixels.

9. The display device according to claim 8, characterized in that: The groove has a size corresponding to a plurality of sub-pixels, and A plurality of conductive patterns are disposed in the grooves.

10. A splicing display device, characterized in that: The splicing display device comprises: A plurality of display devices each comprising pixels, wherein the plurality of display devices are arranged adjacent to each other at a spacing corresponding to the spacing between the pixels, At least one of the plurality of display devices includes: a substrate including a groove on a lower surface; a conductive pattern disposed in the groove of the substrate; a bridge pattern disposed on the substrate and electrically connected to the conductive pattern through a contact hole passing through the substrate; a first insulating layer disposed on the substrate and covering the bridge pattern; a transistor disposed on the first insulating layer; a second insulating layer disposed on the substrate and covering the transistor; and a light emitting element disposed on the second insulating layer. The bridge pattern is electrically connected to the transistor or the light emitting element, and A first valley different from the groove is further formed on the lower surface of the substrate.

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