Semiconductor device and HEMT device

Abstract

The utility model relates to a semiconductor device and an HEMT device. The HEMT device comprises a semiconductor body with a semiconductor heterostructure; comprising a semiconductor material, the control region on the semiconductor body, the control region having a top surface and a plurality of lateral sides; a control terminal of a conductive material extending on and in contact with a top surface of the control region; a passivation layer of a non-conductive material, the passivation layer extending on the semiconductor body, partially on a top surface of the control region, and on the plurality of lateral sides of the control region, the passivation layer being laterally arranged and a distance from the control terminal; and a plurality of spacer regions of a non-conductive material, the plurality of spacer regions extending between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions. The utility model is used in the field of integrated circuits, and has the technical effect that the leakage of the grid is reduced.

Description

Technical Field

[0001] The present disclosure relates to high electron mobility transistor (HEMT) devices with reduced gate leakage. Background Art

[0002] As is well known, HEMT devices, commonly referred to as heterostructure field effect transistors (HFETs), have been widely used in high-power and fast-switching applications due to their high breakdown voltage and the possibility of operating at high voltages with high carrier density and mobility.

[0003] In HEMT devices, the semiconductor heterostructure (usually based on AlGaN / GaN layers) allows the spontaneous generation of a so-called two-dimensional electron gas (2DEG) in the device, forming a channel path for the charges. The spontaneous channel can be modulated by applying a suitable voltage at the gate region above the channel path.

[0004] AlGaN / GaN HEMTs are usually depletion mode. However, for practical applications, enhancement mode (normally off) devices are preferred for safe operation and simplified drive circuits.

[0005] Several approaches have been proposed to realize normally-off HEMTs based on AlGaN / GaN layers, including forming a recessed gate transistor, performing manufacturing steps such as incorporating a fluorine plasma under the gate, or forming the gate region of pGaN. The last solution is used, for example, in products available on the market and is considered below.

[0006] For example, Figure 1 A HEMT device 1 is shown formed on a semiconductor body 2 , here comprising a substrate layer 3 , a first layer 4 and a second layer 6 (hereinafter also referred to as a channel layer 4 and a barrier layer 6 ).

[0007] The substrate layer 3 may include Figure 1 The silicon substrate and gallium nitride (GaN) buffer layer are not shown separately.

[0008] The channel layer 4 is a first semiconductor material, such as, for example, a first semiconductor alloy of elements of Group III-V of the periodic table; for example, the channel layer 4 may be gallium nitride (GaN).

[0009] The barrier layer 6 covers and directly contacts the channel layer 4 and is a second semiconductor material, such as a second semiconductor alloy of elements of the III-V group of the periodic table different from the first semiconductor alloy. For example, the barrier layer 6 may be aluminum gallium nitride (AlGaN).

[0010] The channel layer 4 and the barrier layer 6 are, for example, of N-type.

[0011] A gate region 7 of conductive material extends on the barrier layer 6. The gate region 7 is formed, for example, of a third semiconductor material, such as, for example, a third semiconductor alloy of elements of the III-V group of the periodic table; in more detail, here the gate region 7 is formed of P conductivity type gallium nitride (pGaN).

[0012] The passivation layer 8 covers the top surface of the barrier layer 6 and lateral surfaces ("sidewalls") laterally to the gate region 7 and partially covers the top surface of the gate region 7. The passivation layer 8 is formed of a layer of non-conductive material, for example an oxide such as Al2O3.

[0013] A first insulating layer 9 , for example silicon oxide, extends over the passivation layer 8 .

[0014] An opening 11 extends through the first insulating layer 9 and the passivation layer 8 on top of the gate region 7 , and a gate metal region 10 of, for example, TiN / AlCu / TiN extends in the opening 11 in direct electrical contact with the gate region 7 and partially on the first insulating layer 9 .

[0015] A second insulating layer 12 , for example silicon oxide, extends over the first insulating layer 9 and the gate metal region 10 .

[0016] exist Figure 1 In the embodiment, a field plate 13 of conductive material extends on the first insulating layer 9, laterally to the gate metal region 10 and below the second insulating layer 12. The field plate 13 is optional and may be formed from the same metal layer as the gate metal region 10.

[0017] The source metal region 15, such as Ti / AlCu / TiN, extends on the barrier layer 6 and is in direct electrical contact with the barrier layer 6; the source metal region 15 also extends laterally to the second insulating layer 12 and extends on the second insulating layer 12. In the HEMT device 1, the source metal region 15 has a portion extending above the gate metal region 10 and above the field plate region 13, and has a shielding function.

[0018] A drain metal region 16 of, for example, Ti / AlCu / TiN, extends over the barrier layer 6 and is in direct electrical contact with the barrier layer 6; in addition, the drain metal region 16 extends laterally to the second insulating layer 12 and partially extends over the second insulating layer 12 (on the opposite side of the gate region 7 relative to the source metal region 15).

[0019] In this type of HEMT transistor, etching of the layers above the semiconductor body 2 is critical and may affect the electrical properties of the device, such as the threshold voltage.

[0020] In fact, the threshold voltage of the HEMT device is affected by any gate leakage occurring in particular on the sidewalls of the gate region 7 and may shift during stress conditions: typically, a negative shift in the threshold voltage originates from the high-drain gate region 7. On the other hand, a positive shift in the threshold voltage is caused by the low-drain gate region 7. In commercial devices, a trade-off between positive and negative shifts is desirable.

[0021] Gate leakage exhibits both bulk and parasitic contributions during device operation (ie, when the control voltage applied to the gate terminal is greater than zero).

[0022] In particular, the parasitic contribution originates from the top surface of the gate region 7 (ie, on the portion where no Schottky contact exists between the gate metal region 10 and the gate region 7 ) and on the sidewalls of the gate region 7 .

[0023] The parasitic gate leakage through the top surface of the pGaN material is due to the presence of electronic surface states induced by polarized net charges, which are inherent in stacking GaN-AlGaN-pGaN layers for HEMT transistors of the type under consideration.

[0024] Alternatively, the parasitic gate leakage through the sidewalls of the gate region 7 is process dependent, and in particular, is caused by the etching conditions in terms of the chemistry of the pGaN layer and the power employed when forming the gate region 7. In detail, the damage caused by etching may result in the formation of vacancies, such as nitrogen vacancies, resulting in the trapping of a high concentration of electrons by the sidewalls of the gate region 7. This forms a current leakage path from the lower edge of the gate metal region 10 along the sidewalls of the gate region 7 to the barrier layer 6 and the channel layer 4 (i.e., to the channel region of the HEMT device 1 in the operating state of the HEMT device 1). In other words, the pGaN etching may result in depletion on the surface side of the gate region 7; therefore, when a 2DEG is formed at the interface between the channel layer 4 and the barrier layer 6 (when the HEMT device 1 is turned on), an inversion channel is formed on the sidewalls of the gate region 7.

[0025] The body gate leakage contribution is mainly affected by the following factors: damage to the gate region 7 during the formation of the gate metal region 10 by etching, for example due to partial removal or roughening of the pGaN material; and the concentration of doping ions (such as magnesium) that define the p-type doping of the GaN material forming the gate region 7.

[0026] Surface passivation of barrier layer 6 and gate region 7 by atomic layer deposition (“ALD”) of ammonium hydroxide resistant materials such as Al 2 O 3 or AlN, as done for passivation layer 8 , is a known solution to attempt to compensate for the presence of electronic surface states and defects caused by pGaN etching. Utility Model Content

[0027] The applicant has demonstrated that the deposition of such a layer is not always sufficiently effective to significantly reduce the gate leakage. Moreover, in some cases, the arrangement of such a surface passivation may introduce detrimental effects, affecting other electrical characteristics of the transistor: the dielectric parameters (e.g. thickness and material) of the passivation layer 8 affect the gate leakage and the on-resistance Ron of the device in an opposite way; therefore, an optimal value that reduces the gate leakage may result in a deterioration of the on-resistance Ron.

[0028] Therefore, an object of the present disclosure is to overcome the disadvantages and limitations of the prior art.

[0029] According to the present disclosure, a HEMT device is provided, comprising a semiconductor body having a semiconductor heterostructure; a control region comprising a semiconductor material, the control region being located on the semiconductor body, the control region having a top surface and a plurality of lateral sides; a control terminal of a conductive material, the control terminal extending on the top surface of the control region and in contact with the top surface of the control region; a passivation layer of a non-conductive material, the passivation layer extending on the semiconductor body, partially on the top surface of the control region and on the plurality of lateral sides of the control region, the passivation layer being arranged laterally and at a distance from the control terminal; and a plurality of spacer regions of a non-conductive material, the plurality of spacer regions extending between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions.

[0030] Preferably, the plurality of spacer regions are thicker than the passivation layer.

[0031] Preferably, the control terminal includes a narrow portion extending between the plurality of spacer regions and an upper portion extending over the plurality of spacer regions.

[0032] Preferably, the HEMT device further comprises an insulating structure extending on the passivation layer, wherein a control opening extends in the insulating structure and through the passivation layer and at least partially accommodates the control terminal and the plurality of spacer regions, the control opening having lateral sides, and the plurality of spacer regions extending on the plurality of lateral sides of the control opening.

[0033] Preferably, the insulating structure includes a first insulating layer extending on the passivation layer, and a second insulating layer extending on the first insulating layer, and wherein the control opening extends through the first insulating layer and the passivation layer and accommodates the multiple spacer areas and at least partially accommodates the control terminal, and the second insulating layer extends on the control terminal.

[0034] Preferably, the insulating structure includes a first insulating layer extending on the passivation layer, and a second insulating layer extending on the first insulating layer, and wherein the control opening extends through the first insulating layer, the second insulating layer and the passivation layer and accommodates the multiple spacer areas and the control terminal.

[0035] Preferably, the HEMT device further includes a field plate, and the field plate is located between the first insulating layer and the second insulating layer.

[0036] Preferably, the HEMT device further comprises a first current conducting terminal and a second current conducting terminal, wherein the first current conducting terminal and the second current conducting terminal are partially located between the first insulating layer and the second insulating layer, and the first current conducting terminal and the second current conducting terminal are in contact with the semiconductor body.

[0037] Preferably, the HEMT device further comprises a first current conducting terminal and a second current conducting terminal, wherein the first current conducting terminal and the second current conducting terminal are partially located above the first insulating layer and the second insulating layer, the first current conducting terminal and the second current conducting terminal are in contact with the semiconductor body, and the first current conducting terminal is partially located above the control terminal and the field plate.

[0038] Preferably, the insulating structure and the plurality of spacer regions are different, selectively etchable materials.

[0039] Preferably, the insulating structure is silicon oxide and the plurality of spacer regions are silicon nitride.

[0040] Preferably, the control region includes a channel modulation region and an interlayer region covering the channel modulation region.

[0041] According to the present disclosure, a device is also provided, including a semiconductor heterostructure; a control region located on the heterostructure, the control region having a first surface and multiple sides; a terminal located on the first surface of the control region and in contact with it; a passivation layer located on the heterostructure, on the first surface of the control region, and on the multiple sides of the control region, the passivation layer having a second surface transverse to the first surface; and multiple non-conductive spacer regions located between the terminal and the passivation layer, the second surface of the passivation layer being in contact with the multiple spacer regions.

[0042] Preferably, the device also includes a first insulating layer located on the passivation layer; a second insulating layer located on the first insulating layer, the first insulating layer and the second insulating layer contacting the multiple spacer regions at the second surface; and a field plate located between the first insulating layer and the second insulating layer.

[0043] The technical effect of the utility model is to reduce the gate leakage of the HEMT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to understand the present disclosure, embodiments thereof will now be described, purely as non-limiting examples, with reference to the accompanying drawings, in which:

[0045] Figure 1 is the cross section of a known HEMT device;

[0046] Figure 2 is a cross section of a HEMT device according to an embodiment;

[0047] Figures 3A-3F yes Figure 2 A cross section of a semiconductor wafer in a subsequent manufacturing step of a HEMT device;

[0048] Figure 4 is a cross-section of a HEMT device according to another embodiment;

[0049] Figures 5A-5C yes Figure 4 a cross section of a semiconductor wafer in a subsequent manufacturing step of a HEMT device; and

[0050] Figure 6 and Figure 7 is a cross section of a HEMT device according to various embodiments. DETAILED DESCRIPTION

[0051] The following description refers to the arrangements shown in the accompanying drawings; therefore, expressions such as "above", "below", "upper", "lower", "top", "bottom", "right", "left", etc. are relative to the drawings and should not be interpreted in a limiting manner.

[0052] Figure 2 A HEMT device 50 is shown, which comprises a semiconductor body 52 , here formed by a substrate layer 53 , a channel layer 54 and a barrier layer 56 .

[0053] The substrate layer 53 may include Figure 2 The silicon substrate and gallium nitride (GaN) buffer layer are not shown separately.

[0054] The channel layer 54 is a first semiconductor material, such as a first semiconductor alloy of elements of Group III and Group V of the periodic table; for example, the channel layer 54 may be gallium nitride (GaN).

[0055] The barrier layer 56 covers and directly contacts the channel layer 54 and is a second semiconductor material, such as a second semiconductor alloy of elements of Group III-V of the periodic table different from the first semiconductor alloy. For example, the barrier layer 56 may be aluminum gallium nitride (AlGaN).

[0056] The channel layer 54 and the barrier layer 56 are, for example, of N-type.

[0057] A gate region 57 of conductive material extends over and contacts the barrier layer 56. The gate region 57 is a control region, and in particular a channel modulation region.

[0058] In a manner not shown, the gate region 57 is strip-shaped and extends along a first horizontal axis Y of the Cartesian reference system XYZ. The gate region 57 is formed of a conductive material, typically a doped third semiconductor material, such as a third semiconductor alloy of elements of the III-V group of the periodic table; specifically, here the gate region 57 is formed of P-conductivity type gallium nitride (pGaN).

[0059] As known to those skilled in the art, the gate region 57 is used to modulate the thickness of a channel formed at the interface between the channel layer 54 and the barrier layer 56 based on a voltage applied thereto.

[0060] Passivation layer 58 covers the top surface of barrier layer 56, as well as lateral surfaces (also indicated as sidewalls of gate region 57), and partially covers the top surface of gate region 57. Similar to gate region 57, passivation layer 58 also extends along first horizontal axis Y the entire length of gate region 57.

[0061] The passivation layer 58 is a non-conductive material, for example an oxide, such as Al2O3, AlN, SiN, HfO2, SiO2, AlSiO, and has a thickness between 2 nm and 10 nm, for example 5 nm.

[0062] A first insulating layer 66 , such as silicon oxide, extends over the passivation layer 58 .

[0063] The gate opening 67 extends through the first insulating layer 66 and the passivation layer 58 on top of the gate region 57 .

[0064] The spacer region 62 extends in the gate opening 67 , on lateral sides of the gate opening 67 , on the top surface of the gate region 57 , and is in direct contact with the top surface of the gate region 57 .

[0065] The spacer region 62 is here strip-shaped and extends along the first horizontal axis Y. In practice, the spacer region 62 laterally delimits a spacer opening 71 which is narrower than the gate opening 67 .

[0066] The spacer region 62 is here a dielectric material, such as silicon nitride (“SiN”), for example in its stable configuration Si 3 N 4 . The dielectric material of the spacer region 62 may be an oxide, but is typically different from the material of the first insulating layer 66 .

[0067] A control terminal (hereinafter indicated as gate metal region 68 , eg, a multilayer of TiN / AlCu / TiN) is in direct electrical contact with a central portion of gate region 57 , extending in spacer opening 71 , over spacer region 62 and partially over first insulating region 66 .

[0068] In practice, gate metal region 68 includes a narrow portion 68A extending between spacer regions 62 and an upper portion 68B extending over spacer regions 62 .

[0069] In other words, Figure 2 In the embodiment of FIG. 5 , spacer region 62 extends below gate metal region 68 and is adjacent to two opposing sides of narrow portion 68A.

[0070] Other materials such as Ti, Ta, TiW, TaW may be used in place of TiN for the alloy of gate metal region 68 .

[0071] Narrow portion 68A of gate metal region 68 and gate region 57 form a Schottky contact.

[0072] A second insulating layer 69 , such as silicon oxide, extends over the first insulating layer 66 and the gate metal 68 .

[0073] The first insulating layer 66 and the second insulating layer 69 form an insulating structure 66, 69. The insulating structure 66, 69 has first and second current conducting openings extending on different sides of the gate region 57, respectively indicated below as source opening 82 and drain opening 83. The source opening 82 and the drain opening 83 extend through the entire thickness of the insulating structure 66, 69 and expose the barrier layer 56.

[0074] exist Figure 2 In FIG. 6 , the field plate 70 extends on the first insulating layer 66 , on one side below the second insulating layer 69 but at a distance from the gate metal region 68 . The field plate 70 is optional and may be formed of the same metal layer as the gate metal region 68 .

[0075] A first current conducting terminal, hereinafter indicated as source metal region 72 of, for example, Ti / AlCu / TiN, extends in source opening 82 and here is in direct electrical contact with barrier layer 56. In HEMT device 50, source metal region 72 has a portion that also extends on second insulating layer 69, over gate metal 68 and over field plate 70, and has a shielding function.

[0076] The source metal region 72 may be electrically connected to the field plate 70 .

[0077] A second current conducting terminal, hereinafter indicated as drain metal region 73 of, for example, Ti / AlCu / TiN, extends in drain opening 83 and here is in direct electrical contact with barrier layer 56. Drain metal region 73 is located on the opposite side of gate region 57 relative to source metal region 72.

[0078] Figure 2 The HEMT device 50 has improved performance in reducing lateral gate leakage originating from the pGaN sidewall of the gate region 57 .

[0079] In more detail, using Figure 2 In the structure of FIG. 5 , the spacer region 62 is interposed between the gate metal region 68 and the passivation layer 58, thereby separating them and blocking any current leakage path from the lower edge of the gate metal region 68 along the top surface and sidewalls of the gate region 57 to the channel region of the HEMT device 50 formed during operation.

[0080] Therefore, during device operation, the gate current is forced to flow only in a localized (here central) portion of the upper surface of gate region 57 , ie, only at the Schottky contact between gate metal region 68 and gate region 57 .

[0081] The HEMT device 50 thus allows a good compromise to be obtained between gate current, threshold voltage and on-resistance.

[0082] The HEMT device 50 may be Figures 3A-3F As shown in the manufacture, Figures 3A-3F The wafer is shown before dicing and using Figure 2 The same reference numerals are used for areas with the same name.

[0083] Figure 3A A wafer 80 is shown comprising a layer stack including a substrate layer 53, a channel layer 54 and a barrier layer 56. A gate region 57 has been formed on the barrier layer 56, for example by epitaxial growth of p-doped GaN material using MOCVD (Metal Organic Chemical Vapor Deposition) and by lithographic definition thereof, using standard etching processes.

[0084] exist Figure 3BIn the embodiment, a passivation layer 58 is formed on the exposed gate region 57 and the barrier layer 56, and then a first insulating layer 66 is formed.

[0085] For example, the passivation layer 58 is thermally deposited or plasma deposited using an ALD (atomic layer deposition) technique in a H 2 O-based environment at 300° C. to a thickness of, for example, 5 nm.

[0086] The first insulating layer 66 may be deposited, for example, by PECVD (Plasma Enhanced Chemical Vapor Deposition) in a SiH 4 based environment to a thickness of, for example, 260 nm.

[0087] exist Figure 3C In the embodiment, the first insulating layer 66 and the passivation layer 58 are etched using a mask (not shown) to form a gate opening 67, thereby exposing the top surface of the gate region 57. The etching to form the gate opening 67 can be, for example, a time etching in CF4 or using endpoint detection for removing the first insulating layer 66, and a BCl3 etching for removing the passivation layer 58.

[0088] Depending on the width of the gate region 57 , the gate opening 67 may have a width along the second horizontal axis X of the Cartesian reference system XYZ of, for example, between 0.9 μm and 5.5 μm.

[0089] exist Figure 3D In the embodiment, a sacrificial layer 81 of a dielectric material is formed on the first insulating layer 66 and in the gate opening 67 , on a portion of the gate region 57 exposed by the gate opening 67 .

[0090] For example, the sacrificial layer 81 is deposited by PECVD to a thickness of, for example, 300 nm.

[0091] exist Figure 3E In the embodiment of the present invention, the sacrificial layer 81 is anisotropically (dry) etched (e.g., in a CF4 environment) without a mask ("blanket") to remove it until it reaches the central portion of the top surface of the gate region 57, thereby defining the spacer opening 71 within the gate opening 67 and forming the spacer region 62. The sacrificial layer 81 is also removed from the top of the first insulating layer 66 (outside the gate opening 67).

[0092] Thus, the spacer region 62 may have a width of approximately 300 nm near the bottom of the gate region 57 , and the spacer opening 71 may have a width of between 0.3 μm and 5 μm near the bottom of the gate region 57 .

[0093] In this embodiment, the spacer region 62 has the same thickness as the portion of the first insulating layer 66 over the gate region 57 , but this is not critical.

[0094] exist Figure 3FIn the embodiment of the present invention, a gate metal layer is deposited and defined to form a gate metal region 68 (extending in the spacer opening 71 and partially extending over the first insulating region 66) and a field plate 70 (extending laterally thereto).

[0095] Then, in a manner not shown, a second insulating layer 69 is deposited and then defined together with the first insulating layer 66 and the passivation layer 58 (using a mask not shown) to form a source opening 82 and a drain opening 83. Thereafter, a source / drain metal layer is deposited and defined to form a source metal region 72 and a drain metal region 73.

[0096] The final manufacturing steps are then performed, including depositing an outer passivation layer (not shown), forming opening contacts (not shown), and dicing the wafer 80 to obtain Figure 2 HEMT device 50.

[0097] Actually, in the above process, the spacer region 62 for blocking lateral leakage from the gate region 57 is formed after the gate opening 67 is formed, thereby isolating the gate metal region 68 from the passivation layer 58 .

[0098] Figure 4 A HEMT device 100 is shown in which the source and drain metal regions are formed before the gate metal region.

[0099] In detail, Figure 4 Among them, Figure 2 Regions common to the HEMT device 50 have been indicated using the same reference numerals, with the source opening indicated here by 82' and the drain opening indicated here by 83' extending only through the first insulating layer 66. In addition, the gate opening indicated here by 67' extends through both the first insulating layer 66 and the second insulating layer 69.

[0100] Similarly, in this embodiment, the spacer opening, indicated here by 71 ′, and the spacer region, indicated here by 62 ′, extend through the entire insulating structure 66 , 69 .

[0101] By Figure 4 By forming one or more through holes through the first insulating layer 66 and the second insulating layer 69 at locations not shown in the figure, the shielding area 86 can be electrically coupled to other areas in the substrate 52.

[0102] The HEMT device 100 may be Figures 5A-5C Manufactured as shown in .

[0103] In detail, Figure 5A In forming the first insulating layer 66 ( Figure 3B) After that, the first insulating layer 66 is defined to form a source opening 82' and a drain opening 83'. Then, a source metal region 72', a drain metal region 73' and a field plate 70 are formed by depositing and defining the same metal layer or a stack of layers such as Ti / AlCu / TiN.

[0104] exist Figure 5B In the process, the second insulating layer 69 is deposited and etched (together with the first insulating layer 66 and the passivation layer 58) to form a gate opening 67'.

[0105] Then, in Figure 5C In, similar to Figure 3D , a sacrificial layer 81 is deposited on the second insulating layer 69 and in the gate opening 67 ′.

[0106] After blanket etching of the sacrificial layer 81 and final fabrication steps, Figure 2 Embodiment, obtain Figure 4 A HEMT device 100 is provided.

[0107] In particular, if Figure 4 As shown in , when a gate metal region, indicated here by 68 ′, is formed in spacer opening 71 ′ (eg, by depositing and defining a metal layer or stack, such as Ti / AlCu / TiN), shielding region 86 may be formed from the same metal layer as gate metal 68 ′.

[0108] Figure 6 Various embodiments are involved, wherein Figure 2 The common areas of the HEMT device 50 have been indicated using the same reference numerals. Figure 6 In FIG. 1 , the HEMT device 200 has a gate region 57 ′ including a channel modulation region 90 (of pGaN material) and an interlayer region 59 .

[0109] The channel modulation region 90 has Figure 2 The gate region 57 has the same structure and electrical characteristics.

[0110] The interlayer region 59 of conductive material (eg, metal such as TiN) extends on top of the channel modulation region 90 along the second horizontal axis X of the Cartesian reference system XYZ and may be narrower than the channel modulation region 90 .

[0111] Furthermore, interlayer region 59 is in direct electrical contact with gate metal region 68 at spacer opening 71 and extends under spacer region 62 .

[0112] Similar to the passivation layer 58 , the passivation layer 58 ′ covers the portion of the top surface of the interlayer region 59 below the first insulating layer 66 , the lateral surfaces of the interlayer region 59 , the edge of the top surface of the channel modulation region 90 , the sidewalls of the channel modulation region 90 , and the top surface of the barrier layer 56 .

[0113] Therefore, also in Figure 6 In the HEMT device 200 of FIG. 1 , the passivation layer 58 ′ extends at a distance from the gate region 57 ′.

[0114] The interlayer region 59 is used to facilitate the turn-on of the channel modulation region 90 and to form a barrier to the diffusion of contaminants from the upper layers.

[0115] Figure 7 In another embodiment, the HEMT device 300 includes an interlayer region 59 (as shown in FIG. Figure 6 described) and wherein the source and drain metal regions are formed before the gate metal region (as described in reference Figure 4 described). Figure 7 In, with Figure 4 The common regions of the HEMT device 100 and Figure 6 Regions common to the HEMT device 200 have been indicated using the same reference numerals.

[0116] The interlayer region 59 has Figure 6 Similar positions and features to the corresponding regions shown in .

[0117] Finally, it is evident that numerous variations and modifications may be made to the HEMT devices and processes described and illustrated herein, all of which fall within the scope of the present disclosure as defined.

[0118] In summary, example embodiments of the present disclosure are as follows.

[0119] Example 1. A HEMT device (50; 100; 200; 300), comprising:

[0120] A semiconductor body (52) having a semiconductor heterostructure (54, 56);

[0121] a control region (57; 57') comprising a semiconductor material arranged on the semiconductor body (52), the control region (57; 57') having a top surface and lateral sides;

[0122] a control terminal (68; 68') of conductive material extending over and in contact with the top surface of the control region (57; 57'); and

[0123] a passivation layer (58; 58') of non-conductive material extending over the semiconductor body (52), partially over the top surface of the control region (57; 57') and on the lateral sides of the control region (57; 57');

[0124] The passivation layer (58; 58') is arranged laterally and at a certain distance from the control terminal (68; 68').

[0125] Example 2. The HEMT device according to Example 1, further comprising a spacer region (62; 62') of non-conductive material extending between the control terminal (68; 68') and the passivation layer (58; 58').

[0126] Example 3. The HEMT device according to the preceding example, wherein the control terminal (68; 68') comprises a narrow portion (68A) extending between the spacer regions (62; 62') and an upper portion (68B) extending over the spacer regions.

[0127] Example 4. The HEMT device according to example 2 or 3 further includes an insulating structure (66, 69) extending on the passivation layer (58; 58'), wherein a control opening (67; 67') extends in the insulating structure (66, 69) and through the passivation layer (58; 58') and at least partially accommodates the control terminal (68; 68') and the spacer region (62; 62'), the control opening having lateral sides, and the spacer region (62; 62') extending on the lateral sides of the control opening (67; 67').

[0128] Example 4bis. The HEMT device of any of the preceding examples, further comprising a first current conducting opening (82; 82') of the first current conducting terminal (72; 72') at least partially accommodating the conductive material; and

[0129] A second current conducting opening (83; 83') of a second current conducting terminal (73; 73') at least partially receives the conductive material.

[0130] Example 5. A HEMT device according to the preceding example, wherein the insulating structure (66, 69) comprises a first insulating layer (66) extending over the passivation layer (58; 58') and a second insulating layer (69) extending over the first insulating layer, and wherein the control opening (67) extends through the first insulating layer (66) and the passivation layer (58; 58') and accommodates the spacer region (62) and at least partially accommodates the control terminal (68), and the second insulating layer (69) extends over the control terminal (68).

[0131] Example 6. The HEMT device according to Example 4, wherein the insulating structure (66, 69) includes a first insulating layer (66) extending on the passivation layer (58; 58') and a second insulating layer (69) extending on the first insulating layer (66), and wherein the control opening (67') extends through the first and second insulating layers (66, 69) and the passivation layer (58; 58') and accommodates the spacer region (62') and the control terminal (68).

[0132] Example 7. The HEMT device of any of Examples 4-6, wherein the insulating structure (66, 69) and the spacer region (62; 62') are different, selectively etchable materials.

[0133] Example 8. The HEMT device according to the preceding example, wherein the insulating structure (66, 69) is silicon oxide and the spacer region (62; 62') is silicon nitride.

[0134] Example 9. The HEMT device according to any of the preceding examples, wherein the control region (57') includes a channel modulation region (90) and an interlayer region (59) covering the channel modulation region.

[0135] Example 10. A process for manufacturing a HEMT device (50; 100; 200; 300), the process comprising:

[0136] forming a control region (57; 57') on a semiconductor body (52) having a semiconductor heterostructure (54, 56), the control region (57; 57') comprising a semiconductor material and arranged on the semiconductor body (52), the control region (57; 57') having a top surface and lateral sides;

[0137] forming a passivation layer (58; 58') of non-conductive material on the semiconductor body (52), partially on the top surface of the control region (57; 57') and on the lateral sides of the control region (57; 57'); and

[0138] On the top surface of the control region (57; 57') and in contact therewith, laterally and at a distance from the passivation layer (58; 58'), a control terminal (68; 68') of conductive material is formed.

[0139] Example 11. The process according to the preceding example further comprises forming a spacer region (62; 62') of non-conductive material extending between the control terminal (68; 68') and the passivation layer (58; 58') before forming the control terminal (68; 68').

[0140] Example 12. A process according to the preceding example, wherein:

[0141] Forming a passivation layer (58; 58') and forming a spacer region (62) includes:

[0142] forming a portion of a passivation layer (58; 58') covering a top surface of the gate region (57; 57');

[0143] forming an insulating layer (66; 69) on the passivation layer (58; 58');

[0144] Forming a control opening (67; 67') in the insulating layer (66; 69) comprises selecting

[0145] removing the portion of the passivation layer (58; 58'); and

[0146] A spacer region (62; 67') is formed on the lateral sides of the control opening (67; 67').

[0147] 62'); and

[0148] Forming the control terminal (68; 68') includes forming a portion of the control terminal in the control opening (67; 67'), between and on the spacer regions (62; 62').

[0149] Example 13. According to the process of the above example,

[0150] The forming of the spacer region (62; 62') includes:

[0151] forming a sacrificial layer (81) on the insulating layer (66; 69) and in the control opening (67; 67'); and

[0152] The sacrificial layer (81) is removed from the insulating layer (66; 69) and the control opening (67; 67'), except for the lateral sides of the control opening.

[0153] Example 14. The process according to the previous example, wherein the insulating layer is a first insulating layer (66), the process further comprising:

[0154] After forming the control terminal (68), forming a second insulating layer (69);

[0155] forming first and second current conducting openings (82, 83) through first and second insulating layers (66, 69) and a passivation layer (58; 58') on first and second sides of the control region (57; 57'), respectively; and

[0156] A first current conducting terminal (72) extending at least partially in the first current conducting opening (82) and a second current conducting terminal (73) extending at least partially in the second current conducting opening (83) are formed, the first and second current conducting terminals (72, 73) being in contact with the semiconductor body (52).

[0157] Example 15. The process according to Example 13, further comprising a first insulating layer (66), wherein the insulating layer is a second insulating layer (69), the control opening (67') extending through both the first and second insulating layers (66, 69), the process further comprising:

[0158] After forming the first insulating layer (66), forming first and second current conducting openings (82', 83') through the first insulating layer (66) and the passivation layer (58; 58') on first and second sides of the control region (57; 57'), respectively; and

[0159] A first current conducting terminal (72') extending at least partially in the first current conducting opening (82') and a second current conducting terminal (73') extending at least partially in the second current conducting opening (83) are formed, the first and second current conducting terminals being in contact with the semiconductor body (52).

[0160] A HEMT device (50; 100; 200; 300) can be summarized as comprising: a semiconductor body (52) having a semiconductor heterostructure (54, 56); a control region (57; 57') arranged on the semiconductor body (52) and comprising a semiconductor material, the control region (57; 57') having a top surface and lateral sides; a control terminal (68; 68') of conductive material extending on and in contact with the top surface of the control region (57; 57'); and a passivation layer (58; 58') of non-conductive material extending on the semiconductor body (52), partially on the top surface of the control region (57; 57') and on the lateral sides of the control region (57; 57'), the passivation layer (58; 58') being arranged laterally and at a distance from the control terminal (68; 68').

[0161] The HEMT device may also include a spacer region (62; 62') of non-conductive material extending between the control terminal (68; 68') and the passivation layer (58; 58').

[0162] Wherein the control terminal (68; 68') may include a narrow portion (68A) extending between the spacer regions (62; 62') and an upper portion (68B) extending over the spacer regions.

[0163] The HEMT device may further include an insulating structure (66, 69) extending on the passivation layer (58; 58'), wherein a control opening (67; 67') extends in the insulating structure (66, 69) and through the passivation layer (58; 58') and at least partially accommodates a control terminal (68; 68') and a spacer region (62; 62'), the control opening having lateral sides, and the spacer region (62; 62') extending on the lateral sides of the control opening (67; 67').

[0164] The insulating structure (66, 69) may include a first insulating layer (66) extending over the passivation layer (58; 58'), and a second insulating layer (69) extending over the first insulating layer (66), and the control opening (67) may extend through the first insulating layer (66) and the passivation layer (58; 58') and accommodate the spacer region (62) and at least partially accommodate the control terminal (68), and the second insulating layer (69) extends over the control terminal (68).

[0165] wherein the insulating structure (66, 69) may include a first insulating layer (66) extending over the passivation layer (58; 58') and a second insulating layer (69) extending over the first insulating layer (66), and wherein the control opening (67') may extend through the first and second insulating layers (66, 69) and the passivation layer (58; 58') and accommodate a spacer region (62') and a control terminal (68).

[0166] The insulating structures (66, 69) and the spacer regions (62, 62') may be different, selectively etchable materials.

[0167] The insulating structures (66, 69) may be silicon oxide, and the spacer regions (62, 62') may be silicon nitride.

[0168] The control region (57') may include a channel modulation region (90) and an interlayer region (59) covering the channel modulation region.

[0169] A process for manufacturing a HEMT device (50; 100; 200; 300), the process can be summarized as comprising: forming a control region (57; 57) on a semiconductor body (52) having a semiconductor heterostructure (54, 56), the control region (57; 57') comprising a semiconductor material and arranged on the semiconductor body (52), the control region (57; 57') having a top surface and lateral sides; forming a passivation layer (58; 58') of non-conductive material on the semiconductor body (52), partially on the top surface of the control region (57; 57') and on the lateral sides of the control region (57; 57'); and forming a control terminal (68; 68') of conductive material on and in contact with the top surface of the control region (57; 57'), laterally and at a distance from the passivation layer (58; 58').

[0170] The process may also include, prior to forming the control terminal (68; 68'), forming a spacer region (62; 62') of non-conductive material extending between the control terminal (68; 68') and the passivation layer (58; 58').

[0171] Forming a passivation layer (58; 58') and forming an isolation region (62) may include: forming a portion of the passivation layer (58; 58') covering the top surface of the gate region (57; 57'); forming an insulating layer (66; 69) on the passivation layer (58; 58'); forming a control opening (67; 67') in the insulating layer (66; 69), including selectively removing the portion of the passivation layer (58; 58'); and forming a spacer region (62; 62') on a lateral side of the control opening (67; 67'); and forming a control terminal (68; 68') may include forming a portion of the control terminal in the control opening (67; 67'), between the spacer regions (62; 62') and on the spacer regions (62; 62').

[0172] Wherein forming the spacer region (62; 62') may include: forming a sacrificial layer (81) on the insulating layer (66; 69) and in the control opening (67; 67'); and removing the sacrificial layer (81) from the insulating layer (66; 69) and the control opening (67; 67'), except for lateral sides of the control opening.

[0173] Wherein the insulating layer is a first insulating layer (66), the process may further include: forming a second insulating layer (69) after forming the control terminal (68); forming first and second current conduction openings (82, 83) through the first and second insulating layers (66, 69) and the passivation layer (58; 58') on the first side and the second side of the control region (57; 57'), respectively; and forming a first current conduction terminal (72) extending at least partially in the first current conduction opening (82) and a second current conduction terminal (73) extending at least partially in the second current conduction opening (83), the first and second current conduction terminals (72, 73) contacting the semiconductor body (52).

[0174] The process may further include a first insulating layer (66), wherein the insulating layer is a second insulating layer (69), and the control opening (67') extends through the first and second insulating layers (66, 69), and the process further includes: after forming the first insulating layer (66), forming first and second current conduction openings (82', 83') through the first insulating layer (66) and the passivation layer (58; 58') on the first side and the second side of the control region (57; 57'), respectively; and forming a first current conduction terminal (72') extending at least partially in the first current conduction opening (82') and a second current conduction terminal (73') extending at least partially in the second current conduction opening (83'), the first and second current conduction terminals contacting the semiconductor body (52).

[0175] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0176] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms granted by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. A HEMT device, characterized in that: The HEMT device comprises: A semiconductor body having a semiconductor heterostructure; a control region comprising a semiconductor material, the control region being located on the semiconductor body, the control region having a top surface and a plurality of lateral sides; a control terminal of conductive material, the control terminal extending over and contacting the top surface of the control region; a passivation layer of a non-conductive material, the passivation layer extending on the semiconductor body, partly on the top surface of the control region and on the lateral sides of the control region, the passivation layer being arranged laterally and at a distance from the control terminal; and A plurality of spacer regions of non-conductive material extend between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions.

2. The HEMT device according to claim 1, characterized in that: The plurality of spacer regions have a thickness greater than that of the passivation layer.

3. The HEMT device according to claim 2, characterized in that: The control terminal includes a narrow portion extending between the plurality of spacer regions and an upper portion extending over the plurality of spacer regions.

4. The HEMT device according to claim 2, characterized in that: The HEMT device further includes an insulating structure extending on the passivation layer, wherein a control opening extends in the insulating structure and through the passivation layer and at least partially accommodates the control terminal and the plurality of spacer regions, the control opening having lateral sides, the plurality of spacer regions extending on the plurality of lateral sides of the control opening.

5. The HEMT device according to claim 4, characterized in that: The insulating structure comprises: a first insulating layer extending over the passivation layer, and a second insulating layer extending over the first insulating layer, and The control opening extends through the first insulating layer and the passivation layer and accommodates the plurality of spacer regions and at least partially accommodates the control terminal, and the second insulating layer extends over the control terminal.

6. The HEMT device according to claim 4, characterized in that: The insulating structure comprises: a first insulating layer extending over the passivation layer, and a second insulating layer extending over the first insulating layer, and The control opening extends through the first insulating layer, the second insulating layer, and the passivation layer and accommodates the plurality of spacer regions and the control terminal.

7. The HEMT device according to claim 6, characterized in that: The HEMT device further includes a field plate located between the first insulating layer and the second insulating layer.

8. The HEMT device according to claim 7, characterized in that: The HEMT device further includes a first current conducting terminal and a second current conducting terminal, the first current conducting terminal and the second current conducting terminal being partially located between the first insulating layer and the second insulating layer, the first current conducting terminal and the second current conducting terminal being in contact with the semiconductor body.

9. The HEMT device according to claim 7, characterized in that: The HEMT device further includes a first current conducting terminal and a second current conducting terminal, the first current conducting terminal and the second current conducting terminal being partially located above the first insulating layer and the second insulating layer, the first current conducting terminal and the second current conducting terminal being in contact with the semiconductor body, and the first current conducting terminal being partially located above the control terminal and the field plate.

10. The HEMT device according to claim 6, characterized in that: The insulating structure and the plurality of spacer regions are different, selectively etchable materials.

11. The HEMT device according to claim 10, characterized in that: The insulating structure is silicon oxide, and the plurality of spacer regions are silicon nitride.

12. The HEMT device according to claim 11, characterized in that: The control region includes a channel modulation region and an interlayer region covering the channel modulation region.

13. A semiconductor device, characterized in that: include: Semiconductor heterostructures; a control region located on the heterostructure, the control region having a first surface and a plurality of side surfaces; a terminal located on and in contact with the first surface of the control region; a passivation layer located on the heterostructure, on the first surface of the control region, and on the multiple side surfaces of the control region, the passivation layer having a second surface transverse to the first surface; as well as A plurality of non-conductive spacer regions are located between the terminal and the passivation layer, and the second surface of the passivation layer is in contact with the plurality of spacer regions.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: a first insulating layer located on the passivation layer; a second insulating layer on the first insulating layer, the first insulating layer and the second insulating layer contacting the plurality of spacer regions at the second surface; and A field plate is located between the first insulating layer and the second insulating layer.

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