Aircraft test flight testing device

Abstract

An aircraft test flight testing device comprises a conditioning circuit, a relay switching circuit, an acquisition circuit and an FPGA. The conditioning circuit converts the current sensor signal and the IEPE sensor signal into voltage signals and outputs the voltage signals; the relay switching circuit is connected with the FPGA, an input end of the relay switching circuit is respectively connected with a voltage sensor signal, an RS484 sensor signal, an RS232 sensor signal and two paths of voltage signals output by the conditioning circuit, and one path of signals entering from the input end is selected according to a control signal of the FPGA and is transmitted to a backward stage; the acquisition circuit converts a voltage sensor signal or a voltage signal into a digital quantity and then outputs the digital quantity to the FPGA, or converts an RS484 sensor signal / RS232 sensor signal into an LVTTL digital signal and then outputs the LVTTL digital signal to the FPGA; wherein the sensors corresponding to the plurality of sensor signals are respectively arranged at different positions of the aircraft body. The device can be compatible with various sensor signals and perform switching acquisition, is convenient to carry, install and perform configuration configuration, and is suitable for flight tests from large aircrafts to small aircrafts.

Description

Technical Field

[0001] The present application relates to aircraft testing technology, and in particular to an aircraft flight test device. Background Art

[0002] At present, the types of aircraft are changing with each passing day, and various types of aircraft emerge in an endless stream. Each aircraft needs to undergo a large number of flight tests before it is officially put into use. Through flight tests, the software and hardware of the aircraft can be fully verified and evaluated, and the problems found can be adjusted in time to ensure that the aircraft can work stably for a long time after it is officially put into use. Flight test equipment is generally deployed on the aircraft during the flight test phase to assist the aircraft in evaluating multiple parameters. The flight test equipment is generally removed from the aircraft that has been finalized or officially put into use. Traditional flight test equipment is integrated using a standard computer platform and bus module. The equipment implemented in this way is large in size and weight, which is not conducive to the testing of the aircraft itself and may affect the performance of the aircraft itself. Utility Model Content

[0003] In order to address the deficiencies of the above-mentioned prior art, the present application provides an aircraft flight test device that is compatible with a variety of sensor signals and can switch and collect them. It is easy to carry and install, and is easy to configure. It is suitable for flight tests of large aircraft to small aircraft.

[0004] In order to achieve the above purpose, the utility model adopts the following technologies:

[0005] An aircraft flight test device includes a conditioning circuit, a relay switching circuit, an acquisition circuit, an FPGA and a power conversion module;

[0006] The power conversion module is connected to an external power supply, and is used to convert the voltage provided by the external power supply to power the test device; the input end of the conditioning circuit is connected to the current sensor signal and the IEPE sensor signal among the multiple sensor signals, and is used to convert the current sensor signal and the IEPE sensor signal into voltage signals and output them respectively; the relay switching circuit is connected to the FPGA, and its input end is respectively connected to the voltage sensor signal, the RS484 sensor signal, the RS232 sensor signal and the two voltage signals output by the conditioning circuit among the multiple sensor signals, and is used to select one signal from the input end to be transmitted to the subsequent stage according to the control signal of the FPGA; the input end of the acquisition circuit is connected to the output end of the relay switching circuit, and is used to perform AD acquisition on the voltage sensor signal or the voltage signal to convert the analog quantity into a digital quantity and output it, or perform UART acquisition on the RS484 sensor signal or the RS232 sensor signal to convert it into an LVTTL digital signal and output it; the FPGA is connected to the acquisition circuit, and is used to obtain the digital quantity or digital signal output by the acquisition circuit and process it; wherein the sensors corresponding to the multiple sensor signals are respectively installed at different positions of the aircraft body.

[0007] Furthermore, the conditioning circuit includes a current signal conditioning unit and an IEPE signal conditioning unit. The current signal conditioning unit is used to convert the current sensor signal into a voltage signal and then output it. The IEPE signal conditioning unit is used to convert the IEPE sensor signal into a voltage signal and then output it.

[0008] Furthermore, the relay switching circuit includes multiple switching units, and the voltage sensor signal, RS484 sensor signal, RS232 sensor signal, voltage signal output by the current signal conditioning unit, and voltage signal output by the IEPE signal conditioning unit are respectively connected to a switching unit and then connected to the acquisition circuit.

[0009] Further, the acquisition circuit includes an AD acquisition unit and a UART acquisition unit, the UART acquisition unit includes an RS484 conversion circuit and an RS232 conversion circuit, the input end of the RS484 conversion circuit is connected to the output end of the switching unit corresponding to the RS484 sensor signal, the input end of the RS232 conversion circuit is connected to the output end of the switching unit corresponding to the RS232 sensor signal, the input end of the AD acquisition unit is connected to the switching unit corresponding to the voltage sensor signal, the switching unit corresponding to the current signal conditioning unit, and the switching unit corresponding to the IEPE signal conditioning unit, and the output ends of the AD acquisition unit, the RS484 conversion circuit, and the RS232 conversion circuit are connected to the FPGA;

[0010] The AD acquisition unit is used to convert the voltage sensor signal, or the voltage signal output by the current signal conditioning unit, or the voltage signal output by the IEPE signal conditioning unit into a digital quantity and then output it to the FPGA; the RS484 conversion circuit is used to perform UART acquisition on the RS484 sensor signal to convert it into an LVTTL digital signal and then output it to the FPGA; the RS232 conversion circuit is used to perform UART acquisition on the RS232 sensor signal to convert it into an LVTTL digital signal and then output it to the FPGA.

[0011] Furthermore, the FPGA is also connected to the EMMC storage circuit.

[0012] The beneficial effects of the utility model are:

[0013] The test device of the utility model is compatible with acquiring signals from multiple sensors and can perform switch acquisition. It is constructed through FPGA and related conditioning circuits and acquisition circuits, is easy to implement, and is easy to carry, easy to install, and easy to configure. It is suitable for flight tests of large aircraft to small aircraft. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a block diagram of the overall structure of the testing device of an embodiment of the present application.

[0015] Figure 2 It is a basic circuit structure block diagram of the test device of an embodiment of the present application.

[0016] Figure 3 It is a circuit schematic diagram of a current signal conditioning unit according to an embodiment of the present application.

[0017] Figure 4 It is a circuit schematic diagram of an IEPE signal conditioning unit according to an embodiment of the present application.

[0018] Figure 5 It is a schematic diagram of the switching unit circuit of an embodiment of the present application.

[0019] Figure 6 This is an application scenario of the test device in the embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the utility model clearer, the implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings, but the embodiments described in the utility model are only part of the embodiments of the utility model, rather than all the embodiments.

[0021] The present application embodiment provides an aircraft flight test device, such as Figure 1As shown, it includes a relay switching circuit, a conditioning circuit, an acquisition circuit, an FPGA, a power conversion module, etc., which are used to obtain multi-channel sensor signals. These sensor signals come from sensors installed at different positions on the aircraft body, such as Figure 6 The application scenario of the test device of this embodiment is set between the sensor and the flight control computer. The multi-channel sensor signal includes one or more of a voltage sensor signal, a current sensor signal, an IEPE sensor signal, an RS484 sensor signal, and an RS232 sensor signal.

[0022] The power conversion module is connected to an external power source and is used to convert the voltage provided by the external power source to power the test device. Figure 1 As shown, the external +24V power supply is input to the power conversion module, and the power input is converted into the power required by the test device and the sensor through the DC-DC module and the LDO module.

[0023] The input end of the conditioning circuit is connected to the current sensor signal and the IEPE sensor signal among the multiple sensor signals, and is used for converting the current sensor signal and the IEPE sensor signal into voltage signals respectively and then outputting them; the relay switching circuit is connected to the FPGA, and its input end is respectively connected to the voltage sensor signal, the RS484 sensor signal, the RS232 sensor signal among the multiple sensor signals and the two voltage signals output by the conditioning circuit, and is used for selecting one of the signals entering the input end according to the control signal of the FPGA and transmitting it to the subsequent stage.

[0024] The input end of the acquisition circuit is connected to the output end of the relay switching circuit, and is used to perform AD acquisition on the voltage sensor signal or voltage signal to convert the analog quantity into a digital quantity and then output it, or perform UART acquisition on the RS484 sensor signal or RS232 sensor signal to convert it into an LVTTL digital signal and then output it; the FPGA is connected to the acquisition circuit, and is used to obtain the digital quantity or digital signal output by the acquisition circuit and process it.

[0025] FPGA can connect to DB9 serial port through MAX232, and connect to RJ45 network port through Ethernet PHY to communicate with the outside, such as flight control computer. FPGA is connected to reset chip circuit, and key reset can be realized through key connected to reset chip circuit. FPGA is also connected to EMMC storage circuit.

[0026] like Figure 2 As shown, the conditioning circuit includes a current signal conditioning unit and an IEPE signal conditioning unit. The current signal conditioning unit is used to convert the current sensor signal into a voltage signal and then output it. The IEPE signal conditioning unit is used to convert the IEPE sensor signal into a voltage signal and then output it.

[0027] The relay switching circuit includes multiple switching units. The voltage sensor signal, RS484 sensor signal, RS232 sensor signal, voltage signal output by the current signal conditioning unit, and voltage signal output by the IEPE signal conditioning unit are connected to a switching unit and then connected to the acquisition circuit. The control end of each switching unit is connected to the control signal output end of the FPGA, and only one switching unit is turned on at a time according to the control signal of the FPGA to conduct the corresponding connected signal to the subsequent circuit.

[0028] The acquisition circuit includes an AD acquisition unit and a UART acquisition unit, and the UART acquisition unit includes an RS484 conversion circuit and an RS232 conversion circuit. Optionally, the AD acquisition unit can be constructed using an ADC chip, the RS232 conversion circuit can be constructed using a MAX3232EUE chip, and the RS484 conversion circuit can be constructed using a MAX3490ESA chip.

[0029] The input end of the RS484 conversion circuit is connected to the output end of the switching unit corresponding to the RS484 sensor signal, the input end of the RS232 conversion circuit is connected to the output end of the switching unit corresponding to the RS232 sensor signal, the input end of the AD acquisition unit is connected to the switching unit corresponding to the voltage sensor signal, the switching unit corresponding to the current signal conditioning unit, and the switching unit corresponding to the IEPE signal conditioning unit, and the output ends of the AD acquisition unit, the RS484 conversion circuit, and the RS232 conversion circuit are connected to the FPGA.

[0030] The AD acquisition unit is used to convert the voltage sensor signal, or the voltage signal output by the current signal conditioning unit, or the voltage signal output by the IEPE signal conditioning unit into a digital quantity and then output it to the FPGA; the RS484 conversion circuit is used to perform UART acquisition on the RS484 sensor signal to convert it into an LVTTL digital signal and then output it to the FPGA; the RS232 conversion circuit is used to perform UART acquisition on the RS232 sensor signal to convert it into an LVTTL digital signal and then output it to the FPGA.

[0031] Specifically, Figure 3The figure shows an optional example of a current signal conditioning unit, which includes resistors R17, R18, R19 and an op amp chip U1, etc. Among them, one end of resistor R17 and resistor R18 is the input end of the current signal conditioning unit, connected to the current sensor signal, the other end of resistor R17 is connected to one end of resistor R19 and the 1in+ pin of the op amp chip U1, the other end of resistor R18 is connected to AGND (analog ground), the 1out pin and 1in- pin of the op amp chip U1 are the output ends of the current signal conditioning unit, connected to the corresponding switching unit input end in the relay switching circuit, the Vcc- pin is connected to ISOGND (isolated ground), the Vcc+ pin is connected to +24V, and can be configured as a single power supply, and the 2in+ pin, 2in- pin, and 2out pin are suspended.

[0032] Resistor R18 is used as a sampling resistor for current signals, and can convert current sensor signals into voltage signals; the other end of resistor R17 is connected to one end of resistor R19 to form a voltage divider circuit, and the voltage signal at resistor R18 is reduced to a reasonable range. Preferably, the current signal conditioning unit also includes a low-pass filter formed by capacitors C7 and C8, the other end of resistor R17 is connected to one end of capacitor C7 and one end of capacitor C8, the other end of capacitor C7 and the other end of capacitor C8 are connected to AGND, the low-pass filter filters the signal, and the filtered signal enters the first channel of the operational amplifier chip U1 (i.e., the path formed by the 1in+ pin, 1in- pin, and 1out pin of the corresponding operational amplifier chip U1), and the first channel of the operational amplifier chip U1 constitutes a voltage follower circuit, which plays a role in increasing impedance on the one hand, and can protect the ADC chip in the acquisition circuit at the back end on the other hand, and avoid damage to the ADC chip when the front-end circuit fails; in order to improve the signal quality, the operational amplifier chip U1 is powered by an isolated power supply.

[0033] Specifically, as one of the optional implementation forms, Figure 4 As shown, the IEPE signal conditioning unit includes resistor R11, resistor R14, capacitor C5, resistor R15, resistor R16, resistor R8, resistor R9, operational amplifier chip U2, capacitor C6, resistor R12, capacitor C4, resistor R10, resistor R13, capacitor C3, resistor R4, resistor R5, operational amplifier chip U3, capacitor C1, resistor R1, resistor R2, resistor R3, transistor T1, resistor R6, capacitor C2, resistor R7, etc., wherein resistor R14 is a matching resistor and capacitor C5 is an AC coupling capacitor.

[0034] Among them, one end of the resistor R11 and the resistor R14 are the input ends of the IEPE signal conditioning unit, which are connected to the IEPE sensor signal. The other end of the resistor R14 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to one end of the resistor R15, one end of the resistor R16, one end of the resistor R8 and the 2in+ pin of the operational amplifier chip U2. The other end of the resistor R8 is connected to one end of the resistor R9 and the 2out pin and 2in- pin of the operational amplifier chip U2. The other end of the resistor R9 is connected to the 1in+ pin of the operational amplifier chip U2. The Vcc+ pin of the operational amplifier chip U2 is connected to ISO0_2V5 (isolated power supply 2 .5V) and one end of capacitor C6, the other end of capacitor C6 is connected to ISOGND, resistor R12 is connected between the 1out pin and 1in- pin of the operational amplifier chip U2, capacitor C4 is connected in parallel across resistor R12, one end of capacitor C4 is connected to one end of resistor R10, the other end of resistor R10 is the output end of the IEPE signal conditioning unit, the other end of capacitor C4 is connected to one end of resistor R13, the other end of resistor R13 is connected to one end of capacitor C3 and ISOGND, the other end of capacitor C3 is connected to the other end of resistor R10; the other ends of resistors R15 and R16 are connected to ISOGND.

[0035] The other end of resistor R11 is connected to one end of resistor R6, one end of capacitor C2 and the 1in+ pin of op amp chip U3. The 1out pin and 1in- pin of op amp chip U3 are connected to one end of resistor R5. The other end of resistor R5 is connected to one end of resistor R4 and the 2in+ pin of op amp chip U3. The other end of resistor R4 is connected to REF_2V5 (reference voltage 2.5V). The Vcc+ pin of op amp chip U3 is connected to ISO0_+24V (isolated power supply +24V), and the Vcc- pin is connected to ISOGND. The 2in- pin of the op amp chip U3 is connected to one end of the capacitor C1, one end of the resistor R2, and one end of the resistor R3. The other end of the resistor R3 is connected to ISOGND. The other end of the resistor R2 is connected to pin 3 of the transistor T1 and the other end of the resistor R6. The 2out pin of the op amp chip U3 is connected to the other end of the capacitor C1 and one end of the resistor R1. The other end of the resistor R1 is connected to pin 1 of the transistor T1. Pin 2 of the transistor T1 is connected to ISO0_+24V. The other end of the capacitor C2 is connected to one end of the resistor R7. The other end of the resistor R7 is connected to ISOGND.

[0036] The working principle of the IEPE signal conditioning unit includes two parts: providing a constant current source to the sensor and collecting sensor signals.

[0037] The implementation principle of the constant current source circuit is as follows: the first channel of the dual-channel operational amplifier chip U3 is a voltage follower circuit, which plays a high impedance role; the second channel of the operational amplifier chip U3 and the transistor T1, resistor R6, resistor R1, resistor R2, resistor R4, and resistor R5 constitute a current negative feedback circuit; REF_2V5 provides an accurate voltage reference for the current negative feedback circuit, and the output current of the circuit can be adjusted by adjusting the resistance value of resistor R6. A constant current signal can be provided through the current negative feedback circuit. The constant current signal passes through the current limiting resistor R11 and is connected to the sensor interface IEPE_IN to provide power for the sensor.

[0038] The principle of the sensor signal acquisition circuit is as follows: the IEPE sensor signal is an AC signal, which is output from the IEPE_IN interface, and enters the second channel of the dual-channel operational amplifier chip U2 for proportional amplification after passing through the matching resistor R14 and the AC coupling capacitor C5. The amplified signal is connected to the first channel of the operational amplifier chip U2 for filtering. The filtering here is performed by a filter circuit composed of capacitor C4, capacitor C3, resistor R10, resistor R13, and resistor R12. The filtered signal can be connected to the back-end switching unit through the IEPE_OUT interface for switching and selection, and then supplied to the AD acquisition unit for acquisition.

[0039] Preferably, Figure 4 In the example shown, the other end of capacitor C5 is connected to the positive electrode of Schottky diode D1 and the negative electrode of Schottky diode D2, the negative electrode of Schottky diode D1 is connected to ISO0_2V5, and the positive electrode of Schottky diode D2 is connected to ISO0_-2V5. By setting Schottky diode D1 and Schottky diode D2, the signal is limited to protect the back-end operational amplifier chip U2 from being damaged by signals higher than the supply voltage.

[0040] Specifically, each switching unit includes a relay, a switching diode, an N-channel MOS tube, etc. Specifically, Figure 5 As shown, a switching unit connected to an IEPE sensor signal is used as an example for explanation. In this example, a relay K10, a freewheeling diode D39, and an N-channel MOS tube Q10 are included. The G pole of the N-channel MOS tube Q10 is connected to the control signal output end of the FPGA through a resistor R862, the S pole is connected to GND, the D pole is connected to the positive pole of the freewheeling diode D39 and the 8th pin of the relay K10, the 2nd and 7th pins of the relay K10 are suspended, the 1st pin is connected to the negative pole of the freewheeling diode D39 and DC12V (here, DC12V is the power supply for the line package of the relay K10), the 4th and 5th pins are used to access a signal transmitted from the previous stage, which is the voltage signal after the IEPE sensor signal is converted by the IEPE signal conditioning unit, and the 3rd and 4th pins are connected to the input end of the acquisition circuit of the subsequent stage. For the IEPE sensor signal, the 3rd and 4th pins are connected to the input end of the AD acquisition unit.

[0041] When relay K10 needs to be closed, FPGA outputs a high-level control signal, the OD drive circuit composed of MOS tube Q10 will be turned on, the D pole of MOS tube Q10 becomes low level, and the coil of relay K10 will generate current to drive relay K10 to operate, so that relay K10 is closed, and the switching unit where relay K10 is located is turned on, and the signal is output to the subsequent acquisition circuit. The freewheeling diode D39 mainly plays a protective role. When FPGA outputs a low-level control signal, MOS tube Q10 will be disconnected, and the current in the coil of relay K10 cannot be released through the path of MOS tube Q10, so adding the freewheeling diode D39 can release this part of energy.

[0042] It should be noted that in actual applications, the relays of each switching unit are disconnected by default. When switching is required, the connected signal is disconnected first and then the new signal is connected to avoid short circuits or abnormal problems caused by connecting different signal channels at the same time.

[0043] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application.

Claims

1. An aircraft flight test device, characterized in that: Including conditioning circuit, relay switching circuit, acquisition circuit, FPGA and power conversion module; The power conversion module is connected to the external power supply and is used to convert the voltage provided by the external power supply to power the test device; The input end of the conditioning circuit is connected to a current sensor signal and an IEPE sensor signal among the multiple sensor signals, and is used to convert the current sensor signal and the IEPE sensor signal into voltage signals respectively and then output them; The relay switching circuit is connected to the FPGA, and its input end is respectively connected to a voltage sensor signal, an RS484 sensor signal, an RS232 sensor signal and two voltage signals output by the conditioning circuit among a variety of sensor signals, and is used to select one signal from the input end to be transmitted to the subsequent stage according to the control signal of the FPGA; The input end of the acquisition circuit is connected to the output end of the relay switching circuit, and is used to perform AD acquisition on the voltage sensor signal or voltage signal to convert the analog quantity into a digital quantity and then output it, or perform UART acquisition on the RS484 sensor signal or RS232 sensor signal to convert it into an LVTTL digital signal and then output it; The FPGA is connected to the acquisition circuit to obtain the digital quantity or digital signal output by the acquisition circuit and process it; Among them, sensors corresponding to various sensor signals are respectively installed at different positions of the aircraft body.

2. The aircraft flight test device according to claim 1, characterized in that: The conditioning circuit includes a current signal conditioning unit and an IEPE signal conditioning unit. The current signal conditioning unit is used to convert the current sensor signal into a voltage signal and then output it. The IEPE signal conditioning unit is used to convert the IEPE sensor signal into a voltage signal and then output it.

3. The aircraft flight test device according to claim 2, characterized in that: The current signal conditioning unit includes resistor R17, resistor R18, resistor R19 and operational amplifier chip U1, wherein one end of resistor R17 and resistor R18 is the input end of the current signal conditioning unit, which is connected to the current sensor signal, the other end of resistor R17 is connected to one end of resistor R19 and the 1in+ pin of operational amplifier chip U1, the other end of resistor R18 is connected to AGND, the 1out pin and 1in- pin of operational amplifier chip U1 are the output ends of the current signal conditioning unit, which are connected to the relay switching circuit, the Vcc- pin is connected to ISOGND, the Vcc+ pin is connected to +24V, and the 2in+ pin, 2in- pin and 2out pin are suspended.

4. The aircraft flight test device according to claim 3, characterized in that: The current signal conditioning unit further includes a capacitor C7 and a capacitor C8. The other end of the resistor R17 is connected to one end of the capacitor C7 and one end of the capacitor C8. The other end of the capacitor C7 and the other end of the capacitor C8 are connected to AGND.

5. The aircraft flight test device according to claim 2, characterized in that: The IEPE signal conditioning unit includes a resistor R11, a resistor R14, a capacitor C5, a resistor R15, a resistor R16, a resistor R8, a resistor R9, an operational amplifier chip U2, a capacitor C6, a resistor R12, a capacitor C4, a resistor R10, a resistor R13, a capacitor C3, a resistor R4, a resistor R5, an operational amplifier chip U3, a capacitor C1, a resistor R1, a resistor R2, a resistor R3, a transistor T1, a resistor R6, a capacitor C2, and a resistor R7; Among them, one end of the resistor R11 and the resistor R14 is the input end of the IEPE signal conditioning unit, which is connected to the IEPE sensor signal, the other end of the resistor R14 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected to one end of the resistor R15, one end of the resistor R16, one end of the resistor R8 and the 2in+ pin of the operational amplifier chip U2, the other end of the resistor R8 is connected to one end of the resistor R9 and the 2out pin and 2in- pin of the operational amplifier chip U2, the other end of the resistor R9 is connected to the 1in+ pin of the operational amplifier chip U2, and the Vcc+ pin of the operational amplifier chip U2 is connected to ISO0_2V5 and one end of capacitor C6, the other end of capacitor C6 is connected to ISOGND, resistor R12 is connected between 1out pin and 1in- pin of operational amplifier chip U2, capacitor C4 is connected in parallel to both ends of resistor R12, one end of capacitor C4 is connected to one end of resistor R10, the other end of resistor R10 is the output end of IEPE signal conditioning unit, the other end of capacitor C4 is connected to one end of resistor R13, the other end of resistor R13 is connected to one end of capacitor C3 and ISOGND, the other end of capacitor C3 is connected to the other end of resistor R10; the other ends of resistors R15 and R16 are connected to ISOGND; The other end of resistor R11 is connected to one end of resistor R6, one end of capacitor C2 and the 1in+ pin of op amp chip U3. The 1out pin and 1in- pin of op amp chip U3 are connected to one end of resistor R5. The other end of resistor R5 is connected to one end of resistor R4 and the 2in+ pin of op amp chip U3. The other end of resistor R4 is connected to REF_2V5. The Vcc+ pin of op amp chip U3 is connected to ISO0_+24V, the Vcc- pin is connected to ISOGND, and the 2in- The pin is connected to one end of capacitor C1, one end of resistor R2, and one end of resistor R3. The other end of resistor R3 is connected to ISOGND. The other end of resistor R2 is connected to pin 3 of transistor T1 and the other end of resistor R6. The 2out pin of op amp chip U3 is connected to the other end of capacitor C1 and one end of resistor R1. The other end of resistor R1 is connected to pin 1 of transistor T1. Pin 2 of transistor T1 is connected to ISO0_+24V. The other end of capacitor C2 is connected to one end of resistor R7. The other end of resistor R7 is connected to ISOGND.

6. The aircraft flight test device according to claim 5, characterized in that: The other end of capacitor C5 is connected to the anode of Schottky diode D1 and the cathode of Schottky diode D2. The cathode of Schottky diode D1 is connected to ISO0_2V5, and the anode of Schottky diode D2 is connected to ISO0_-2V5.

7. The aircraft flight test device according to claim 2, characterized in that: The relay switching circuit includes multiple switching units. The voltage sensor signal, RS484 sensor signal, RS232 sensor signal, voltage signal output by the current signal conditioning unit, and voltage signal output by the IEPE signal conditioning unit are respectively connected to a switching unit and then connected to the acquisition circuit.

8. The aircraft flight test device according to claim 7, characterized in that: The switching unit includes a relay K10, a freewheeling diode D39, and an N-channel MOS tube Q10; the G pole of the N-channel MOS tube Q10 is connected to the control signal output end of the FPGA through a resistor R862, the S pole is connected to GND, the D pole is connected to the positive pole of the freewheeling diode D39 and the 8th pin of the relay K10, the 2nd and 7th pins of the relay K10 are suspended, the 1st pin is connected to the negative pole of the freewheeling diode D39 and DC12V, the 4th and 5th pins are used to access a signal transmitted from the previous stage, and the 3rd and 4th pins are connected to the input end of the acquisition circuit of the subsequent stage.

9. The aircraft flight test device according to claim 7, characterized in that: The acquisition circuit includes an AD acquisition unit and a UART acquisition unit, the UART acquisition unit includes an RS484 conversion circuit and an RS232 conversion circuit, the input end of the RS484 conversion circuit is connected to the output end of the switching unit corresponding to the RS484 sensor signal, the input end of the RS232 conversion circuit is connected to the output end of the switching unit corresponding to the RS232 sensor signal, the input end of the AD acquisition unit is connected to the switching unit corresponding to the voltage sensor signal, the switching unit corresponding to the current signal conditioning unit, and the switching unit corresponding to the IEPE signal conditioning unit, and the output ends of the AD acquisition unit, the RS484 conversion circuit, and the RS232 conversion circuit are connected to the FPGA; The AD acquisition unit is used to convert the voltage sensor signal, or the voltage signal output by the current signal conditioning unit, or the voltage signal output by the IEPE signal conditioning unit into a digital quantity and then output it to the FPGA; The RS484 conversion circuit is used to collect RS484 sensor signals through UART to convert them into LVTTL digital signals and then output them to FPGA; The RS232 conversion circuit is used to collect RS232 sensor signals through UART, convert them into LVTTL digital signals and then output them to FPGA.

10. The aircraft flight test device according to claim 1, characterized in that: The FPGA is also connected to the EMMC storage circuit.

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