Comparator circuit structure with enhanced low-frequency gain
By changing the first stage load structure of the amplifier and adopting a new load structure composed of NMOS tubes and resistors, the problem of low frequency gain of existing amplifiers is solved, and the full swing amplification effect is achieved under small voltage difference.
Patent Information
- Application Number
- CN202421054418.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-15
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-05-15
AI Technical Summary
Existing amplifiers have low gains in the low frequency range, especially when the voltage difference between the positive and negative inputs is small, which is not conducive to amplification to full swing.
By changing the first stage load structure based on a conventional current mirror amplifier, a new load structure consisting of a first NMOS tube and a second NMOS tube, as well as a first resistor and a second resistor, the low frequency gain is enhanced.
The effect of fully amplifying to full swing when the voltage difference at the input end is small, which significantly improves the low-frequency gain.
Smart Images
Figure CN222620998U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of analog circuits, in particular to a comparator circuit structure with enhanced low-frequency gain. Background Art
[0002] A common method used by existing comparators is to use OP as a comparator. This is a current mirror amplifier that can be used as a comparator when used as an open loop. Its obvious defect is that the low-frequency gain is low. When the voltage difference between the negative input terminal voltage and the positive input terminal voltage is small, it will be unfavorable for the amplifier to amplify to the full swing. Utility Model Content
[0003] Technical problems to be solved by utility models
[0004] The technical problem to be solved by the utility model is to provide a comparator circuit structure with low-frequency gain enhancement, which solves the problem that the low-frequency gain of the existing amplifier is low and it is not conducive to amplifying to the full swing when the voltage difference between the positive and negative input terminals is small.
[0005] Technical Solution
[0006] In order to solve the above problems, the technical solution provided by the utility model is:
[0007] A comparator circuit structure with low-frequency gain enhancement includes a first NMOS tube and a second NMOS tube, and a first resistor and a second resistor, wherein the gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are grounded respectively, the first resistor is connected in series with the second resistor, the gates of the first NMOS tube and the second NMOS tube are connected between the first resistor and the second resistor, the drain of the first NMOS tube is connected to an end of the first resistor that is not connected to the second resistor, and the drain of the second NMOS tube is connected to an end of the second resistor that is not connected to the first resistor.
[0008] Furthermore, it also includes a third NMOS tube and the fourth NMOS tube, the gate of the third NMOS tube is connected to the drain of the first NMOS tube, the gate of the fourth NMOS tube is connected to the drain of the second NMOS tube, and the sources of the third NMOS tube and the fourth NMOS tube are grounded respectively.
[0009] Furthermore, it also includes a first PMOS tube and a second PMOS tube, the gate of the first PMOS tube is connected to the negative input terminal, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the second PMOS tube is connected to the positive input terminal, and the drain of the second PMOS tube is connected to the drain of the second NMOS tube.
[0010] Furthermore, it also includes a third PMOS tube, the source of the third PMOS tube is connected to the power supply, the drain of the third PMOS tube is connected to the sources of the first PMOS tube and the second PMOS tube, and the gate of the third PMOS tube is connected to the bias voltage.
[0011] Furthermore, it also includes a fourth PMOS tube, the source of the fourth PMOS tube is connected to the power supply, and the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube.
[0012] Furthermore, it also includes a fifth PMOS tube, the source of the fifth PMOS tube is connected to the power supply, the drain of the fifth PMOS tube is connected to the drain of the third NMOS tube, and the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube.
[0013] Beneficial Effects
[0014] Compared with the prior art, the technical solution provided by the utility model has the following beneficial effects:
[0015] The technical solution provided by the utility model enhances the low-frequency gain by changing the structure of the first-stage load on the basis of a conventional current mirror amplifier, so that the differential input terminal signal can be fully amplified to the full swing even when the difference is small. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a structural schematic diagram of an embodiment of the utility model;
[0017] Figure 2 It is a schematic structural diagram of a comparative example of the present utility model. DETAILED DESCRIPTION
[0018] In order to further understand the content of the utility model, the utility model is described in detail in conjunction with the accompanying drawings and embodiments.
[0019] Example
[0020] Combined with Figure 1 A comparator circuit structure with low-frequency gain enhancement is provided. The first NMOS tube mn1 and the second NMOS tube mn2, as well as the first resistor r1 and the second resistor r2 form a new load structure of the first-stage amplifier. The first NMOS tube mn1 and the second NMOS tube mn2 and the first resistor r1, the second resistor r2 and the first PMOS tube mp1, the second PMOS tube mp2, and the third PMOS tube mp3 form a first-stage amplifier. The third NMOS tube mn3 and the fourth NMOS tube mn4 and the fourth PMOS tube mp4 and the fifth PMOS tube mp5 form a second-stage amplifier.
[0021] The gate of the first NMOS transistor mn1 is connected to the gate of the second NMOS transistor mn2, the sources of the first NMOS transistor mn1 and the second NMOS transistor mn1 are respectively connected to the ground gnd, the first resistor r1 and the second resistor r2 are connected in series, the gates of the first NMOS transistor mn1 and the second NMOS transistor mn2 are connected between the first resistor r1 and the second resistor r2, the drain of the first NMOS transistor mn1 is connected to an end of the first resistor r1 that is not connected to the second resistor r2, and the drain of the second NMOS transistor mn2 is connected to an end of the second resistor r2 that is not connected to the first resistor r1.
[0022] In addition to providing a stable DC bias point, the load structure of the above technical solution changes the small signal impedance of this load from the output impedance 1 / gm of the diode-form MOS to rout / / r1, thereby achieving the function of gain increase, so that when the voltage difference between the inputs vn and vp is small, the effect of amplification to the full swing can still be achieved.
[0023] The gate of the third NMOS transistor mn3 is connected to the drain of the first NMOS transistor mn1, the gate of the fourth NMOS transistor mn4 is connected to the drain of the second NMOS transistor mn2, and the sources of the third NMOS transistor mn3 and the fourth NMOS transistor mn4 are grounded to gnd respectively.
[0024] The gate of the first PMOS transistor mp1 is connected to the negative input terminal vn, and the drain of the first PMOS transistor mp1 is connected to the drain of the first NMOS transistor mn1.
[0025] The gate of the second PMOS transistor mp2 is connected to the positive input terminal vp, and the drain of the second PMOS transistor mp2 is connected to the drain of the second NMOS transistor mn2.
[0026] The source of the third PMOS tube mp3 is connected to the power supply VDD, the drain of the third PMOS tube mp3 is connected to the sources of the first PMOS tube mp1 and the second PMOS tube mp2, and the gate of the third PMOS tube mp3 is connected to the bias voltage Vbp.
[0027] A source of the fourth PMOS tube mp4 is connected to a power source VDD, a drain of the fourth PMOS tube mp4 is connected to a drain of the fourth NMOS tube mn4, and a drain of the fourth PMOS tube mp4 is connected to an output voltage Vout.
[0028] The source of the fifth PMOS tube mp5 is connected to the power supply VDD, the drain of the fifth PMOS tube mp5 is connected to the drain of the third NMOS tube mn3, and the gate of the fifth PMOS tube mp5 is connected to the drain of the fifth PMOS tube mn5.
[0029] By changing the load of the first-stage amplifier from a diode-type MOS to a brand-new load structure of the first-stage amplifier composed of the first NMOS tube mn1 and the second NMOS tube mn2, and the first resistor r1 and the second resistor r2 in the above technical solution, this new load structure can not only provide a stable DC bias point, that is, the DC bias point of the new structure is the same as that of the diode-type MOS load, so that the new structure is as stable as the diode-type MOS load, but also the small signal impedance of this load is changed from the output impedance 1 / gm of the diode-type MOS to rout / / r1, thereby realizing the function of increasing gain.
[0030] Its gain effect is explained as follows:
[0031] For example, mp5 is the same as mp4, mn1 is the same as mn3, mn2 is the same as mn4, r1=r2=r, mp1 is the same as mp2, and gm2 is the transconductance of mp2.
[0032] Then the gain A=A1*A2;
[0033] The first stage gain A1 = gm2*(r / / rout_n2), where rout_n2 is the small signal output resistance of mn2;
[0034] The second stage gain A2 = gm4*(rout_p4 / / rout_n4), gm4 is the transconductance of mn4,
[0035] Where rout_p4 is the small signal output resistance of mp4, and rout_n4 is the small signal output resistance of mn4;
[0036] That is to say, the total gain A=gm2*(r / / rout_n2)*gm4*(rout_p4 / / rout_n4).
[0037] Comparative Example:
[0038] A more conventional comparator in the prior art is a method commonly used to use the op as a comparator, using a current mirror amplifier as an open loop to be used as a comparator, and its specific structure is:
[0039] The first NMOS tube mn1 and the second NMOS tube mn2 form a diode-shaped MOS load, and the first NMOS tube mn1 and the second NMOS tube mn2 and the first PMOS tube mp1, the second PMOS tube mp2, and the third PMOS tube mp3 form a first-stage amplifier, and the third NMOS tube mn3 and the fourth NMOS tube mn4 and the fourth PMOS tube mp4 and the fifth PMOS tube mp5 form a second-stage amplifier.
[0040] The drain of the first NMOS transistor mn1 is connected to the gate of the first NMOS transistor mn1, the source of the first NMOS transistor mn1 is grounded to gnd, the drain of the second NMOS transistor mn2 is connected to the gate of the second NMOS transistor mn2, and the source of the second NMOS transistor mn2 is grounded to gnd.
[0041] The third NMOS transistor mn3 and the fourth NMOS transistor mn4, the gate of the third NMOS transistor mn3 is connected to the gate of the first NMOS transistor mn1.
[0042] The gate of the fourth NMOS transistor mn4 is connected to the gate of the second NMOS transistor mn2, and the sources of the third NMOS transistor mn3 and the fourth NMOS transistor mn4 are connected to the ground gnd respectively.
[0043] The gate of the first PMOS transistor mp1 is connected to the negative input terminal vn, and the drain of the first PMOS transistor mp1 is connected to the drain of the first NMOS transistor mn1.
[0044] The gate of the second PMOS transistor mp2 is connected to the positive input terminal vp, and the drain of the second PMOS transistor mp2 is connected to the drain of the second NMOS transistor mn2.
[0045] The source of the third PMOS tube mp3 is connected to the power supply VDD, the drain of the third PMOS tube mp3 is connected to the sources of the first PMOS tube mp1 and the second PMOS tube mp2, and the gate of the third PMOS tube mp3 is connected to the bias voltage Vbp.
[0046] A source of the fourth PMOS tube mp4 is connected to a power source VDD, a drain of the fourth PMOS tube mp4 is connected to a drain of the fourth NMOS tube mn4, and a drain of the fourth PMOS tube mp4 is connected to an output voltage Vout.
[0047] The source of the fifth PMOS tube mp5 is connected to the power supply VDD, the drain of the fifth PMOS tube mp5 is connected to the drain of the third NMOS tube mn3, and the gate of the fifth PMOS tube mp5 is connected to the drain of the fifth PMOS tube mn5.
[0048] The main defect is: the defect is that the low-frequency gain is low. If the voltage difference between the input vn and vp is small, it is not conducive to amplifying to the full swing.
[0049] Its gain effect is explained as follows:
[0050] Taking mp5 and mp4 as the same, mn1 and mn3 as the same, and mn2 and mn4 as the same, the gain is only gm2*rout, where gm2 is the transconductance of mp2, and rout is the output impedance of the output node vout, which is equal to the parallel connection of the output impedances of mp4 and mn4, that is, rout=rout_p4 / / rout_n4;
[0051] That is, A=gm2*(rout_p4 / / rout_n4).
[0052] Compare the embodiment with the comparative example:
[0053] The proportional gain A=gm2*(rout_p4 / / rout_n4).
[0054] The gain A of the embodiment = gm2*(r / / rout_n2)*gm4*(rout_p4 / / rout_n4),
[0055] It can be seen that the gain A of the embodiment is much greater than the gain A=gm2*(rout_p4 / / rout_n4) of the comparative example.
[0056] It can be seen that by changing the load structure of the first-stage amplifier, the low-frequency gain can be significantly improved, and when the voltage difference between the inputs vn and vp is small, it can still be amplified to the full swing.
[0057] The above schematically describes the present invention and its implementation methods, which are not restrictive. The drawings show only one implementation method of the present invention, and the actual structure is not limited thereto. Therefore, if ordinary technicians in this field are inspired by it and design structural methods and embodiments similar to the technical solution without creativity without departing from the purpose of the present invention, they should all fall within the protection scope of the present invention.
Claims
1. A comparator circuit structure with low-frequency gain enhancement, characterized in that: The invention comprises a first NMOS tube and a second NMOS tube, and a first resistor and a second resistor, wherein the gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are grounded respectively, the first resistor and the second resistor are connected in series, the gates of the first NMOS tube and the second NMOS tube are connected to between the first resistor and the second resistor, the drain of the first NMOS tube is connected to an end of the first resistor that is not connected to the second resistor, and the drain of the second NMOS tube is connected to an end of the second resistor that is not connected to the first resistor.
2. The comparator circuit structure with low-frequency gain enhancement according to claim 1, characterized in that: It also includes a third NMOS tube and a fourth NMOS tube, wherein the gate of the third NMOS tube is connected to the drain of the first NMOS tube, the gate of the fourth NMOS tube is connected to the drain of the second NMOS tube, and the sources of the third NMOS tube and the fourth NMOS tube are grounded respectively.
3. The comparator circuit structure with low-frequency gain enhancement according to claim 1, characterized in that: It also includes a first PMOS tube and a second PMOS tube, wherein the gate of the first PMOS tube is connected to the negative input terminal, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the second PMOS tube is connected to the positive input terminal, and the drain of the second PMOS tube is connected to the drain of the second NMOS tube.
4. The comparator circuit structure with low-frequency gain enhancement according to claim 3, characterized in that: It also includes a third PMOS tube, the source of the third PMOS tube is connected to the power supply, the drain of the third PMOS tube is connected to the sources of the first PMOS tube and the second PMOS tube, and the gate of the third PMOS tube is connected to the bias voltage.
5. The comparator circuit structure with low-frequency gain enhancement according to claim 2, characterized in that: It also includes a fourth PMOS tube, a source of the fourth PMOS tube is connected to a power source, and a drain of the fourth PMOS tube is connected to a drain of the fourth NMOS tube.
6. The comparator circuit structure with low-frequency gain enhancement according to claim 5, characterized in that: It also includes a fifth PMOS tube, the source of the fifth PMOS tube is connected to the power supply, the drain of the fifth PMOS tube is connected to the drain of the third NMOS tube, and the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube.