High-side current detection amplifier

Abstract

The utility model relates to the field of high-side current detection amplifiers, in particular to a high-side current detection amplifier. Comprising an input resistance module, a common-base differential input pair module, a VICM reference point obtaining module, a cascode tail current source module, a cascode current source module, a high-voltage-resistant module, a positive common-mode operational amplifier module, a negative common-mode operational amplifier module, a current mirror image module, a feedback module and an output module, the circuit works in a working voltage rail from Vdd to gnd, the VICM is changed from being higher than Vdd to being lower than gnd, and the current mirror image module changes from being higher than Vdd to being lower than gnd. The common-base differential input pair of the negative common mode part is firstly turned into conduction from closing, then the feedback module of the negative common mode part is switched into conduction from closing through a working point, meanwhile, the feedback module of the positive common mode part is turned into closing from conduction, and finally, the common-base differential input pair of the positive common mode part is turned into closing from conduction. Conversion that the positive common-mode operational amplifier feedback loop and the negative common-mode operational amplifier feedback loop are used as dominant work in sequence is achieved.

Description

Technical Field

[0001] The utility model relates to the field of high-side current detection amplifiers, in particular to a high-side current detection amplifier. Background Art

[0002] A high-side current sense amplifier is an electronic device used to detect and amplify high-side current signals. It is often used to monitor and control high-side current. This amplifier usually has high precision and high stability, and can accurately measure the high-side current and amplify it to an appropriate level. It usually includes a current sensor, amplifier, and output stage, through which the current signal can be detected and amplified. High-side current sense amplifiers usually have a high input voltage range and low drift to ensure accurate current measurement. It also usually has protection functions to prevent overload and short circuit to protect the safety of circuits and equipment.

[0003] In actual applications, unexpected load paths to ground may occur. In this case, high-side current detection can detect overcurrent events more safely than low-side current detection. However, high-side detection often requires a small resistor to be connected in series with the positive output end of the power supply to minimize the power supply voltage loss, so as to obtain its voltage drop as a differential input voltage, and amplify it to the output to characterize the load current. In addition, in applications with limited power consumption and heat generation, the chip needs to work on the working voltage rail of the subsequent comparison quantization circuit, which requires an input stage with a common-mode input voltage range that exceeds its working voltage rail. However, existing conventional high-side current detection amplifiers only have the function of detecting within the positive common-mode input voltage range. In some application scenarios, this will complicate the design of the overcurrent detection circuit. Utility Model Content

[0004] The utility model aims to provide a high-side current detection amplifier, aiming to improve the problem that a conventional high-side current detection device only has a detection function within a positive common-mode input voltage range.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A high-side current detection amplifier includes an input resistor module, a common base differential input pair module, a V ICM Reference point acquisition module, cascode tail current source module, cascode current source module, high voltage resistance module, positive common mode operational amplifier module, negative common mode operational amplifier module, current mirror module, feedback module and output module;

[0007] The first input terminal and the second input terminal of the input resistance module are electrically connected to the outside as the same direction input terminal and the reverse direction input terminal; the first input terminal and the second input terminal of the common base differential input pair module are electrically connected to the first output terminal and the second output terminal of the input resistance module respectively;

[0008] The cascode tail current source module is electrically connected to the power input terminal of the common-base differential input pair module, and the first output terminal and the second output terminal of the common-base differential input pair module are electrically connected to the input terminals of the positive common-mode operational amplifier module and the negative common-mode operational amplifier module respectively; the feedback module is electrically connected between the output terminals of the positive common-mode operational amplifier module and the negative common-mode operational amplifier module, the input resistance module and the common-base differential input pair module; the output terminal of the positive common-mode operational amplifier module is electrically connected to the input terminal of the output module; the output terminal of the negative common-mode operational amplifier module is electrically connected to the input terminal of the current mirror module; the output terminal of the current mirror module is electrically connected to the input terminal of the output module,

[0009] The V ICM The reference point acquisition module is electrically connected between the first input terminal, the second input terminal, the power input terminal, the first input terminal, the second input terminal and the high-voltage resistant module of the common-base differential input pair module, the output terminal of the cascode current source module is electrically connected to the high-voltage resistant module, and the high-voltage resistant module is electrically connected to the first input terminal, the second input terminal of the common-base differential input pair module, the output terminal of the feedback module, the input terminal of the positive common-mode operational amplifier module and the input terminal of the negative common-mode operational amplifier module.

[0010] Furthermore, the cascode current source module includes a MOS transistor MP2, a MOS transistor MP3, a MOS transistor MN2 and a MOS transistor MN3;

[0011] The cascode tail current source module includes a MOS tube MP4, a MOS tube MP5, a MOS tube MP9, a MOS tube MN4, a MOS tube MN5 and a MOS tube MN8;

[0012] The source of the MOS transistor MP2, the drain of the MOS transistor MN8 and the source of the MOS transistor MP4 are all electrically connected to an external power supply, the drain of the MOS transistor MP2 is electrically connected to the source of the MOS transistor MP3, the drain of the MOS transistor MP4 is electrically connected to the source of the MOS transistor MP5; the drain of the MOS transistor MP5 is electrically connected to the source of the MOS transistor MP9;

[0013] The drain of the MOS tube MP3, the drain of the MOS tube MN3, the drain of the MOS tube MP5 and the drain of the MOS tube MN5 are all electrically connected to the high-voltage resistance module; the source of the MOS tube MN3 is electrically connected to the drain of the MOS tube MN2; the drain of the MOS tube MN5 is also electrically connected to the source of the MOS tube MN8, the source of the MOS tube MN5 is electrically connected to the drain of the MOS tube MN4, the drain of the MOS tube MP9, the source of the MOS tube MN2 and the source of the MOS tube MN4 are all grounded,

[0014] The gates of the MOS tube MP2, the MOS tube MP3, the MOS tube MN2 and the MOS tube MN3 are electrically connected to the first output terminal of the external bias voltage, the second output terminal of the external bias voltage, the fourth output terminal of the external bias voltage and the third output terminal of the external bias voltage, respectively; the gates of the MOS tube MP4, the MOS tube MP5, the MOS tube MN4 and the MOS tube MN5 are electrically connected to the first output terminal of the external bias voltage, the second output terminal of the external bias voltage, the fourth output terminal of the external bias voltage and the third output terminal of the external bias voltage, respectively; the gates of the MOS tube MP9 and the MOS tube MN8 are electrically connected to the second output terminal of the external bias voltage and the third output terminal of the external bias voltage, respectively.

[0015] Further, the high-voltage resistant module includes MOS tube HVP102, MOS tube HVP103, MOS tube HVP104, MOS tube HVP201, MOS tube HVP202, MOS tube HVP203, MOS tube HVP204, MOS tube HVP205, MOS tube HVN101, MOS tube HVN102, MOS tube HVN103, MOS tube HVN104, MOS tube HVN105, MOS tube HVN202, MOS tube HVN203, MOS tube HVN204 and diodes HVD101, diode HVD102, diode HVD103, diode HVD201, diode HVD202, diode HVD203;

[0016] The drain of the MOS transistor MP3 is electrically connected to the source of the MOS transistor HVP201, and the drain of the MOS transistor HVP201 is electrically connected to the anode of the diode HVD101, the gate of the MOS transistor HVN203, the gate of the MOS transistor HVN103, the gate of the MOS transistor HVN204, and the gate of the MOS transistor HVN104;

[0017] The drain of the MOS tube HVN203 and the drain of the MOS tube HVN204 are electrically connected to the input end of the negative common mode operational amplifier module;

[0018] The source of the MOS transistor HVP202 is electrically connected to the drain of the MOS transistor MP5 and the source of the MOS transistor MP9; the source of the MOS transistor HVN102 is electrically connected to the drain of the MOS transistor MN5 and the source of the MOS transistor MN8;

[0019] The source of the MOS tube HVN203 is electrically connected to the source of the MOS tube HVN103; the drain of the MOS tube HVP202 is electrically connected to the drain of the MOS tube HVP102; the source of the MOS tube HVN204 is electrically connected to the source of the MOS tube HVN104;

[0020] The common-base differential input pair module is electrically connected to the cathode of the diode HVD103, the anode of the diode HVD203, the drain of the MOS transistor HVN103, the source of the MOS transistor HVP102, the drain of the MOS transistor HVN104, the drain of the MOS transistor HVP203, the source of the MOS transistor HVN202, and the drain of the MOS transistor HVP204;

[0021] The cathode of the diode HVD101 is connected to the gate of the MOS tube HVN202 and V ICM The reference point acquisition module is electrically connected;

[0022] The positive electrode of the diode HVD201 is connected to the gate of the MOS tube HVP102 and V ICM The reference point acquisition module is electrically connected;

[0023] The cathode of the diode HVD201 is electrically connected to the drain of the MOS tube HVN101, the gate of the MOS tube HVP203, the gate of the MOS tube HVP103, the gate of the MOS tube HVP204 and the gate of the MOS tube HVP104; the gate of the MOS tube HVN101 is electrically connected to the external power supply, and the source of the MOS tube HVN101 is electrically connected to the drain of the MOS tube MN3; the source of the MOS tube HVP203 is electrically connected to the source of the MOS tube HVP103, the drain of the MOS tube HVN202 is electrically connected to the drain of the MOS tube HVN102, and the gate of the MOS tube HVN102 is electrically connected to the external power supply; the source of the MOS tube HVP204 is electrically connected to the source of the MOS tube HVP104, and the drain of the MOS tube HVP104 and the drain of the MOS tube HVP103 are both electrically connected to the input end of the positive common mode operational amplifier module;

[0024] The anode of the diode HVD103 is electrically connected to the cathode of the diode HVD102, the anode of the diode HVD102 is electrically connected to the drain of the MOS transistor HVP205, the source of the MOS transistor HVP205 is electrically connected to the feedback module, and the gate of the MOS transistor HVP205 is grounded;

[0025] The cathode of the diode HVD203 is electrically connected to the anode of the diode HVD202, the cathode of the diode HVD202 is electrically connected to the drain of the MOS transistor HVN105, the source of the MOS transistor HVN105 is electrically connected to the feedback module, and the gate of the MOS transistor HVN105 is electrically connected to the external power supply.

[0026] Further, the common-base differential input pair module includes transistor QN1, transistor QN2, transistor QN3, transistor QN4, transistor QP1, transistor QP2, transistor QP3 and transistor QP4;

[0027] The input resistance module includes a resistor R1 and a resistor R2;

[0028] The V ICM The reference point acquisition module includes a MOS tube MP1, a MOS tube MN1 and a diode D1, a diode D2, a diode D3, and a diode D4;

[0029] One end of the resistor R1 is electrically connected to the source of the MOS transistor MN1 and the source of the MOS transistor MP1, and is electrically connected to the outside as a non-inverting input end; the drain and gate of the MOS transistor MN1 are electrically connected to the cathode of the diode HVD101 and the gate of the MOS transistor HVN202; the gate and drain of the MOS transistor MP1 are electrically connected to the anode of the diode HVD201 and the gate of the MOS transistor HVP102;

[0030] The other end of the resistor R1 is electrically connected to the emitter of transistor QN1, the emitter of transistor QP1, the emitter of transistor QN2, the emitter of transistor QP2, the anode of diode D1, the cathode of diode D3 and the anode of diode HVD203;

[0031] The collector of the transistor QN1 is electrically connected to the drain of the MOS transistor HVN103, and the base of the transistor QN1 is electrically connected to the base, collector, cathode of the diode D1, cathode of the diode D2, base, collector of the transistor QN3, base of the transistor QN4, and source of the MOS transistor HVP102; the collector of the transistor QP1 is electrically connected to the drain of the MOS transistor HVP203, and the base of the transistor QP1 is electrically connected to the base, collector, anode of the diode D3, anode of the diode D4, base, collector of the transistor QP3, base of the transistor QP4, and source of the MOS transistor HVN202;

[0032] One end of the resistor R2 is electrically connected to the outside as a reverse input end, and the other end of the resistor R2 is electrically connected to the emitter of the transistor QN4, the emitter of the transistor QP4, the emitter of the transistor QN3, the emitter of the transistor QP3, the anode of the diode D2, the cathode of the diode D4 and the cathode of the diode HVD103; the collector of the transistor QN4 is electrically connected to the drain of the MOS transistor HVN104, and the collector of the transistor QP4 is electrically connected to the drain of the MOS transistor HVP204.

[0033] Further, the negative common mode operational amplifier module includes a first voltage amplifier 100, a load resistor R3 and a load resistor R4;

[0034] The positive common mode operational amplifier module includes a third voltage amplifier 102, a load resistor R5 and a load resistor R6;

[0035] The feedback module includes a MOS transistor MP6, a MOS transistor MN6, a resistor R7 and a resistor R9;

[0036] One end of the load resistor R3 and the load resistor R4 are both electrically connected to the external power supply, the other end of the load resistor R3 is electrically connected to the reverse input end of the first voltage amplifier 100 and the drain of the MOS tube HVN203, and the other end of the load resistor R4 is electrically connected to the non-inverting input end of the first voltage amplifier 100 and the drain of the MOS tube HVN204; the output end of the first voltage amplifier 100 is electrically connected to the gate of the MOS tube MP6, the source of the MOS tube MP6 is electrically connected to the current mirror module and one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the external power supply; the drain of the MOS tube MP6 is electrically connected to the source of the MOS tube HVP205;

[0037] One end of the load resistor R5 is electrically connected to the same-direction input end of the third voltage amplifier 102 and the drain of the MOS tube HVP103, one end of the load resistor R6 is electrically connected to the reverse input end of the third voltage amplifier 102 and the drain of the MOS tube HVP104, and the other ends of the load resistor R5 and the load resistor R6 are both grounded; the output end of the third voltage amplifier 102 is electrically connected to the gate of the MOS tube MN6, the source of the MOS tube MN6 is electrically connected to the output module and one end of the resistor R9, and the other end of the resistor R9 is grounded; the drain of the MOS tube MN6 is electrically connected to the source of the MOS tube HVN105.

[0038] Furthermore, the current mirror module includes a second voltage amplifier 101, a MOS tube MP7 and a resistor R8;

[0039] The output module includes a voltage buffer 103;

[0040] The non-inverting input terminal of the second voltage amplifier 101 is electrically connected to the source of the MOS transistor MP6 and one end of the resistor R7, the inverting input terminal of the second voltage amplifier 101 is electrically connected to one end of the resistor R8 and the source of the MOS transistor MP7, the other end of the resistor R8 is electrically connected to an external power supply, the output terminal of the second voltage amplifier 101 is electrically connected to the gate of the MOS transistor MP7, the drain of the MOS transistor MP7 is electrically connected to the source of the MOS transistor MN6, one end of the resistor R9 and the input terminal of the voltage buffer 103, and the output terminal of the voltage buffer 103 outputs VO.

[0041] Further, the MOS tube HVP102, MOS tube HVP103, MOS tube HVP104, MOS tube HVP201, MOS tube HVP202, MOS tube HVP203, MOS tube HVP204 and MOS tube HVP205 are all high-voltage PMOS tubes;

[0042] The MOS tube HVN101, MOS tube HVN102, MOS tube HVN103, MOS tube HVN104, MOS tube HVN105, MOS tube HVN202, MOS tube HVN203 and MOS tube HVN204 are all high-voltage NMOS tubes;

[0043] The diode HVD101 , the diode HVD102 , the diode HVD103 , the diode HVD201 , the diode HVD202 and the diode HVD203 are all high voltage diodes.

[0044] Furthermore, the following conditions are met:

[0045] W HVN103 =W HVN104

[0046] L HVN103 =L HVN104

[0047] W HVN203 =W HVN204

[0048] L HVN203 =L HVN204

[0049] W HVP103 =W HVP104

[0050] L HVP103 =L HVP104

[0051] W HVP203 =W HVP204

[0052] L HVP203 =L HVP204

[0053] Where W HVN103 is the width of MOS tube HVN103, W HVN104 is the width of MOS tube HVN104, W HVN203 is the width of MOS tube HVN203, W HVN204 is the width of MOS tube HVN204, W HVP103 is the width of MOS tube HVP103, W HVP104 is the width of MOS tube HVP104, W HVP203 is the width of MOS tube HVP203, W HVP204 is the width of MOS tube HVP204;

[0054] L HVN103 is the length of MOS tube HVN103, L HVN104 is the length of MOS tube HVN104, L HVN203 is the length of MOS tube HVN203, L HVN204 is the length of MOS tube HVN204, L HVP103 is the length of MOS tube HVP103, L HVP104 is the length of MOS tube HVP104, L HVP203 is the length of MOS tube HVP203, L HVP204 It is the length of MOS tube HVP204.

[0055] Furthermore, the following conditions are met:

[0056] DA D1 =DA D2 =DA D3 =DA D4

[0057] EA QN1 =EA QN2 =EA QN3 =EA QN4

[0058] EA QP1 =EA QP2 =EA QP3 =EA QP4

[0059] Among them, DA D1 is the junction area of ​​diode D1, DA D2 is the junction area of ​​diode D2, DA D3 is the junction area of ​​diode D3, DA D4 is the junction area of ​​diode D4; EA QN1is the emitter junction area of ​​transistor QN1, EA QN2 is the emitter junction area of ​​transistor QN2, EA QN3 is the emitter junction area of ​​transistor QN3, EA QN4 is the emitter junction area of ​​transistor QN4; EA QP1 is the emitter junction area of ​​transistor QP1, EA QP2 is the emitter junction area of ​​transistor QP2, EA QP3 is the emitter junction area of ​​transistor QP3, EA QP4 is the emitter junction area of ​​transistor QP4.

[0060] Furthermore, the following conditions are met:

[0061] R1=R2=R9·Av_103 / H_ideal

[0062] R3=R4

[0063] R5=R6

[0064] Wherein, Av_103 is the voltage gain of the voltage buffer 103, and H_ideal is the ideal input differential voltage V of the design indicator. IDM to the DC voltage gain of the output VO.

[0065] After adopting the above technical solution, the utility model has the following advantages compared with the background technology:

[0066] The circuit operates within the operating voltage rail from Vdd to gnd, V ICM In the process of changing from higher than Vdd to lower than gnd, the common-base differential input pair of the negative common-mode part first changes from off to on, and then through a working point switching, the feedback module of the negative common-mode part changes from off to on while the feedback module of the positive common-mode part changes from on to off, and finally the common-base differential input pair of the positive common-mode part changes from on to off, to realize the conversion of the positive common-mode op amp feedback loop and the negative common-mode op amp feedback loop as the dominant work in turn, so as to realize a wide common-mode input voltage range and meet the function of detecting the positive and negative common-mode input range. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 This is a circuit diagram of the high-side current detection amplifier described in the utility model. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0069] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0070] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0071] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.

[0072] Example

[0073] In an embodiment, W Nn is the width of MOS tube MNn; L Nn is the length of MOS tube MNn; W Pn is the width of the MOS tube MPn; L Pn is the length of the MOS tube MPn; W HVNn is the width of the MOS tube HVNn; L HVNn is the length of MOS tube HVNn; W HVPn is the width of MOS tube HVPn; L HVPn DA is the length of MOS tube HVPn; Dn is the junction area of ​​diode Dn; EA QNn is the emitter junction area of ​​transistor QNn; Vce_Nn is the collector-emitter voltage of transistor QNn at the working point; EA QPn is the emitter junction area of ​​transistor QPn; Vec_Pn is the emitter-collector voltage of transistor QPn at the operating point; Rn is the resistance value of resistor Rn; IRn is the voltage drop of resistor Rn at the operating point; Av_n is the voltage gain of voltage amplifier n; V IDM is the input differential voltage (VIP-VIN); V ICM is the input common mode voltage (VIP+VIN) / 2; V ICMR is the input common-mode voltage range (max(V ICM)-min(V ICM )); H(V ICM ) is the actual input differential voltage V IDM The DC voltage gain to the output is a function of the input common-mode voltage; H_ideal is the ideal input differential-mode voltage V IDM H_actual is the actual input differential voltage V IDM to the output VO, which is the average DC voltage gain of all influencing factors except the offset voltage; Vd in the embodiment uniformly refers to the voltage drop on a diode, a high-voltage diode or a parasitic diode working in a forward bias, and the distinction between different types and different working points of the voltage drop is omitted; Vthn in the embodiment uniformly refers to the threshold voltage of NMOS and high-voltage NMOS, and the size difference of different types, different sizes and different working points is omitted; Vthn_Nn is the threshold voltage of MOS tube MNn and MOS tube HVNn; Vov_Nn is the overdrive voltage of MOS tube MNn and MOS tube HVNn; VGS_Nn is the gate-source voltage of MOS tube MNn and MOS tube HVNn; VDS_Nn is the drain-source voltage; Vdsat_Nn is the saturated drain-source voltage of the MOS tube MNn and the MOS tube HVNn; Vthp in the embodiment uniformly refers to the absolute value of the threshold voltage of PMOS and high-voltage PMOS, and omits the size differences of different types, different sizes, and different working points; Vthp_Pn is the absolute value of the threshold voltage of the MOS tube MPn and the MOS tube HVPn; Vov_Pn is the over-drive voltage of the MOS tube MPn and the MOS tube HVPn; VSG_Pn is the source-gate voltage of the MOS tube MPn and the MOS tube HVPn; VSD_Pn is the source-drain voltage of the MOS tube MPn and the MOS tube HVPn; Vdsat_Pn is the saturated drain-source voltage of the MOS tube MPn and the MOS tube HVPn.

[0074] Please refer to Figure 1As shown, this embodiment provides a high-side current detection amplifier, including an input resistance module, a common-base differential input pair module, a cascode tail current source module, a positive common-mode operational amplifier module, a negative common-mode operational amplifier module, a current mirror module, a feedback module and an output module. The first input terminal and the second input terminal of the input resistance module are electrically connected to the outside as the same-direction input terminal and the reverse input terminal. The first input terminal and the second input terminal of the common-base differential input pair module are electrically connected to the first output terminal and the second output terminal of the input resistance module. The cascode tail current source module is electrically connected to the power input terminal of the common base differential input pair module, and the first output terminal and the second output terminal of the common base differential input pair module are electrically connected to the input terminals of the positive common mode operational amplifier module and the negative common mode operational amplifier module respectively; the feedback module is electrically connected between the output terminals of the positive common mode operational amplifier module and the negative common mode operational amplifier module, the input resistance module and the common base differential input pair module; the output terminal of the positive common mode operational amplifier module is electrically connected to the input terminal of the output module; the output terminal of the negative common mode operational amplifier module is electrically connected to the input terminal of the current mirror module; and the output terminal of the current mirror module is electrically connected to the input terminal of the output module. Among them, the common base differential input pair module, the cascode tail current source module and the feedback module can be further subdivided into a positive common mode part and a negative common mode part. The positive common-mode op amp feedback loop is composed of a positive common-mode op amp module, a common-base differential input pair module of the positive common-mode part, a cascode tail current source module, and a feedback module; the negative common-mode op amp feedback loop is composed of a negative common-mode op amp module, a common-base differential input pair module of the negative common-mode part, a cascode tail current source module, and a feedback module.

[0075] The circuit operates within the operating voltage rail from Vdd to gnd, V ICM In the process of changing from higher than Vdd to lower than gnd, the common-base differential input pair of the negative common-mode part first changes from off to on, and then passes through a working point switch, the feedback module of the negative common-mode part changes from off to on, while the feedback module of the positive common-mode part changes from on to off, and finally the common-base differential input pair of the positive common-mode part changes from on to off, to realize the conversion of the positive common-mode op amp feedback loop and the negative common-mode op amp feedback loop as the dominant work in turn, so as to achieve a wide common-mode input voltage range.

[0076] Specifically, the high-side current detection amplifier also includes a cascode current source module, a high voltage resistance module and a V ICM Reference point acquisition module. ICMThe reference point acquisition module is electrically connected between the first input terminal, the second input terminal, the power input terminal, the first input terminal, the second input terminal of the input resistance module and the high voltage resistance module. The output terminal of the cascode current source module is electrically connected to the high voltage resistance module. The high voltage resistance module is electrically connected to the first input terminal, the second input terminal of the common base differential input pair module, the output terminal of the feedback module, the input terminal of the positive common mode operational amplifier module and the input terminal of the negative common mode operational amplifier module. The cascode current source module, the high voltage resistance module and V ICM The reference point acquisition module together forms a pressure-resistant protection structure with high accuracy and wide V ICMR , and in actual devices V ICM When the operating voltage rail is exceeded, the parasitic diode is prevented from conducting and generating a large current path, thus ensuring normal circuit operation.

[0077] With V ICM For large signal changes, the feedback loops where the positive common-mode op amp module and the negative common-mode op amp module are located work independently. For any input differential voltage, the open-loop feedback generated by each is also a function of the loop gain and offset. Since the respective loop gains and offsets are different, the open-loop feedback is also different. Assuming that there are two operating points where the two loops work at the same time, a small signal disturbance is introduced at the differential input. If the feedback of one of them is slightly larger, the differential input of the other will be reduced. This is a positive feedback, so that in the end only one feedback loop will exist at the same time and become dominant, and it will change with V ICM The simulation shows that if there are no diodes HVD103 and HVD203, when considering the input offset voltage of the two op amps, a large output nonlinear error will be generated at the switching point. Although the addition of diodes HVD103 and HVD203 can solve this problem, it also increases the time required to determine V IDM_MAX The minimum Vdd requirement will be discussed at the end of the embodiment. In addition, since the feedback loops working independently have independent loop gain and offset, V ICM It becomes the main factor of output nonlinear error, which can be reduced by increasing the loop gain without affecting stability.

[0078] Specifically, the cascode current source module includes MOS transistor MP2, MOS transistor MP3, MOS transistor MN2 and MOS transistor MN3; the cascode tail current source module includes MOS transistor MP4, MOS transistor MP5, MOS transistor MP9, MOS transistor MN4, MOS transistor MN5 and MOS transistor MN8.

[0079] The source of MOS tube MP2, the drain of MOS tube MN8 and the source of MOS tube MP4 are all electrically connected to the external power supply. The drain of MOS tube MP2 is electrically connected to the source of MOS tube MP3, the drain of MOS tube MP4 is electrically connected to the source of MOS tube MP5; the drain of MOS tube MP5 is electrically connected to the source of MOS tube MP9. The drain of MOS tube MP3, the drain of MOS tube MN3, the drain of MOS tube MP5 and the drain of MOS tube MN5 are all electrically connected to the high-voltage resistance module. The source of MOS tube MN3 is electrically connected to the drain of MOS tube MN2; the drain of MOS tube MN5 is also electrically connected to the source of MOS tube MN8, the source of MOS tube MN5 is electrically connected to the drain of MOS tube MN4, and the drain of MOS tube MP9, the source of MOS tube MN2 and the source of MOS tube MN4 are all grounded.

[0080] The gates of the MOS tube MP2, the MOS tube MP3, the MOS tube MN2 and the MOS tube MN3 are electrically connected to the first output terminal of the external bias voltage, the second output terminal of the external bias voltage, the fourth output terminal of the external bias voltage and the third output terminal of the external bias voltage respectively; the gates of the MOS tube MP4, the MOS tube MP5, the MOS tube MN4 and the MOS tube MN5 are electrically connected to the first output terminal of the external bias voltage, the second output terminal of the external bias voltage, the fourth output terminal of the external bias voltage and the third output terminal of the external bias voltage respectively; the gates of the MOS tube MP9 and the MOS tube MN8 are electrically connected to the second output terminal of the external bias voltage and the third output terminal of the external bias voltage respectively.

[0081] Specifically, the high-voltage resistant module includes MOS tube HVP102, MOS tube HVP103, MOS tube HVP104, MOS tube HVP201, MOS tube HVP202, MOS tube HVP203, MOS tube HVP204, MOS tube HVP205, MOS tube HVN101, MOS tube HVN102, MOS tube HVN103, MOS tube HVN104, MOS tube HVN105, MOS tube HVN202, MOS tube HVN203, MOS tube HVN204 and diodes HVD101, diode HVD102, diode HVD103, diode HVD201, diode HVD202, and diode HVD203.

[0082] The drain of MOS transistor MP3 is electrically connected to the source of MOS transistor HVP201 , and the drain of MOS transistor HVP201 is electrically connected to the anode of diode HVD101 , the gate of MOS transistor HVN203 , the gate of MOS transistor HVN103 , the gate of MOS transistor HVN204 , and the gate of MOS transistor HVN104 .

[0083] The drain of MOS tube HVN203 and the drain of MOS tube HVN204 are electrically connected to the input end of the negative common mode operational amplifier module. The source of MOS tube HVP202 is electrically connected to the drain of MOS tube MP5 and the source of MOS tube MP9; the source of MOS tube HVN102 is electrically connected to the drain of MOS tube MN5 and the source of MOS tube MN8. The source of MOS tube HVN203 is electrically connected to the source of MOS tube HVN103; the drain of MOS tube HVP202 is electrically connected to the drain of MOS tube HVP102; the source of MOS tube HVN204 is electrically connected to the source of MOS tube HVN104.

[0084] The common base differential input pair module is electrically connected to the cathode of diode HVD103, the anode of diode HVD203, the drain of MOS transistor HVN103, the source of MOS transistor HVP102, the drain of MOS transistor HVN104, the drain of MOS transistor HVP203, the source of MOS transistor HVN202, and the drain of MOS transistor HVP204. The cathode of diode HVD101 is connected to the gate of MOS transistor HVN202 and V ICM The reference point acquisition module is electrically connected. The anode of the diode HVD201 is connected to the gate of the MOS tube HVP102 and V ICM The reference point acquisition module is electrically connected. The cathode of the diode HVD201 is electrically connected to the drain of the MOS transistor HVN101, the gate of the MOS transistor HVP203, the gate of the MOS transistor HVP103, the gate of the MOS transistor HVP204 and the gate of the MOS transistor HVP104; the gate of the MOS transistor HVN101 is electrically connected to the external power supply, and the source of the MOS transistor HVN101 is electrically connected to the drain of the MOS transistor MN3; the source of the MOS transistor HVP203 is electrically connected to the source of the MOS transistor HVP103, the drain of the MOS transistor HVN202 is electrically connected to the drain of the MOS transistor HVN102, and the gate of the MOS transistor HVN102 is electrically connected to the external power supply; the source of the MOS transistor HVP204 is electrically connected to the source of the MOS transistor HVP104, and the drain of the MOS transistor HVP104 and the drain of the MOS transistor HVP103 are both electrically connected to the input end of the positive common mode operational amplifier module. The anode of the diode HVD103 is electrically connected to the cathode of the diode HVD102, the anode of the diode HVD102 is electrically connected to the drain of the MOS tube HVP205, the source of the MOS tube HVP205 is electrically connected to the feedback module, and the gate of the MOS tube HVP205 is grounded; the cathode of the diode HVD203 is electrically connected to the anode of the diode HVD202, the cathode of the diode HVD202 is electrically connected to the drain of the MOS tube HVN105, the source of the MOS tube HVN105 is electrically connected to the feedback module, and the gate of the MOS tube HVN105 is electrically connected to the external power supply.

[0085] Specifically, the common base differential input pair module includes transistors QN1, QN2, QN3, QN4, QP1, QP2, QP3 and QP4; the input resistor module includes resistors R1 and R2; V ICM The reference point acquisition module includes a MOS transistor MP1, a MOS transistor MN1 and a diode D1, a diode D2, a diode D3 and a diode D4.

[0086] One end of the resistor R1 is electrically connected to the source of the MOS transistor MN1 and the source of the MOS transistor MP1, and is electrically connected to the outside as a non-inverting input end. The drain and gate of the MOS transistor MN1 are electrically connected to the cathode of the diode HVD101 and the gate of the MOS transistor HVN202; the gate and drain of the MOS transistor MP1 are electrically connected to the anode of the diode HVD201 and the gate of the MOS transistor HVP102. The other end of the resistor R1 is electrically connected to the emitter of the transistor QN1, the emitter of the transistor QP1, the emitter of the transistor QN2, the emitter of the transistor QP2, the anode of the diode D1, the cathode of the diode D3, and the anode of the diode HVD203. The collector of transistor QN1 is electrically connected to the drain of MOS transistor HVN103, and the base of transistor QN1 is electrically connected to the base and collector of transistor QN2, the cathode of diode D1, the cathode of diode D2, the base and collector of transistor QN3, the base of transistor QN4 and the source of MOS transistor HVP102; the collector of transistor QP1 is electrically connected to the drain of MOS transistor HVP203, and the base of transistor QP1 is electrically connected to the base and collector of transistor QP2, the anode of diode D3, the anode of diode D4, the base and collector of transistor QP3, the base of transistor QP4 and the source of MOS transistor HVN202.

[0087] One end of the resistor R2 is electrically connected to the outside as a reverse input end, and the other end of the resistor R2 is electrically connected to the emitter of the transistor QN4, the emitter of the transistor QP4, the emitter of the transistor QN3, the emitter of the transistor QP3, the anode of the diode D2, the cathode of the diode D4 and the cathode of the diode HVD103; the collector of the transistor QN4 is electrically connected to the drain of the MOS transistor HVN104, and the collector of the transistor QP4 is electrically connected to the drain of the MOS transistor HVP204.

[0088] Specifically, the negative common mode operational amplifier module includes a first voltage amplifier 100, a load resistor R3 and a load resistor R4; the positive common mode operational amplifier module includes a third voltage amplifier 102, a load resistor R5 and a load resistor R6; and the feedback module includes a MOS tube MP6, a MOS tube MN6, a resistor R7 and a resistor R9.

[0089] One end of the load resistor R3 and the load resistor R4 are both electrically connected to the external power supply, the other end of the load resistor R3 is electrically connected to the inverting input end of the first voltage amplifier 100 and the drain of the MOS tube HVN203, and the other end of the load resistor R4 is electrically connected to the non-inverting input end of the first voltage amplifier 100 and the drain of the MOS tube HVN204; the output end of the first voltage amplifier 100 is electrically connected to the gate of the MOS tube MP6, the source of the MOS tube MP6 is electrically connected to the current mirror module and one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the external power supply; the drain of the MOS tube MP6 is electrically connected to the source of the MOS tube HVP205.

[0090] One end of the load resistor R5 is electrically connected to the same-direction input end of the third voltage amplifier 102 and the drain of the MOS tube HVP103, one end of the load resistor R6 is electrically connected to the reverse input end of the third voltage amplifier 102 and the drain of the MOS tube HVP104, and the other ends of the load resistor R5 and the load resistor R6 are both grounded; the output end of the third voltage amplifier 102 is electrically connected to the gate of the MOS tube MN6, the source of the MOS tube MN6 is electrically connected to the output module and one end of the resistor R9, and the other end of the resistor R9 is grounded; the drain of the MOS tube MN6 is electrically connected to the source of the MOS tube HVN105.

[0091] Specifically, the current mirror module includes a second voltage amplifier 101 , a MOS tube MP7 and a resistor R8 ; and the output module includes a voltage buffer 103 .

[0092] The non-inverting input terminal of the second voltage amplifier 101 is electrically connected to the source of the MOS transistor MP6 and one end of the resistor R7, the inverting input terminal of the second voltage amplifier 101 is electrically connected to one end of the resistor R8 and the source of the MOS transistor MP7, the other end of the resistor R8 is electrically connected to the external power supply, the output terminal of the second voltage amplifier 101 is electrically connected to the gate of the MOS transistor MP7, the drain of the MOS transistor MP7 is electrically connected to the source of the MOS transistor MN6, one end of the resistor R9 and the input terminal of the voltage buffer 103, and the output terminal of the voltage buffer 103 outputs VO.

[0093] In this embodiment, MOS transistor HVP102, MOS transistor HVP103, MOS transistor HVP104, MOS transistor HVP201, MOS transistor HVP202, MOS transistor HVP203, MOS transistor HVP204 and MOS transistor HVP205 are all high-voltage PMOS transistors;

[0094] MOS tube HVN101, MOS tube HVN102, MOS tube HVN103, MOS tube HVN104, MOS tube HVN105, MOS tube HVN202, MOS tube HVN203 and MOS tube HVN204 are all high-voltage NMOS tubes;

[0095] Diode HVD101, diode HVD102, diode HVD103, diode HVD201, diode HVD202 and diode HVD203 are all high voltage diodes;

[0096] MOS tube MN1, MOS tube MN2, MOS tube MN3, MOS tube MN4, MOS tube MN5 and MOS tube MN6 are all NMOS tubes;

[0097] MOS tube MP1, MOS tube MP2, MOS tube MP3, MOS tube MP4, MOS tube MP5, MOS tube MP6 and MOS tube MP7 are all PMOS tubes;

[0098] Transistor QN1, transistor QN2, transistor QN3 and transistor QN4 are all NPN transistors;

[0099] Transistor QP1, transistor QP2, transistor QP3 and transistor QP4 are all PNP transistors;

[0100] In this embodiment, the voltage buffer 103 is a voltage buffer with gain.

[0101] In this embodiment, the high-side current sensing amplifier meets the following conditions:

[0102] W HVN103 =W HVN104

[0103] L HVN103 =L HVN104

[0104] W HVN203 =W HVN204

[0105] L HVN203 =L HVN204

[0106] W HVP103 =W HVP104

[0107] L HVP103 =L HVP104

[0108] W HVP203 =W HVP204

[0109] LHVP203 =L HVP204

[0110] DA D1 =DA D2 =DA D3 =DA D4

[0111] EA QN1 =EA QN2 =EA QN3 =EA QN4

[0112] EA QP1 =EA QP2 =EA QP3 =EA QP4

[0113] R1=R2=R9·Av_103 / H_ideal

[0114] R3=R4

[0115] R5=R6

[0116] Where W HVN103 is the width of MOS tube HVN103, W HVN104 is the width of MOS tube HVN104, W HVN203 is the width of MOS tube HVN203, W HVN204 is the width of MOS tube HVN204, W HVP103 is the width of MOS tube HVP103, W HVP104 is the width of MOS tube HVP104, W HVP203 is the width of MOS tube HVP203, W HVP204 is the width of MOS tube HVP204; L HVN103 is the length of MOS tube HVN103, L HVN104 is the length of MOS tube HVN104, L HVN203 is the length of MOS tube HVN203, L HVN204 is the length of MOS tube HVN204, L HVP103 is the length of MOS tube HVP103, L HVP104 is the length of MOS tube HVP104, L HVP203 is the length of MOS tube HVP203, L HVP204 DA is the length of MOS tube HVP204. D1 is the junction area of ​​diode D1, DA D2 is the junction area of ​​diode D2, DA D3 is the junction area of ​​diode D3, DA D4 is the junction area of ​​diode D4; EA QN1is the emitter junction area of transistor QN1, EA QN2 is the emitter junction area of transistor QN2, EA QN3 is the emitter junction area of transistor QN3, EA QN4 is the emitter junction area of transistor QN4; EA QP1 is the emitter junction area of transistor QP1, EA QP2 is the emitter junction area of transistor QP2, EA QP3 is the emitter junction area of transistor QP3, EA QP4 is the emitter junction area of transistor QP4. Av_103 is the voltage gain of voltage buffer 103, and H_ideal is the ideal input differential-mode voltage V IDM to the DC voltage gain of output VO.

[0117] Strictly match the devices described by the above equations on the layout to optimize the symmetry of the common-base differential input pair module, improve CMR, and reduce the partial offset voltage of the loop introduced by the common-base differential input pair module.

[0118] Analyze the large signal: Assume that the VIP potential is approximately equal to V when the input differential mode is small ICM .

[0119] For the positive input common-mode voltage operation with Vdd < V ICM :

[0120] The VDS of MOS transistors HVN101, HVN102, HVN103, HVN104, and HVN105 is responsible for the breakdown voltage. Among them, MOS transistors HVN101 and HVN102 clamp the drain voltages of MOS transistors MN3 in the cascode current source module and MOS transistor MN5 in the cascode tail current source module respectively, and operate in the saturation region; MOS transistors HVN103 and HVN104 need to operate in the cut-off region, and their drain potentials are clamped by the forward-biased collector junctions of diodes D1, D2, transistors QN1, and QN4 respectively: VD = V ICM -2Vd, and the gate potential is pulled to Vdd by MOS transistors MP2, MP3, and HVP201 operating in the linear region: VG = Vdd. Looking from the source end, they are the series resistances R3 and R4 of the forward-biased diodes of MOS transistors HVN203 and HVN204 to Vdd respectively: VS = Vdd - IR3 + Vd. It is necessary to ensure that VGS < Vthn, that is, when IR3 < Vthn + Vd, it operates in the cut-off region;

[0121] MOS transistor HVN105 clamps the drain voltage of MOS transistor MN6 and operates in the saturation region;

[0122] The VDS of MOS transistors HVP102, HVP103, and HVP104 is responsible for the breakdown voltage, where:

[0123] MOS transistor HVP102 needs to operate in the cut-off region, and the drain potential is clamped by MOS transistor MP9: VD = Vbias2 + VSG_P9, VG = V ICM -VSG_P1, VS = V ICM -Vd, it is necessary to ensure that VSG < Vthp, that is: VSG_P1 - Vd < Vthp_P102. When Vthp_P1 = Vthp_P102, that is: Vov_P1 < Vd, it operates in the cut-off region;

[0124] MOS transistors HVP103 and HVP104 operate in the saturation region when V ICM is large enough. Their drain potentials are the voltage drops across resistor R5 and resistor R6 respectively: VD = IR5. The gate potential is obtained from V by MOS transistors MP1 and HVD201 ICM : VG = V ICM -VSG_P1 - Vd. At the same time, looking from the source end, they are MOS transistors HVP203, HVP204, and bipolar transistor QP1 operating in the reverse linear region respectively. The collector of bipolar transistor QP4: VS = V ICM -Vec_P1 = VG + VSG_P103. For example, when VSG_P1 = VSG_P103, the collectors of bipolar transistor QP1 and bipolar transistor QP4 are clamped: Vec_P1 = Vd;

[0125] Diodes HVD101, HVD102, and HVD103 are reverse-biased and responsible for withstanding positive voltage;

[0126] For the operation with the negative input common-mode voltage of V ICM <gnd:

[0127] The VDS of MOS transistors HVN202, HVN203, and HVN204 is responsible for the breakdown voltage, where:

[0128] MOS transistor HVN202 needs to operate in the cut-off region, and the drain potential is clamped by MOS transistor MN8: VD = Vbias3 - VGS_N8, VG = V ICM +VGS_N1, VS = V ICM +Vd, it is necessary to ensure that VGS < Vthn, that is: VGS_N1 - Vd < Vthn_N202. When Vthn_N1 = Vthp_N202, that is: Vov_N1 < Vd, it operates in the cut-off region;

[0129] MOS transistors HVN203 and HVN204 at VICM When it is small enough, it works in the saturation region, and its drain potential is the power supply voltage Vdd minus the voltage drops across resistors R3 and R4: VD = Vdd - IR3. The gate potential is obtained from MOS transistor MN1 and MOS transistor HVD101 from V ICM as: VG = V ICM + VSG_N1 + Vd. At the same time, looking from the source side, MOS transistors HVN103, HVN104, and bipolar transistor QN1 that work in the reverse linear region can be seen. The collector of bipolar transistor QN4: VS = V ICM + Vce_N1 = VG - VGS_N203. When VGS_N1 = VGS_N203, the collectors of bipolar transistors QN1 and QN4 are clamped: Vce_N1 = Vd;

[0130] The VDS of MOS transistors HVP201, HVP202, HVP203, HVP204, and HVP205 is responsible for the breakdown voltage withstand, where:

[0131] MOS transistors HVP201 and HVP202 clamp the drain voltages of MOS transistor MP3 in the cascode current source module and MOS transistor MP5 in the cascode tail current source module respectively, and work in the saturation region;

[0132] MOS transistors HVP203 and HVP204 need to work in the cut-off region, and their drain potentials are clamped by diodes D3, D4, bipolar transistor QP1, and the forward-biased collector junctions of bipolar transistor QP4 respectively: VD = V ICM + 2Vd, and the gate potential is pulled to gnd by MOS transistors MN2, MN3, and MOS transistor HVN101 that work in the linear region: VG = 0. Looking from the source side, the series resistance R5 of the forward-biased diodes of MOS transistors HVP103 and HVP104 and resistor R6 to gnd can be seen: VS = IR5 - Vd. It is necessary to ensure that VSG < Vthp, that is, when IR5 < Vthp + Vd, it works in the cut-off region;

[0133] MOS transistor HVP205 clamps the drain voltage of MOS transistor MP6 and works in the saturation region;

[0134] Diodes HVD201, HVD202, and HVD203 are reverse-biased and responsible for negative voltage withstand;

[0135] For operation at an input common-mode voltage within the power supply voltage rail where gnd < V ICM < Vdd:

[0136] In order to meet the minimum operating voltage as low as possible, the MOS tube HVP102 and the MOS tube HVN202 need to be turned on in the reverse linear region when the MOS tube MP5 and the MOS tube MN5 just enter the saturation region.

[0137] Because the structure is symmetrical up and down, the MOS tube HVN202 is used as an example below.

[0138] When the MOS tube MN5 just enters the saturation region, for the MOS tube HVN202:

[0139] VD=VDS_N4+Vdsat_N5

[0140] VS=V ICM -Vd

[0141] VG=V ICM +VGS_N1

[0142] V at this moment ICM satisfy:

[0143] V ICM =VDS_N4+Vdsat_N5+Vd

[0144] Therefore:

[0145] VGS=Vd+VGS_N1>Vthn

[0146] VGD=Vd+VGS_N1>Vthn

[0147] Satisfy the conduction condition in the reverse linear region.

[0148] For the circuit described in this embodiment, in order to ensure both a minimum operating voltage as low as possible and a sufficiently large CMRR, a cascode tail current structure is adopted.

[0149] In addition, it is necessary to ensure that V ICM When the large signal changes to the operating point switching, the two feedback paths are disconnected before the corresponding common-base differential input pairs to avoid the problem of output nonlinearity, that is:

[0150] Vdsat_N6+2Vd>VDS_N4+Vdsat_N5+Vd

[0151] 2Vd-Vdsat_P6>VSD_P4-Vdsat_P5+Vd

[0152] Finally, consider the full V ICMR Internal limit V IDM_MAX The worst case occurs when both feedback paths are disconnected, so the design indicators Vdd and V IDM_MAX The relationship between:

[0153] Vdd=max{[(R9 / R1+R7 / R2)(V IDM_MAX +|Vos|)+Vdsat_N6-Vdsat_P6+4Vd], [H_ideal·(V IDM_MAX +|Vos|)+Vdsat103]}

[0154] Wherein, Vdsat103 is the absolute value of the saturated source-drain voltage drop of the output tube of the VO port of the voltage buffer 103, and Vos is the input offset voltage equivalent to the VIP and VIN ports. For example, let V IDM_MAX is much larger than Vos, it can be further simplified as:

[0155]

[0156] It can be seen that under the low operating voltage rail, the first term in the above formula is very important for determining the design indicator V IDM_MAX The minimum Vdd after 101 plays a major limiting role. If a sufficiently large voltage gain Av_103 of the voltage buffer 103 is selected, the limitation of the previous term can be ignored, but at the cost of a reduced bandwidth or increased power consumption of the voltage buffer 103.

[0157] The above is only a preferred specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A high-side current sensing amplifier, characterized in that: Including input resistance module, common base differential input pair module, V ICM Reference point acquisition module, cascode tail current source module, cascode current source module, high voltage resistance module, positive common mode operational amplifier module, negative common mode operational amplifier module, current mirror module, feedback module and output module; The first input terminal and the second input terminal of the input resistance module are electrically connected to the outside as the same direction input terminal and the reverse direction input terminal; the first input terminal and the second input terminal of the common base differential input pair module are electrically connected to the first output terminal and the second output terminal of the input resistance module respectively; The cascode tail current source module is electrically connected to the power input terminal of the common-base differential input pair module, and the first output terminal and the second output terminal of the common-base differential input pair module are electrically connected to the input terminals of the positive common-mode operational amplifier module and the negative common-mode operational amplifier module respectively; the feedback module is electrically connected between the output terminals of the positive common-mode operational amplifier module and the negative common-mode operational amplifier module, the input resistance module and the common-base differential input pair module; the output terminal of the positive common-mode operational amplifier module is electrically connected to the input terminal of the output module; the output terminal of the negative common-mode operational amplifier module is electrically connected to the input terminal of the current mirror module; the output terminal of the current mirror module is electrically connected to the input terminal of the output module, The V ICM The reference point acquisition module is electrically connected between the first input terminal, the second input terminal, the power input terminal, the first input terminal, the second input terminal and the high-voltage resistant module of the common-base differential input pair module, the output terminal of the cascode current source module is electrically connected to the high-voltage resistant module, and the high-voltage resistant module is electrically connected to the first input terminal, the second input terminal of the common-base differential input pair module, the output terminal of the feedback module, the input terminal of the positive common-mode operational amplifier module and the input terminal of the negative common-mode operational amplifier module.

2. The high-side current sensing amplifier according to claim 1, wherein: The cascode current source module includes a MOS transistor MP2, a MOS transistor MP3, a MOS transistor MN2 and a MOS transistor MN3; The cascode tail current source module includes a MOS tube MP4, a MOS tube MP5, a MOS tube MP9, a MOS tube MN4, a MOS tube MN5 and a MOS tube MN8; The source of the MOS transistor MP2, the drain of the MOS transistor MN8 and the source of the MOS transistor MP4 are all electrically connected to an external power supply, the drain of the MOS transistor MP2 is electrically connected to the source of the MOS transistor MP3, the drain of the MOS transistor MP4 is electrically connected to the source of the MOS transistor MP5; the drain of the MOS transistor MP5 is electrically connected to the source of the MOS transistor MP9; The drain of the MOS tube MP3, the drain of the MOS tube MN3, the drain of the MOS tube MP5 and the drain of the MOS tube MN5 are all electrically connected to the high-voltage resistance module; the source of the MOS tube MN3 is electrically connected to the drain of the MOS tube MN2; the drain of the MOS tube MN5 is also electrically connected to the source of the MOS tube MN8, the source of the MOS tube MN5 is electrically connected to the drain of the MOS tube MN4, the drain of the MOS tube MP9, the source of the MOS tube MN2 and the source of the MOS tube MN4 are all grounded, The gates of the MOS tube MP2, the MOS tube MP3, the MOS tube MN2 and the MOS tube MN3 are electrically connected to the first output terminal of the external bias voltage, the second output terminal of the external bias voltage, the fourth output terminal of the external bias voltage and the third output terminal of the external bias voltage, respectively; the gates of the MOS tube MP4, the MOS tube MP5, the MOS tube MN4 and the MOS tube MN5 are electrically connected to the first output terminal of the external bias voltage, the second output terminal of the external bias voltage, the fourth output terminal of the external bias voltage and the third output terminal of the external bias voltage, respectively; the gates of the MOS tube MP9 and the MOS tube MN8 are electrically connected to the second output terminal of the external bias voltage and the third output terminal of the external bias voltage, respectively.

3. The high-side current sensing amplifier according to claim 2, wherein: The high-voltage resistant module includes MOS tube HVP102, MOS tube HVP103, MOS tube HVP104, MOS tube HVP201, MOS tube HVP202, MOS tube HVP203, MOS tube HVP204, MOS tube HVP205, MOS tube HVN101, MOS tube HVN102, MOS tube HVN103, MOS tube HVN104, MOS tube HVN105, MOS tube HVN202, MOS tube HVN203, MOS tube HVN204 and diodes HVD101, diode HVD102, diode HVD103, diode HVD201, diode HVD202, diode HVD203; The drain of the MOS transistor MP3 is electrically connected to the source of the MOS transistor HVP201, and the drain of the MOS transistor HVP201 is electrically connected to the anode of the diode HVD101, the gate of the MOS transistor HVN203, the gate of the MOS transistor HVN103, the gate of the MOS transistor HVN204, and the gate of the MOS transistor HVN104; The drain of the MOS tube HVN203 and the drain of the MOS tube HVN204 are electrically connected to the input end of the negative common mode operational amplifier module; The source of the MOS transistor HVP202 is electrically connected to the drain of the MOS transistor MP5 and the source of the MOS transistor MP9; the source of the MOS transistor HVN102 is electrically connected to the drain of the MOS transistor MN5 and the source of the MOS transistor MN8; The source of the MOS tube HVN203 is electrically connected to the source of the MOS tube HVN103; the drain of the MOS tube HVP202 is electrically connected to the drain of the MOS tube HVP102; the source of the MOS tube HVN204 is electrically connected to the source of the MOS tube HVN104; The common-base differential input pair module is electrically connected to the cathode of the diode HVD103, the anode of the diode HVD203, the drain of the MOS transistor HVN103, the source of the MOS transistor HVP102, the drain of the MOS transistor HVN104, the drain of the MOS transistor HVP203, the source of the MOS transistor HVN202, and the drain of the MOS transistor HVP204; The cathode of the diode HVD101 is connected to the gate of the MOS tube HVN202 and V ICM The reference point acquisition module is electrically connected; The positive electrode of the diode HVD201 is connected to the gate of the MOS tube HVP102 and V ICM The reference point acquisition module is electrically connected; The cathode of the diode HVD201 is electrically connected to the drain of the MOS tube HVN101, the gate of the MOS tube HVP203, the gate of the MOS tube HVP103, the gate of the MOS tube HVP204 and the gate of the MOS tube HVP104; the gate of the MOS tube HVN101 is electrically connected to the external power supply, and the source of the MOS tube HVN101 is electrically connected to the drain of the MOS tube MN3; the source of the MOS tube HVP203 is electrically connected to the source of the MOS tube HVP103, the drain of the MOS tube HVN202 is electrically connected to the drain of the MOS tube HVN102, and the gate of the MOS tube HVN102 is electrically connected to the external power supply; the source of the MOS tube HVP204 is electrically connected to the source of the MOS tube HVP104, and the drain of the MOS tube HVP104 and the drain of the MOS tube HVP103 are both electrically connected to the input end of the positive common mode operational amplifier module; The anode of the diode HVD103 is electrically connected to the cathode of the diode HVD102, the anode of the diode HVD102 is electrically connected to the drain of the MOS transistor HVP205, the source of the MOS transistor HVP205 is electrically connected to the feedback module, and the gate of the MOS transistor HVP205 is grounded; The cathode of the diode HVD203 is electrically connected to the anode of the diode HVD202, the cathode of the diode HVD202 is electrically connected to the drain of the MOS transistor HVN105, the source of the MOS transistor HVN105 is electrically connected to the feedback module, and the gate of the MOS transistor HVN105 is electrically connected to the external power supply.

4. The high-side current sensing amplifier according to claim 3, characterized in that: The common-base differential input pair module includes transistor QN1, transistor QN2, transistor QN3, transistor QN4, transistor QP1, transistor QP2, transistor QP3 and transistor QP4; The input resistance module includes a resistor R1 and a resistor R2; The V ICM The reference point acquisition module includes a MOS tube MP1, a MOS tube MN1 and a diode D1, a diode D2, a diode D3, and a diode D4; One end of the resistor R1 is electrically connected to the source of the MOS transistor MN1 and the source of the MOS transistor MP1, and is electrically connected to the outside as a non-inverting input end; the drain and gate of the MOS transistor MN1 are electrically connected to the cathode of the diode HVD101 and the gate of the MOS transistor HVN202; the gate and drain of the MOS transistor MP1 are electrically connected to the anode of the diode HVD201 and the gate of the MOS transistor HVP102; The other end of the resistor R1 is electrically connected to the emitter of transistor QN1, the emitter of transistor QP1, the emitter of transistor QN2, the emitter of transistor QP2, the anode of diode D1, the cathode of diode D3 and the anode of diode HVD203; The collector of the transistor QN1 is electrically connected to the drain of the MOS transistor HVN103, and the base of the transistor QN1 is electrically connected to the base, collector, cathode of the diode D1, cathode of the diode D2, base, collector of the transistor QN3, base of the transistor QN4, and source of the MOS transistor HVP102; the collector of the transistor QP1 is electrically connected to the drain of the MOS transistor HVP203, and the base of the transistor QP1 is electrically connected to the base, collector, anode of the diode D3, anode of the diode D4, base, collector of the transistor QP3, base of the transistor QP4, and source of the MOS transistor HVN202; One end of the resistor R2 is electrically connected to the outside as a reverse input end, and the other end of the resistor R2 is electrically connected to the emitter of the transistor QN4, the emitter of the transistor QP4, the emitter of the transistor QN3, the emitter of the transistor QP3, the anode of the diode D2, the cathode of the diode D4 and the cathode of the diode HVD103; the collector of the transistor QN4 is electrically connected to the drain of the MOS transistor HVN104, and the collector of the transistor QP4 is electrically connected to the drain of the MOS transistor HVP204.

5. The high-side current sensing amplifier according to claim 4, characterized in that: The negative common mode operational amplifier module includes a first voltage amplifier 100, a load resistor R3 and a load resistor R4; The positive common mode operational amplifier module includes a third voltage amplifier 102, a load resistor R5 and a load resistor R6; The feedback module includes a MOS transistor MP6, a MOS transistor MN6, a resistor R7 and a resistor R9; One end of the load resistor R3 and the load resistor R4 are both electrically connected to the external power supply, the other end of the load resistor R3 is electrically connected to the reverse input end of the first voltage amplifier 100 and the drain of the MOS tube HVN203, and the other end of the load resistor R4 is electrically connected to the non-inverting input end of the first voltage amplifier 100 and the drain of the MOS tube HVN204; the output end of the first voltage amplifier 100 is electrically connected to the gate of the MOS tube MP6, the source of the MOS tube MP6 is electrically connected to the current mirror module and one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the external power supply; the drain of the MOS tube MP6 is electrically connected to the source of the MOS tube HVP205; One end of the load resistor R5 is electrically connected to the same-direction input end of the third voltage amplifier 102 and the drain of the MOS tube HVP103, one end of the load resistor R6 is electrically connected to the reverse input end of the third voltage amplifier 102 and the drain of the MOS tube HVP104, and the other ends of the load resistor R5 and the load resistor R6 are both grounded; the output end of the third voltage amplifier 102 is electrically connected to the gate of the MOS tube MN6, the source of the MOS tube MN6 is electrically connected to the output module and one end of the resistor R9, and the other end of the resistor R9 is grounded; the drain of the MOS tube MN6 is electrically connected to the source of the MOS tube HVN105.

6. The high-side current sensing amplifier according to claim 5, characterized in that: The current mirror module includes a second voltage amplifier 101, a MOS tube MP7 and a resistor R8; The output module includes a voltage buffer 103; The non-inverting input terminal of the second voltage amplifier 101 is electrically connected to the source of the MOS transistor MP6 and one end of the resistor R7, the inverting input terminal of the second voltage amplifier 101 is electrically connected to one end of the resistor R8 and the source of the MOS transistor MP7, the other end of the resistor R8 is electrically connected to an external power supply, the output terminal of the second voltage amplifier 101 is electrically connected to the gate of the MOS transistor MP7, the drain of the MOS transistor MP7 is electrically connected to the source of the MOS transistor MN6, one end of the resistor R9 and the input terminal of the voltage buffer 103, and the output terminal of the voltage buffer 103 outputs VO.

7. The high-side current sensing amplifier according to claim 3, characterized in that: The MOS tube HVP102, MOS tube HVP103, MOS tube HVP104, MOS tube HVP201, MOS tube HVP202, MOS tube HVP203, MOS tube HVP204 and MOS tube HVP205 are all high-voltage PMOS tubes; The MOS tube HVN101, MOS tube HVN102, MOS tube HVN103, MOS tube HVN104, MOS tube HVN105, MOS tube HVN202, MOS tube HVN203 and MOS tube HVN204 are all high-voltage NMOS tubes; The diode HVD101 , the diode HVD102 , the diode HVD103 , the diode HVD201 , the diode HVD202 and the diode HVD203 are all high voltage diodes.

8. The high-side current sensing amplifier according to claim 3, characterized in that: The following conditions are met: IN HVN103 =In HVN104 L HVN103 =L HVN104 IN HVN203 =In HVN204 L HVN203 =L HVN204 IN HVP103 =In HVP104 L HVP103 =L HVP104 IN HVP203 =In HVP204 L HVP203 =L HVP204 Where W HVN103 is the width of MOS tube HVN103, W HVN104 is the width of MOS tube HVN104, W HVN203 is the width of MOS tube HVN203, W HVN204 is the width of MOS tube HVN204, W HVP103 is the width of MOS tube HVP103, W HVP104 is the width of MOS tube HVP104, W HVP203 is the width of MOS tube HVP203, W HVP204 is the width of MOS tube HVP204; L HVN103 is the length of MOS tube HVN103, L HVN104 is the length of MOS tube HVN104, L HVN203 is the length of MOS tube HVN203, L HVN204 is the length of MOS tube HVN204, L HVP103 is the length of MOS tube HVP103, L HVP104 is the length of MOS tube HVP104, L HVP203 is the length of MOS tube HVP203, L HVP204 It is the length of MOS tube HVP204.

9. The high-side current sensing amplifier according to claim 4, characterized in that: The following conditions are met: YES D1 =YES D2 =YES D3 =YES D4 YES QN1 =EA QN2 =EA QN3 =EA QN4 YES QP1 =EA QP2 =EA QP3 =EA QP4 Among them, DA D1 is the junction area of ​​diode D1, DA D2 is the junction area of ​​diode D2, DA D3 is the junction area of ​​diode D3, DA D4 is the junction area of ​​diode D4; EA QN1 is the emitter junction area of ​​transistor QN1, EA QN2 is the emitter junction area of ​​transistor QN2, EA QN3 is the emitter junction area of ​​transistor QN3, EA QN4 is the emitter junction area of ​​transistor QN4; EA QP1 is the emitter junction area of ​​transistor QP1, EA QP2 is the emitter junction area of ​​transistor QP2, EA QP3 is the emitter junction area of ​​transistor QP3, EA QP4 is the emitter junction area of ​​transistor QP4.

10. The high-side current sensing amplifier according to claim 6, characterized in that: The following conditions are met: R1=R2=R9·Av_103 / H_ideal R3=R4 R5=R6 Wherein, Av_103 is the voltage gain of the voltage buffer 103, and H_ideal is the ideal input differential voltage V of the design indicator. IDM to the DC voltage gain of the output VO.

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