An inertial device data communication system based on FPGA and DSP

Abstract

The utility model proposes an inertial device data communication system based on FPGA and DSP, comprising an FPGA module, a DSP module, a FIFO cache module and an EMIF communication module; the FPGA module is responsible for reading the data of the inertial device in parallel through a serial port, and writing the data into the FIFO cache module of an IP core after completing the reading task, and is also responsible for monitoring the data volume in the FIFO, and when the data volume reaches a preset value, sending an interrupt request to the DSP module; the FIFO cache module adopts a non-read and write address line mode to perform a process of writing and reading data; the DSP module communicates with the FPGA module through the EMIF communication module, and when receiving the interrupt request of the FPGA module, the DSP module starts EMIF transmission, reads the cache data of the target address from the FPGA module, and the DSP module reads the data using an external interrupt mechanism, and performs corresponding processing, and after the processing is completed, transmits the processed data back to the FPGA module through the EMIF bus.

Description

Technical Field

[0001] The utility model relates to the technical field of data communication and signal processing, in particular to an inertial device data communication system based on FPGA (field programmable gate array) and DSP (digital signal processor). Background Art

[0002] Inertial devices, such as gyroscopes and accelerometers, are important measurement components for aircraft and various moving objects. These devices generate a large amount of data that needs to be processed and transmitted efficiently and accurately.

[0003] In modern electronic systems, the communication between FPGA (field programmable gate array) and DSP (digital signal processor) plays a vital role. FPGA is known for its powerful parallel processing capabilities and high customizability, while DSP is known for its excellent digital signal processing capabilities and algorithm execution efficiency. Therefore, the combination of the two can greatly improve the overall performance of the system.

[0004] At present, there are various communication methods between FPGA and DSP, including EMIF, uPP and other communication protocols. These communication methods can indeed meet most application requirements in terms of performance, but there are also some problems that cannot be ignored. Some companies have integrated FPGA and DSP on a core board. Although this has a high degree of integration and simplifies system design to a certain extent, the price of the core board is often expensive and easily constrained by the supplier's technology, which increases the cost of the entire system.

[0005] Therefore, how to reduce the cost of FPGA and DSP communication systems and improve the stability and efficiency of communication while ensuring performance has become an urgent problem to be solved. Utility Model Content

[0006] The utility model proposes an inertial device data communication system based on FPGA and DSP, which uses the EMIF module integrated in the DSP chip to transfer all the data collected by FPGA to the DSP for processing, verifies the feasibility of this method, and saves the cost for the electrical design of the inertial system.

[0007] The utility model is achieved through the following technical solutions.

[0008] An inertial device data communication system based on FPGA and DSP, including an FPGA module, a DSP module, a FIFO cache module, and an EMIF communication module;

[0009] The FPGA module is responsible for reading the data of the inertial device in parallel through the serial port. After completing the reading task, it writes the data into the FIFO cache module of the IP core. It is also responsible for monitoring the amount of data in the FIFO. When the amount of data reaches the preset value, it sends an interrupt request to the DSP module.

[0010] The FIFO buffer module uses a process of writing and reading data without read and write address lines;

[0011] The DSP module communicates with the FPGA module through the EMIF communication module. When receiving an interrupt request from the FPGA module, the DSP module starts EMIF transmission and reads the cache data of the target address from the FPGA module. The DSP module uses the external interrupt mechanism to read the data and performs corresponding processing. After the processing is completed, the processed data is transmitted back to the FPGA module through the EMIF bus.

[0012] After the FPGA module receives the data sent back by the DSP module, it outputs the data to the host computer for display through the network port or other communication interface.

[0013] Beneficial effects of the utility model:

[0014] 1. The utility model makes full use of the versatility and popularity of existing FPGA and DSP, and does not need to use a specially integrated or customized core board. Through universal communication protocols such as EMIF (external memory interface), stable communication between FPGA and DSP can be achieved; this method not only broadens the purchase channels, but also greatly reduces the hardware cost of the system, making the communication system of the utility model more competitive in the market;

[0015] 2. The utility model improves the stability and efficiency of communication by optimizing the communication protocol and hardware design. The EMIF communication protocol is simple and reliable, and can ensure the correct transmission of data between FPGA and DSP. At the same time, the utility model also adopts an efficient data transmission mechanism, such as DMA (direct memory access) technology, which further improves the speed and efficiency of data transmission and meets the real-time requirements of inertial device data communication;

[0016] 3. This utility model focuses on the flexibility and scalability of the system. Due to the use of general FPGA and DSP, users can flexibly configure and expand the functions of the system according to actual needs. Whether it is to increase data processing capabilities or improve communication performance, it can be achieved through simple hardware upgrades and software adjustments, which provides great convenience for system upgrades and maintenance;

[0017] 4. The inertial device data communication system based on FPGA and DSP designed in the utility model has the advantages of low cost and strong flexibility. It is suitable for various scenarios that require efficient processing of inertial device data and has important practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of an inertial device data communication system based on FPGA and DSP in the utility model;

[0019] Figure 2 This is a schematic diagram of FIFO data buffer in the FPGA of the utility model;

[0020] Figure 3 This is the interface connection diagram of DSP and FPGA of the utility model. DETAILED DESCRIPTION

[0021] The exemplary embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the accompanying drawings are merely exemplary and are intended to illustrate the principles and spirit of the present invention, rather than to limit the scope of the present invention.

[0022] like Figure 1 As shown, the utility model is an inertial device data communication system based on FPGA and DSP, including an FPGA module, a DSP module, a FIFO cache module, and an EMIF communication module;

[0023] The FPGA module is responsible for reading the data of the inertial device in parallel through the serial port. After completing the reading task, it writes the data into the FIFO cache module of the IP core. It is also responsible for monitoring the amount of data in the FIFO. When the amount of data reaches the preset value (set to 10 frames in the specific implementation), it sends an interrupt request to the DSP module.

[0024] The FIFO buffer module uses a non-read / write address line method to write and read data; this method does not need to wait for the operation of the read / write address line, thereby greatly improving the data storage efficiency. The principle of data transmission between the serial port and the FIFO is as follows Figure 2 shown.

[0025] The DSP module communicates with the FPGA module through the EMIF communication module. When receiving an interrupt request from the FPGA module, the DSP module starts EMIF transmission and reads the cached data of the target address from the FPGA module. The DSP module uses the external interrupt mechanism to read the data and performs corresponding processing. After the processing is completed, the processed data is transmitted back to the FPGA module through the EMIF bus. In this embodiment, the processing includes filtering, solving, calibration and other operations to ensure the accuracy and validity of the data.

[0026] It can be seen that EMIF, as an asynchronous bus communication method, can efficiently realize data transmission between FPGA and DSP. In addition, as an asynchronous connection device of DSP, FPGA has no clock signal for synchronization. Therefore, the start and end of FPGA are mainly determined by the high and low levels of the signal line CS, and the control signal WE is used as a judgment mark for data reading and writing. Figure 3 shown.

[0027] After receiving the data sent back by the DSP module, the FPGA module outputs the data to the host computer through the network port or other communication interface for display. The user can view and process the data of the inertial device in real time.

[0028] In addition, the system has certain flexibility and scalability. Users can adjust the FIFO size, interrupt threshold, processing algorithm and other parameters according to actual needs to meet different application requirements. At the same time, due to the use of general FPGA and DSP hardware platforms, the system also has high compatibility and portability.

[0029] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

[0030] For those skilled in the art, it is obvious that the embodiments of the present invention are not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic features of the embodiments of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the embodiments of the present invention is limited by the attached claims rather than the above description, so it is intended to include all changes that fall within the meaning and scope of the equivalent elements of the claims in the embodiments of the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is obvious that the word "including" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units, modules or devices stated in the system, device or terminal claims can also be implemented by the same unit, module or device through software or hardware. The words first, second, etc. are used to indicate the name, and do not indicate any specific order.

[0031] Finally, it should be noted that the above implementation modes are only used to illustrate the technical solutions of the embodiments of the utility model and are not limiting. Although the embodiments of the utility model are described in detail with reference to the above preferred implementation modes, ordinary technicians in this field should understand that the technical solutions of the embodiments of the utility model can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the embodiments of the utility model.

Claims

1. An inertial device data communication system based on FPGA and DSP, characterized in that: Including FPGA module, DSP module, FIFO cache module, EMIF communication module; The FPGA module is responsible for reading the data of the inertial device in parallel through the serial port. After completing the reading task, it writes the data into the FIFO cache module of the IP core. It is also responsible for monitoring the amount of data in the FIFO. When the amount of data reaches the preset value, it sends an interrupt request to the DSP module. The FIFO buffer module uses a process of writing and reading data without read and write address lines; The DSP module communicates with the FPGA module through the EMIF communication module. When receiving an interrupt request from the FPGA module, the DSP module starts EMIF transmission and reads the cache data of the target address from the FPGA module. The DSP module uses the external interrupt mechanism to read the data and performs corresponding processing. After the processing is completed, the processed data is transmitted back to the FPGA module through the EMIF bus. After the FPGA module receives the data sent back by the DSP module, it outputs the data to the host computer for display through the network port or other communication interface.

2. The inertial device data communication system based on FPGA and DSP as claimed in claim 1, characterized in that: The preset value of the data amount is 10 frames.

3. An inertial device data communication system based on FPGA and DSP as claimed in claim 1 or 2, characterized in that: The processing includes filtering, solving, and calibration operations.

4. An inertial device data communication system based on FPGA and DSP as claimed in claim 1 or 2, characterized in that: The start and end of the FPGA module are determined according to the high and low levels of the signal line CS, and the control signal WE is used as a determination mark for data reading and writing.

5. The inertial device data communication system based on FPGA and DSP as claimed in claim 1 or 2, characterized in that: Users can adjust the FIFO size, interrupt threshold, and processing algorithm parameters according to actual needs.

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