LED display device array

Abstract

The utility model discloses an LED display device array, which comprises a plurality of display devices with the same structure, each display device comprises an active matrix type driving IC, four chips and a metal conducting layer, the four chips and the active matrix type driving IC are welded on the same side of the metal conducting layer, and a double-layer design is realized without adding guide holes; the four chips are respectively a red light chip, two green light chips and a blue light chip, and the two green light chips are arranged diagonally; in the LED display device array, the distance between every two adjacent chips in the X direction and the Y direction is the preset chip distance. A chip is used as a matrix element, any minimum 2 * 2 matrix forms a display pixel in an LED display device array, pixel multiplexing can reduce the pixel pitch, the LED display device array adopts an active matrix type driving IC, the active matrix type driving IC can change the processing mode, and the manufacturing difficulty and cost of the Mini / Mirco LED can be reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of display devices, in particular to an LED display device array. Background Art

[0002] With the promotion of Mini / Mirco LED, LED display screens have entered the era of micro-pitch. LED micro-pitch display technology is an emerging display technology. It has the characteristics of high definition, high brightness and high contrast, and can present very clear and delicate image effects.

[0003] Since the cost of a passive matrix (PM) driver IC is relatively low and it is easier to implement technically, in traditional technology, a PM driver IC is usually used to manufacture Mini / Mirco LEDs.

[0004] However, as the pixel pitch of Mini / Mirco LEDs becomes smaller, the size of the chips, drivers, substrates and lamp beads of LED displays are getting smaller and smaller, and the difficulty and cost of making PM driver ICs are also getting higher and higher, especially in the stage below P0.7mm (dot pitch 0.7mm), the production and processing difficulty of PM driver ICs and LED display substrates will be higher, which will lead to increased costs. Utility Model Content

[0005] The utility model provides an LED display device array to solve the problems of high difficulty and high cost in manufacturing and processing of Mini / Mirco LEDs with micro spacing.

[0006] The utility model provides an LED display device array, comprising a plurality of display devices of the same structure, each of the display devices comprising an active matrix driver IC, four chips and a metal conductive layer, the four chips and the active matrix driver IC being welded on the same side of the metal conductive layer;

[0007] The four chips are respectively one red light chip, two green light chips and one blue light chip, and the two green light chips are arranged diagonally;

[0008] In the LED display device array, the spacing between adjacent chips in the X direction and the Y direction is a preset chip spacing;

[0009] With the chip as a matrix element, any minimum 2×2 matrix constitutes a display pixel in the LED display device array.

[0010] Optionally, two adjacent display pixels reuse one or two chips.

[0011] Optionally, the active matrix driver IC includes 1 first positive pin, 4 second positive pins, 1 first negative pin, 1 second negative pin and 1 third negative pin, and the active matrix driver IC also includes a CLK pin, a DATA pin, a Col pin and a Row pin;

[0012] The first positive pin, the two second positive pins, the first negative pin and the second negative pin are arranged in a first edge area of ​​the active matrix driver IC;

[0013] The third negative electrode pin and the two second positive electrode pins are arranged in a second edge region of the active matrix driver IC, and the first edge region is parallel to the second edge region;

[0014] The CLK pin, the DATA pin, the Col pin and the Row pin are evenly arranged in a third edge region and a fourth edge region of the active matrix driver IC, and the third edge region is parallel to the fourth edge region.

[0015] Optionally, an electric conductor is provided in the display device, and the wiring mode of the electric conductor is single-layer wiring.

[0016] Optionally, the active matrix driver IC includes 1 first positive pin, 4 second positive pins, 1 first negative pin, 1 second negative pin and 1 third negative pin, and the active matrix driver IC also includes a CLK pin, a DATA pin, a Col pin and a Row pin;

[0017] The first positive pin, the two second positive pins, the first negative pin and the second negative pin are arranged in a first edge area of ​​the active matrix driver IC;

[0018] The third negative electrode pin and the two second positive electrode pins are arranged in a second edge region of the active matrix driver IC, and the first edge region is parallel to the second edge region;

[0019] The CLK pin, the DATA pin, the Col pin and the Row pin are evenly arranged in a third edge region and a fourth edge region of the active matrix driver IC, and the third edge region is parallel to the fourth edge region.

[0020] Optionally, in the display device, the wiring mode of the electrical conductors is single-layer wiring.

[0021] Optionally, in the display device, the metal conductive layer is provided with 4 die-bonding pads, 1 device positive electrode pin, 1 device negative electrode pin, 1 clock CLK signal pin, 1 data DATA signal pin, 1 column address Col signal pin, and 1 row address Row signal pin, and each of the die-bonding pads includes a positive electrode pad and a negative electrode pad;

[0022] The positive pin of the device is connected to the first positive pin through a metal trace; the negative pin of the device is connected to the third negative pin through a metal trace;

[0023] The positive electrode pad of each of the die-bonding pads is connected to one of the second positive electrode pins through a metal trace; the negative electrode pads of two of the die-bonding pads are respectively connected to the first negative electrode pin and the second negative electrode pin through metal traces; the negative electrode pads of the remaining two die-bonding pads are connected to the negative electrode pin of the device through metal traces;

[0024] The clock CLK signal pin, the data DATA signal pin, the column address Col signal pin, and the row address Row signal pin are respectively connected to the CLK pin, the DATA pin, the Col pin, and the Row pin through metal wiring.

[0025] Optionally, the device positive pin and the device negative pin are respectively located on the side where the first edge area is located and the side where the second edge area is located.

[0026] Optionally, in the ath row of the display device, two chips are adjacent to the first edge region, the positive pin of the device is located between the two chips, the negative pins of the two chips are electrically connected to the first negative pin and the second negative pin in the first edge region, respectively, and the positive pins of the two chips are electrically connected to the two second positive pins in the first edge region, respectively;

[0027] In the bth row of the display device, two chips are adjacent to the second edge region, the device cathode pin is located between the two chips, the cathode pins of the two chips are electrically connected to the device cathode pin, and the anode pins of the two chips are electrically connected to the two second anode pins in the second edge region respectively;

[0028] Among them, 1≤a≤2, 1≤b≤2, a and b are both integers and different.

[0029] Optionally, the positive pin and the negative pin of the chip are arranged side by side in the X direction.

[0030] In the ath row of the display device, the positive pins of the two chips are arranged on a side away from the positive pin of the device, and the negative pins of the two chips are arranged on a side close to the positive pin of the device;

[0031] In the bth row of the display device, the positive pins of two chips are arranged on a side close to the negative pins of the device, and the negative pins of two chips are arranged on a side away from the negative pins of the device.

[0032] Optionally, in each of the display devices, an intersection of the center point connecting lines of the four chips coincides with the center point of the active matrix driver IC.

[0033] Optionally, the clock CLK signal pin and the column address Col signal pin are located between two chips in the mth column of the display device; the data DATA signal pin and the row address Row signal pin are located between two chips in the nth column of the display device;

[0034] Among them, 1≤m≤2, 1≤n≤2, m and n are both integers and different.

[0035] Optionally, the first negative electrode pin, the second negative electrode pin and the third negative electrode pin are electrically connected internally.

[0036] The utility model provides an LED display device array, comprising a plurality of display devices of the same structure, each display device comprising an active matrix driver IC, four chips and a metal conductive layer, the four chips and the active matrix driver IC are welded on the same side of the metal conductive layer, no guide hole is added to make a double-layer design, and the manufacturing difficulty and cost of Mini / Mirco LED are reduced; the four chips are respectively one red chip, two green chips and one blue chip, and the two green chips are arranged diagonally; in the LED display device array, the spacing between adjacent chips in the X direction and the Y direction is a preset chip spacing; using the chip as a matrix element, any minimum 2×2 matrix constitutes a display pixel in the LED display device array, then each display pixel can include chips of the three primary colors of red, green and blue, and adjacent display pixels have pixel reuse, and the mixed color of the display pixel is used as the acquisition reference color of the light-emitting point, then the processed light-emitting point is displaced toward the center direction of the virtual pixel (display pixel), so that the point spacing of the processed light-emitting point is smaller than the light-emitting point spacing of the original display device, that is, the pixel spacing is reduced, which is conducive to the realization of Mini / Mirco The production of LEDs reduces the difficulty and cost of Mini / Mirco LED production; and achieves the effect of more light points on the same area, improves the smoothness of the single-primary color image on the display screen and improves the display image effect, and can also save the number of chips, further reducing the production cost of Mini / Mirco LED. In addition, the LED display device array uses an active matrix driver IC, which will change the processing mode and also reduce the difficulty and cost of Mini / Mirco LED production.

[0037] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is a schematic diagram of the structure of an LED display device array provided by an embodiment of the utility model;

[0040] Figure 2 It is a structural schematic diagram of another LED display device array provided by an embodiment of the utility model;

[0041] Figure 3 It is a schematic diagram of a plurality of display pixels in an LED display device array provided by an embodiment of the utility model;

[0042] Figure 4 This is a schematic diagram of the structure of an active matrix driver IC provided by an embodiment of the utility model;

[0043] Figure 5 It is a structural schematic diagram of a display device provided by an embodiment of the utility model.

[0044] The above drawings include the following reference numerals:

[0045] A1, display device; 11, red light chip; 12, green light chip; 13, blue light chip; 40, active matrix driver IC; 41, first positive pin; 42, second positive pin; 43, first negative pin; 44, second negative pin; 45, third negative pin; 46, CLK pin; 47, DATA pin; 48, Col pin; 49, Row pin; 51, metal conductive layer; 52, die bonding pad; 521, positive pad; 522, negative pad; 53, device positive pin; 54, device negative pin; 55, clock CLK signal pin; 56, data DATA signal pin; 57, column address Col signal pin; 58, row address Row signal pin. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0047] Figure 1 A schematic diagram of the structure of an LED display device array provided by an embodiment of the utility model is shown as follows: Figure 1 As shown, the LED display device array includes a plurality of display devices A1 of the same structure. Figure 1 Four display devices are given as examples, each display device A1 includes an active matrix driver IC ( Figure 1 Not shown), 4 chips and a metal conductive layer ( Figure 1 The four chips are respectively one red chip, two green chips and one blue chip, and the two green chips are arranged diagonally. Figure 1 As shown, in the display device A1, in the order from left to right and from top to bottom, the first chip is a red chip 11, the second and third chips are green chips 12, and the fourth chip is a blue chip 13, and the two green chips 12 are arranged diagonally. Optionally, the four chips can be flip chips, and the material of the metal conductive layer is usually copper.

[0048] The utility model adopts an active matrix (AM) driver IC, considering that the PM driver connection is complex, and the parasitic resistance and capacitance are large, resulting in low efficiency, short pixel luminescence time, and thus low effective brightness, easy crosstalk between pixels, and high frequency requirements for scanning signals. When the pixel pitch enters the micro-pitch stage, especially the stage below P0.7mm, the PM driver IC and the substrate of the LED display screen are more difficult to manufacture and process. Therefore, the AM driver IC is adopted, and an independent driving circuit is used to control the LED one-to-one. Each pixel can be driven to emit light continuously and independently, and the manufacturing difficulty and cost of Mini / Mirco LED can also be reduced. In addition, the AM driver IC and the PM driver IC are both semiconductor products. When the size of the AM driver IC is small enough, the cost of the AM driver IC required for the LED display device array will also be low.

[0049] Figure 2 A schematic diagram of the structure of another LED display device array provided by an embodiment of the utility model, such as Figure 2As shown, the LED display device array includes multiple display devices A1 of the same structure. In the display device A1, in order from left to right and from top to bottom, the first chip is a blue light chip 13, the second and third chips are green light chips 12, and the fourth chip is a red light chip 11, wherein two green light chips 12 are diagonally arranged.

[0050] Apart from Figure 1 , Figure 2 The two chip arrangement modes shown in the figure also have two other different chip arrangement modes. In the first arrangement mode, in the display device A1, the first chip and the fourth chip are both set as green light chips 12, and the second chip and the third chip are respectively set as red light chips 11 and blue light chips 13. For example, in the second arrangement mode, in the display device A1, the first chip and the fourth chip are both set as green light chips 12, and the second chip and the third chip are respectively set as blue light chips 13 and red light chips 11. Under the premise that each display device A1 has the same structure, the utility model only limits the diagonal arrangement of two green light chips 12, and does not limit the placement of the red light chip 11 and the blue light chip 13.

[0051] It should be noted that in Figure 1 , Figure 2 In the figure, the range corresponding to the circle in the display device A1 indicates that the chip in the display device A1 can form one display pixel.

[0052] In the display device A1, four chips and an active matrix driver IC are welded on the same side of the metal conductive layer. The electrical conductors inside the display device A1 made with this structure can be a single-layer design, without adding guide holes to make a double-layer design, because the double-layer design is usually more complicated and difficult to make, especially for Mini / Mirco LEDs with fine pitches. Adding guide holes will also occupy space in the metal conductive layer, which is not conducive to the layout of pads, pins, etc., making it more difficult to make. It can be seen that the utility model adopts a single-layer design to reduce the difficulty and cost of making Mini / Mirco LEDs.

[0053] In order to ensure the display effect of pixel multiplexing, it is necessary to ensure that the left-right and top-bottom spacing of the chips in the LED display device array is consistent. Figure 1 In the LED display device array shown, the spacing between adjacent chips in the X direction and the Y direction is the preset chip spacing. Adjacent chips in the X direction are chips adjacent to each other on the left and right, and adjacent chips in the Y direction are chips adjacent to each other on the top and bottom. Moreover, chips located in different displays A1 can also be adjacent chips.

[0054] With the chip as a matrix element, any minimum 2×2 matrix constitutes a display pixel in the LED display device array. For example, the chip is used as a matrix element and numbered, and each chip is numbered as X. RC , R represents the row where the chip is located, C represents the column where the chip is located, then chip X 12 , X 13 , X 22 , X 23 Can form a display pixel, X 13 , X 14 , X 23 , X 24 It can also form a display pixel, and so on.

[0055] It should be noted that the display pixels in the present invention are virtual pixels. Virtual pixel technology is a technology used in LED display screens. It controls the light-emitting chips of each color through software algorithms so that these light-emitting chips participate in the imaging of multiple adjacent pixels. In an embodiment of the present invention, when the display pixel achieves white balance, the brightness of the two green light chips 12 in the display pixel is reduced to half of the maximum brightness. Because when the LED lamp beads achieve white balance, the brightness ratio of the red light, green light, and blue light LED chips is about 3:6:1. At this time, the brightness of the green light chip 12 is the highest, the corresponding current is the highest, and the light efficiency is relatively low. Using two green light chips 12 can reduce the brightness of a single green light chip 12, so that the brightness of the green light chip 12 is reduced to half of the original, which can reduce the current, improve the light efficiency, and the light efficiency improvement is the largest. In addition, the diagonal arrangement can make the green light relatively evenly and dispersedly displayed on the light-emitting surface of the display screen.

[0056] The obtained mixed color of the display pixel is used as the acquisition reference color of the luminous point, and the processed luminous point is offset toward the center direction of the virtual pixel (display pixel). Figure 3 is a schematic diagram of a plurality of display pixels in an LED display device array, such as Figure 3 As shown, the LED display device array includes 4 display devices A1, the chip matrix size is a 4×4 matrix, and any smallest 2×2 matrix constitutes a display pixel in the LED display device array. There are 9 different smallest 2×2 matrices, and there are 9 display pixels. After processing, the centers of display pixels ①, ③, ⑦, and ⑨ are still in the display device A1, while the centers of display pixels ②, ④, ⑤, ⑥, and ⑧ are at the junction of two display devices A1.

[0057] Combination Figure 1 and Figure 3It can be seen that the display pixels corresponding to the original four display devices A1 correspond to display pixels ①, ③, ⑦, and ⑨, and the number of display pixels is 4. Through pixel multiplexing technology, the number of display pixels can be increased within the same unit area without increasing the number of chips, that is, the density of display pixels is increased, the distance between display pixels is reduced, and the pixel resolution is improved. At present, the minimum size of real pixel lamp beads is 0404, that is, 0.4*0.4mm, and the applicable dot pitch LED display screen is P0.6mm or above. The solution of the utility model proposes that the lamp beads can achieve a minimum dot pitch of 0.31mm for the LED display screen. It can be seen that the solution of the utility model is conducive to the production of Mini / Mirco LED, reducing the difficulty and cost of Mini / Mirco LED production; and, on the same area, the effect of more light-emitting points is achieved, the smoothness of the single-primary color image of the display screen is improved, and the display image effect is improved. It can also save the number of chips and further reduce the production cost of Mini / MircoLED.

[0058] Optionally, two adjacent display pixels reuse one or two chips, such as Figure 3 As shown, display pixel ① is adjacent to display pixels ②, ④, and ⑤ and there is pixel multiplexing. Display pixel ① and display pixels ② and ④ multiplex two chips, and display pixel ① and display pixel ⑤ multiplex one chip.

[0059] Optional, such as Figure 4 As shown, Figure 4 Schematic diagram of the structure of an active matrix driver IC, the active matrix driver IC 40 includes a first positive pin 41, four second positive pins 42, a first negative pin 43, a second negative pin 44 and a third negative pin 45, the active matrix driver IC 40 also includes a CLK pin 46, a DATA pin 47, a Col pin 48 and a Row pin 49, the first positive pin 41, the two second positive pins 42, the first negative pin 43 and the second negative pin 44 are arranged in a first edge area of ​​the active matrix driver IC 40;

[0060] The third negative electrode pin 45 and the two second positive electrode pins 42 are arranged in the second edge region of the active matrix driver IC 40, and the first edge region is parallel to the second edge region;

[0061] The CLK pin 46, the DATA pin 47, the Col pin 48 and the Row pin 49 are evenly arranged in the third edge region and the fourth edge region of the active matrix driver IC 40, and the third edge region is parallel to the fourth edge region. The "evenly arranged" here means that the four pins are evenly distributed in the third edge region and the fourth edge region, that is, two pins are distributed in each of the third edge region and the fourth edge region.

[0062] Among them, the CLK pin 46 is the clock input / output terminal, which is used for reading and writing time; the DATA pin 47 is the communication interaction interface, the Col pin 48 is used to output the column address signal, and the Row pin 49 is used to output the row address signal. The column address signal and the row address signal are the address selection signals of the chip.

[0063] It can be seen that the first edge region, the second edge region, the third edge region and the fourth edge region are respectively four edge regions where pins are set in the active matrix driver IC 40. The first edge region is the upper region and the third edge region is the left region, then the second edge region is the lower region and the fourth edge region is the right region. From the above pin distribution, the number of pins arranged in the first edge region and the second edge region is relatively large. Therefore, the first edge region and the second edge region usually correspond to the long side region in the active matrix driver IC 40, and the third edge region and the fourth edge region usually correspond to the short side region in the active matrix driver IC 40. Since there are overlapping parts between adjacent edge regions, the specific range of each edge region can be adjusted according to the actual needs when arranging the pins.

[0064] exist Figure 4 In the embodiment, the DATA pin 47 and the Row pin 49 are arranged at the third edge region of the active matrix driver IC 40, and the CLK pin 46 and the Col pin 48 are arranged at the fourth edge region of the active matrix driver IC 40. However, it should be noted that Figure 4 The arrangement of the CLK pin 46, DATA pin 47, Col pin 48 and Row pin 49 shown is only an example, and the positions of these four pins are interchangeable. For example, the DATA pin 47 and Col pin 48 can be arranged in the third edge area of ​​the active matrix driver IC 40, and the CLK pin 46 and Row pin 49 can be arranged in the fourth edge area of ​​the active matrix driver IC 40. The DATA pin 47 and Row pin 49 can also be arranged in the fourth edge area of ​​the active matrix driver IC 40, and the CLK pin 46 and Col pin 48 can be arranged in the third edge area of ​​the active matrix driver IC 40, and so on. The arrangement of the CLK pin 46, DATA pin 47, Col pin 48 and Row pin 49 can be set according to the layout of the corresponding pins in the display device and based on the principle of saving wiring.

[0065] Optionally, the first negative electrode pin 43 , the second negative electrode pin 44 and the third negative electrode pin 45 are electrically connected internally.

[0066] Optionally, the display device is provided with electric conductors, and the wiring method of the electric conductors is single-layer wiring. The four chips and the active matrix driver IC 40 are welded on the same side of the metal conductive layer. Under the condition of reasonable layout of the chips, pins and the active matrix driver IC 40, the wiring method of single-layer wiring is feasible. The advantage of single-layer wiring is that there is no need to add guide holes to make a double-layer design. Therefore, the utility model adopts a single-layer wiring wiring method to set the electric conductors. The manufacturing difficulty of the single-layer design is lower than that of the double-layer design, which can reduce the manufacturing difficulty of Mini / Mirco LED.

[0067] Optional, such as Figure 5 As shown, Figure 5 It is a structural schematic diagram of a display device. In the display device A1, four die-bonding pads 52, one device positive pin 53, one device negative pin 54, one clock CLK signal pin 55, one data DATA signal pin 56, one column address Col signal pin 57, and one row address Row signal pin 58 are arranged on the metal conductive layer 51. Each die-bonding pad 52 includes a positive pad 521 and a negative pad 522.

[0068] The pins and pads on the metal conductive layer 51 are electrically connected to the corresponding pins in the active matrix driver IC 40 through metal traces. Figure 5 In the active matrix driver IC 40, the pin arrangement is similar to Figure 4 The specific connection method is that the device positive pin 53 is connected to the first positive pin 41 through a metal trace; the device negative pin 54 is connected to the third negative pin 45 through a metal trace; the positive pad 521 in each die-bonding pad 52 is connected to a second positive pin 42 through a metal trace; the negative pads 522 of the two die-bonding pads 52 are respectively connected to the first negative pin 43 and the second negative pin 44 through metal traces; the negative pads 522 of the remaining two die-bonding pads 52 are connected to the device negative pin 54 through metal traces; it can be seen that the two negative pads 522 connected to the device negative pin 54 are ultimately electrically connected to the third negative pin 45. In addition, the clock CLK signal pin 55, the data DATA signal pin 56, the column address Col signal pin 57, and the row address Row signal pin 58 are respectively connected to the CLK pin 46, the DATA pin 47, the Col pin 48, and the Row pin 49 through metal traces.

[0069] like Figure 5As shown, after the metal routing is set according to the above connection relationship, the die-bonding pad 52, the pins of the display device A1 and the active matrix driver IC 40 are still on the same surface of the metal conductive layer 51, wherein the four die-bonding pads 52 are used to fix the four chips in the display device A1, and each chip is fixed in a die-bonding pad 52. When the chip is fixed on the die-bonding pad 52, the positive pin of the chip is connected to the positive pad 521, and the negative pin of the chip is connected to the negative pad 522, so that the chip can be effectively connected to the active matrix driver IC 40, and there is no need to set vias on the metal conductive layer 51, thereby realizing a single-layer design.

[0070] The logic pin is a pin corresponding to the logic control function. In this embodiment, the logic pin includes 1 device positive pin 53, 1 device negative pin 54, 1 clock CLK signal pin 55, 1 data DATA signal pin 56, 1 column address Col signal pin 57, 1 row address Row signal pin 58, and also includes 4 second positive pins 42 (each chip performs logic control separately), so there are 10 logic pins in total. Generally speaking, the number of pads / pins in the active matrix driver IC 40 corresponds to the number of logic pins. However, in this embodiment, 12 logic pins are set in the active matrix driver IC 40. Compared with the conventional design, 2 VDD pins are added, namely the first negative pin 43 and the second negative pin 44. By adding these two pins, the metal routing distance can be reduced and the difficulty of routing operation can be reduced. There is no need to add guide holes to make a double-layer design, which can avoid the crossing of metal routing, and further ensure the feasibility of realizing the display device A1 of a single-layer design.

[0071] Optional, in Figure 5 In the active matrix driver IC 40, the pin arrangement is similar to Figure 4 Consistent, such as Figure 5 As shown, the device positive pin 53 and the device negative pin 54 are respectively located on the side where the first edge area is located and the side where the second edge area is located.

[0072] Optionally, in the ath row of the display device, two chips are adjacent to the first edge region, the device positive pin 53 is located between the two chips, the negative pins of the two chips are electrically connected to the first negative pin 43 and the second negative pin 44 in the first edge region, respectively, and the positive pins of the two chips are electrically connected to the two second positive pins 42 in the first edge region, respectively;

[0073] In the bth row of the display device, two chips are adjacent to the second edge region, the device cathode pin 54 is located between the two chips, the cathode pins of the two chips are electrically connected to the device cathode pin 54, and the anode pins of the two chips are electrically connected to the two second anode pins 42 in the second edge region respectively;

[0074] Wherein, 1≤a≤2, 1≤b≤2, a and b are both integers and are different, that is, when a=1, b=2, and when a=2, b=1.

[0075] In the display device A1 , the arrangement of the active matrix driver IC 40 may be different, so that the first edge region and the second edge region are at different positions. Then, the arrangement and connection of the chips of the display device A1 are adapted to the arrangement of the active matrix driver IC 40 .

[0076] The first arrangement can be as follows Figure 5 As shown, the first edge area is the upper area in the active matrix driver IC 40, and the second edge area is the lower area in the active matrix driver IC 40; then in the first row of the display device A1, two chips are adjacent to the first edge area, the device positive pin 53 is located between the two chips, the negative pins of the two chips are electrically connected to the first negative pin 43 and the second negative pin 44 in the first edge area, respectively, and the positive pins of the two chips are electrically connected to the two second positive pins 42 in the first edge area, respectively; in the second row of the display device A1, two chips are adjacent to the second edge area, the device negative pin 54 is located between the two chips, the negative pins of the two chips are electrically connected to the device negative pin 54, and the positive pins of the two chips are electrically connected to the two second positive pins 42 in the second edge area, respectively.

[0077] In the second arrangement, the second edge region is the upper region of the active matrix driver IC 40, and the first edge region is the lower region of the active matrix driver IC 40. In this case, the arrangement of the active matrix driver IC 40 in the display device A1 is the same as that in FIG. Figure 5 On the contrary; in the second row of display device A1, two chips are adjacent to the first edge area, the device positive pin 53 is located between the two chips, the negative pins of the two chips are electrically connected to the first negative pin 43 and the second negative pin 44 in the first edge area, respectively, and the positive pins of the two chips are electrically connected to the two second positive pins 42 in the first edge area, respectively; in the first row of display device A1, two chips are adjacent to the second edge area, the device negative pin 54 is located between the two chips, the negative pins of the two chips are electrically connected to the device negative pin 54, and the positive pins of the two chips are electrically connected to the two second positive pins 42 in the second edge area, respectively.

[0078] Optionally, the positive pins and negative pins of the chip are arranged side by side in the X direction. When the chip is die-bonded in the display device A1, in the ath row of the display device A1, the positive pins of the two chips are arranged on the side away from the positive pin 53 of the device, and the negative pins of the two chips are arranged on the side close to the positive pin 53 of the device; in the bth row of the display device, the positive pins of the two chips are arranged on the side close to the negative pin 54 of the device, and the negative pins of the two chips are arranged on the side away from the negative pin 54 of the device.

[0079] It can be seen that the arrangement of the positive and negative pins of the chip is compatible with the arrangement of the device positive pin 53 , the device negative pin 54 and the pins in the active matrix driver IC 40 .

[0080] Optionally, in each display device, the intersection of the center point connection lines of the four chips coincides with the center point of the active matrix driver IC 40. The distances from the active matrix driver IC 40 to the center points of the various chips can be made equal, and the routing distances from the active matrix driver IC 40 to the various chips are equal or similar, so that the chips and the active matrix driver IC 40 are neatly arranged in the display device.

[0081] Optionally, the clock CLK signal pin 55 and the column address Col signal pin 57 are located between the two chips in the mth column of the display device A1; the data DATA signal pin 56 and the row address Row signal pin 58 are located between the two chips in the nth column of the display device A1;

[0082] Wherein, 1≤m≤2, 1≤n≤2, m and n are both integers and are different. That is, when m=1, n=2, and when m=2, n=1.

[0083] In addition, in the display device A1, the arrangement of the clock CLK signal pin 55, the data DATA signal pin 56, the column address Col signal pin 57 and the row address Row signal pin 58 may also be different, and the arrangement of these pins can be designed separately from the arrangement of other pins such as the device positive pin 53, the device negative pin 54, etc.

[0084] The clock CLK signal pin 55, the data DATA signal pin 56, the column address Col signal pin 57 and the row address Row signal pin 58 are arranged as follows:

[0085] The first arrangement, such as Figure 5 As shown, Figure 5 The pin arrangement of the active matrix driver IC 40 is similar to Figure 4Assuming that a chip is fixed on the die bonding pad 52, the clock CLK signal pin 55 and the column address Col signal pin 57 are located between the two chips in the second column of the display device A1; the data DATA signal pin 56 and the row address Row signal pin 58 are located between the two chips in the first column of the display device A1;

[0086] In the second arrangement, the clock CLK signal pin 55 and the column address Col signal pin 57 are located between the two chips in the first column of the display device A1; the data DATA signal pin 56 and the row address Row signal pin 58 are located between the two chips in the second column of the display device A1.

[0087] It can be seen that in this embodiment, the arrangement of the pins in the display device A1 can be varied, but it should be noted that the arrangement of the pins in the display device A1 is compatible with the arrangement of the active matrix driver IC 40 .

[0088] Optionally, the positive pins and negative pins of the chip are arranged side by side in the X direction. In the i-th row of the display device A1, the positive pins of the two chips are arranged on the side away from the positive pin 53 of the device, and the negative pins of the two chips are arranged on the side close to the positive pin 53 of the device; in the j-th row of the display device A1, the positive pins of the two chips are arranged on the side close to the negative pin 54 of the device, and the negative pins of the two chips are arranged on the side away from the negative pin 54 of the device.

[0089] There are two situations for chip arrangement:

[0090] The first one, such as Figure 5 As shown, in the first row of display device A1, the positive pins of the two chips are arranged on the side away from the positive pin 53 of the device, and the negative pins of the two chips are arranged on the side close to the positive pin 53 of the device; in the second row of display device A1, the positive pins of the two chips are arranged on the side close to the negative pin 54 of the device, and the negative pins of the two chips are arranged on the side away from the negative pin 54 of the device.

[0091] The second type is that in the second row of the display device A1, the positive pins of the two chips are set on the side away from the positive pin 53 of the device, and the negative pins of the two chips are set on the side close to the positive pin 53 of the device; in the first row of the display device A1, the positive pins of the two chips are set on the side close to the negative pin 54 of the device, and the negative pins of the two chips are set on the side away from the negative pin 54 of the device.

[0092] The utility model provides display devices A1 with a variety of different arrangement modes, which can be applicable to the needs of different LED display device arrays, making the preparation of micro-pitch Mini / Mirco LED feasible.

[0093] For example, the pad size of the AM driver IC is 20um, the pad spacing is 20um (the chip spacing is usually smaller than the pad spacing), the AM driver IC size is 100um*180um, and the flip-chip 0103 LED chip, the chip size is 25um*75um, can be made into a P0.39mm LED display device A1, the corresponding structure can refer to Figure 5 .

[0094] In the description of this article, it is necessary to understand that the terms "up", "down", "left", "right", etc., and the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of description and simplification of operation, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0095] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0096] In the description of this specification, reference to the terms "embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An LED display device array, characterized in that: A plurality of display devices of the same structure are included, each of the display devices includes an active matrix driver IC, four chips and a metal conductive layer, and the four chips and the active matrix driver IC are welded on the same side of the metal conductive layer; The four chips are respectively one red light chip, two green light chips and one blue light chip, and the two green light chips are arranged diagonally; In the LED display device array, the spacing between adjacent chips in the X direction and the Y direction is a preset chip spacing; With the chip as a matrix element, any minimum 2×2 matrix constitutes a display pixel in the LED display device array.

2. The LED display device array according to claim 1, characterized in that: Two adjacent display pixels reuse one or two chips.

3. The LED display device array according to any one of claims 1 to 2, characterized in that: The active matrix driver IC includes 1 first positive pin, 4 second positive pins, 1 first negative pin, 1 second negative pin and 1 third negative pin, and the active matrix driver IC also includes CLK pin, DATA pin, Col pin and Row pin; The first positive pin, the two second positive pins, the first negative pin and the second negative pin are arranged in a first edge area of ​​the active matrix driver IC; The third negative electrode pin and the two second positive electrode pins are arranged in a second edge region of the active matrix driver IC, and the first edge region is parallel to the second edge region; The CLK pin, the DATA pin, the Col pin and the Row pin are evenly arranged in a third edge region and a fourth edge region of the active matrix driver IC, and the third edge region is parallel to the fourth edge region.

4. The LED display device array according to claim 3, characterized in that: The display device is provided with electric wires, and the wiring mode of the electric wires is single-layer wiring.

5. The LED display device array according to claim 4, characterized in that: In the display device, the metal conductive layer is provided with 4 die-bonding pads, 1 device positive electrode pin, 1 device negative electrode pin, 1 clock CLK signal pin, 1 data DATA signal pin, 1 column address Col signal pin, and 1 row address Row signal pin, and each of the die-bonding pads includes a positive electrode pad and a negative electrode pad; The positive pin of the device is connected to the first positive pin through a metal trace; the negative pin of the device is connected to the third negative pin through a metal trace; The positive electrode pad of each of the die-bonding pads is connected to one of the second positive electrode pins through a metal trace; the negative electrode pads of two of the die-bonding pads are respectively connected to the first negative electrode pin and the second negative electrode pin through metal traces; the negative electrode pads of the remaining two die-bonding pads are connected to the negative electrode pin of the device through metal traces; The clock CLK signal pin, the data DATA signal pin, the column address Col signal pin, and the row address Row signal pin are respectively connected to the CLK pin, the DATA pin, the Col pin, and the Row pin through metal wiring.

6. The LED display device array according to claim 5, characterized in that: The device positive pin and the device negative pin are respectively located on the side where the first edge area is located and the side where the second edge area is located.

7. The LED display device array according to claim 5, characterized in that: In the ath row of the display device, two chips are adjacent to the first edge region, the positive pin of the device is located between the two chips, the negative pins of the two chips are electrically connected to the first negative pin and the second negative pin in the first edge region, respectively, and the positive pins of the two chips are electrically connected to the two second positive pins in the first edge region, respectively; In the bth row of the display device, two chips are adjacent to the second edge region, the device cathode pin is located between the two chips, the cathode pins of the two chips are electrically connected to the device cathode pin, and the anode pins of the two chips are electrically connected to the two second anode pins in the second edge region respectively; Among them, 1≤a≤2, 1≤b≤2, a and b are both integers and different.

8. The LED display device array according to claim 7, characterized in that: The positive and negative pins of the chip are arranged side by side in the X direction. In the ath row of the display device, the positive pins of the two chips are arranged on a side away from the positive pin of the device, and the negative pins of the two chips are arranged on a side close to the positive pin of the device; In the bth row of the display device, the positive pins of two chips are arranged on a side close to the negative pins of the device, and the negative pins of two chips are arranged on a side away from the negative pins of the device.

9. The LED display device array according to claim 7, characterized in that: In each of the display devices, the intersection of the center point connecting lines of the four chips coincides with the center point of the active matrix driver IC.

10. The LED display device array according to claim 5, characterized in that: The clock CLK signal pin and the column address Col signal pin are located between the two chips in the mth column of the display device; the data DATA signal pin and the row address Row signal pin are located between the two chips in the nth column of the display device; Among them, 1≤m≤2, 1≤n≤2, m and n are both integers and different.

11. The LED display device array according to claim 3, characterized in that: The first negative electrode pin, the second negative electrode pin and the third negative electrode pin are electrically connected internally.

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