Test fixture for layered test of high-frequency performance of radio frequency chip

Abstract

The utility model provides a clamp for testing the high-frequency performance of a radio frequency chip in a layered manner, which comprises a supporting mechanism, the top of the supporting mechanism is fixedly connected with a testing seat mechanism, the top of the testing seat mechanism is rotatably connected with a cover body mechanism, and a testing mechanism is arranged between the testing seat mechanism and the cover body mechanism. The multi-layer stacked digital and radio frequency chip testing device can test multi-layer stacked digital and radio frequency chips through the testing seat mechanism, the cover body mechanism and the testing mechanism, solves the problem of testing of multi-layer stacked digital and radio frequency chip products within 67 GHz, provides guarantee for production and testing of the multi-layer stacked chips, enables the testing precision to be higher and more accurate, is high in testing efficiency, and improves the testing efficiency of the multi-layer stacked digital and radio frequency chips. During operation, multiple layers of chips can be tested only by respectively placing the chips in the test fixture, a product can be taken down after the test is completed, a certain layer can be independently replaced for re-testing aiming at a bad layer, a fault layer can be conveniently positioned, the test cost is relatively low, the chips do not need to be welded, the test process is simplified, and manpower and material resources are saved.

Description

Technical Field

[0001] The utility model relates to a test fixture, in particular to a test fixture for layered testing of high-frequency performance of radio frequency chips, belonging to the technical field of chip test fixtures. Background Art

[0002] With the development of highly integrated technology and the strict requirements of aerospace equipment on volume and weight, RF highly integrated circuits are widely used because of their small size and light weight. The original modular RF transceiver components or RF devices such as multi-channel amplifiers and phase shifters, and the digital-to-analog conversion parts are packaged into RF chips through semiconductor processes. Due to the large number of chip functions, a single-layer layout can no longer meet the requirements. Under this premise, multi-layer stacked chips are born. Multi-layer stacked chips have very obvious advantages in terms of volume and cost of use, greatly reducing the volume and weight of the entire device, while reducing the power consumption of the entire device. The reliability is also higher, reducing many process assembly steps, and is the current mainstream development of RF components. It also brings the following problems:

[0003] 1. The testing process of multi-layer stacked chips is complicated and the trial and error cost is high;

[0004] 2. Testing a single layer alone cannot complete the test of the complete function, and the test environment will cause test errors, and the overall performance after final assembly cannot be guaranteed;

[0005] 3. The stacking welding test method has high requirements on welding technology and the welding process is also complicated. When the whole chip is abnormal during the test after welding, it is impossible to determine which layer of chip causes the abnormality, and it is also impossible to determine whether it is caused by poor welding, resulting in the inability to locate the fault;

[0006] 4. After the chip test is abnormal, the chip after welding is repeatedly disassembled and assembled, which wastes a lot of manpower and material resources, and the disassembly process may damage the chip;

[0007] 5. The industry limits the number of re-welding times for chips to three times. If it exceeds three times, the chip is not allowed to be shipped and will be scrapped. The high production cost restricts the mass production of this type of chip.

[0008] Therefore, a hierarchical test fixture for high-frequency performance of RF chips is proposed. Utility Model Content

[0009] In view of this, the utility model provides a hierarchical test fixture for testing the high-frequency performance of radio frequency chips to solve or alleviate the technical problems existing in the prior art and at least provide a beneficial choice.

[0010] The technical solution of the embodiment of the utility model is implemented as follows: a hierarchical test fixture for high-frequency performance of radio frequency chips, comprising a support mechanism, a test seat mechanism is fixedly connected to the top of the support mechanism, a cover mechanism is rotatably connected to the top of the test seat mechanism, a test mechanism is arranged between the test seat mechanism and the cover mechanism, and the test mechanism comprises a test PCB board, a first conductive diaphragm, a first limit frame, a first test chip, a second limit frame, a second conductive diaphragm and a second test chip;

[0011] A first conductive diaphragm is fixedly connected to the top of the test PCB board, a first limit frame is fixedly connected to the top of the first conductive diaphragm, a first test chip is installed inside the first limit frame, a plurality of second limit frames are sequentially arranged on the top of the first limit frame from bottom to top, a second conductive diaphragm is fixedly connected to the inner side wall of the second limit frame, a second test chip is installed on the top of the second conductive diaphragm, the second test chip is installed inside the second limit frame, limit pins and pin holes are relatively arranged on the first limit frame and the plurality of second limit frames, a fixing plate is fixedly connected to the bottom of the second limit frame by bolts, and the second conductive diaphragm is arranged between the fixing plate and the second limit frame.

[0012] Further preferably: the support mechanism comprises a bottom plate, legs and a base assembly;

[0013] The bottom of the base plate is symmetrically and fixedly connected with supporting feet, and the top of the base plate is fixedly connected with a base assembly, and the base assembly includes a first base and a second base.

[0014] Further preferably: the support mechanism further comprises a radio frequency connector, a radio frequency cable and a crimping sleeve;

[0015] A plurality of radio frequency connectors are installed on both sides of the first base, a radio frequency cable is installed on one side of the radio frequency connector, and a crimping sleeve is fixedly connected to one end of the radio frequency cable.

[0016] Further preferably: a test seat mechanism is provided on the top of the base assembly, and the test seat mechanism comprises a first test seat, a second test seat and a common ground connection block;

[0017] The inner side wall of the first test seat is fixedly connected with a common ground connection block, and the crimping sleeve is installed inside the common ground connection block.

[0018] Further preferably, the cover mechanism comprises a first cover assembly and a second cover assembly, wherein the first cover assembly comprises a first cover plate, a knob, a first lock and a pressure block;

[0019] The top of the first cover plate is threadedly connected with a knob, the front surface of the first cover plate is installed with a first lock buckle, and the inner side wall of the first cover plate is slidably connected with a pressing block.

[0020] Further preferably, the first cover plate is rotatably connected to the top of the first test seat.

[0021] Further preferably: the second cover assembly includes a second cover plate, a second lock and a signal connector;

[0022] A second lock buckle is installed on the front surface of the second cover plate, and a plurality of signal connectors are installed on the inner side wall of the second cover plate.

[0023] Further preferably, the second cover plate is rotatably connected to the top of the second test seat.

[0024] The embodiment of the utility model has the following advantages due to the adoption of the above technical solution:

[0025] 1. The utility model can test multi-layer stacked digital and radio frequency chips through the test seat mechanism, the cover mechanism and the test mechanism, solves the problem of testing multi-layer stacked digital and radio frequency chip products within 67GHz, provides guarantee for the production test of multi-layer stacked chips, and makes the test accuracy higher and more accurate;

[0026] 2. The utility model has high testing efficiency. During operation, it is only necessary to place the multi-layer chips into the test fixture for testing. After the test is completed, the product can be removed. For defects, a certain layer can be replaced and retested, which is convenient for locating the faulty layer;

[0027] 3. The testing cost is low, and the testing can be realized without welding the chip, which simplifies the testing process and saves manpower and material resources;

[0028] 4. Easy to use, no special debugging required, reducing the labor intensity and skill requirements of the staff, and only needs to complete the chip placement operation;

[0029] 5. The testing process is relatively simple, which reduces the difficulty of automated testing and lays the foundation for automated production.

[0030] The above summary is for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the utility model will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a structural diagram of the utility model;

[0033] Figure 2 This is the internal structure diagram of the first test socket of the utility model;

[0034] Figure 3 This is a structural diagram of the testing mechanism of the utility model;

[0035] Figure 4 This is a structural diagram of the second test socket of the utility model;

[0036] Figure 5 This is a structural diagram of the utility model after the second cover plate is removed;

[0037] Figure 6 This is a structural diagram of the first test socket of the utility model;

[0038] Figure 7 This is a structural diagram of the second limiting frame of the utility model.

[0039] 1. The PCB board is provided with a plurality of support members, each of which is provided with a plurality of support members. The support members are provided with a plurality of support members, each of which is provided with a plurality of support members. The support members are provided with a plurality of support members, each of which is provided with a plurality of support members. DETAILED DESCRIPTION

[0040] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0041] The embodiments of the present utility model are described in detail below with reference to the accompanying drawings.

[0042] Embodiment 1

[0043] like Figure 1-Figure 3 As shown, the embodiment of the utility model provides a hierarchical test RF chip high-frequency performance test fixture, including a support mechanism 10, characterized in that: a test seat mechanism 20 is fixedly connected to the top of the support mechanism 10, a cover mechanism 30 is rotatably connected to the top of the test seat mechanism 20, a test mechanism 40 is arranged between the test seat mechanism 20 and the cover mechanism 30, and the test mechanism 40 includes a test PCB board 41, a first conductive diaphragm 42, a first limit frame 43, a first test chip 44, a second limit frame 45, a second conductive diaphragm 46, a second test chip 47 and a fixed plate 48;

[0044] A first conductive diaphragm 42 is fixedly connected to the top of the test PCB board 41, a first limit frame 43 is fixedly connected to the top of the first conductive diaphragm 42, a first test chip 44 is installed inside the first limit frame 43, a plurality of second limit frames 45 are sequentially arranged on the top of the first limit frame 43 from bottom to top, a second conductive diaphragm 46 is fixedly connected to the inner side wall of the second limit frame 45, a second test chip 47 is installed on the top of the second conductive diaphragm 46, and the second test chip 47 is installed inside the second limit frame 45. Limiting pins and pin holes are relatively arranged on the first limit frame 43 and the plurality of second limit frames 45. The number of the second limit frames 45, the second conductive diaphragm 46 and the second test chips 47 can be adjusted according to the number of chip stacking layers during the test process, and a fixing plate 48 is fixedly connected to the bottom of the second limit frame 45 by bolts, and the second conductive diaphragm 46 is arranged between the fixing plate 48 and the second limit frame 45.

[0045] In this embodiment, specifically: the support mechanism 10 includes a base plate 11, a support leg 12 and a base assembly 13;

[0046] The bottom of the bottom plate 11 is symmetrically fixedly connected with the supporting legs 12 , and the top of the bottom plate 11 is fixedly connected with the base assembly 13 , which includes a first base 131 .

[0047] In this embodiment, specifically: the support mechanism 10 further includes a radio frequency connector 14, a radio frequency cable 15 and a crimping sleeve 16;

[0048] A plurality of RF connectors 14 are installed on both sides of the first base 131 , a RF cable 15 is installed on one side of the RF connector 14 , and a crimping sleeve 16 is fixedly connected to one end of the RF cable 15 .

[0049] In this embodiment, specifically: a test seat mechanism 20 is disposed on the top of the base assembly 13, and the test seat mechanism 20 includes a first test seat 21 and a common ground connection block 23;

[0050] The inner side wall of the first test seat 21 is fixedly connected with a common ground connection block 23, and the crimping sleeve 16 is installed inside the common ground connection block 23. The shape and size of the test seat mechanism 20 and the cover plate can be adjusted according to actual test requirements.

[0051] In this embodiment, specifically: the cover mechanism 30 includes a first cover assembly 31 and a second cover assembly 32, the first cover assembly 31 includes a first cover plate 311, a knob 312, a first lock buckle 313 and a pressing block 314;

[0052] The top of the first cover plate 311 is threadedly connected with a knob 312 , the front surface of the first cover plate 311 is installed with a first lock buckle 313 , and the inner side wall of the first cover plate 311 is slidably connected with a pressing block 314 .

[0053] In this embodiment, specifically: the first cover plate 311 is rotatably connected to the top of the first test seat 21 .

[0054] When the utility model is in operation: the first test chip 44 is installed inside the first limit frame 43, on the top of the first conductive diaphragm 42; the second test chip 47 is installed inside the second limit frame 45, on the top of the second conductive diaphragm 46; the positioning pins and pin holes on the limit frame are used to vertically arrange multiple second limit frames 45 in sequence and place them on the top of the first limit frame 43; the first cover 311 is closed; the first cover 311 and the first test seat 21 are connected by the first lock 313; the knob 312 is turned to make the pressure block 314 press the multi-layer test chips and the conductive diaphragm; the test PCB board 41 is connected to the test equipment through the RF connector 14 and the RF cable 15 for testing.

[0055] Embodiment 2

[0056] like Figure 3-Figure 5 As shown, the embodiment of the utility model provides a hierarchical test fixture for high-frequency performance of radio frequency chips, including a base assembly 13, a test seat mechanism 20, a cover mechanism 30 and a test mechanism 40, wherein the test mechanism 40 includes a test PCB board 41, a first conductive film 42, a first limit frame 43, a first test chip 44, a second limit frame 45, a second conductive film 46, a second test chip 47 and a fixing plate 48;

[0057] A first conductive diaphragm 42 is fixedly connected to the top of the test PCB board 41, a first limit frame 43 is fixedly connected to the top of the first conductive diaphragm 42, a first test chip 44 is installed inside the first limit frame 43, a plurality of second limit frames 45 are sequentially arranged on the top of the first limit frame 43 from bottom to top, a second conductive diaphragm 46 is fixedly connected to the inner side wall of the second limit frame 45, a second test chip 47 is installed on the top of the second conductive diaphragm 46, the second test chip 47 is installed inside the second limit frame 45, limit pins and pin holes are relatively arranged on the first limit frame 43 and the plurality of second limit frames 45, the second limit frame 45, the second conductive diaphragm 46 and the second test chip 47, the bottom of the second limit frame 45 is fixedly connected to a fixing plate 48 by bolts, and the second conductive diaphragm 46 is arranged between the fixing plate 48 and the second limit frame 45.

[0058] In the embodiment, specifically: the base assembly 13 includes a second base 132 .

[0059] In the embodiment, specifically: the test seat mechanism 20 includes a second test seat 22 .

[0060] In this embodiment, specifically: the cover mechanism 30 includes a second cover assembly 32, and the second cover assembly 32 includes a second cover plate 321, a second lock buckle 322 and a signal connector 323;

[0061] A second lock buckle 322 is installed on the front surface of the second cover plate 321 , and a plurality of signal connectors 323 are installed on the inner side wall of the second cover plate 321 . The signal connectors 323 are used for inputting analog signals.

[0062] In this embodiment, specifically: the second cover assembly 32 is rotatably connected to the top of the second test seat 22 .

[0063] When in use, the first test chip 44 is installed inside the first limit frame 43, on the top of the first conductive diaphragm 42, and the second test chip 47 is installed inside the second limit frame 45, on the top of the second conductive diaphragm 46. The positioning pins and pin holes on the limit frames are used to vertically arrange multiple second limit frames 45 in sequence on the top of the first limit frame 43. The analog signal is input through the signal connector 323 to test the high-frequency performance of the chip.

[0064] Embodiment 2 is used for testing digital and digital-to-analog conversion stacked chips, and is different from embodiment 1 RF stacked chips in that: the bottom of the digital and digital-to-analog conversion stacked chips no longer requires RF coaxial lead-out, and high-speed digital chips are prone to inaccurate bit error testing through cable switching. Therefore, the test is directly performed by testing the PCB board 41 plus the peripheral circuit to simulate the normal working state, and the analog signal is introduced from the top of the fixture to ensure the accuracy of the test results. The two implementation methods of embodiment 1 and embodiment 2 can be used in combination.

[0065] The utility model can perform RF FPGA, RF chip, QFN, SIP, silicon-based chip, and other forms of stacked chips testing. The test objects of the utility model include but are not limited to other RF and digital surface contact point products.

[0066] This design can solve the multi-layer stacked RF and digital chip testing, and can also be applied to other types of high-speed chip function testing. The patent discloses the use of chip layered limiting signal connection device, using conductive film to connect digital and RF signals between layered chips, to achieve the whole performance test of multi-layer stacked chips without welding; the use of the structure and principle of this patent to make a multi-layer stacked chip test device for digital and RF microwave chip performance test measurement, as well as the use of the stacked transmission method disclosed in this patent alone to make digital and RF chip stacked chip test devices or fixtures, are all within the scope of protection of this patent.

[0067] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A jig for testing the high-frequency performance of a radio frequency chip by layered testing, comprising a supporting mechanism (10), characterized in that: The top of the support mechanism (10) is fixedly connected to a test seat mechanism (20), the top of the test seat mechanism (20) is rotatably connected to a cover mechanism (30), a test mechanism (40) is arranged between the test seat mechanism (20) and the cover mechanism (30), and the test mechanism (40) comprises a test PCB board (41), a first conductive film (42), a first limit frame (43), a first test chip (44), a second limit frame (45), a second conductive film (46), a second test chip (47) and a fixed plate (48); The top of the test PCB board (41) is fixedly connected to a first conductive film (42), the top of the first conductive film (42) is fixedly connected to a first limit frame (43), a first test chip (44) is installed inside the first limit frame (43), a plurality of second limit frames (45) are arranged in sequence from bottom to top on the top of the first limit frame (43), a second conductive film (46) is fixedly connected to the inner side wall of the second limit frame (45), a second test chip (47) is installed on the top of the second conductive film (46), and the second test chip (47) is installed inside the second limit frame (45), the first limit frame (43) and the plurality of second limit frames (45) are relatively provided with limit pins and pin holes, the bottom of the second limit frame (45) is fixedly connected to a fixing plate (48) by bolts, and the second conductive film (46) is arranged between the fixing plate (48) and the second limit frame (45); The support mechanism (10) comprises a base plate (11), supporting legs (12) and a base assembly (13); The bottom of the base plate (11) is symmetrically and fixedly connected with a support foot (12), and the top of the base plate (11) is fixedly connected with a base assembly (13), wherein the base assembly (13) comprises a first base (131) and a second base (132); The support mechanism (10) further comprises a radio frequency connector (14), a radio frequency cable (15) and a crimping sleeve (16); A plurality of radio frequency connectors (14) are installed on both sides of the first base (131), a radio frequency cable (15) is installed on one side of the radio frequency connector (14), and one end of the radio frequency cable (15) is fixedly connected to a crimping sleeve (16).

2. A hierarchical test fixture for high-frequency performance of radio frequency chips according to claim 1, characterized in that: A test seat mechanism (20) is provided on the top of the base assembly (13), and the test seat mechanism (20) comprises a first test seat (21), a second test seat (22) and a common ground connection block (23); The inner side wall of the first test seat (21) is fixedly connected to a common ground connection block (23), and the crimping sleeve (16) is installed inside the common ground connection block (23).

3. A hierarchical test fixture for high-frequency performance of radio frequency chips according to claim 2, characterized in that: The cover body mechanism (30) comprises a first cover body assembly (31) and a second cover body assembly (32); the first cover body assembly (31) comprises a first cover plate (311), a knob (312), a first lock buckle (313) and a pressing block (314); The top of the first cover plate (311) is threadedly connected to a knob (312), the front surface of the first cover plate (311) is mounted with a first lock buckle (313), and the inner side wall of the first cover plate (311) is slidably connected to a pressing block (314).

4. A hierarchical test fixture for high-frequency performance of radio frequency chips according to claim 3, characterized in that: The first cover plate (311) is rotatably connected to the top of the first test seat (21).

5. A hierarchical test fixture for high-frequency performance of radio frequency chips according to claim 3, characterized in that: The second cover body assembly (32) comprises a second cover plate (321), a second lock buckle (322) and a signal connector (323); A second lock buckle (322) is installed on the front surface of the second cover plate (321), and a plurality of signal connectors (323) are installed on the inner side wall of the second cover plate (321).

6. A hierarchical test fixture for high-frequency performance of radio frequency chips according to claim 5, characterized in that: The second cover plate (321) is rotatably connected to the top of the second test seat (22).

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