Sending card for LED display screen

Abstract

The utility model discloses a transmitting card for an LED display screen, which is provided with an HDM I input / output interface circuit in an HDM I receiving and transmitting module so as to receive audio and video signals transmitted by external equipment and transmit the audio and video signals to an FPGA main control module. Due to the TTL / LVDS interface circuit in the DM I receiving and transmitting module, the transmitting card can support LVDS input and output or TTL input and output, the flexibility and expandability of the system are improved, and the compatibility of the transmitting card is improved. By integrating the FPGA master control module, the Ethernet signal receiving and transmitting module, the single chip microcomputer module, the storage module, the HDM I receiving and transmitting module, the USB interface module and the power module, integration of multiple functions is achieved, and the sending card can improve the overall performance and the function integration level of a system.

Description

Technical Field

[0001] The utility model relates to the technical field of sending cards, in particular to a sending card for an LED display screen. Background Art

[0002] At present, LED display sending card systems have been widely used in various display scenarios. However, the existing sending card systems still need to be improved in terms of function integration, data processing efficiency, and cost-effectiveness.

[0003] China Publication No. CN209625764U discloses a sending card and a sending card system, including: an input interface, an output interface, and a field programmable gate array FPGA module and a video processing module that are mutually communicatively connected, wherein the input interface and the output interface are respectively connected to the FPGA module, and the FPGA module includes an FPGA processor for processing video data and an identification module for identifying the video data format; wherein, when the identification module identifies that the video data is a type that is not processed by the FPGA processor, the FPGA module transmits the video data to the video processing module for conversion into a type processed by the FPGA processor; thus, the above sending card integrates a video processing module, by sending the unparsed video data to the video processing module, and then parsing the video data in the video processing module and transmitting it to the FPGA module, so that the FPGA module converts the video data into a network data packet form of a data transmission protocol and sends it to the receiving card, so that the sending card can directly obtain the unparsed video data, thereby expanding the function of the sending card and reducing the equipment cost. Although the above sending card system integrates a video processing module, it still has deficiencies in the video data processing flow, the synergy of functional modules and the overall performance of the system.

[0004] Therefore, how to overcome the above-mentioned defects has become an important issue to be solved urgently by those skilled in the art. Utility Model Content

[0005] The utility model overcomes the shortcomings of the above-mentioned technology and provides a sending card for an LED display screen.

[0006] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0007] A sending card for an LED display screen, comprising: an FPGA main control module 1, an Ethernet signal transceiver module 2, a single-chip computer module 3, a storage module 4, an HDMI transceiver module 5, a USB interface module 6 and a power supply module 7 for supplying power to each module; the Ethernet signal transceiver module 2, the single-chip computer module 3, the storage module 4, the HDMI transceiver module 5 are all connected to the FPGA main control module 1; the single-chip computer module 3 is respectively connected to the FPGA main control module 1 and the HDMI transceiver module 5; the HDMI transceiver module 5 is used to receive audio and video signals transmitted by an external device and send them to the FPGA main control module 1, the FPGA main control module 1 is used to encapsulate the audio and video signals into a format suitable for Ethernet transmission and send them to the Ethernet signal transceiver module 2, the storage module 4 is used to realize data storage and facilitate data call, and the USB interface module 6 is used to realize serial communication between an external PC and the FPGA main control module 1; wherein the HDMI transceiver module 5 comprises: an HDMI transceiver for receiving and sending audio and video signals I input / output interface circuit 51, TTL / LVDS interface circuit 52 for LVDS input and output or TTL input and output.

[0008] Preferably, the HDMI input / output interface circuit 51 includes an HDMI input interface sub-circuit 511, an HDMI output interface sub-circuit 512, and a signal transmission protection circuit 513 connected between the HDMI input interface sub-circuit 511 and the HDMI output interface sub-circuit 512; the HDMI input interface sub-circuit 511 is provided with multiple audio and video signal receiving ends and a CEC communication receiving end T1 for CEC protocol communication, and the HDMI output interface sub-circuit 512 is provided with multiple audio and video signal sending ends and a CEC communication sending end T2 for CEC protocol communication; the signal transmission protection circuit 513 includes: a first interface U12A that integrates all receiving ends with all sending ends, one or more ESD electrostatic diodes of model RCLAMP0524P connected between multiple audio and video signal receiving ends and the first interface U12A, and one or more ESD electrostatic diodes of model RCLAMP0524P connected between the first interface U12A and multiple audio and video signal sending ends.

[0009] Preferably, the HDMI transceiver module 5 also includes: a functional circuit 53 for implementing CEC communication and for transmitting multi-channel audio signals, the functional circuit 53 is provided with a CEC communication protocol terminal T3 and multiple audio data transmission terminals for transmitting audio channel data; the signal transmission protection circuit 513 also includes a CEC signal protection subcircuit 5131 connected between the CEC communication receiving terminal T1 and the CEC communication sending terminal T2, the CEC signal protection subcircuit 5131 includes: a first resistor R115, a second resistor R116, and a chip varistor ESD1 with model AVLC18S02015, the CEC communication receiving terminal T1 is connected to the CEC communication protocol terminal T3 through the first resistor R115, the CEC communication protocol terminal T3 is connected to the CEC communication sending terminal T2 through the second resistor R116, and the chip varistor ESD1 is connected between the CEC communication sending terminal T2 and the ground terminal.

[0010] Preferably, a first power supply management subcircuit 5111 is connected between the HDM I input interface subcircuit 511 and the power supply output end of the power module 7, and a second power supply management subcircuit 5121 is connected between the HDM I output interface subcircuit 512 and the power supply output end of the power module 7;

[0011] The first power supply management sub-circuit 5111 includes: a first capacitor C200, a third resistor R101, a fourth resistor R111, a fifth resistor R112, and a dual common cathode Schottky diode pair D7, wherein the anode of one of the Schottky diodes of the dual common cathode Schottky diode pair D7 is connected to the power supply output terminal of the power module 7, and the anode of the other Schottky diode is connected to the power supply input terminal of the HDMI input interface sub-circuit 511, and the dual common cathodes of the dual common cathode Schottky diode pair D7 are connected to the clock signal terminal of the HDMI input interface sub-circuit 511 through the fourth resistor R111, and are also connected to the data signal terminal of the HDMI input interface sub-circuit 511 through the fifth resistor R112, and the first capacitor C200 and the third resistor R101 are both connected in parallel between the power supply output terminal and the ground terminal of the power module 7; the second power supply management sub-circuit 5121 is a power distribution switch circuit using a chip model of TPS2051 BDBVR.

[0012] Preferably, the HDMI transceiver module 5 is a high-definition multimedia interface receiver chip of model GSV2011.

[0013] Preferably, the single-chip microcomputer module 3 includes: a single-chip microcomputer chip circuit with a chip model of STM32F030C8, and the single-chip microcomputer chip circuit is connected to the FPGA main control module 1;

[0014] The Ethernet signal transceiver module 2 includes: a PHY chip circuit 21 with a chip model of YT8521SC-CA, a network transformer circuit 22 connected to the PHY chip circuit 21, and a first network port socket 23 connected to the PHY chip circuit 21;

[0015] The FPGA main control module 1 includes: an FPGA chip circuit 11 using a chip model of PH1A180SFG676 and an FPGA configuration circuit 12 connected to the FPGA chip circuit 11;

[0016] The storage module 4 is a storage chip circuit using chip model MT41K256M16TW-107.

[0017] Preferably, the FPGA configuration circuit 12 includes: a flash memory circuit 121, a JTAG interface circuit 122, and a crystal oscillator circuit 123 respectively connected to the FPGA chip circuit 11; the flash memory circuit 121 includes: a flash memory chip U11 of model MT25QL256ABA1 EW7 / MX25L25635FZ connected to the FPGA chip circuit 11 and its peripheral circuits.

[0018] Preferably, the output end of the USB interface module 6 is connected to the FPGA main control module 1; the USB interface module 6 includes: a first interface chip circuit 61 using a chip model of GL850G and a second interface chip circuit 62 using a chip model of CP2102.

[0019] Compared with the prior art, the beneficial effects of the utility model are:

[0020] 1. This case uses the setting of the HDMI input / output interface circuit in the HDMI transceiver module to receive the audio and video signals transmitted by the external device and send these audio and video signals to the FPGA main control module. The setting of the FPGA main control module can serve as the core of the sending card and is responsible for encapsulating and processing the received audio and video signals. The setting of the Ethernet signal transceiver module connected to the FPGA main control module is responsible for transmitting the encapsulated audio and video signals through Ethernet. The setting of the single-chip microcomputer module connected to the FPGA main control module and the HDMI transceiver module provides the control and monitoring functions of the sending card. The setting of the storage module can store the configuration information and audio and video data of the sending card for subsequent calling and use. The setting of the TTL / LVDS interface circuit in the DM I transceiver module enables the sending card to support LVDS input and output or TTL input and output, increases the flexibility and scalability of the system, and improves the compatibility of the sending card. The setting of the USB interface module can realize serial communication between the external PC and the FPGA main control module, so as to facilitate the parameter setting, software upgrade and other operations of the sending card. To sum up, the sending card in this case integrates FPGA main control module, Ethernet signal transceiver module, single-chip microcomputer module, storage module, HDMI transceiver module, USB interface module and power module to achieve the integration of multiple functions, thereby improving the overall performance and functional integration of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the structure of the sending card in this case.

[0022] Figure 2 It is the circuit diagram of the HDMI input / output interface circuit in this case.

[0023] Figure 3 This is the circuit diagram of the TTL / LVDS interface circuit in this case.

[0024] Figure 4 It is the circuit diagram of the functional circuit in this case.

[0025] Figure 5 This is the circuit diagram of the microcontroller module in this case.

[0026] Figure 6 This is the circuit diagram of the FPGA chip circuit in this case.

[0027] Figure 7 It is the circuit diagram of the FPGA configuration circuit in this case.

[0028] Figure 8 It is the circuit diagram of the Ethernet signal transceiver module in this case.

[0029] Fig. 9It is the circuit diagram of the storage module in this case.

[0030] Fig.10 It is the circuit diagram of the USB interface module in this case.

[0031] Fig.11 This is the circuit diagram of the power module in this case. DETAILED DESCRIPTION

[0032] The following examples further illustrate the features of the present invention and other related features to facilitate understanding by technicians in the same industry:

[0033] like Figures 1 to 11 As shown, a sending card for an LED display screen is characterized in that it includes: an FPGA main control module 1, an Ethernet signal transceiver module 2, a single-chip computer module 3, a storage module 4, an HDMI transceiver module 5, a USB interface module 6, and a power supply module 7 for supplying power to each module;

[0034] The Ethernet signal transceiver module 2, the single-chip computer module 3, the storage module 4, and the HDMI transceiver module 5 are all connected to the FPGA main control module 1; the single-chip computer module 3 is respectively connected to the FPGA main control module 1 and the HDMI transceiver module 5; the HDMI transceiver module 5 is used to receive the audio and video signals transmitted by the external device and send them to the FPGA main control module 1, the FPGA main control module 1 is used to encapsulate the audio and video signals into a format suitable for Ethernet transmission and send them to the Ethernet signal transceiver module 2, the storage module 4 is used to realize data storage and facilitate data call, and the USB interface module 6 is used to realize serial communication between the external PC and the FPGA main control module 1;

[0035] The HDMI transceiver module 5 includes: an HDMI input / output interface circuit 51 for receiving and sending audio and video signals, and a TTL / LVDS interface circuit 52 for LVDS input and output or TTL input and output.

[0036] As described above, in this case, the HDMI input / output interface circuit 51 in the HDMI transceiver module 5 is set to receive the audio and video signals transmitted by the external device and send these audio and video signals to the FPGA main control module. The setting of the FPGA main control module 1 can serve as the core of the sending card and is responsible for encapsulating and processing the received audio and video signals. The setting of the Ethernet signal transceiver module 2 connected to the FPGA main control module 1 is responsible for transmitting the encapsulated audio and video signals through Ethernet. The setting of the single-chip computer module 3 connected to the FPGA main control module 1 and the HDMI transceiver module 5 provides the control and monitoring functions of the sending card. The setting of the storage module 4 can store the configuration information and audio and video data of the sending card for subsequent calling and use. The setting of the TTL / LVDS interface circuit 52 in the DM I transceiver module 5 enables the sending card to support LVDS input and output or TTL input and output, increases the flexibility and scalability of the system, and improves the compatibility of the sending card. The setting of the USB interface module 6 can realize serial communication between the external PC and the FPGA main control module 1, so as to facilitate parameter setting, software upgrade and other operations on the sending card. In summary, the sending card in this case integrates FPGA main control module 1, Ethernet signal transceiver module 2, single-chip module 3, storage module 4, HDMI transceiver module 5, USB interface module 6, power module 7, and realizes the integration of multiple functions. The sending card can not only improve the overall performance and functional integration of the system.

[0037] In addition, due to the setting of the Ethernet signal transceiver module 2, it is also possible to send audio and video data to other sending cards or receive data from other sending cards; and because the HDMI transceiver module 5 is provided with an HDMI input / output interface circuit 51, the sending card can not only be used to receive audio and video signals transmitted from external devices, but also receive signals from other sending cards, and can send the signals of this card to other sending cards; and the sending card is provided with an independent power supply module 7 to ensure that each sending card can obtain a stable and reliable power supply. In this way, the sending card in this case can be cascaded with multiple other sending cards, and can be applied to scenes where multiple sending cards need to be spliced ​​to display a large screen, thereby improving product competitiveness.

[0038] like Figures 2 to 4As shown, in a specific implementation, the HDMI input / output interface circuit 51 includes an HDMI input interface subcircuit 511, an HDMI output interface subcircuit 512, and a signal transmission protection circuit 513 connected between the HDMI input interface subcircuit 511 and the HDMI output interface subcircuit 512; the HDMI input interface subcircuit 511 is provided with a plurality of audio and video signal receiving terminals (such as RXA0_P, RXA0_N, RXA1_P, RXA1_N, etc.) and a CEC communication receiving terminal T1 for CEC protocol communication, and the HDMI The I output interface sub-circuit 512 is provided with multiple audio and video signal sending terminals (such as TXA0_P, TXA0_N, TXA1_P, TXA1_N, etc.) and a CEC communication sending terminal T2 for CEC protocol communication; the signal transmission protection circuit 513 includes: a first interface 5131 that integrates all receiving terminals with all sending terminals, one or more ESD electrostatic diodes of model RCLAMP0524P connected between multiple audio and video signal receiving terminals and the first interface U12A, and one or more ESD electrostatic diodes of model RCLAMP0524P connected between the first interface U12A and multiple audio and video signal sending terminals.

[0039] As described above, the HDMI input / output interface circuit 51 can realize the reception and transmission of audio and video signals respectively through the setting of the HDMI input interface subcircuit 511 and the HDMI output interface subcircuit 512, without the need to separately set the receiving module and the sending module, so that the reception and transmission of audio and video signals are integrated in the same interface circuit, data exchange and signal processing are more efficient, the loss and delay of the signal during the transmission process are reduced, and the quality and transmission efficiency of the audio and video signals are improved. Through the setting of the signal transmission protection circuit 513, the stability of the HDMI interface during the signal transmission process is ensured. The ESD electrostatic diode with the model number of RCLAMP0524P is adopted to facilitate the absorption and release of static electricity, and prevent electrostatic discharge ESD from damaging the HDMI input / output interface circuit 51, thereby improving the reliability and durability of the entire system. The setting of the CEC communication receiving terminal T1 and the CEC communication sending terminal T2 is convenient for subsequent connection with the functional circuit 53 to realize CEC protocol communication, so that the sending card can communicate bidirectionally with other HDMI devices (such as projectors, LED display screens, etc.), and realize intelligent control and interconnection of the equipment. The arrangement of the first power supply terminal T2 of the HDMI input interface subcircuit 511 and the second power supply terminal T4 of the HDMI output interface subcircuit 512 ensures stable power supply of the HDMI interface circuit.

[0040] like Figure 4As shown, in a specific implementation, the HDMI transceiver module 5 also includes: a functional circuit 53 for realizing CEC communication and for transmitting multi-channel audio signals, the functional circuit 53 is provided with a CEC communication protocol terminal T3 and a plurality of audio data transmission terminals (such as AUD_D1, AUD_D2, etc.) for transmitting audio channel data; the signal transmission protection circuit 513 also includes a CEC signal protection subcircuit 5131 connected between the CEC communication receiving terminal T1 and the CEC communication transmitting terminal T2, the CEC signal protection subcircuit 5131 includes: a first resistor R115, a second resistor R116, and a chip varistor ESD1 of model AVLC18S02015, the CEC communication receiving terminal T1 is connected to the CEC communication protocol terminal T3 through the first resistor R115, the CEC communication protocol terminal T3 is connected to the CEC communication transmitting terminal T2 through the second resistor R116, and the chip varistor ESD1 is connected between the CEC communication transmitting terminal T2 and the ground terminal.

[0041] As described above, the CEC communication protocol terminal T3 and multiple audio data transmission terminals of the functional circuit 53 in the HDMI transceiver module 5 of this case realize the transmission of CEC consumer electronic control communication and multi-channel audio signals. On the one hand, through CEC communication, users can use a single remote control to control multiple HDMI-connected devices, which improves the convenience of operation; the transmission capability of multi-channel audio signals provides stereo function to meet the user's demand for high-quality audio and video. The CEC signal protection subcircuit 5131 is set up through the first resistor R115, the second resistor R116 and the chip varistor ESD1, model AVLC18S02015, so as to ensure the stability and security of signal transmission, which is conducive to improving the signal quality and transmission efficiency.

[0042] like Figure 2 As shown, in a specific implementation, a first power supply management subcircuit 5111 is connected between the HDMI input interface subcircuit 511 and the power supply output end of the power module 7, and a second power supply management subcircuit 5121 is connected between the HDMI output interface subcircuit 512 and the power supply output end of the power module 7;

[0043] The first power supply management subcircuit 5111 includes: a first capacitor C200, a third resistor R101, a fourth resistor R111, a fifth resistor R112, and a dual common cathode Schottky diode pair D7, wherein the dual common cathode Schottky diode pair D7 has a model of BAT54C; the anode of one of the Schottky diodes of the dual common cathode Schottky diode pair D7 is connected to the power supply output terminal of the power module 7, and the anode of the other Schottky diode is connected to the power supply input terminal of the HDMI input interface subcircuit 511, and the dual common cathodes of the dual common cathode Schottky diode pair D7 are connected to the clock signal terminal of the HDMI input interface subcircuit 511 through the fourth resistor R111, and are also connected to the data signal terminal of the HDMI input interface subcircuit 511 through the fifth resistor R112, and the first capacitor C200 and the third resistor R101 are both connected in parallel between the power supply output terminal and the ground terminal of the power module 7;

[0044] The second power supply management sub-circuit 5121 is a power distribution switch circuit using a chip model TPS2051 BDBVR.

[0045] As described above, the dual common cathode Schottky diode pair D7 of the first power supply management subcircuit 5111 provides a protection function for the HDMI input interface subcircuit 511, and can prevent the overvoltage or reverse voltage on the clock signal terminal RXA_SCL and the data signal terminal RXA_SDA from damaging the interface circuit. The fourth resistor R111 and the fifth resistor R112 are set so as to limit the current passing through the dual common cathode Schottky diode pair D7 and protect the diode from being damaged by excessive current. The first capacitor C200 and the third resistor R101 form a filter circuit so as to reduce power supply noise and improve power supply quality.

[0046] The second power supply management sub-circuit 5121 adopts a power distribution switch circuit with a chip model of TPS2051 BDBVR, which can integrate over-current protection, over-heat protection and short-circuit protection functions to provide stable and reliable power supply for the HDMI output interface sub-circuit 512.

[0047] As a preferred embodiment, the HDMI transceiver module 5 is a high-definition multimedia interface receiver chip of model GSV2011. Thus, the high-definition multimedia interface receiver chip GSV20112 can receive and decode high-definition video signals, and also provides powerful signal processing functions, including color space conversion, video scaling, image enhancement and noise reduction, etc. So that the sending card in this case can improve the video quality with these functions, and adapt to different display devices, so as to be widely used in LCD TVs, monitors, audio and video interface converters and other multimedia applications.

[0048] like Figure 5As shown, the single-chip microcomputer module 3 includes: a single-chip microcomputer chip circuit with a chip model of STM32F030C8, and the single-chip microcomputer chip circuit is connected to the FPGA main control module 1; thus, the STM32F030C8 single-chip microcomputer adopts a high-performance Cortex-M0 core, which has the characteristics of low power consumption and high performance, so that the single-chip microcomputer module can effectively reduce energy consumption while providing powerful processing capabilities.

[0049] like Figure 8 As shown, the Ethernet signal transceiver module 2 includes: a PHY chip circuit 21 with a chip model of YT8521 SC-CA, a network transformer circuit 22 connected to the PHY chip circuit 21, and a first network port socket 23 connected to the PHY chip circuit 21; in this way, the FPGA main control module 1 communicates with the Ethernet through the first network port socket 23, and the Ethernet is linked in through the first network port socket 23, and the network transformer circuit 22 is used to provide isolation and adaptation of the physical layer, so as to ensure the electrical isolation, signal adaptation and compatibility between the FPGA main control module 1 and the Ethernet network, improve the reliability and stability of communication, and protect the equipment from electrical shock and interference. The Ethernet coupling signal of the network transformer circuit 22 is transmitted to the PHY chip circuit 21, and through the physical layer conversion, speed matching, interface standardization, automatic negotiation and electrical isolation in the PHY chip, it is ensured that the FPGA main control module can communicate with the Ethernet device stably and reliably.

[0050] like Figure 6 and Figure 7As shown, the FPGA master control module 1 includes: an FPGA chip circuit 11 using a chip model of PH1A180SFG676 and an FPGA configuration circuit 12 connected to the FPGA chip circuit 11. In specific implementation, the PGA master control chip uses an FPGA chip of model PH1A180SFG676, so that the FPGA master control module 1 has the characteristics of low power consumption, high speed, high bandwidth, large capacity, integration, support for multiple communication protocols, strong reprogrammability, rich IP resources, etc., effectively using the PH1A platform to achieve complex design, can provide various IP resources, convenient for users to directly call debugging, solve the problem of insufficient resources caused by complex logic, and provide strong guarantee for users to design high-quality products. Specifically, the PH1A180SFG676 chip is equipped with a large number of logic resources, PLL, ERAM, PLB, PMB, a large number of IO resources and DSP blocks, which can realize complex calculations, high-speed data throughput and signal processing tasks. It has a large logic capacity and storage capacity, and can support large-scale design and application. It provides a rich programmable logic unit and a SERDES with a maximum rate of 10GHz, which can flexibly meet the needs of different applications. It has large logic capacity and storage capacity, can support large-scale design and application, and provides a wealth of programmable logic units, which can flexibly meet the needs of different applications and help improve market competitiveness. In specific implementation, PH1A180SFG676 is a blank board without sending card code when powered on. When it is powered on and configured, it will load the pre-made code in the flash of the sending card. After the configuration is completed, the pre-stored parameters in the flash are read to configure the code parameters of the FPGA and the data of the GSV2011 chip in the HDMI transceiver module 5 of the single-chip transmission configuration. After the power-on configuration of PH1A180SFG676 is completed, ddr3 in the storage module 4 will be initialized and communicated with the PHY chip through the RGMII protocol. When these actions are completed, the PH1A180SFG676 chip will cache the image data transmitted by the GSV2011 chip into DDR3, and then read the image data from DDR3 and transmit it to the PHY chip. Then the data is exchanged with the receiving card through the sending card PHY. This is the main workflow of the sending card.

[0051] like Fig. 9 As shown, the storage module 4 is a storage chip circuit using the chip model MT41K256M16TW-107. In this way, the storage module 4 has the synergy of DDR and FPGA, and realizes stable and efficient data storage and processing through clock synchronization, address control, data transmission, cache management, error detection and other aspects.

[0052] As a preferred implementation method, Figure 7As shown, the FPGA configuration circuit 12 includes: a flash memory circuit 121, a JTAG interface circuit 122, and a crystal oscillator circuit 123 respectively connected to the FPGA chip circuit 11; the flash memory circuit 121 includes: a flash memory chip U11 of model MT25QL256ABA1 EW7 / MX25L25635FZ connected to the FPGA chip circuit 11 and its peripheral circuits. In specific implementation, JTAG provides a standardized interface and protocol, so that the FPGA master control module can receive programming data through the JTAG interface in the JTAG interface circuit, load it into the internal configuration memory, and configure the FPGA. The flash memory circuit 121 using the MT25QL256ABA1 EW7 / MX25L25635FZ flash memory chip has the advantages of large-capacity storage, high-speed data transmission, flexible data access, reliability and stability, low power consumption, and optimized system performance.

[0053] like Fig.10 As shown, the output end of the USB interface module 6 is connected to the FPGA main control module 1; the USB interface module 6 includes: a first interface chip circuit 61 using a chip model of GL850G and a second interface chip circuit 62 using a chip model of CP2102. In this way, by using the first interface chip circuit 61 with a chip model of GL850G, a single USB port can be expanded into multiple USB ports, usually up to 4 USB ports, so that users can connect more USB devices. By using the second interface chip circuit 62 with a chip model of CP2102, traditional serial port devices can be easily connected to the USB host, realizing the convenience and efficiency of serial port communication.

[0054] As mentioned above, this case protects a sending card for LED display screens. All technical solutions that are the same or similar to this case should be deemed to fall within the scope of protection of this case.

Claims

1. A sending card for LED display screen, characterized in that: include: FPGA main control module (1), Ethernet signal transceiver module (2), single chip computer module (3), storage module (4), HDMI transceiver module (5), USB interface module (6) and power supply module (7) for supplying power to each module; The Ethernet signal transceiver module (2), the single-chip computer module (3), the storage module (4), and the HDMI transceiver module (5) are all connected to the FPGA main control module (1); the single-chip computer module (3) is respectively connected to the FPGA main control module (1) and the HDMI transceiver module (5); the HDMI transceiver module (5) is used to receive audio and video signals transmitted by an external device and send them to the FPGA main control module (1); the FPGA main control module (1) is used to encapsulate the audio and video signals into a format suitable for Ethernet transmission and send them to the Ethernet signal transceiver module (2); the storage module (4) is used to realize data storage and facilitate data call; the USB interface module (6) is used to realize serial communication between an external PC and the FPGA main control module (1); The HDMI transceiver module (5) comprises: an HDMI input / output interface circuit (51) for receiving and sending audio and video signals, and a TTL / LVDS interface circuit (52) for LVDS input and output or TTL input and output.

2. A sending card for an LED display screen according to claim 1, characterized in that: The HDMI input / output interface circuit (51) comprises an HDMI input interface subcircuit (511), an HDMI output interface subcircuit (512), and a signal transmission protection circuit (513) connected between the HDMI input interface subcircuit (511) and the HDMI output interface subcircuit (512); the HDMI input interface subcircuit (511) is provided with a plurality of audio and video signal receiving terminals and a CEC communication receiving terminal (T1) for CEC protocol communication, and the HDMI output interface subcircuit (512) is provided with a plurality of audio and video signal sending terminals and a CEC communication sending terminal (T2) for CEC protocol communication; The signal transmission protection circuit (513) comprises: a first interface (U12A) integrating all receiving ends and all sending ends, one or more ESD electrostatic diodes of model RCLAMP0524P connected between multiple audio and video signal receiving ends and the first interface (U12A), and one or more ESD electrostatic diodes of model RCLAMP0524P connected between the first interface (U12A) and multiple audio and video signal sending ends.

3. A sending card for an LED display screen according to claim 2, characterized in that: The HDMI transceiver module (5) further comprises: a functional circuit (53) for implementing CEC communication and for transmitting multi-channel audio signals, wherein the functional circuit (53) is provided with a CEC communication protocol terminal (T3) and a plurality of audio data transmission terminals for transmitting audio channel data; the signal transmission protection circuit (513) further comprises a CEC signal protection subcircuit (5131) connected between the CEC communication receiving terminal (T1) and the CEC communication transmitting terminal (T2), wherein the CEC signal protection subcircuit (5131) comprises: a first resistor (R115), a second resistor (R116), and a chip varistor (ESD1) of model AVLC18S02015, wherein the CEC communication receiving terminal (T1) is connected to the CEC communication protocol terminal (T3) via the first resistor (R115), the CEC communication protocol terminal (T3) is connected to the CEC communication transmitting terminal (T2) via the second resistor (R116), and the chip varistor (ESD1) is connected between the CEC communication transmitting terminal (T2) and the ground terminal.

4. A sending card for an LED display screen according to claim 2, characterized in that: A first power supply management subcircuit (5111) is connected between the HDMI input interface subcircuit (511) and the power supply output end of the power supply module (7), and a second power supply management subcircuit (5121) is connected between the HDMI output interface subcircuit (512) and the power supply output end of the power supply module (7); The first power supply management subcircuit (5111) comprises: a first capacitor (C200), a third resistor (R101), a fourth resistor (R111), a fifth resistor (R112), and a dual common cathode Schottky diode pair (D7); the anode of one Schottky diode of the dual common cathode Schottky diode pair (D7) is connected to the power supply output end of the power module (7), the anode of the other Schottky diode is connected to the power supply input end of the HDMI input interface subcircuit (511); the dual common cathodes of the dual common cathode Schottky diode pair (D7) are connected to the clock signal end of the HDMI input interface subcircuit (511) through the fourth resistor (R111), and are also connected to the data signal end of the HDMI input interface subcircuit (511) through the fifth resistor (R112); the first capacitor (C200) and the third resistor (R101) are both connected in parallel between the power supply output end and the ground end of the power module (7); The second power supply management sub-circuit (5121) is a power distribution switch circuit using a chip model TPS2051 BDBVR.

5. A sending card for an LED display screen according to any one of claims 1 to 4, characterized in that: The HDMI transceiver module (5) is a high-definition multimedia interface receiver chip of model GSV2011.

6. A sending card for an LED display screen according to claim 1, characterized in that: The single-chip computer module (3) comprises: a single-chip computer chip circuit with a chip model of STM32F030C8, wherein the single-chip computer chip circuit is connected to the FPGA main control module (1); The Ethernet signal transceiver module (2) comprises: a PHY chip circuit (21) with a chip model of YT8521 SC-CA, a network transformer circuit (22) connected to the PHY chip circuit (21), and a first network port socket (23) connected to the PHY chip circuit (21); The FPGA main control module (1) comprises: an FPGA chip circuit (11) with a chip model of PH1A180SFG676 and an FPGA configuration circuit (12) connected to the FPGA chip circuit (11); The storage module (4) is a storage chip circuit using a chip model MT41 K256M16TW-107.

7. A sending card for an LED display screen according to claim 6, characterized in that: The FPGA configuration circuit (12) comprises: a flash memory circuit (121), a JTAG interface circuit (122), and a crystal oscillator circuit (123) respectively connected to the FPGA chip circuit (11); the flash memory circuit (121) comprises: a flash memory chip U11 of model MT25QL256ABA1 EW7 / MX25L25635FZ connected to the FPGA chip circuit (11) and its peripheral circuits.

8. The sending card for LED display screen according to claim 1, characterized in that: The output end of the USB interface module (6) is connected to the FPGA main control module (1); the USB interface module (6) comprises: a first interface chip circuit (61) using a chip model GL850G and a second interface chip circuit (62) using a chip model CP2102.

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