Mute detection device

Abstract

The utility model discloses a mute detection device. The device comprises a decoding earphone amplifier device, an input device and an earphone device. The decoding ear amplifier device comprises a mute circuit, an audio amplification circuit, a digital-to-analog conversion circuit, a connection circuit and a control circuit. The mute circuit generates a corresponding mute detection signal and sends the mute detection signal to the control circuit based on the use of the power supply when detecting that the connection circuit is disconnected from or connected with the input device, and the control circuit performs mute control processing according to the mute detection signal so as to avoid the generation of noise at the earphone device end. And the functionality of the device is improved, so that the use experience of a user is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of decoding headphone amplifiers, and particularly relates to a mute detection device. Background Art

[0002] With the application of portable decoding headphone amplifier devices, it brings convenience to users to supply power through a USB interface. However, when a headphone device is connected to the decoding headphone amplifier device and the connection cable on the USB interface is unplugged or plugged in, at this time, a relatively large noise will be emitted at the headphone device end. This results in low functionality of the decoding headphone amplifier device, thus causing a problem of low usage experience. Content of the Utility Model

[0003] The utility model provides a mute detection device, aiming to solve the problem in the prior art that when a headphone device is connected to a decoding headphone amplifier device and the connection cable on the USB interface is unplugged or plugged in, a relatively large noise will be emitted at the headphone device end, which results in low functionality of the decoding headphone amplifier device, thus causing a problem of low usage experience.

[0004] To solve the above problems, the utility model proposes a mute detection device, which includes a decoding headphone amplifier device, an input device and a headphone device; the decoding headphone amplifier device includes a mute circuit, an audio amplification circuit, a digital-to-analog conversion circuit, a connection circuit and a control circuit; the mute circuit is connected to the connection circuit and also connected to the control circuit; the audio amplification circuit is connected to the digital-to-analog conversion circuit and also connected to the control circuit; the digital-to-analog conversion circuit is connected to the input device through the connection circuit; the control circuit is also connected to the headphone device;

[0005] Among them, the input device is used to send initial audio data to the connection circuit and provide a power supply for use; the connection circuit is used to connect the digital-to-analog conversion circuit to the input device and the mute circuit to the input device to transmit the initial audio data and the power supply for use; the digital-to-analog conversion circuit is used to receive the initial audio data through the connection circuit, perform digital-to-analog conversion processing on the initial audio data to obtain analog audio data, and send the analog audio data to the audio amplification circuit; the mute circuit is used to obtain the power supply for use through the connection circuit, generate a corresponding mute detection signal based on the power supply for use when detecting that the connection circuit is disconnected from or connected to the input device, and send the mute detection signal to the control circuit; the audio amplification circuit is used to receive the analog audio data, perform amplification processing on the analog audio data to obtain target audio data, and send the target audio data to the control circuit; the control circuit is used to receive the mute detection signal, perform mute control processing according to the mute detection signal, and send the received target audio data to the headphone device; the headphone device is used to perform playback processing on the target audio data.

[0006] Compared with the prior art, the utility model provides a mute detection device, which includes a decoding and headphone amplifier device, an input device, and a headphone device; the decoding and headphone amplifier device includes a mute circuit, an audio amplification circuit, a digital-to-analog conversion circuit, a connection circuit, and a control circuit; the mute circuit is connected to the connection circuit and also to the control circuit; the audio amplification circuit is connected to the digital-to-analog conversion circuit and also to the control circuit; the digital-to-analog conversion circuit is connected to the input device through the connection circuit; the control circuit is also connected to the headphone device; wherein, the input device is used to send initial audio data to the connection circuit and provide a power supply for use; the connection circuit is used to connect the digital-to-analog conversion circuit to the input device, and the mute circuit to the input device to transmit the initial audio data and the power supply for use; the digital-to-analog conversion circuit is used to receive the initial audio data through the connection circuit, and perform digital-to-analog conversion processing on the initial audio data to obtain analog audio data and send it to the audio amplification circuit; the mute circuit is used to obtain the power supply for use through the connection circuit, generate corresponding mute detection signals based on the power supply for use when detecting that the connection circuit is disconnected from or connected to the input device, and send the mute detection signals to the control circuit; the audio amplification circuit is used to receive the analog audio data, and perform amplification processing on the analog audio data to obtain target audio data and send it to the control circuit; the control circuit is used to receive the mute detection signals, perform mute control processing according to the mute detection signals, and send the received target audio data to the headphone device; the headphone device is used to perform playback processing on the target audio data. By implementing the embodiments of the utility model, the mute circuit generates corresponding mute detection signals based on the power supply for use when the connection circuit is disconnected from or connected to the input device, and sends the mute detection signals to the control circuit. The control circuit performs mute control processing according to the mute detection signals to avoid the generation of noise at the headphone device end, improve the functionality of the device, and thus improve the user experience. Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0008] Figure 1 It is a schematic block diagram of a mute detection device provided by an embodiment of the present utility model;

[0009] Figure 2Schematic circuit diagram of the decoding headphone amplifier device in the mute detection device provided by an embodiment of the present utility model.

[0010] Among them, the reference numerals in the figure are as follows:

[0011] 1. Mute detection device; 10. Decoding headphone amplifier device; 11. Mute circuit; 12. Audio amplification circuit; 13. Digital-to-analog conversion circuit; 14. Connection circuit; 15. Control circuit; 20. Input device; 30. Headphone device. Detailed implementation manners

[0012] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0013] The directional terms mentioned in the present utility model, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model. In addition, in the drawings, structures that are similar or the same are denoted by the same reference numerals.

[0014] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0015] It should also be understood that the terms used in the specification of the present utility model are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. As used in the specification of the present utility model and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0016] It should be further understood that the term " / and / " used in the specification of the present utility model and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0017] Please refer to Figures 1 to 2, the present utility model provides a mute detection device 1, which includes a decoding headphone amplifier device 10, an input device 20, and a headphone device 30; the decoding headphone amplifier device 10 includes a mute circuit 11, an audio amplification circuit 12, a digital-to-analog conversion circuit 13, a connection circuit 14, and a control circuit 15; the mute circuit 11 is connected to the connection circuit 14 and also connected to the control circuit 15; the audio amplification circuit 12 is connected to the digital-to-analog conversion circuit 13 and also connected to the control circuit 15; the digital-to-analog conversion circuit 13 is connected to the input device 20 through the connection circuit 14; the control circuit 15 is also connected to the headphone device 30;

[0018] Among them, the input device 20 is used to send initial audio data to the connection circuit 14 and provide a power supply for use; the connection circuit 14 is used to connect the digital-to-analog conversion circuit 13 and the input device 20, and the mute circuit 11 and the input device 20 to transmit the initial audio data and the power supply for use; the digital-to-analog conversion circuit 13 is used to receive the initial audio data through the connection circuit 14, and perform digital-to-analog conversion processing on the initial audio data to obtain analog audio data and send it to the audio amplification circuit 12; the mute circuit 11 is used to obtain the power supply for use through the connection circuit 14, and generate corresponding mute detection signals based on the power supply for use when detecting that the connection circuit 14 is disconnected from or connected to the input device 20, and send the mute detection signals to the control circuit 15; the audio amplification circuit 12 is used to receive the analog audio data, and perform amplification processing on the analog audio data to obtain target audio data and send it to the control circuit 15; the control circuit 15 is used to receive the mute detection signals, perform mute control processing according to the mute detection signals, and send the received target audio data to the headphone device 30; the headphone device 30 is used to perform playback processing on the target audio data.

[0019] In this embodiment, as Figure 1 shown, the input device 20 can be a mobile phone device or a computer device; the headphone device 30 can be a wired headphone; the decoding headphone amplifier device 10 is an audio device that improves sound quality and provides a better music experience; the digital-to-analog conversion circuit 13 can include components such as a digital-to-analog converter, which can convert digital signals into analog signals, that is, the initial audio data is a digital signal, and the digital-to-analog conversion circuit 13 is required to convert the initial audio data of the digital signal into the analog audio data of the analog signal. As Figure 2As shown, the power supply used is represented as VBUS, the analog audio data is represented as L_IN and R_IN, and the target audio data is represented as PH_OUT_L and PH_OUT_R. The connection circuit 14 is connected to the input device 20.

[0020] The mute circuit 11 can be connected to the input device 20 through the connection circuit 14, and can also be connected to the headphone device 30 through the control circuit 15; the audio amplification circuit 12 can be connected to the headphone device 30 through the control circuit 15; the digital-to-analog conversion circuit 13 can be connected to the input device 20 through the connection circuit 14; the control circuit 15 can also be connected to the headphone device 30, that is, when ensuring that the mute detection device 1 is normally connected and the decoding headphone amplifier device 10 communicates and operates normally with the input device 20 and the headphone device 30; the mute circuit 11 generates a corresponding mute detection signal when detecting that the connection circuit 14 is disconnected from or connected to the input device 20, and sends the mute detection signal to the control circuit 15; the control circuit 15 receives the mute detection signal and performs mute control processing according to the mute detection signal to achieve mute control of the headphone device 30; thereby avoiding the generation of noise at the headphone device 30 end to block the emission of noise and improving the user experience.

[0021] Through the above embodiments, it can be seen that the mute circuit 11 generates a corresponding mute detection signal when the connection circuit 14 is disconnected from or connected to the input device 20, and sends the mute detection signal to the control circuit 15; the control circuit 15 receives the mute detection signal and performs mute control processing according to the mute detection signal to achieve mute control of the headphone device 30. Therefore, the generation of noise at the headphone device 30 end is avoided, thereby blocking the emission of noise, improving the functionality of the device, and thus improving the user experience.

[0022] In one embodiment, as Figures 1 to 2 shown, the mute circuit 11 includes a first resistor R1, a second resistor R2, a first diode D1, a first capacitor C1, a third resistor R3, a first triode Q1, a second triode Q2, a second capacitor C2, a third triode Q3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

[0023] The first end of the first resistor R1 is connected to the connection circuit 14, the emitter of the first triode Q1, the first end of the second resistor R2, and the positive electrode of the first diode D1. The second end of the first resistor R1 is connected to the positive electrode of the second capacitor C2 and the first end of the third resistor R3. The base of the first triode Q1 is connected to the second end of the third resistor R3. The collector of the first triode Q1 is connected to the first end of the sixth resistor R6, the collector of the second triode Q2, and the base of the third triode Q3. The second end of the second resistor R2 is connected to the base of the second triode Q2. The emitter of the second triode Q2 is connected to the negative electrode of the first diode D1, the positive electrode of the first capacitor C1, and the control circuit 15. The collector of the third triode Q3 is connected to the first end of the fourth resistor R4, the first end of the fifth resistor R5, and the control circuit 15.

[0024] In this embodiment, as Figures 1 to 2 shown, the specification of the first resistor R1 can be 10K; the specification of the second resistor R2 can be 10K; the type of the first diode D1 is a Schottky diode, and its model can be PMEG2010; the specification of the first capacitor C1 can be 220uF / 10V; the specification of the third resistor R3 can be 3K; the type of the first triode Q1 is a PNP type triode, and its model can be S8550; the type of the second triode Q2 is a PNP type triode, and its model can be S8550; the specification of the second capacitor C2 can be 47uF / 10V; the type of the third triode Q3 is an NPN type triode and is a damped triode, and its model can be DTC124EKA; the specification of the fourth resistor R4 can be 20K; the specification of the fifth resistor R5 can be 10K; the specification of the sixth resistor R6 can be 47K.

[0025] The negative electrode of the first capacitor C1, the negative electrode of the second capacitor C2, the second end of the sixth resistor R6, the emitter of the third triode Q3, and the second end of the fourth resistor R4 are all grounded. That is, the first resistor R1 and the third resistor R3 are grounded through the second capacitor C2. The collector of the first triode Q1, the collector of the second diode, and the base of the third triode Q3 are all grounded through the sixth resistor R6. The negative electrode of the first diode D1 and the emitter of the second triode Q2 are all grounded through the first capacitor C1. The collector of the third triode Q3 is grounded through the fourth resistor R4. The second end of the fifth resistor R5 is connected to the power supply module of the decoding headphone amplifier device 10, and a 5V power supply VDD_5V is input to the mute circuit 11 through the fifth resistor R5.

[0026] The input device 20 provides the operating power supply to the mute circuit 11 through the connection circuit 14; the mute circuit 11 utilizes the operating power supply to generate a corresponding mute detection signal when the connection circuit 14 is disconnected from or connected to the input device 20, and sends the mute detection signal to the control circuit 15.

[0027] When the mute circuit 11 detects that the connection circuit 14 is connected to the input device 20, that is, when the input device 20 is connected to the mute circuit 11 through the connection circuit 14; the mute circuit 11 receives the operating power supply, and the operating power supply charges the second capacitor C2 through the first resistor R1. On the other hand, the operating power supply charges the second capacitor C2 through the emitter and base of the first triode Q1 and the third resistor R3, so that the first triode Q1 is in a conducting state and provides a bias voltage for the third triode Q3, so that the third triode Q3 is in a conducting state. At the same time, the operating power supply charges the first capacitor C1 through the first diode D1 and provides a power supply for the control circuit 15; the base of the second triode Q2 receives the operating power supply through the second resistor R2, and the emitter of the second triode Q2 is connected to the positive electrode of the first capacitor C1. At this time, the second triode Q2 is in a cut-off state. Wherein, the voltage corresponding to the operating power supply is +5V.

[0028] In this way, when the third triode Q3 is in a conducting state, the mute detection signal is generated and sent to the control circuit 15, so that the control circuit 15 performs mute control processing according to the mute detection signal.

[0029] In addition, when the mute circuit 11 detects that the connection circuit 14 is connected to the input device 20, that is, after the input device 20 is connected to the mute circuit 11 through the connection circuit 14; after a certain period of time of the charging voltage of the second capacitor C2, the voltage across the two ends of the second capacitor C2 approaches the operating power supply. At this time, the first triode Q1 is in a cut-off state, and the third triode Q3 is also in a cut-off state.

[0030] When the mute circuit 11 detects that the connection circuit 14 is disconnected from the input device 20, that is, when the input device 20 is not connected to the mute circuit 11 through the connection circuit 14; the voltage of the power supply used drops rapidly from 5V to 0V, the base of the second triode Q2 is pulled low through the second resistor R2, and the emitter of the second triode Q2 is connected to the positive electrode of the first capacitor C1, so it still remains 5V. At this time, the second triode Q2 is in a conducting state; the third triode Q3 is also in a conducting state, generating the mute detection signal and sending it to the control circuit 15 for the control circuit 15 to perform mute control processing according to the mute detection signal.

[0031] Through the above embodiments, it can be seen that when the connection circuit 14 is connected to the input device 20, the mute circuit 11 uses the power supply used to make the third triode Q3 in a conducting state through the first triode Q1, the third resistor R3, and the second capacitor C2, and sends the mute detection signal to the control circuit 15 for the control circuit 15 to perform mute control processing according to the mute detection signal; when the connection circuit 14 is disconnected from the input device 20, the mute circuit 11 uses the second diode, the second resistor R2, and the first capacitor C1 to make the third triode Q3 in a conducting state and sends the mute detection signal to the control circuit 15 for the control circuit 15 to perform mute control processing according to the mute detection signal. It can be seen that when the connection circuit 14 is connected to or disconnected from the input device 20, the third triode Q3 is made in a conducting state through the first triode Q1, the third resistor R3, the second capacitor C2 or the second diode, the second resistor R2, and the first capacitor C1, and the mute detection signal is sent to the control circuit 15 for the control circuit 15 to perform mute control processing according to the mute detection signal. Therefore, the generation of noise at the headphone device 30 end is avoided, the functionality of the device is improved, and thus the user experience is improved; at the same time, it is also convenient for subsequent targeted processing according to the mute detection signal.

[0032] In one embodiment, as Figures 1 to 2 shown, the control circuit 15 includes a control chip U1, a third capacitor C3, and a fourth capacitor C4; the second pin and the third pin of the control chip U1 are connected to the headphone device 30, the fourth pin and the fourteenth pin of the control chip U1 are connected to the mute circuit 11, the ninth pin and the eleventh pin of the control chip U1 are connected to the audio amplification circuit 12, the thirteenth pin of the control chip U1 is connected to the first end of the fourth capacitor C4, and the fourteenth pin of the control chip U1 is also connected to the first end of the third capacitor C3.

[0033] In this embodiment, as Figures 1 to 2As shown, the model of the control chip U1 can be RT1238Q; the specification of the third capacitor C3 can be 105; the specification of the fourth capacitor C4 can be 104.

[0034] Among them, the 5th, 6th, 7th, 8th, 10th, 12th, and 16th pins of the control chip U1 are all grounded; the second end of the fourth capacitor C4 is grounded, that is, the 13th pin of the control chip U1 is grounded through the fourth capacitor C4; the second end of the third capacitor C3 is grounded, that is, the 14th pin of the control chip U1 is grounded through the third capacitor C3.

[0035] The 4th pin of the control chip U1 is connected to the mute circuit 11 to receive the mute detection signal sent by the mute circuit 11 and perform mute control processing according to the mute detection signal; at the same time, the 14th pin of the control chip U1 is also connected to the mute circuit 11 to receive the power supply provided by the mute circuit 11 and perform control processing using the power supply; the 9th and 11th pins of the control chip U1 are connected to the audio amplification circuit 12 to receive the target audio data sent by the audio amplification circuit 12; the 2nd and 3rd pins of the control chip U1 are connected to the headphone device 30 to send the target audio data to the headphone device 30.

[0036] Through the above embodiments, it can be seen that after the control chip U1 receives the mute detection signal, it is convenient to subsequently control the on / off processing of its pins according to the mute detection signal to achieve targeted mute control processing.

[0037] In one embodiment, as Figures 1 to 2 shown, the 4th pin of the control chip U1 is connected to the collector of the third triode Q3, the first end of the fourth resistor R4, and the first end of the fifth resistor R5; the 14th pin of the control chip U1 is connected to the negative electrode of the first diode D1, the emitter of the second triode Q2, and the positive electrode of the first capacitor C1.

[0038] In this embodiment, as Figures 1 to 2 shown, the 4th pin of the control chip U1 is connected to the mute circuit 11, that is, the 4th pin of the control chip U1 is connected to the collector of the third triode Q3, the first end of the fourth resistor R4, and the first end of the fifth resistor R5; the 14th pin of the control chip U1 is connected to the mute circuit 11, that is, the 14th pin of the control chip U1 is connected to the negative electrode of the first diode D1, the emitter of the second triode Q2, and the positive electrode of the first capacitor C1.

[0039] The audio amplification circuit 12 and the headphone device 30 establish a data connection through the control chip U1; the function of the control chip U1 is equivalent to an electronic switch. When receiving the mute detection signal, it disconnects the audio amplification circuit 12 from the headphone device 30, and the headphone device 30 is in a mute state, that is, the mute process is completed.

[0040] When the mute circuit 11 detects that the connection circuit 14 is connected to the input device 20, that is, when the input device 20 is connected to the mute circuit 11 through the connection circuit 14; the power supply charges the second capacitor C2 through the emitter and base of the first triode Q1 and the third resistor R3, so that the first triode Q1 is in a conducting state and provides a bias voltage for the third triode Q3, so that the third triode Q3 is in a conducting state, generates the mute detection signal, and sends the mute detection signal to the 4th pin of the control chip U1; the mute detection signal pulls down the 4th pin of the control chip U1 to a low level. At this time, the control chip U1 controls its 12th pin to conduct with the 2nd pin, the 10th pin to conduct with the 3rd pin, the 11th pin to disconnect from the 2nd pin, and the 9th pin to disconnect from the 3rd pin; equivalently, the control chip U1 disconnects the audio amplification circuit 12 from the headphone device 30 and is in a mute state, that is, the mute process is completed.

[0041] In addition, when the mute circuit 11 detects that the connection circuit 14 is connected to the input device 20, that is, after the input device 20 is connected to the mute circuit 11 through the connection circuit 14; after a certain period of time of the charging voltage of the second capacitor C2, the voltage across the two ends of the second capacitor C2 approaches the power supply. At this time, the first triode Q1 is in a cut-off state, and the third triode Q3 is also in a cut-off state, causing the 4th pin of the control chip U1 to become a high level. At this time, the control chip U1 controls its 12th pin to disconnect from the 2nd pin, the 10th pin to disconnect from the 3rd pin, the 11th pin to conduct with the 2nd pin, and the 9th pin to conduct with the 3rd pin; equivalently, the control chip U1 establishes the connection between the audio amplification circuit 12 and the headphone device 30 and is in a normal working state, and the headphone device 30 plays normally.

[0042] When the mute circuit 11 detects that the connection circuit 14 is disconnected from the input device 20, that is, when the input device 20 is not connected to the mute circuit 11 through the connection circuit 14; the voltage of the power supply used drops rapidly from 5V to 0V, the base of the second triode Q2 is pulled low through the second resistor R2, and the emitter of the second triode Q2 is connected to the positive electrode of the first capacitor C1, so it still remains 5V. At this time, the second triode Q2 is in a conducting state; the third triode Q3 is also in a conducting state, generating the mute detection signal and sending the mute detection signal to the 4th pin of the control chip U1; the mute detection signal pulls down the 4th pin of the control chip U1 to become a low level. At this time, the control chip U1 controls its 12th pin to conduct with the 2nd pin, the 10th pin to conduct with the 3rd pin, the 11th pin to disconnect from the 2nd pin, and the 9th pin to disconnect from the 3rd pin; equivalently, the control chip U1 disconnects the audio amplifier circuit 12 from the headphone device 30 and is in a mute state, that is, the mute processing is completed.

[0043] Through the above embodiments, it can be seen that after receiving the mute detection signal, the control chip U1 controls the on-off processing of its corresponding pins according to the mute detection signal, thereby realizing the mute control processing. Therefore, the generation of noise in the headphone device 30 is avoided, the functionality of the device is improved, and thus the user experience is improved.

[0044] In one embodiment, as Figures 1 to 2 shown, the audio amplifier circuit 12 includes a seventh resistor R7, a first amplifier A1, a fifth capacitor C5, an eighth resistor R8, a sixth capacitor C6, a ninth resistor R9, a tenth resistor R10, and a seventh capacitor C7;

[0045] The first end of the seventh resistor R7 is connected to the digital-to-analog conversion circuit 13, and the second end of the seventh resistor R7 is connected to the 3rd pin of the first amplifier A1 and the second end of the sixth capacitor C6; the 2nd pin of the first amplifier A1 is connected to the second end of the ninth resistor R9, the first end of the tenth resistor R10, and the first end of the seventh capacitor C7. The 1st pin of the first amplifier A1 is connected to the second end of the tenth resistor R10, the second end of the seventh capacitor C7, the second end of the eighth resistor R8, and the control circuit 15; the first end of the sixth capacitor C6 is connected to the first end of the ninth resistor R9; the first end of the eighth resistor R8 is connected to the second end of the fifth capacitor C5.

[0046] In this embodiment, as Figures 1 to 2As shown, the specification of the seventh resistor R7 can be 1.2K; the specification of the sixth capacitor C6 can be 102 (COG); the specification of the ninth resistor R9 can be 4.99K; the model of the first amplifier A1 can be SGM8262-2; the specification of the tenth resistor R10 can be 1K; the specification of the seventh capacitor C7 can be 22P (COG); the specification of the fifth capacitor C5 can be 104, and the specification of the eighth resistor R8 can be 10R.

[0047] Among them, the first end of the sixth capacitor C6, the first end of the ninth resistor R9, and the first end of the fifth capacitor C5 are all grounded; that is, the second end of the seventh resistor R7 and the 3rd pin of the first amplifier A1 are grounded through the sixth capacitor C6, the 2nd pin of the first amplifier A1, the first end of the fourth resistor R4, and the first end of the seventh capacitor C7 are grounded through the ninth resistor R9, and the 1st pin of the first amplifier A1, the second end of the tenth resistor R10, and the second end of the seventh capacitor C7 are grounded through the eighth resistor R8 and the fifth capacitor C5.

[0048] The audio amplification circuit 12 receives two channels of analog audio data through the digital-to-analog conversion circuit 13, that is, the analog audio data includes the first analog audio data L_IN and the second analog audio data R_IN; the first analog audio data L_IN is amplified through the seventh resistor R7, the first amplifier A1, the fifth capacitor C5, the eighth resistor R8, the sixth capacitor C6, the ninth resistor R9, the tenth resistor R10, and the seventh capacitor C7 to obtain the first target audio data PH_OUT_L, and the first target audio data PH_OUT_L is sent to the control chip U1. Among them, the target audio data includes the first target audio data PH_OUT_L and the second target audio data PH_OUT_R.

[0049] Through the above embodiments, it can be seen that the audio amplification circuit 12 amplifies the first analog audio data L_IN of one channel through the seventh resistor R7, the first amplifier A1, the fifth capacitor C5, the eighth resistor R8, the sixth capacitor C6, the ninth resistor R9, the tenth resistor R10, and the seventh capacitor C7 to obtain the first target audio data PH_OUT_L, and sends it to the control chip U1 for subsequent targeted processing according to the first target audio data PH_OUT_L. Therefore, the accuracy of the data is improved, and thus the user experience is improved.

[0050] In one embodiment, as Figures 1 to 2As shown, the first pin of the first amplifier A1, the second end of the tenth resistor R10, the second end of the seventh capacitor C7, and the second end of the eighth resistor R8 are all connected to the eleventh pin of the control chip U1.

[0051] In this embodiment, as Figures 1 to 2 shown, the audio amplification circuit 12 is connected to the control circuit 15, that is, the first pin of the first amplifier A1, the second end of the tenth resistor R10, the second end of the seventh capacitor C7, and the second end of the eighth resistor R8 are all connected to the eleventh pin of the control chip U1.

[0052] The audio amplification circuit 12 receives two channels of analog audio data through the digital-to-analog conversion circuit 13, that is, the analog audio data includes the first analog audio data L_IN and the second analog audio data R_IN; the first analog audio data L_IN is amplified through the seventh resistor R7, the first amplifier A1, the fifth capacitor C5, the eighth resistor R8, the sixth capacitor C6, the ninth resistor R9, the tenth resistor R10, and the seventh capacitor C7 to obtain the first target audio data PH_OUT_L, and the first target audio data PH_OUT_L is sent to the eleventh pin of the control chip U1, and the control chip U1 sends the first target audio data PH_OUT_L to the headphone device 30 through its second pin.

[0053] Through the above embodiment, it can be seen that the audio amplification circuit 12 amplifies the first analog audio data L_IN of one channel through the seventh resistor R7, the first amplifier A1, the fifth capacitor C5, the eighth resistor R8, the sixth capacitor C6, the ninth resistor R9, the tenth resistor R10, and the seventh capacitor C7 to obtain the first target audio data PH_OUT_L, and sends it to the eleventh pin of the control chip U1, so that the control chip U1 sends the first target audio data PH_OUT_L to the headphone device 30 through its second pin. Therefore, the accuracy of the data is improved, and thus the user experience is improved.

[0054] In one embodiment, as Figures 1 to 2 shown, the audio amplification circuit 12 further includes an eleventh resistor R11, an eighth capacitor C8, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a ninth capacitor C9, and a tenth capacitor C10;

[0055] The first end of the eleventh resistor R11 is connected to the digital-to-analog conversion circuit 13, and the second end of the eleventh resistor R11 is connected to the fifth pin of the first amplifier A1 and the second end of the eighth capacitor C8; the sixth pin of the first amplifier A1 is connected to the second end of the thirteenth resistor R13, the first end of the fourteenth resistor R14, and the first end of the ninth capacitor C9, and the seventh pin of the first amplifier A1 is connected to the second end of the fourteenth resistor R14, the second end of the ninth capacitor C9, the first end of the twelfth resistor R12, and the control circuit 15; the first end of the eighth capacitor C8 is connected to the first end of the thirteenth resistor R13; the second end of the twelfth resistor R12 is connected to the first end of the tenth capacitor C10.

[0056] In this embodiment, as Figures 1 to 2 shown, the specification of the eleventh resistor R11 can be 1.2K; the specification of the eighth capacitor C8 can be 102 (COG); the specification of the thirteenth resistor R13 can be 4.99K; the model of the first amplifier A1 can be SGM8262-2; the specification of the fourteenth resistor R14 can be 1K; the specification of the ninth capacitor C9 can be 22P (COG); the specification of the tenth capacitor C10 can be 104, and the specification of the twelfth resistor R12 can be 10R.

[0057] Among them, the first ends of the eighth capacitor C8, the thirteenth resistor R13, and the tenth capacitor C10 are all grounded; that is, the second end of the eleventh resistor R11 and the fifth pin of the first amplifier A1 are grounded through the eighth capacitor C8, the sixth pin of the first amplifier A1, the first end of the fourteenth resistor R14, and the first end of the ninth capacitor C9 are grounded through the thirteenth resistor R13, and the seventh pin of the first amplifier A1, the second end of the fourteenth resistor R14, and the second end of the ninth capacitor C9 are grounded through the twelfth resistor R12 and the tenth capacitor C10.

[0058] The audio amplification circuit 12 receives two-channel analog audio data through the digital-to-analog conversion circuit 13, that is, the analog audio data includes the first analog audio data L_IN and the second analog audio data R_IN; the second analog audio data R_IN is amplified through the eleventh resistor R11, the first amplifier A1, the eighth capacitor C8, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the ninth capacitor C9, and the tenth capacitor C10 to obtain the second target audio data PH_OUT_R, and the second target audio data PH_OUT_R is sent to the control chip U1.

[0059] From the above embodiments, it can be seen that the audio amplification circuit 12 amplifies the second analog audio data R_IN of the other path through the eleventh resistor R11, the first amplifier A1, the eighth capacitor C8, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the ninth capacitor C9 and the tenth capacitor C10 to obtain the second target audio data PH_OUT_R, and sends it to the control chip U1 for subsequent targeted processing according to the second target audio data PH_OUT_R. Therefore, the accuracy of the data is improved, and thus the user experience is improved.

[0060] In one embodiment, as Figures 1 to 2 shown, the 7th pin of the first amplifier A1, the second end of the fourteenth resistor R14, the second end of the ninth capacitor C9 and the first end of the twelfth resistor R12 are all connected to the 9th pin of the control chip U1.

[0061] In this embodiment, as Figures 1 to 2 shown, the audio amplification circuit 12 is connected to the control circuit 15, that is, the 7th pin of the first amplifier A1, the second end of the fourteenth resistor R14, the second end of the ninth capacitor C9 and the first end of the twelfth resistor R12 are all connected to the 9th pin of the control chip U1.

[0062] The audio amplification circuit 12 receives two paths of analog audio data through the digital-to-analog conversion circuit 13, that is, the analog audio data includes the first analog audio data L_IN and the second analog audio data R_IN; the second analog audio data R_IN is amplified through the eleventh resistor R11, the first amplifier A1, the eighth capacitor C8, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the ninth capacitor C9 and the tenth capacitor C10 to obtain the second target audio data PH_OUT_R, and the second target audio data PH_OUT_R is sent to the 9th pin of the control chip U1, and the control chip U1 sends the second target audio data PH_OUT_R to the headphone device 30.

[0063] Through the above embodiments, it can be seen that the audio amplification circuit 12 amplifies the second analog audio data R_IN of the other path through the eleventh resistor R11, the first amplifier A1, the eighth capacitor C8, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the ninth capacitor C9 and the tenth capacitor C10 to obtain the second target audio data PH_OUT_R, and sends it to the 9th pin of the control chip U1, so that the control chip U1 sends the second target audio data PH_OUT_R to the headphone device 30 through its 3rd pin. Therefore, the accuracy of the data is improved, and the user experience is further improved.

[0064] In one embodiment, as Figures 1 to 2 shown, the connection circuit 14 includes a USB chip USB1, an eleventh capacitor C11, a thirteenth resistor R13 and a fourteenth resistor R14;

[0065] The A4 pin, A9 pin, B4 pin and B9 pin of the USB chip USB1 are all connected to the first end of the eleventh capacitor C11 and the mute circuit 11; the A5 pin of the USB chip USB1 is connected to the first end of the thirteenth resistor R13; the B5 pin of the USB chip USB1 is connected to the first end of the fourteenth resistor R14; the A6 pin, A7 pin, B6 pin and B7 pin of the USB chip USB1 are connected to the digital-to-analog conversion circuit 13.

[0066] In this embodiment, as Figures 1 to 2 shown, the model of the interface corresponding to the USB chip USB1 can be TYPE-C_2.1MM, that is, the inner diameter of the plug of the interface corresponding to the USB chip is 2.1MM + 0.05MM (millimeter) size USBTYPE-C standard interface; the specification of the eleventh capacitor C11 can be 226 / 10V; the specification of the thirteenth resistor R13 can be 5.1K; the model of the fourteenth resistor R14 can be 5.1K.

[0067] Among them, the second ends of the eleventh capacitor C11, the thirteenth resistor R13 and the fourteenth resistor R14 are all grounded; that is, the A4 pin, A9 pin, B4 pin and B9 pin of the USB chip USB1 are all grounded through the eleventh capacitor C11, the A5 pin of the USB chip USB1 is grounded through the thirteenth resistor R13, and the B5 pin of the USB chip USB1 is grounded through the fourteenth resistor R14. The A1 pin, A12 pin, B1 pin and B12 pin of the USB chip USB1 are all grounded.

[0068] The input device 20 is connected to the mute circuit 11 through the A4 pin, A9 pin, B4 pin, and B9 pin of the USB chip USB1 to supply the operating power to the mute circuit 11; the input device 20 is connected to the digital-to-analog conversion circuit 13 through the A6 pin, A7 pin, B6 pin, and B7 pin of the USB chip USB1 to send the initial audio data to the digital-to-analog conversion circuit 13.

[0069] The connection circuit 14 further includes a connecting wire for connecting the input device 20 to the mute circuit 11 and the input device 20 to the digital-to-analog conversion circuit 13. The connecting wire is adapted to the corresponding interface of the USB chip USB1, that is, the type of the connecting wire is a data cable with a TYPE-C 2.1MM standard.

[0070] Through the above embodiments, it can be seen that the connection circuit 14 connects the input device 20 to the mute circuit 11 and the input device 20 to the digital-to-analog conversion circuit 13 to achieve data communication, ensuring the accuracy of the data, and thus improving the user experience.

[0071] In one embodiment, as Figures 1 to 2 shown, the A4 pin, A9 pin, B4 pin, and B9 pin of the USB chip USB1 are all connected to the first end of the first resistor R1, the emitter of the first triode Q1, the first end of the second resistor R2, and the positive pole of the first diode D1.

[0072] In this embodiment, as Figures 1 to 2 shown, the input device 20 is connected to the first end of the first resistor R1, the emitter of the first triode Q1, the first end of the second resistor R2, and the positive pole of the first diode D1 through the connecting wire and the A4 pin, A9 pin, B4 pin, and B9 pin of the USB chip USB1 to supply the operating power to the mute circuit 11.

[0073] Through the above embodiments, it can be seen that the input device 20 is connected to the first end of the first resistor R1, the emitter of the first triode Q1, the first end of the second resistor R2, and the positive pole of the first diode D1 through the connecting wire and the A4 pin, A9 pin, B4 pin, and B9 pin of the USB chip USB1 to supply the operating power to the mute circuit 11, providing a basis for the mute circuit 11 to generate a mute detection signal subsequently.

[0074] The above are only the specific embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.

Claims

1. A silence detection device, characterized in that: It includes a decoding headphone amplifier device, an input device and a headphone device; the decoding headphone amplifier device includes a mute circuit, an audio amplifier circuit, a digital-to-analog conversion circuit, a connection circuit and a control circuit; the mute circuit is connected to the connection circuit and also to the control circuit; the audio amplifier circuit is connected to the digital-to-analog conversion circuit and also to the control circuit; the digital-to-analog conversion circuit is connected to the input device through the connection circuit; the control circuit is also connected to the headphone device; The input device is used to send initial audio data to the connection circuit and provide power for use; the connection circuit is used to connect the digital-to-analog conversion circuit and the input device, and the mute circuit and the input device to transmit the initial audio data and the power for use; the digital-to-analog conversion circuit is used to receive the initial audio data through the connection circuit, and perform digital-to-analog conversion on the initial audio data to obtain analog audio data to send to the audio amplification circuit; the mute circuit is used to obtain the power for use through the connection circuit, and based on the power for use, generate a corresponding mute detection signal when detecting that the connection circuit is disconnected or connected to the input device, and send the mute detection signal to the control circuit; the audio amplification circuit is used to receive the analog audio data, and amplify the analog audio data to obtain target audio data to send to the control circuit; the control circuit is used to receive the mute detection signal, perform mute control processing according to the mute detection signal, and send the received target audio data to the headphone device; the headphone device is used to play the target audio data.

2. The device according to claim 1, characterized in that The mute circuit includes a first resistor, a second resistor, a first diode, a first capacitor, a third resistor, a first triode, a second triode, a second capacitor, a third triode, a fourth resistor, a fifth resistor and a sixth resistor; The first end of the first resistor is connected to the connecting circuit, the emitter of the first transistor, the first end of the second resistor and the anode of the first diode, and the second end of the first resistor is connected to the anode of the second capacitor and the first end of the third resistor; the base of the first transistor is connected to the second end of the third resistor, the collector of the first transistor is connected to the first end of the sixth resistor, the collector of the second transistor and the base of the third transistor; the second end of the second resistor is connected to the base of the second transistor; the emitter of the second transistor is connected to the cathode of the first diode, the anode of the first capacitor and the control circuit; the collector of the third transistor is connected to the first end of the fourth resistor, the first end of the fifth resistor and the control circuit.

3. The device according to claim 2, characterized in that The control circuit includes a control chip, a third capacitor and a fourth capacitor; the second pin and the third pin of the control chip are connected to the headphone device, the fourth pin and the fourteenth pin of the control chip are connected to the mute circuit, the ninth pin and the eleventh pin of the control chip are connected to the audio amplifier circuit, the thirteenth pin of the control chip is connected to the first end of the fourth capacitor, and the fourteenth pin of the control chip is also connected to the first end of the third capacitor.

4. The device according to claim 3, characterized in that The 4th pin of the control chip is connected to the collector of the third transistor, the first end of the fourth resistor and the first end of the fifth resistor; the 14th pin of the control chip is connected to the cathode of the first diode, the emitter of the second transistor and the anode of the first capacitor.

5. The device according to claim 3, characterized in that The audio amplifier circuit includes a seventh resistor, a first amplifier, a fifth capacitor, an eighth resistor, a sixth capacitor, a ninth resistor, a tenth resistor and a seventh capacitor; The first end of the seventh resistor is connected to the digital-to-analog conversion circuit, and the second end of the seventh resistor is connected to the third pin of the first amplifier and the second end of the sixth capacitor; the second pin of the first amplifier is connected to the second end of the ninth resistor, the first end of the tenth resistor and the first end of the seventh capacitor, and the first pin of the first amplifier is connected to the second end of the tenth resistor, the second end of the seventh capacitor, the second end of the eighth resistor and the control circuit; the first end of the sixth capacitor is connected to the first end of the ninth resistor; and the first end of the eighth resistor is connected to the second end of the fifth capacitor.

6. The device according to claim 5, characterized in that The first pin of the first amplifier, the second end of the tenth resistor, the second end of the seventh capacitor and the second end of the eighth resistor are all connected to the 11th pin of the control chip.

7. The device according to claim 5, characterized in that The audio amplifier circuit further includes an eleventh resistor, an eighth capacitor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a ninth capacitor and a tenth capacitor; The first end of the eleventh resistor is connected to the digital-to-analog conversion circuit, and the second end of the eleventh resistor is connected to the 5th pin of the first amplifier and the second end of the eighth capacitor; the 6th pin of the first amplifier is connected to the second end of the thirteenth resistor, the first end of the fourteenth resistor and the first end of the ninth capacitor, and the 7th pin of the first amplifier is connected to the second end of the fourteenth resistor, the second end of the ninth capacitor, the first end of the twelfth resistor and the control circuit; the first end of the eighth capacitor is connected to the first end of the thirteenth resistor; and the second end of the twelfth resistor is connected to the first end of the tenth capacitor.

8. The device according to claim 7, characterized in that The seventh pin of the first amplifier, the second end of the fourteenth resistor, the second end of the ninth capacitor and the first end of the twelfth resistor are all connected to the ninth pin of the control chip.

9. The device according to claim 2, characterized in that The connecting circuit includes a USB chip, an eleventh capacitor, a thirteenth resistor and a fourteenth resistor; The A4 pin, A9 pin, B4 pin and B9 pin of the USB chip are all connected to the first end of the eleventh capacitor and the mute circuit; the A5 pin of the USB chip is connected to the first end of the thirteenth resistor; the B5 pin of the USB chip is connected to the first end of the fourteenth resistor; the A6 pin, A7 pin, B6 pin and B7 pin of the USB chip are connected to the digital-to-analog conversion circuit.

10. The device according to claim 9, characterized in that The A4 pin, the A9 pin, the B4 pin and the B9 pin of the USB chip are all connected to the first end of the first resistor, the emitter of the first transistor, the first end of the second resistor and the anode of the first diode.

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