Display panel and display device including the same

Abstract

Disclosed are a display panel and a display device including the same, the display panel including: pixels each including a light emitting element and a pixel circuit connected to the light emitting element; data lines arranged in the plurality of columns, in which the data lines provide data signals to the pixel circuits; a data pad connected to the data line; a first protection circuit connected between a first data line among the data lines and a first gate power line to which a first gate power voltage is applied; and a second protection circuit connected between a second one of the data lines and a second gate power line to which a second gate power voltage is applied.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0119947, filed on September 8, 2023, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present utility model relate to a display panel and a display device including the display panel. Background art

[0004] A display device generally includes a data driver, a gate driver, and pixels. The data driver may provide a data signal to the pixels through data lines. The gate driver may generate a gate signal using an external start signal and a clock signal, and sequentially provide the gate signal to the pixels through gate lines. Each of the pixels may record a corresponding data signal in response to the gate signal and emit light in response to the data signal. Summary of the utility model

[0005] In a display device, when static electricity flows from the outside into the display device, the internal circuits of the display device may malfunction or be damaged due to the static electricity. Therefore, an electrostatic discharge circuit may be electrically connected to the data lines to prevent the flow of static electricity therein.

[0006] However, when a constant bias voltage is applied for a long time to operate the electrostatic discharge circuit, corrosion of the circuits in the display panel may be accelerated due to moisture penetration.

[0007] Embodiments of the present utility model provide a display panel and a display device including the display panel that can effectively protect internal circuits by including an electrostatic discharge circuit capable of reducing corrosion of circuits caused by a bias voltage.

[0008] The object of the present disclosure is not limited to the foregoing, and other objects not described herein will be clearly understood by those skilled in the art from the following description.

[0009] A display panel according to an embodiment of the present utility model includes: pixels, each including a light - emitting element and a pixel circuit for driving the light - emitting element; data lines arranged in a plurality of columns, wherein the data lines provide a data signal to the pixel circuits; data pads connected to the data lines; a first protection circuit (also referred to as a "first - type protection circuit") connected between a first data line (also referred to as a "first - type data line") among the data lines and a first gate power line to which a first gate power voltage is applied; and a second protection circuit (also referred to as a "second - type protection circuit") connected between a second data line (also referred to as a "second - type data line") among the data lines and a second gate power line to which a second gate power voltage is applied.

[0010] In an embodiment, the pixel circuit may include a first transistor connected between a first power supply and a light-emitting element, a second transistor connected between a corresponding data line in the data lines and the first transistor, a first pixel node connected between the first transistor and the second transistor, and a second pixel node connected between the first transistor and the light-emitting element.

[0011] In an embodiment, the semiconductor layer of the transistors constituting the first protection circuit and the second protection circuit may be provided in the same layer as the semiconductor layer of the first transistor constituting the pixel circuit.

[0012] In an embodiment, the first gate power voltage may have a voltage level higher than that of the second gate power voltage.

[0013] In an embodiment, the first protection circuit may include a first transistor, and the second protection circuit may include a second transistor, where the first transistor may include: a gate electrode; a first electrode connected to a first gate power line and electrically connected to the gate electrode of the first transistor; and a second electrode connected to a first data line, and the second transistor may include: a gate electrode electrically connected to a second data line; a first electrode connected to a second gate power line, and a second electrode connected to the second data line.

[0014] In an embodiment, the first data line may be an odd-numbered data line in the data lines, and the second data line may be an even-numbered data line in the data lines.

[0015] In an embodiment, the display panel may include a plurality of first protection circuits and a plurality of second protection circuits. The plurality of first protection circuits include the first protection circuit, the plurality of second protection circuits include the second protection circuit. A plurality of consecutive first data lines in the data lines may be connected to the plurality of first protection circuits, a plurality of consecutive second data lines in the data lines may be connected to the plurality of second protection circuits, and the plurality of consecutive first data lines and the plurality of consecutive second data lines may be disposed adjacent to each other.

[0016] In an embodiment, the first protection circuit may further include a third transistor, and the second protection circuit may further include a fourth transistor, where the third transistor may include: a gate electrode; a first electrode connected to the second electrode of the first transistor; and a second electrode connected to the first gate power line, and the fourth transistor may include: a gate electrode; a first electrode connected to the second electrode of the second transistor; and a second electrode connected to the second gate power line.

[0017] In an embodiment, the first data line may be an odd-numbered data line in the data lines, and the second data line may be an even-numbered data line in the data lines.

[0018] In an embodiment, the display panel may include a plurality of first protection circuits and a plurality of second protection circuits. The plurality of first protection circuits include the first protection circuit, and the plurality of second protection circuits include the second protection circuit. A plurality of consecutive first data lines in the data lines may be connected to the plurality of first protection circuits, a plurality of consecutive second data lines in the data lines may be connected to the plurality of second protection circuits, and the plurality of consecutive first data lines and the plurality of consecutive second data lines may be arranged adjacent to each other.

[0019] The display panel according to an embodiment of the present invention includes: pixels, each including a light-emitting element and a pixel circuit connected to the light-emitting element; data lines, arranged in a plurality of columns, wherein the data lines supply data signals to the pixel circuits; data pads, connected to the data lines; and protection circuits, connected to the data lines, wherein each of the protection circuits includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes: a gate electrode; a first electrode, connected to a first gate power line and electrically connected to the gate electrode of the first transistor; and a second electrode, connected to a corresponding data line in the data lines. The second transistor includes: a gate electrode; a first electrode, connected to the second electrode of the first transistor; and a second electrode, electrically connected to the gate electrode of the second transistor and connected to the first gate power line. The third transistor includes: a gate electrode; a first electrode, connected to a second gate power line; and a second electrode, connected to a corresponding data line in the data lines and electrically connected to the gate electrode of the third transistor. And the fourth transistor includes: a gate electrode; a first electrode, connected to the second electrode of the third transistor and connected to the second gate power line; and a second electrode, electrically connected to the gate electrode of the fourth transistor.

[0020] In an embodiment, the pixel circuit may include a first transistor connected between a first power supply and the light-emitting element, a second transistor connected between a corresponding data line in the data lines and the first transistor, a first pixel node connected between the first transistor and the second transistor, and a second pixel node connected between the first transistor and the light-emitting element.

[0021] In an embodiment, the semiconductor layer of the transistor constituting the protection circuit may be provided in the same layer as the semiconductor layer of the first transistor constituting the pixel circuit.

[0022] A display device according to an embodiment of the present invention includes: a display panel including pixels; and a data driver applying data signals to the pixels, wherein the display panel includes: data lines arranged in a plurality of columns, wherein the data lines supply data signals to the pixels; data pads connected to the data lines; a first protection circuit connected between a first data line among the data lines and a first gate power line to which a first gate power voltage is applied; and a second protection circuit connected between a second data line among the data lines and a second gate power line to which a second gate power voltage is applied.

[0023] In an embodiment, the display device may further include: a gate driver supplying gate signals to the pixels based on a start signal and a clock signal; a start signal line transmitting the start signal to the gate driver; and a clock signal line transmitting the clock signal to the gate driver.

[0024] In an embodiment, each of the pixels may include a light-emitting element and a pixel circuit connected to the light-emitting element, and the pixel circuit may include a first transistor connected between a first power supply and the light-emitting element, a second transistor connected between a corresponding data line among the data lines and the first transistor, a first pixel node connected between the first transistor and the second transistor, and a second pixel node connected between the first transistor and the light-emitting element.

[0025] In an embodiment, a semiconductor layer of a transistor constituting the first protection circuit and the second protection circuit may be provided in the same layer as a semiconductor layer of the first transistor constituting the pixel circuit.

[0026] According to an embodiment of the present invention, a display panel capable of effectively protecting an internal circuit by including an electrostatic discharge circuit capable of reducing corrosion of a circuit caused by a bias voltage and a display device including the display panel may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0028] Figure 2 is a circuit diagram showing an embodiment of a pixel included in Figure 1 the display device.

[0029] Figure 3 is a block diagram showing an embodiment of a gate driver included in Figure 1 the display device.

[0030] Figure 4 is a timing diagram showing an embodiment of a signal measured in Figure 3 the gate driver.

[0031] Figure 5 It is a block diagram showing an embodiment of a protection circuit according to an embodiment of the present invention.

[0032] Figure 6 It is a block diagram showing Figure 5 an embodiment of a protection circuit.

[0033] Figure 7 It is a block diagram showing an embodiment of a protection circuit according to an embodiment of the present invention.

[0034] Figure 8 It is a block diagram showing Figure 7 an embodiment of a protection circuit.

[0035] Figure 9 It is a block diagram showing a protection circuit included in Figure 1 a display device.

[0036] Figure 10 It is a block diagram showing Figure 9 an embodiment of a protection circuit.

[0037] Figure 11 It is a block diagram showing a protection circuit included in Figure 1 a display device.

[0038] Figure 12 It is a block diagram showing Figure 11 an embodiment of a protection circuit.

[0039] Figure 13 It is a block diagram showing a protection circuit included in Figure 1 a display device.

[0040] Figure 14 It is a block diagram showing Figure 13 an embodiment of a protection circuit.

[0041] Figure 15 It is a block diagram showing a display panel including Figure 6 and Figure 8 an embodiment of a protection circuit.

[0042] Figure 16 It is a block diagram showing a display panel including Figure 6 and Figure 8 another embodiment of a protection circuit.

[0043] Figure 17 It is a block diagram showing a display panel including Figure 10 and Figure 12 an embodiment of a protection circuit.

[0044] Figure 18is a block diagram showing another embodiment of a display panel including Figure 10 and Figure 12 a protection circuit.

[0045] Figure 19 is a block diagram showing an embodiment of a display panel including Figure 14 a protection circuit. DETAILED DESCRIPTION

[0046] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals always denote like elements.

[0047] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0048] Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" with another element therebetween. The terms used in this specification are for the purpose of describing embodiments and are not intended to limit the present invention.

[0049] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a", "an", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural, unless the context clearly dictates otherwise. Thus, a reference to "an" element followed by a reference to "the" element includes one element and a plurality of elements. For example, "element" has the same meaning as "at least one element", unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "a" or "an". "At least one of X, Y, and Z" and "at least one selected from X, Y, and Z" can be construed as any combination of X, Y, Z, or two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, and ZZ). "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and / or "comprising" or "includes" and / or "including" specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0050] Here, terms such as first, second, etc. may be used to describe various components, but these components are not limited to these terms. These terms are only used to distinguish one component element from another. Thus, within the scope of the disclosure herein, a first component may be referred to as a second component.

[0051] For descriptive purposes, spatial relative terms such as "below", "above", etc. may be used to describe the relationship of one element or feature to another (other) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatial relative terms are intended to include different directions in use, operation, and / or manufacture. For example, if the device shown in the drawings is flipped, an element depicted as being "below" other elements or features may be positioned "above" the other elements or features. Thus, in an embodiment, the term "below" can include both the upward and downward directions. Additionally, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative terms used herein should be interpreted accordingly.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] Various embodiments are described with reference to the accompanying drawings of idealized embodiments. Accordingly, it will be appreciated that shapes may vary depending, for example, on tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, and should be construed as including, for example, changes in shape resulting from manufacturing. Thus, the shapes shown in the drawings may not depict the actual shape of the regions of the device, and the embodiments are not limited thereto.

[0054] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0055] Reference Figure 1 , embodiments of the display device DD may include a display panel DP, a gate driver GDV (or gate driver circuit GDV), a data driver DDV (or data driver circuit DDV), and a timing controller TC (or timing controller circuit TC).

[0056] The display panel DP may include a substrate SUB. The substrate SUB (or the display panel DP) may include a display area DA for displaying an image and a non-display area NDA (e.g., an edge area of the display area DA) around the display area DA. Pixels PXL may be provided on the display panel DP. The gate driver GDV, pads PAD, signal lines, etc. may be provided in the non-display area NDA. The non-display area NDA may include a pad area A_PAD provided on one side of the display area DA. The pads PAD may be provided in the pad area A_PAD.

[0057] The display panel DP may include gate lines S1 to Sn (where n is a positive integer), data lines D1 to Dm (where m is a positive integer), pixels PXL, and pads PAD. The gate lines S1 to Sn may extend in a first direction DR1 and be arranged in sequence in a second direction DR2 intersecting the first direction DR1. The data lines D1 to Dm may extend in the second direction DR2 and be arranged in sequence in the first direction DR1. Each of the pixels PXL may be connected to a corresponding one of the gate lines S1 to Sn and a corresponding one of the data lines D1 to Dm. The pad PAD may be connected to the signal lines of the display panel DP (e.g., the gate lines S1 to Sn and the data lines D1 to Dm) and transmit signals provided from the outside to the signal lines.

[0058] The pad PAD may include a gate pad PAD_G, a data pad PAD_D, and a power pad PAD_P.

[0059] The gate pad PAD_G may be configured to transmit a gate control signal to the gate driver GDV through a gate control line GCL. The gate pad PAD_G may be configured to transmit a gate power voltage to the gate driver GDV through a gate power line GPL. The gate control signal may include a start signal (or start pulse), a clock signal, etc. The gate control signal may be provided from a timing controller TC. The gate power voltage may be a power voltage or a driving voltage for operating the gate driver GDV. The gate power voltage may be provided from a power supply (not shown) or a data driver DDV. The gate power voltage may include a first gate power voltage and a second gate power voltage. In an embodiment, for example, the first gate power voltage may be at a conductive level that turns on at least one transistor included in the pixel PXL. In an embodiment, for example, the second gate power voltage may be at a cut-off level that turns off at least one transistor included in the pixel PXL. However, the embodiments of the present utility model are not limited thereto, and the first gate power voltage may be at a cut-off level, and the second gate power voltage may be at a conductive level.

[0060] The data pad PAD_D may be configured to transmit data signals (or data voltages) to the data lines D1 to Dm. The data signals may be provided from a data driver DDV.

[0061] The power pad PAD_P can transmit a first power voltage ELVDD to the pixel PXL through a first power line ELVDDL. The power pad PAD_P can transmit a second power voltage ELVSS to the pixel PXL through a second power line ELVSSL. The first power voltage ELVDD and the second power voltage ELVSS can be power voltages required to operate the pixel PXL, and can be provided from a power source (not shown). The first power voltage ELVDD can have a higher voltage level than the second power voltage ELVSS.

[0062] The protection circuit PC can be disposed in the non-display area NDA and / or the display area DA of the display panel DP. In an embodiment, for example, the protection circuit PC can be disposed adjacent to the pad area A_PAD in the non-display area NDA. The protection circuit PC can be connected (e.g., electrically connected) to at least one selected from the data lines D1 to Dm.

[0063] The protection circuit PC can be connected to at least one selected from the data lines D1 to Dm to which a pulse-shaped signal or an alternating current signal is applied, and can discharge static electricity (e.g., a surge) flowing from the outside into the data lines D1 to Dm, and protect the internal circuit (e.g., the pixel PXL) from the influence of static electricity. That is, the protection circuit PC can be an electrostatic discharge (ESD) circuit (or an ESD protection circuit).

[0064] In an embodiment, as Figure 1 shown, the protection circuit PC can be disposed adjacent to the pad area A_PAD, but the present invention is not limited thereto. In an embodiment, for example, the protection circuit PC can be disposed in the pad area A_PAD.

[0065] The gate driver GDV can generate a gate signal based on a gate control signal, and provide the gate signal to the gate lines S1 to Sn.

[0066] According to an embodiment, the gate driver GDV can be formed on the display panel DP while being integrated with the pixel PXL. However, the embodiments of the present invention are not limited thereto. In an embodiment, for example, the gate driver GDV can be implemented as an integrated circuit separated from the display panel DP, and mounted on the panel driver circuit PDC. In an embodiment, as Figure 1 shown, the gate driver GDV can be disposed in the non-display area NDA, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the gate driver GDV can be disposed in a distributed manner in the display area DA (e.g., between the pixels PXL).

[0067] The data driver DDV can receive a data control signal and image data from the timing controller TC, and generate a data signal (or data voltage) corresponding to the image data. The data driver DDV can supply the generated data signal to the display panel DP. In an embodiment, for example, the data driver DDV can generate a data signal corresponding to the gray level value in the image data, and supply the data signal to the data lines D1 to Dm in units of pixel rows.

[0068] The data driver DDV can be mounted on the panel driver circuit PDC, connected to the timing controller TC, and connected to the data lines D1 to Dm through the data pads PAD_D.

[0069] The timing controller TC can control the gate driver GDV and the data driver DDV. The timing controller TC can receive input image data (e.g., RGB data) and a control signal from an external device (e.g., a graphics processor, a set-top box, etc.), generate a gate control signal and a data control signal, and generate image data by converting the input image data. The control signal can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a reference clock signal, etc. In an embodiment, for example, the timing controller TC can convert the input image data into image data having a format corresponding to the pixel arrangement in the display panel DP. The timing controller TC can be mounted on the panel driver circuit PDC.

[0070] In an embodiment, as Figure 1 shown, the data driver DDV and the timing controller TC can be implemented as separate integrated circuits, but the present invention is not limited thereto. In an embodiment, for example, the data driver DDV and the timing controller TC can be implemented as one integrated circuit.

[0071] Figure 2 is a circuit diagram showing an embodiment of a pixel included in Figure 1 the display device. Figure 1 The pixels PXL shown in

[0072] can be substantially the same or similar to each other. For ease of description, the pixel PXLij provided in the i-th pixel row (where i is an integer greater than or equal to 1 and less than or equal to n) and the j-th pixel column (where j is an integer greater than or equal to 1 and less than or equal to m) will be described.

[0072] Refer to Figure 1 and Figure 2 . An embodiment of the pixel PXLij can include a pixel circuit PXC and a light-emitting element LD.

[0073] The pixel circuit PXC can include at least two switching elements (e.g., transistors) and at least one storage element (e.g., a capacitor). Refer to Figure 2, in an embodiment, the pixel circuit PXC may include a first pixel transistor Ta (or driving transistor Ta), a second pixel transistor Tb (or switching transistor Tb), and a storage capacitor Cst. However, the embodiments of the present invention are not limited thereto.

[0074] The light-emitting element LD may generate light of a specific brightness in response to the amount of electric current provided from the first pixel transistor Ta. The light-emitting element LD may include a first electrode and a second electrode. The first electrode of the light-emitting element LD may be connected to the second pixel node Nb. The second electrode of the light-emitting element LD may be connected to the second power line ELVSSL to which a second power voltage ELVSS is applied. In an embodiment, the first electrode may be an anode, and the second electrode may be a cathode. According to an embodiment, the first electrode may be a cathode, and the second electrode may be an anode.

[0075] The first electrode of the first pixel transistor Ta may be connected to the first power line ELVDDL to which a first power voltage ELVDD is applied (that is, the first electrode of the first pixel transistor Ta may be connected to a first power supply). The second electrode of the first pixel transistor Ta may be connected to the first electrode of the light-emitting element LD (or the second pixel node Nb). The gate electrode of the first pixel transistor Ta may be connected to the first pixel node Na. In an embodiment, the first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0076] The first pixel transistor Ta may control the amount of electric current flowing to the light-emitting element LD in response to the voltage of the first pixel node Na. In such an embodiment, when the voltage between the first pixel node Na and the second pixel node Nb (for example, the gate-source voltage) is higher than the threshold voltage, the first pixel transistor Ta may be turned on.

[0077] The first electrode of the second pixel transistor Tb may be connected to the j-th data line Dj, and the second electrode of the second pixel transistor Tb may be connected to the first pixel node Na (or the gate electrode of the first pixel transistor Ta). The gate electrode of the second pixel transistor Tb may be connected to the i-th gate line Si. When the i-th gate signal SCi (or the i-th gate signal SCi at a conductive level) is provided to the i-th gate line Si, the second pixel transistor Tb may be turned on, and the data voltage Vdata may be transmitted from the j-th data line Dj to the first pixel node Na.

[0078] The storage capacitor Cst can be connected between the first pixel node Na and the second pixel node Nb. The storage capacitor Cst can be charged during one frame with a data voltage corresponding to the data signal provided to the first pixel node Na. Accordingly, the storage capacitor Cst can store a voltage corresponding to the voltage difference between the first pixel node Na and the second pixel node Nb. It can be determined whether the first pixel transistor Ta is turned on or off based on the voltage stored in the storage capacitor Cst.

[0079] In an embodiment of the present invention, the circuit structure of the pixel PXL is not limited to Figure 2 . In an embodiment, for example, the light-emitting element LD can be disposed between the first power line ELVDDL and the first electrode of the first pixel transistor Ta.

[0080] In an embodiment, as Figure 2 shown, the transistor can be an n-channel metal oxide semiconductor (NMOS) transistor, but the present invention is not limited thereto. In an embodiment, for example, at least one selected from the first pixel transistor Ta and the second pixel transistor Tb can be implemented as a p-channel metal oxide semiconductor (PMOS) transistor. In an embodiment, Figure 2 the first pixel transistor Ta and the second pixel transistor Tb shown in

[0081] Figure 3 can be a thin film transistor including at least one selected from an oxide semiconductor, an amorphous silicon semiconductor, and a polycrystalline silicon semiconductor. Figure 1 is a block diagram showing an embodiment of a gate driver included in the Figure 4 is a timing diagram showing an embodiment of a signal measured in the Figure 3 gate driver.

[0082] Referring to Figure 3 , an embodiment of the gate driver GDV can include a plurality of stages ST1 to STn.

[0083] The stages ST1 to STn can respectively provide gate signals SC1 to SCn to the gate lines S1 to Sn.

[0084] Each of levels ST1 to STn may be connected to a first gate power line VGHL, a second gate power line VGLL, and a clock signal line CLKL (or multiple clock signal lines CLKL). Here, a first gate power voltage VGH may be applied to the first gate power line VGHL, and a second gate power voltage VGL may be applied to the second gate power line VGLL. The first gate power line VGHL and the second gate power line VGLL may be included in a gate power line GPL. The first gate power voltage VGH may have a high voltage level, and the second gate power voltage VGL may have a low voltage level. A clock signal CLK (or multiple clock signals CLK) may be applied to the clock signal line CLKL. As Figure 4 shown, the clock signal CLK may alternately have a conductive level ON (e.g., a high voltage level) and a cutoff level OFF (e.g., a low voltage level). A start signal FLM (or a start pulse FLM) may be applied to a start signal line FLML. As Figure 4 shown, the start signal FLM may have a pulse at the conductive level ON. The clock signal line CLKL and the start signal line FLML may be included in a gate control line GCL. In Figure 4 it, the conductive level ON is shown as being higher than the cutoff level OFF, but the present invention is not limited thereto. In an embodiment, for example, in the case where the transistors included in levels ST1 to STn are implemented as P-type transistors instead of N-type transistors, the conductive level ON may be lower than the cutoff level OFF. In such an embodiment, the conductive level ON may correspond to a low voltage level, and the cutoff level OFF may correspond to a high voltage level.

[0085] Each of levels ST1 to STn may be connected to the start signal line FLML or a carry line, and may generate a gate signal in response to the start signal FLM provided through the start signal line FLML or a previous gate signal (i.e., a carry signal) of the previous stage.

[0086] In an embodiment, for example, the first level ST1 may be connected to the start signal line FLML, and may generate a first gate signal SC1 corresponding to the start signal FLM. As Figure 4As shown, compared to the start signal FLM, the first gate signal SC1 may delay the clock signal CLK by half a cycle, but is not limited thereto. In an embodiment, for example, the second stage ST2 may receive the first gate signal SC1 (or the first carry signal corresponding to the first gate signal SC1) from the first stage ST1 through the first carry line CR1, and may generate a second gate signal SC2 corresponding to the first gate signal SC1. In an embodiment, for example, the third stage ST3 may receive the second gate signal SC2 (or the second carry signal corresponding to the second gate signal SC2) from the second stage ST2 through the second carry line CR2, and may generate a third gate signal SC3 corresponding to the second gate signal SC2. Similarly, the nth stage STn may receive the previous gate signal (or the (n - 1)th carry signal corresponding to the previous gate signal) from the previous stage (e.g., the (n - 1)th stage) through the (n - 1)th carry line CRn - 1, and may generate an nth gate signal SCn corresponding to the previous gate signal. In an embodiment, as Figure 4 shown, the stages ST1 to STn may generate (e.g., sequentially generate) the gate signals SC1 to SCn in response to the start signal FLM.

[0087] Figure 5 is a block diagram showing an embodiment of a protection circuit according to an embodiment of the present invention. For ease of description, the protection circuit PC will be described with reference to the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0088] Referring to Figure 1 and Figure 5 , the j-th data line Dj may connect the j-th data pad PAD_Dj and the pixel PXLij provided at the i-th pixel row and the j-th pixel column. The protection circuit PC may be connected to the j-th data line Dj.

[0089] In an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, a current (e.g., a current due to static electricity) may flow from the j-th data line Dj to the first gate power line VGHL, and the voltage at the j-th data line Dj may be reduced. In other words, the protection circuit PC may reduce a voltage higher than the first gate power voltage VGH.

[0090] In such an embodiment, a current (e.g., a current due to static electricity) may not flow from the first gate power line VGHL to the j-th data line Dj.

[0091] In such an embodiment, the voltage at the j-th data line Dj may be maintained below the first gate power voltage VGH through the protection circuit PC, and the pixel PXLij provided at the i-th pixel row and the j-th pixel column may be protected from static electricity.

[0092] Figure 6 is a block diagram showing Figure 5 an embodiment of a protection circuit.

[0093] Referring to Figure 1 、 Figure 5 and Figure 6 , an embodiment of the protection circuit PC may include the j-th transistor Tj.

[0094] In Figure 6 , the j-th transistor Tj is shown as a PMOS transistor, but the present invention is not limited thereto. In an embodiment, for example, the j-th transistor Tj may be implemented as an NMOS transistor.

[0095] The j-th data line Dj may be connected between the j-th data pad PAD_Dj and the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0096] The first electrode of the j-th transistor Tj may be connected to the j-th data line Dj at the j-th node Nj. The second electrode of the j-th transistor Tj may be connected to the first gate power line VGHL. The gate electrode of the j-th transistor Tj may be connected to the second electrode of the j-th transistor Tj. The j-th transistor Tj may be formed by the same process as the transistors of the pixel circuit PXC (see Figure 2 ). In an embodiment, for example, the semiconductor layer of the j-th transistor Tj constituting the pixel circuit PXC (see Figure 2 ) and the semiconductor layer of the first pixel transistor Ta (see Figure 2 ) may be provided in the same layer (or directly on the same layer as each other). When a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, the j-th transistor Tj may be turned on. In an embodiment, for example, the j-th transistor Tj may be turned on in response to the voltage difference between the gate electrode and the first electrode of the j-th transistor Tj. In this case, current may flow from the j-th data line Dj to the first gate power line VGHL, and the voltage of the j-th data line Dj may be reduced. That is, the j-th transistor Tj may reduce the voltage higher than the first gate power voltage VGH.

[0097] Figure 7 is a block diagram showing an embodiment of a protection circuit according to an embodiment of the present invention. For ease of description, the protection circuit PC will be described with reference to the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0098] Referring to Figure 1 and Figure 7, in an embodiment, the j-th data line Dj may connect the j-th data pad PAD_Dj and the pixel PXLij disposed at the i-th pixel row and the j-th pixel column. The protection circuit PC may be connected to the j-th data line Dj.

[0099] In an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to electrostatic charge, a current (e.g., a current due to electrostatic charge) may flow from the second gate power line VGLL to the j-th data line Dj, and the voltage at the j-th data line Dj may increase. In other words, the protection circuit PC may increase a voltage lower than the second gate power voltage VGL.

[0100] In such an embodiment, a current (e.g., a current due to electrostatic charge) may not flow from the j-th data line Dj to the second gate power line VGLL.

[0101] In an embodiment, the voltage at the j-th data line Dj may be maintained higher than the second gate power voltage VGL by the protection circuit PC, and the pixel PXLij disposed at the i-th pixel row and the j-th pixel column may be protected from electrostatic charge.

[0102] Figure 8 is a block diagram showing Figure 7 an embodiment of the protection circuit.

[0103] Referring to Figure 1 , Figure 7 and Figure 8 , an embodiment of the protection circuit PC may include the j-th transistor Tj.

[0104] In Figure 8 , the j-th transistor Tj is shown as a PMOS transistor, but the present invention is not limited thereto. In an embodiment, for example, the j-th transistor Tj may be an NMOS transistor.

[0105] The j-th data line Dj may be connected between the j-th data pad PAD_Dj and the pixel PXLij disposed at the i-th pixel row and the j-th pixel column.

[0106] The first electrode of the j-th transistor Tj may be connected to the j-th data line Dj at the j-th node Nj. The second electrode of the j-th transistor Tj may be connected to the second gate power line VGLL. The gate electrode of the j-th transistor Tj may be connected to the first electrode of the j-th transistor Tj. The j-th transistor Tj may be formed by the same process as the transistors of the pixel circuit PXC (see Figure 2 ). In an embodiment, for example, the semiconductor layer of the j-th transistor Tj and the first pixel transistor Ta (see Figure 2 ) constituting the pixel circuit PXC (see Figure 2) The semiconductor layers can be disposed in the same layer as each other (or directly on the same layer as each other).

[0107] When a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, the j-th transistor Tj can be turned on. In an embodiment, for example, the j-th transistor Tj can be turned on in response to a voltage difference between the gate electrode and the second electrode of the j-th transistor Tj. In this case, current can flow from the second gate power line VGLL to the j-th data line Dj, and the voltage of the j-th data line Dj can increase. That is, the j-th transistor Tj can increase a voltage lower than the second gate power voltage VGL.

[0108] Figure 9 is a block diagram showing an embodiment of a protection circuit included in Figure 1 the display device. For ease of description, the protection circuit PC will be described with reference to the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0109] Refer to Figure 1 and Figure 9 , in an embodiment, the j-th data line Dj can connect the j-th data pad PAD_Dj and the pixel PXLij provided at the i-th pixel row and the j-th pixel column. The protection circuit PC can be connected to the j-th data line Dj.

[0110] In an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, current (e.g., current due to static electricity) can flow from the j-th data line Dj to the first gate power line VGHL, and the voltage at the j-th data line Dj can decrease. In other words, the protection circuit PC can reduce a voltage higher than the first gate power voltage VGH.

[0111] In such an embodiment, current (e.g., current due to static electricity) can not flow from the first gate power line VGHL to the j-th data line Dj.

[0112] In an embodiment, the voltage at the j-th data line Dj can be maintained lower than the first gate power voltage VGH by the protection circuit PC, and the pixel PXLij provided at the i-th pixel row and the j-th pixel column can be protected from static electricity.

[0113] Figure 10 is a block diagram showing an embodiment of Figure 9 the protection circuit.

[0114] Refer to Figure 1 , Figure 9 and Figure 10, the protection circuit PC may include the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j).

[0115] In Figure 10 , each of the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j) is shown as a PMOS transistor, but is not limited thereto. In an embodiment, for example, at least one of the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j) may be implemented as an NMOS transistor.

[0116] The j-th data line Dj may be connected between the j-th data pad PAD_Dj and the pixel PXLij disposed at the i-th pixel row and the j-th pixel column.

[0117] The first electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the j-th data line Dj at the j-th node Nj. The second electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the first gate power line VGHL. The gate electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the second electrode of the (2j - 1)-th transistor T(2j - 1).

[0118] The first electrode of the 2j-th transistor T(2j) may be connected to the j-th data line Dj at the j-th node Nj. The second electrode of the 2j-th transistor T(2j) may be connected to the first gate power line VGHL. The gate electrode of the 2j-th transistor T(2j) may be connected to the second electrode of the 2j-th transistor T(2j). The first electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the first electrode of the 2j-th transistor T(2j).

[0119] In an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, the (2j - 1)-th transistor T(2j - 1) may be turned on. In an embodiment, for example, the (2j - 1)-th transistor T(2j - 1) may be turned on in response to the voltage difference between the gate electrode and the first electrode of the (2j - 1)-th transistor T(2j - 1). In this case, current may flow from the j-th data line Dj to the first gate power line VGHL, and the voltage of the j-th data line Dj may be reduced. That is, the (2j - 1)-th transistor T(2j - 1) may reduce the voltage higher than the first gate power voltage VGH.

[0120] In such an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, the 2j-th transistor T(2j) can be turned on. In an embodiment, for example, the 2j-th transistor T(2j) can be turned on in response to the voltage difference between the gate electrode and the first electrode of the 2j-th transistor T(2j). In this case, current can flow from the j-th data line Dj to the first gate power line VGHL, and the voltage of the j-th data line Dj can be reduced. That is, the 2j-th transistor T(2j) can reduce the voltage higher than the first gate power voltage VGH.

[0121] According to an embodiment, as described above, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, at least one transistor selected from the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j) can be turned on, and the reliability in removing static electricity can be improved.

[0122] Figure 11 is a block diagram showing an embodiment of a protection circuit included in Figure 1 the display device. For ease of description, the protection circuit PC will be described with reference to the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0123] Refer to Figure 1 and Figure 11 , in an embodiment, the j-th data line Dj can connect the j-th data pad PAD_Dj and the pixel PXLij provided at the i-th pixel row and the j-th pixel column. The protection circuit PC can be connected to the j-th data line Dj.

[0124] In an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, current (e.g., current due to static electricity) can flow from the second gate power line VGLL to the j-th data line Dj, and the voltage at the j-th data line Dj can increase. In other words, the protection circuit PC can increase the voltage lower than the second gate power voltage VGL.

[0125] In such an embodiment, current (e.g., current due to static electricity) may not flow from the j-th data line Dj to the second gate power line VGLL.

[0126] In an embodiment, the voltage at the j-th data line Dj can be maintained higher than the second gate power voltage VGL by the protection circuit PC, and the pixel PXLij provided at the i-th pixel row and the j-th pixel column can be protected from static electricity.

[0127] Figure 12 is a diagram showing Figure 11Block diagram of an implementation of a protection circuit.

[0128] Reference Figure 1 、 Figure 11 and Figure 12 , in an implementation, the protection circuit PC may include the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j).

[0129] In Figure 12 , the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j) are shown as PMOS transistors, but are not limited thereto. In an implementation, for example, the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j) may be implemented as NMOS transistors.

[0130] The j-th data line Dj may be connected between the j-th data pad PAD_Dj and the pixel PXLij disposed at the i-th pixel row and the j-th pixel column.

[0131] The first electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the j-th data line Dj at the j-th node Nj. The second electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the second gate power line VGLL. The gate electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the first electrode of the (2j - 1)-th transistor T(2j - 1).

[0132] The first electrode of the 2j-th transistor T(2j) may be connected to the j-th data line Dj at the j-th node Nj. The second electrode of the 2j-th transistor T(2j) may be connected to the second gate power line VGLL. The gate electrode of the 2j-th transistor T(2j) may be connected to the first electrode of the 2j-th transistor T(2j). The first electrode of the (2j - 1)-th transistor T(2j - 1) may be connected to the first electrode of the 2j-th transistor T(2j).

[0133] In an implementation, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to electrostatic, the (2j - 1)-th transistor T(2j - 1) may conduct. In an implementation, for example, the (2j - 1)-th transistor T(2j - 1) may conduct in response to the voltage difference between the gate electrode and the second electrode of the (2j - 1)-th transistor T(2j - 1). In this case, current may flow from the second gate power line VGLL to the j-th data line Dj, and the voltage of the j-th data line Dj may increase. That is, the (2j - 1)-th transistor T(2j - 1) may increase the voltage lower than the second gate power voltage VGL.

[0134] In such an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, the 2j-th transistor T(2j) can be turned on. In an embodiment, for example, the 2j-th transistor T(2j) can be turned on in response to a voltage difference between the gate electrode and the second electrode of the 2j-th transistor T(2j). In this case, current can flow from the second gate power line VGLL to the j-th data line Dj, and the voltage of the j-th data line Dj can increase. That is, the 2j-th transistor T(2j) can increase a voltage lower than the second gate power voltage VGL.

[0135] According to an embodiment, as described above, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, at least one transistor selected from the (2j - 1)-th transistor T(2j - 1) and the 2j-th transistor T(2j) can be turned on, and reliability in removing static electricity can be improved.

[0136] Figure 13 is a block diagram showing an embodiment of a protection circuit included in Figure 1 a display device. For ease of description, the protection circuit PC will be described with reference to the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0137] Referring to Figure 1 and Figure 13 , in an embodiment, the j-th data line Dj can connect the j-th data pad PAD_Dj and the pixel PXLij provided at the i-th pixel row and the j-th pixel column. The protection circuit PC can be connected to the j-th data line Dj.

[0138] In an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, current (e.g., current due to static electricity) can flow from the j-th data line Dj to the first gate power line VGHL, and the voltage at the j-th data line Dj can decrease. In other words, the protection circuit PC can decrease a voltage higher than the first gate power voltage VGH. Current (e.g., current due to static electricity) can not flow from the first gate power line VGHL to the j-th data line Dj.

[0139] In such an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, a current (e.g., a current due to static electricity) can flow from the second gate power line VGLL to the j-th data line Dj, and the voltage at the j-th data line Dj can increase. In other words, the protection circuit PC can increase a voltage lower than the second gate power voltage VGL. A current (e.g., a current due to static electricity) may not flow from the j-th data line Dj to the second gate power line VGLL.

[0140] In such an embodiment, the voltage at the j-th data line Dj can be maintained between the first gate power voltage VGH and the second gate power voltage VGL by the protection circuit PC. In such an embodiment, the pixel PXLij provided at the i-th pixel row and the j-th pixel column can be protected from static electricity by the protection circuit PC.

[0141] Figure 14 is a block diagram showing Figure 13 an embodiment of the protection circuit.

[0142] Referring to Figure 1 , Figure 13 and Figure 14 , in an embodiment, the protection circuit PC may include the (4j - 3)-th transistor T(4j - 3), the (4j - 2)-th transistor T(4j - 2), the (4j - 1)-th transistor T(4j - 1), and the 4j-th transistor T(4j).

[0143] In Figure 14 , the (4j - 3)-th transistor T(4j - 3) to the 4j-th transistor T(4j) are shown as PMOS transistors, but are not limited thereto. In an embodiment, for example, the (4j - 3)-th transistor T(4j - 3) to the 4j-th transistor T(4j) can be implemented as NMOS transistors.

[0144] The j-th data line Dj can be connected between the j-th data pad PAD_Dj and the pixel PXLij provided at the i-th pixel row and the j-th pixel column.

[0145] The first electrode of the (4j - 3)-th transistor T(4j - 3) can be connected to the j-th data line Dj at the (2j - 1)-th node N(2j - 1). The second electrode of the (4j - 3)-th transistor T(4j - 3) can be connected to the first gate power line VGHL. The gate electrode of the (4j - 3)-th transistor T(4j - 3) can be connected to the second electrode of the (4j - 3)-th transistor T(4j - 3).

[0146] The first electrode of the (4j - 2)-th transistor T(4j - 2) can be connected to the j-th data line Dj at the (2j - 1)-th node N(2j - 1). The second electrode of the (4j - 2)-th transistor T(4j - 2) can be connected to the first gate power line VGHL. The gate electrode of the (4j - 2)-th transistor T(4j - 2) can be connected to the second electrode of the (4j - 2)-th transistor T(4j - 2).

[0147] The first electrode of the (4j - 1)-th transistor T(4j - 1) can be connected to the j-th data line Dj at the 2j-th node N(2j). The second electrode of the (4j - 1)-th transistor T(4j - 1) can be connected to the second gate power line VGLL. The gate electrode of the (4j - 1)-th transistor T(4j - 1) can be connected to the first electrode of the (4j - 1)-th transistor T(4j - 1).

[0148] The first electrode of the 4j-th transistor T(4j) can be connected to the j-th data line Dj at the 2j-th node N(2j). The second electrode of the 4j-th transistor T(4j) can be connected to the second gate power line VGLL. The gate electrode of the 4j-th transistor T(4j) can be connected to the first electrode of the 4j-th transistor T(4j). The first electrode of the (4j - 1)-th transistor T(4j - 1) can be connected to the first electrode of the 4j-th transistor T(4j).

[0149] In an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to electrostatic, the (4j - 3)-th transistor T(4j - 3) can be turned on. In an embodiment, for example, the (4j - 3)-th transistor T(4j - 3) can be turned on in response to the voltage difference between the gate electrode and the first electrode of the (4j - 3)-th transistor T(4j - 3). In this case, current can flow from the j-th data line Dj to the first gate power line VGHL, and the voltage of the j-th data line Dj can be reduced. That is, the (4j - 3)-th transistor T(4j - 3) can reduce the voltage higher than the first gate power voltage VGH.

[0150] In such an embodiment, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to electrostatic, the (4j - 2)-th transistor T(4j - 2) can be turned on. In an embodiment, for example, the (4j - 2)-th transistor T(4j - 2) can be turned on in response to the voltage difference between the gate electrode and the first electrode of the (4j - 2)-th transistor T(4j - 2). In this case, current can flow from the j-th data line Dj to the first gate power line VGHL, and the voltage of the j-th data line Dj can be reduced. That is, the (4j - 2)-th transistor T(4j - 2) can reduce the voltage higher than the first gate power voltage VGH.

[0151] In such an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, the (4j - 1)-th transistor T(4j - 1) can be turned on. In an embodiment, for example, the (4j - 1)-th transistor T(4j - 1) can be turned on in response to the voltage difference between the gate electrode and the second electrode of the (4j - 1)-th transistor T(4j - 1). In this case, current can flow from the second gate power line VGLL to the j-th data line Dj, and the voltage of the j-th data line Dj can increase. That is, the (4j - 1)-th transistor T(4j - 1) can increase the voltage lower than the second gate power voltage VGL.

[0152] In such an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, the 4j-th transistor T(4j) can be turned on. In an embodiment, for example, the 4j-th transistor T(4j) can be turned on in response to the voltage difference between the gate electrode and the second electrode of the 4j-th transistor T(4j). In this case, current can flow from the second gate power line VGLL to the j-th data line Dj, and the voltage of the j-th data line Dj can increase. That is, the 4j-th transistor T(4j) can increase the voltage lower than the second gate power voltage VGL.

[0153] According to an embodiment, as described above, when a voltage higher than the first gate power voltage VGH is applied to the j-th data line Dj due to static electricity, at least one selected from the (4j - 3)-th transistor T(4j - 3) and the (4j - 2)-th transistor T(4j - 2) can be turned on, and the reliability in removing the voltage higher than the first gate power voltage VGH (e.g., the voltage caused by static electricity) can be increased. In such an embodiment, when a voltage lower than the second gate power voltage VGL is applied to the j-th data line Dj due to static electricity, at least one transistor selected from the (4j - 1)-th transistor T(4j - 1) and the 4j-th transistor T(4j) can be turned on, and the reliability in removing the voltage lower than the second gate power voltage VGL (e.g., the voltage caused by static electricity) can be increased.

[0154] Figure 15 is a block diagram showing an embodiment of a display panel including Figure 6 and Figure 8 of a protection circuit.

[0155] Refer to Figure 6 、 Figure 8 and Figure 15, The implementation of the display panel DP may include data pads PAD_D, data lines D1 to Dm, a first gate power line VGHL, a second gate power line VGLL, and protection circuits 1501 to 150m.

[0156] The data pads PAD_D may include a first data pad PAD_D1 to an m-th data pad PAD_Dm.

[0157] The data lines D1 to Dm may extend in a second direction DR2 and be arranged in sequence in a first direction DR1.

[0158] The first data line D1 may connect the first data pad PAD_D1 and a pixel PXL_1 disposed at a first pixel column in the pixel. The first protection circuit 1501 may be connected to the first data line D1 at a first node N1.

[0159] The second data line D2 may connect the second data pad PAD_D2 and a pixel PXL_2 disposed at a second pixel column in the pixel. The second protection circuit 1502 may be connected to the second data line D2 at a second node N2.

[0160] The third data line D3 may connect the third data pad PAD_D3 and a pixel PXL_3 disposed at a third pixel column in the pixel. The third protection circuit 1503 may be connected to the third data line D3 at a third node N3.

[0161] The fourth data line D4 may connect the fourth data pad PAD_D4 and a pixel PXL_4 disposed at a fourth pixel column in the pixel. The fourth protection circuit 1504 may be connected to the fourth data line D4 at a fourth node N4.

[0162] Similarly, the (m - 1)-th data line D(m - 1) may connect the (m - 1)-th data pad PAD_D(m - 1) and a pixel PXL_(m - 1) disposed in the (m - 1)-th pixel column in the pixel. The (m - 1)-th protection circuit 150(m - 1) may be connected to the (m - 1)-th data line D(m - 1) at the (m - 1)-th node N(m - 1).

[0163] The m-th data line Dm may connect the m-th data pad PAD_Dm and a pixel PXL_m disposed in the m-th pixel column in the pixel. The m-th protection circuit 150m may be connected to the m-th data line Dm at the m-th node Nm.

[0164] Each of the first type of data lines among the data lines D1 to Dm may be connected to a first type of protection circuit. Refer to Figure 15, the odd-numbered data lines among the data lines D1 to Dm (e.g., the first data line D1, the third data line D3, and the (m - 1)th data line D(m - 1), etc.) may correspond to the first type of data lines. Refer to Figure 15 , the first protection circuit 1501, the third protection circuit 1503, and the (m - 1)th protection circuit 150(m - 1) may correspond to the first type of protection circuits.

[0165] Each of the second type of data lines among the data lines D1 to Dm may be connected to a second type of protection circuit. Refer to Figure 15 , the even-numbered data lines among the data lines D1 to Dm (e.g., the second data line D2, the fourth data line D4, and the mth data line Dm, etc.) may correspond to the second type of data lines. Refer to Figure 15 , the second protection circuit 1502, the fourth protection circuit 1504, and the mth protection circuit 150m may correspond to the second type of protection circuits.

[0166] Each of the first type of protection circuits 1501, 1503,..., and 150(m - 1) connected to the odd-numbered data lines D1, D3,..., and D(m - 1) among the data lines D1 to Dm may correspond to Figure 6 the protection circuit PC. In an embodiment, for example, the first protection circuit 1501 among the protection circuits 1501, 1503,..., and 150(m - 1) connected to the odd-numbered data lines D1, D3,..., and D(m - 1) may include a first transistor T1. The first electrode of the first transistor T1 may be connected to the first data line D1 at a first node N1. The second electrode of the first transistor T1 may be connected to a first gate power line VGHL. The gate electrode of the first transistor T1 may be connected to the second electrode of the first transistor T1. Similarly, the first electrode of the third transistor T3 in the third protection circuit 1503 may be connected to the third data line D3 at a third node N3, the second electrode of the third transistor T3 may be connected to the first gate power line VGHL, and the gate electrode of the third transistor T3 may be connected to the second electrode of the third transistor T3. The first electrode of the (m - 1)th transistor T(m - 1) in the (m - 1)th protection circuit 150(m - 1) may be connected to the (m - 1)th data line D(m - 1) at the (m - 1)th node N(m - 1), the second electrode of the (m - 1)th transistor T(m - 1) may be connected to the first gate power line VGHL, and the gate electrode of the (m - 1)th transistor T(m - 1) may be connected to the second electrode of the (m - 1)th transistor T(m - 1).

[0167] Each of the second type of protection circuits 1502, 1504,..., and 150m connected to the even-numbered data lines D2, D4,..., and Dm among the data lines D1 to Dm may correspond to Figure 8The protection circuit PC. In an embodiment, for example, the second protection circuit 1502 among the protection circuits 1502, 1504, …, and 150m connected to the even-numbered data lines D2, D4, …, and Dm may include a second transistor T2. The first electrode of the second transistor T2 may be connected to the second gate power line VGLL. The second electrode of the second transistor T2 may be connected to the second data line D2 at the second node N2. The gate electrode of the second transistor T2 may be connected to the second electrode of the second transistor T2. Similarly, the first electrode of the fourth transistor T4 may be connected to the second gate power line VGLL, the second electrode of the fourth transistor T4 may be connected to the fourth data line D4 at the fourth node N4, and the gate electrode of the fourth transistor T4 may be connected to the second electrode of the fourth transistor T4. The first electrode of the m-th transistor Tm may be connected to the second gate power line VGLL, the second electrode of the m-th transistor Tm may be connected to the m-th data line Dm at the m-th node Nm, and the gate electrode of the m-th transistor Tm may be connected to the second electrode of the m-th transistor Tm.

[0168] Figure 16 is a block diagram showing another embodiment of a display panel including Figure 6 and Figure 8 the protection circuit.

[0169] Referring to Figure 6 , Figure 8 and Figure 16 , an embodiment of the display panel DP may include data pads PAD_D, data lines D1 to Dm, a first gate power line VGHL, a second gate power line VGLL, and protection circuits 1601 to 160m.

[0170] The data pads PAD_D may include first data pads PAD_D1 to m-th data pads PAD_Dm.

[0171] The data lines D1 to Dm may extend in the second direction DR2 and be arranged in sequence in the first direction DR1.

[0172] The first data line D1 may connect the first data pad PAD_D1 and the pixel PXL_1 disposed at the first pixel column in the pixel. The first protection circuit 1601 may be connected to the first data line D1 at the first node N1.

[0173] The second data line D2 may connect the second data pad PAD_D2 and the pixel PXL_2 disposed at the second pixel column in the pixel. The second protection circuit 1602 may be connected to the second data line D2 at the second node N2.

[0174] The third data line D3 can connect the third data pad PAD_D3 and the pixel PXL_3 set at the third pixel column in the pixel. The third protection circuit 1603 can be connected to the third data line D3 at the third node N3.

[0175] The fourth data line D4 can connect the fourth data pad PAD_D4 and the pixel PXL_4 set at the fourth pixel column in the pixel. The fourth protection circuit 1504 can be connected to the fourth data line D4 at the fourth node N4.

[0176] In such an embodiment, the (m - 1)-th data line D(m - 1) can connect the (m - 1)-th data pad PAD_D(m - 1) and the pixel PXL_(m - 1) set in the (m - 1)-th pixel column in the pixel. The (m - 1)-th protection circuit 160(m - 1) can be connected to the (m - 1)-th data line D(m - 1) at the (m - 1)-th node N(m - 1).

[0177] The m-th data line Dm can connect the m-th data pad PAD_Dm and the pixel PXL_m set in the m-th pixel column in the pixel. The m-th protection circuit 160m can be connected to the m-th data line Dm at the m-th node Nm.

[0178] At least some of the plurality of consecutive first-type data lines among the data lines D1 to Dm can be connected to a plurality of first-type protection circuits, and the remaining plurality of consecutive second-type data lines among the data lines D1 to Dm can be connected to a plurality of second-type protection circuits.

[0179] Reference Figure 16 , the first data line D1, the second data line D2, the (m - 1)-th data line D(m - 1), the m-th data line Dm, etc. can correspond to the first-type data lines. The first protection circuit 1601, the second protection circuit 1602, the (m - 1)-th protection circuit 160(m - 1), the m-th protection circuit 160m, etc. can correspond to the first-type protection circuits.

[0180] Reference Figure 16 , the third data line D3, the fourth data line D4, etc. can correspond to the second-type data lines. The third protection circuit 1603, the fourth protection circuit 1604, etc. can correspond to the second-type protection circuits.

[0181] The first-type protection circuits 1601, 1602, …, 160(m - 1) and 160m can correspond to the Figure 6 protection circuit PC. The second-type protection circuits 1603, 1604, …, etc. can correspond to the Figure 8 protection circuit PC.

[0182] Figure 17 is shown includingFigure 10 and Figure 12 block diagram of an embodiment of a display panel having a protection circuit.

[0183] Referring Figure 10 、 Figure 12 and Figure 17 , an embodiment of the display panel DP may include data pads PAD_D, data lines D1 to Dm, a first gate power line VGHL, a second gate power line VGLL, and protection circuits 1701 to 170m.

[0184] The data pads PAD_D may include a first data pad PAD_D1 to an m-th data pad PAD_Dm.

[0185] The data lines D1 to Dm may extend in a second direction DR2 and be arranged in sequence in a first direction DR1.

[0186] The first data line D1 may connect the first data pad PAD_D1 and a pixel PXL_1 provided in the first pixel column among the pixels. The first protection circuit 1701 may be connected to the first data line D1 at a first node N1.

[0187] The second data line D2 may connect the second data pad PAD_D2 and a pixel PXL_2 provided in the second pixel column among the pixels. The second protection circuit 1702 may be connected to the second data line D2 at a second node N2.

[0188] The third data line D3 may connect the third data pad PAD_D3 and a pixel PXL_3 provided in the third pixel column among the pixels. The third protection circuit 1703 may be connected to the third data line D3 at a third node N3.

[0189] The fourth data line D4 may connect the fourth data pad PAD_D4 and a pixel PXL_4 provided in the fourth pixel column among the pixels. The fourth protection circuit 1704 may be connected to the fourth data line D4 at a fourth node N4.

[0190] In such an embodiment, the (m - 1)-th data line D(m - 1) may connect the (m - 1)-th data pad PAD_D(m - 1) and a pixel PXL_(m - 1) provided in the (m - 1)-th pixel column among the pixels. The (m - 1)-th protection circuit 170(m - 1) may be connected to the (m - 1)-th data line D(m - 1) at the (m - 1)-th node N(m - 1).

[0191] The m-th data line Dm may connect the m-th data pad PAD_Dm and a pixel PXL_m provided in the m-th pixel column among the pixels. The m-th protection circuit 170m may be connected to the m-th data line Dm at the m-th node Nm.

[0192] Each of the first - type data lines among the data lines D1 to Dm can be connected to a first - type protection circuit. Refer to Figure 17 , the odd - numbered data lines among the data lines D1 to Dm (e.g., the first data line D1, the third data line D3, and the (m - 1)th data line D(m - 1), etc.) can correspond to the first - type data lines. Refer to Figure 17 , the first protection circuit 1701, the third protection circuit 1703, and the (m - 1)th protection circuit 170(m - 1) can correspond to the first - type protection circuits.

[0193] Each of the second - type data lines among the data lines D1 to Dm can be connected to a second - type protection circuit. Refer to Figure 17 , the even - numbered data lines among the data lines D1 to Dm (e.g., the second data line D2, the fourth data line D4, and the mth data line Dm, etc.) can correspond to the second - type data lines. Refer to Figure 17 , the second protection circuit 1702, the fourth protection circuit 1704, and the mth protection circuit 170m can correspond to the second - type protection circuits.

[0194] Each of the first - type protection circuits 1701, 1703, …, and 170(m - 1) connected to the odd - numbered data lines D1, D3, …, and D(m - 1) among the data lines D1 to Dm can correspond to Figure 10 the protection circuit PC. Each of the second - type protection circuits 1702, 1704, …, and 170m connected to the even - numbered data lines D2, D4, …, and Dm among the data lines D1 to Dm can correspond to Figure 12 the protection circuit PC. The connection relationships between the transistors T1 and T2, T5 and T6, …, and T(2m - 2) and T(2m - 3) in the first - type protection circuits 1701, 1703, …, and 170(m - 1), the first gate power line VGHL and the data lines D1, D3, …, and D(m - 1) can be similar to Figure 10 the connection relationships between the transistors T(2j - 1) and T(2j), the first gate power line VGHL and the jth data line Dj in Figure 12 . The connection relationships between the transistors T3 and T4, T7 and T8, …, and T(2m - 1) and T(2m) in the second - type protection circuits 1702, 1704, …, and 170m, the second gate power line VGLL and the data lines D2, D4, …, and Dm can be similar to

[0195] Figure 18 is a diagram showing including Figure 10 and Figure 12Block diagram of another embodiment of a display panel of a protection circuit.

[0196] Reference Figure 10 、 Figure 12 and Figure 18 , an embodiment of the display panel DP may include data pads PAD_D, data lines D1 to Dm, a first gate power line VGHL, a second gate power line VGLL, and protection circuits 1801 to 180m.

[0197] The data pad PAD_D may include a first data pad PAD_D1 to an mth data pad PAD_Dm.

[0198] The data lines D1 to Dm may extend in a second direction DR2 and be arranged in sequence in a first direction DR1.

[0199] The first data line D1 may connect the first data pad PAD_D1 and a pixel PXL_1 disposed at a first pixel column in the pixel. The first protection circuit 1801 may be connected to the first data line D1 at a first node N1.

[0200] The second data line D2 may connect the second data pad PAD_D2 and a pixel PXL_2 disposed at a second pixel column in the pixel. The second protection circuit 1802 may be connected to the second data line D2 at a second node N2.

[0201] The third data line D3 may connect the third data pad PAD_D3 and a pixel PXL_3 disposed at a third pixel column in the pixel. The third protection circuit 1803 may be connected to the third data line D3 at a third node N3.

[0202] The fourth data line D4 may connect the fourth data pad PAD_D4 and a pixel PXL_4 disposed at a fourth pixel column in the pixel. The fourth protection circuit 1804 may be connected to the fourth data line D4 at a fourth node N4.

[0203] In such an embodiment, the (m - 1)th data line D(m - 1) may connect the (m - 1)th data pad PAD_D(m - 1) and a pixel PXL_(m - 1) disposed in the (m - 1)th pixel column in the pixel. The (m - 1)th protection circuit 180(m - 1) may be connected to the (m - 1)th data line D(m - 1) at the (m - 1)th node N(m - 1).

[0204] The mth data line Dm may connect the mth data pad PAD_Dm and a pixel PXL_m disposed in the mth pixel column in the pixel. The mth protection circuit 180m may be connected to the mth data line Dm at the mth node Nm.

[0205] At least some of the plurality of consecutive first - type data lines among the data lines D1 to Dm can be connected to a plurality of first - type protection circuits, and the remaining plurality of consecutive second - type data lines among the data lines D1 to Dm can be connected to a plurality of second - type protection circuits.

[0206] Reference Figure 18 , the first - type data lines can correspond to the first data line D1, the second data line D2, …, the (m - 1)th data line D(m - 1), and the mth data line Dm, and the first protection circuit 1801, the second protection circuit 1802, …, the (m - 1)th protection circuit 180(m - 1), and the mth protection circuit 180m can correspond to the first - type protection circuits.

[0207] Reference Figure 18 , the second - type data lines can correspond to the third data line D3 and the fourth data line D4, and the third protection circuit 1803 and the fourth protection circuit 1804 can correspond to the second - type protection circuits.

[0208] Each of the first - type protection circuits 1801, 1802, …, 180(m - 1), and 180m can correspond to Figure 10 the protection circuit PC. Each of the second - type protection circuits 1803, 1804, …, etc. can correspond to Figure 12 the protection circuit PC.

[0209] Figure 19 is a block diagram showing an embodiment of a display panel including Figure 14 the protection circuit.

[0210] Reference Figure 14 and Figure 19 , an embodiment of the display panel DP can include data pads PAD_D, data lines D1 to Dm, a first gate power line VGHL, a second gate power line VGLL, and protection circuits 1901 to 190m.

[0211] The data pads PAD_D can include the first data pad PAD_D1 to the mth data pad PAD_Dm.

[0212] The data lines D1 to Dm can extend in the second direction DR2 and be arranged in sequence in the first direction DR1.

[0213] The first data line D1 can connect the first data pad PAD_D1 and the pixel PXL_1 disposed at the first pixel column in the pixel. The first protection circuit 1901 can be connected to the first data line D1 at the first node N1 and the second node N2.

[0214] The second data line D2 can connect the second data pad PAD_D2 and the pixel PXL_2 disposed in the second pixel column in the pixel. The second protection circuit 1902 can be connected to the second data line D2 at the third node N3 and the fourth node N4.

[0215] The third data line D3 can connect the third data pad PAD_D3 and the pixel PXL_3 disposed in the third pixel column in the pixel. The third protection circuit 1903 can be connected to the third data line D3 at the fifth node N5 and the sixth node N6.

[0216] The fourth data line D4 can connect the fourth data pad PAD_D4 and the pixel PXL_4 disposed in the fourth pixel column in the pixel. The fourth protection circuit 1904 can be connected to the fourth data line D4 at the seventh node N7 and the eighth node N8.

[0217] In such an embodiment, the (m - 1)th data line D(m - 1) can connect the (m - 1)th data pad PAD_D(m - 1) and the pixel PXL_(m - 1) disposed in the (m - 1)th pixel column in the pixel. The (m - 1)th protection circuit 190(m - 1) can be connected to the (m - 1)th data line D(m - 1) at the (2m - 3)th node N(2m - 3) and the (2m - 2)th node N(2m - 2).

[0218] The mth data line Dm can connect the mth data pad PAD_Dm and the pixel PXL_m disposed in the mth pixel column in the pixel. The mth protection circuit 190m can be connected to the mth data line Dm at the (2m - 1)th node N(2m - 1) and the 2mth node N(2m).

[0219] Each of the protection circuits 1901 to 190m can correspond to Figure 14 the protection circuit PC. In an embodiment, for example, one of the protection circuits 1901 to 190m (e.g., the first protection circuit 1901) can include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0220] The first electrode of the first transistor T1 can be connected to the first data line D1 at the first node N1. The second electrode of the first transistor T1 can be connected to the first gate power line VGHL. The gate electrode of the first transistor T1 can be connected to the second electrode of the first transistor T1.

[0221] The first electrode of the second transistor T2 can be connected to the first data line D1 at the first node N1. The second electrode of the second transistor T2 can be connected to the first gate power line VGHL. The gate electrode of the second transistor T2 can be connected to the second electrode of the second transistor T2.

[0222] The first electrode of the third transistor T3 may be connected to the first data line D1 at the second node N2. The second electrode of the third transistor T3 may be connected to the second gate power line VGLL. The gate electrode of the third transistor T3 may be connected to the first electrode of the third transistor T3.

[0223] The first electrode of the fourth transistor T4 may be connected to the first data line D1 at the second node N2. The second electrode of the fourth transistor T4 may be connected to the second gate power line VGLL. The gate electrode of the fourth transistor T4 may be connected to the first electrode of the fourth transistor T4. The transistors T5, T6, T7, and T8 in the second protection circuit 1902, the transistors T9, T10, T11, and T12 in the third protection circuit 1903, the transistors T13, T14, T15, and T16 in the fourth protection circuit 1904, …, the transistors T(4m - 7), T(4m - 6), T(4m - 5), and T(4m - 4) in the (m - 1)th protection circuit 190(m - 1), and the transistors T(4m - 3), T(4m - 2), T(4m - 1), and T(4m) in the mth protection circuit 190m may be electrically connected to the first gate power line VGHL, the second gate power line VGLL, and the corresponding data lines in a manner similar to that of the transistors T1, T2, T3, and T4 in the first protection circuit 1901, for example.

[0224] According to an embodiment of the present disclosure, as described herein, the pixels PXL provided in the display panel DP may be protected from the influence of static electricity of high voltage and / or low voltage by the protection circuit.

[0225] The present utility model should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present utility model to those skilled in the art.

[0226] Although the present utility model has been specifically shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes may be made therein in form and detail without departing from the spirit or scope of the present utility model as defined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: Pixels, each including a light-emitting element and a pixel circuit connected to the light-emitting element; Data lines, arranged in multiple columns, wherein the data lines provide data signals to the pixel circuits; Data pads, connected to the data lines; A first protection circuit, connected between a first data line among the data lines and a first gate power line to which a first gate power voltage is applied; and A second protection circuit, connected between a second data line among the data lines and a second gate power line to which a second gate power voltage is applied.

2. The display panel according to claim 1, wherein The first protection circuit includes a first transistor, and The second protection circuit includes a second transistor, wherein the first transistor includes: A gate electrode, A first electrode, connected to the first gate power line and electrically connected to the gate electrode of the first transistor, and A second electrode, connected to the first data line, and wherein the second transistor includes: A gate electrode, electrically connected to the second data line, A first electrode, connected to the second gate power line, and A second electrode, connected to the second data line.

3. The display panel according to claim 2, wherein The first data line is an odd-numbered data line among the data lines, and The second data line is an even-numbered data line among the data lines.

4. The display panel according to claim 2, wherein The display panel includes a plurality of first protection circuits and a plurality of second protection circuits, the plurality of first protection circuits include the first protection circuit, the plurality of second protection circuits include the second protection circuit, A plurality of consecutive first data lines among the data lines are connected to the plurality of first protection circuits, A plurality of consecutive second data lines among the data lines are connected to the plurality of second protection circuits, and The plurality of consecutive first data lines and the plurality of consecutive second data lines are arranged adjacent to each other.

5. The display panel according to claim 2, wherein The first protection circuit further includes a third transistor, and The second protection circuit further includes a fourth transistor, wherein the third transistor includes: A gate electrode, A first electrode, connected to the second electrode of the first transistor, and A second electrode, connected to the first gate power line, and wherein the fourth transistor includes: A gate electrode, A first electrode, connected to the second electrode of the second transistor, and A second electrode, connected to the second gate power line.

6. The display panel according to claim 5, wherein The first data line is an odd-numbered data line among the data lines, and The second data line is an even-numbered data line among the data lines.

7. A display panel, characterized in that, The display panel includes: Pixels, each including a light-emitting element and a pixel circuit connected to the light-emitting element; Data lines, arranged in multiple columns, wherein the data lines provide data signals to the pixel circuits; Data pads, connected to the data lines; and A protection circuit, connected to the data lines, Each of the protection circuits includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor includes: a gate electrode, a first electrode connected to a first gate power line and electrically connected to the gate electrode of the first transistor, and a second electrode connected to a corresponding data line among the data lines, wherein the second transistor includes: a gate electrode, a first electrode connected to the second electrode of the first transistor, and a second electrode electrically connected to the gate electrode of the second transistor and connected to the first gate power line, wherein the third transistor includes: a gate electrode, a first electrode connected to a second gate power line, and a second electrode connected to a corresponding one of the data lines among the data lines and electrically connected to the gate electrode of the third transistor, and wherein the fourth transistor includes: a gate electrode, a first electrode connected to the second electrode of the third transistor and connected to the second gate power line, and a second electrode electrically connected to the gate electrode of the fourth transistor.

8. A display device, characterized in that, The display device includes: a display panel including pixels; and a data driver that applies data signals to the pixels, wherein the display panel includes: data lines arranged in a plurality of columns, wherein the data lines supply the data signals to the pixels, data pads connected to the data lines, a first protection circuit connected between a first data line among the data lines and a first gate power line to which a first gate power voltage is applied, and a second protection circuit connected between a second data line among the data lines and a second gate power line to which a second gate power voltage is applied.

9. The display device according to claim 8, characterized in that, The display device further includes: a gate driver that supplies gate signals to the pixels based on a start signal and a clock signal; a start signal line that transmits the start signal to the gate driver; and a clock signal line that transmits the clock signal to the gate driver.

10. The display device according to claim 8, wherein each of the pixels includes a light-emitting element and a pixel circuit connected to the light-emitting element, and the pixel circuit includes a first transistor connected between a first power supply and the light-emitting element, a second transistor connected between a corresponding data line among the data lines and the first transistor, a first pixel node connected between the first transistor and the second transistor, and a second pixel node connected between the first transistor and the light-emitting element.

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