Integrated HDMI loop-out circuit

Abstract

The utility model provides an integrated HDMI (High Definition Multimedia Interface) loop-out circuit which is characterized by comprising an HDMI IN interface, an HDMI distributor chip, a loop-out HDMI OUT interface and a CPU (Central Processing Unit), the HDMI IN interface is connected with the HDMI distributor chip, and the HDMI distributor chip is connected with the loop-out HDMI OUT interface and the CPU. The video signal processing efficiency and real-time performance are significantly improved, the output of converting one HDMI IN signal into two HDMI OUT signals can be completed at the same time, one output is sent to a CPU for video acquisition, and the other output is sent to a display for monitoring.

Description

Technical Field

[0001] The utility model relates to the field of computer technology, in particular to an integrated HDMI loop-out circuit. Background Art

[0002] HDMI (High-Definition Multimedia Interface) is a fully digital video and audio transmission interface for transmitting uncompressed video data and compressed or uncompressed audio data. The HDMI interface can transmit high-definition video and multi-channel audio simultaneously and supports a variety of digital audio formats, including Dolby Digital, DTS, etc. HDMIIN video capture is the process of using the HDMI interface to receive high-definition multimedia signals from external video sources (such as Blu-ray players, game consoles, computers, cameras, etc.) and converting them into a format that can be processed and recorded by a computer or other device. In video surveillance, it is necessary to monitor and record video signals in real time; in television broadcasting and video production, it is necessary to output video signals to monitors and recording devices simultaneously; in educational and training scenarios, such as online courses or distance learning, it is necessary to display the teacher's presentation content to students in real time and record it simultaneously; in VR and AR applications, it is necessary to output video signals to monitors and VR / AR devices simultaneously so that users can experience virtual content in real time. In current HDMIIN video capture applications, video image capture devices often only focus on the recording of video input signals and cannot provide the function of viewing real-time video images at the same time. This results in users being unable to monitor the content being recorded in real time during video recording, which may cause them to miss important scenes or make operational mistakes. Summary of the Utility Model

[0003] In view of this, the purpose of the utility model is to provide an integrated HDMI loop-out circuit, aiming to enable simultaneous recording and viewing of video signals and prevent abnormal situations during the recording process.

[0004] The technical solution adopted by the utility model to solve the above technical problems is as follows:

[0005] The utility model provides an integrated HDMI loop-out circuit, which is characterized by including: an HDMIIN interface, an HDMI splitter chip, a loop-out HDMIOUT interface, and a CPU. The HDMIIN interface is connected to the HDMI splitter chip, and the HDMI splitter chip is connected to the loop-out HDMIOUT interface and the CPU.

[0006] In some embodiments, the HDMI splitter chip divides the HDMI signal received through the HDMIIN interface into two in-phase HDMI signals and transmits them to the loop-out HDMIOUT interface and the CPU.

[0007] In some embodiments, the model of the HDMI splitter chip is MS9332.

[0008] In some embodiments, a power supply module is further included. The power supply module includes a power supply main chip PU6, an input filter circuit, an output filter circuit, and a 5V power supply. The input end of the power supply main chip PU6 is connected to the 5V power supply through the input filter circuit, and the output end of the power supply main chip PU6 is connected to the output filter circuit.

[0009] In some embodiments, the resistor PR126 and the signal GPP_H12 are connected to the enable end of the power supply main chip PU6 to form a power-on timing control. The other end of the resistor PR126 is connected to the +V3.3S power supply terminal. The resistors PR157 and PR155 form an output voltage value control. The resistor PR157 is disposed between the ADJ pin and the VOUT pin of the power supply main chip PU6, and the resistor PR155 is disposed between the ADJ pin and the ground terminal. The input filter circuit is composed of capacitors PC128, PC127, PC127, and PC129, and the output filter circuit is composed of capacitors PC124, PC130, PC125, and PC123. The output filter circuit is connected to the +V1.2_LT power supply terminal.

[0010] In some embodiments, the AVDDT33 pin, AVDDR33 pin, DVDD33 pin, and MV33 pin of the HDMI splitter chip are respectively connected to the +V3.3S power supply terminal through feedback resistors FB27, FB29, FB30, and FB28. The DVDD12 pin, AVDDT12 pin, and AVDDR12 pin of the HDMI splitter chip are respectively connected to the +V1.2_LT power supply terminal through feedback resistors FB25, FB24, and FB26.

[0011] In some embodiments, an HDMI receiver chip is further included. The HDMI receiver chip is connected to the HDMI splitter chip and the CPU, and the model of the HDMI receiver chip is LT6911UXC.

[0012] The integrated HDMI loop-out circuit provided by the embodiment of the present utility model significantly improves the efficiency and real-time performance of video signal processing through innovative circuit design. The use of the MS9332 chip can simultaneously convert 1 HDMI IN signal into 2 HDMI OUT signals, with 1 output for the CPU to perform video capture and 1 output for the monitor for monitoring. This design not only enables the simultaneous recording and viewing of video signals but also prevents abnormal situations during the recording process, greatly improving the flexibility and reliability of video capture. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is the circuit block diagram of the embodiment of the present utility model;

[0014] Figure 2 is the circuit diagram of the power supply module of the embodiment of the present utility model;

[0015] Figure 3 is the circuit diagram of the power supply module of the embodiment of the present utility model;

[0016] Figure 4 is the circuit diagram of the HDMI receiver chip of the embodiment of the present utility model;

[0017] Figure 5 is the circuit diagram of the HDMI splitter chip of the embodiment of the present utility model;

[0018] In the figure: 100, HDMI IN interface; 200, HDMI splitter chip; 300, loop-out HDMI OUT interface; 400, CPU. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The general idea of the technical solution provided by the present utility model is as follows:

[0020] Please refer to Figure 1 , an integrated HDMI loop-out circuit, characterized in that it includes: an HDMI IN interface 100, an HDMI splitter chip 200, a loop-out HDMI OUT interface 300, and a CPU 400. The HDMI IN interface 100 is connected to the HDMI splitter chip 200, and the HDMI splitter chip 200 is connected to the loop-out HDMI OUT interface 300 and the CPU 400.

[0021] The integrated HDMI loop-out circuit is developed based on MS9332, compliant with the HDMI V1.4 standard specification. It uses one MS9332 chip and can simultaneously complete the output of converting 1 HDMI IN to 2 HDMI OUTs. One output is sent to the CPU400 for video acquisition signal, and the other output is sent to the loop-out HDMI OUT to connect to the monitor for monitoring. Thus, it realizes the simultaneous recording and viewing of video signals and prevents abnormal situations during the recording process. It is a product with very high cost performance for the equipment in the live recording industry.

[0022] The integrated HDMI loop-out circuit mainly consists of an HDMI IN interface, an HDMI 1-to-2 MS9332 chip, a loop-out HDMI OUT300, and a CPU400. The acquired video signal is sent to the MS9332 chip through the HDMI IN interface 100. The MS9332 divides 1 HDMI signal into 2 in-phase HDMI signals. One is monitored by the HDMI OUT, and the other is sent to the CPU400 for recording or video editing processing.

[0023] See Figure 1 , the HDMI splitter chip 200 divides the HDMI signal received through the HDMI IN interface 100 into two in-phase HDMI signals and transmits them to the loop-out HDMI OUT interface 300 and the CPU400.

[0024] See Figure 4 , the model of the HDMI splitter chip 200 is MS9332.

[0025] See Figure 2 , it also includes a power supply module. The power supply module includes a power supply main chip PU6, an input filter circuit, an output filter circuit, and a 5V power supply. The input end of the power supply main chip PU6 is connected to the 5V power supply through the input filter circuit, and the output end of the power supply main chip PU6 is connected to the output filter circuit. The power supply main chip PU6 controls the conversion of 5V to +V1.2_LT to supply power to the main chip MS9332. PC128, PC127, PC127, and PC129 form the input filter circuit, PC124, PC130, PC125, and PC123 form the output filter circuit, PR126 and the signal GPP_H12 form the power-on timing control, and PR157 and PR155 form the output voltage value control.

[0026] See Figure 2, the resistor PR126 and the signal GPP_H12 are connected to the enable terminal of the main power supply chip PU6 to form a power-on timing control. The other end of the resistor PR126 is connected to the +V3.3S power supply terminal. The resistors PR157 and PR155 form an output voltage value control. Among them, the resistor PR157 is arranged between the ADJ pin and the VOUT pin of the main power supply chip PU6, and the resistor PR155 is arranged between the ADJ pin and the ground terminal. The input filter circuit is composed of the capacitors PC128, PC127, PC127, and PC129, and the output filter circuit is composed of the capacitors PC124, PC130, PC125, and PC123. The output filter circuit is connected to the +V1.2_LT power supply terminal.

[0027] See Figure 3 , the AVDDT33 pin, AVDDR33 pin, DVDD33 pin, and MV33 pin of the HDMI splitter chip 200 are respectively connected to the +V3.3S power supply terminal through the feedback resistors FB27, FB29, FB30, and FB28. The DVDD12 pin, AVDDT12 pin, and AVDDR12 pin of the HDMI splitter chip 200 are respectively connected to the +V1.2_LT power supply terminal through the feedback resistors FB25, FB24, and FB26.

[0028] The main power supply chip +V3.3S is directly powered by the main board, and the AVDDT33, AVDDR33, DVDD33, and MV33 are separately powered through FB27, FB29, FB30, and FB28, corresponding to the power supply of each pin of the HDMI splitter chip 200, achieving power supply isolation and not affecting each other. The power supply is +V1.2_LT, and the DVDD12, AVDDT12, and AVDDR12 are separately powered through FB25, FB24, and FB26, corresponding to the power supply of each pin of the HDMI splitter chip 200, with the same function as the main +V3.3S.

[0029] See Figure 4 , it further includes an HDMI receiver chip. The HDMI receiver chip is connected to the HDMI splitter chip 200 and the CPU400. The model of the HDMI receiver chip is LT6911UXC. It receives the signals transmitted by U13 through pin2, 3, 5, 6, 8, 9, 11, 12, 15, and 16. After calculation and conversion, it is connected to the CPU400 through pin35, 36, 37, 38, 39, 40, 41, and 42 to achieve system calculation and reception. PIN27, 27, 29, and 30 are the channels for audio transmission to the CPU400 for processing.

[0030] See Figure 5, pins 4, 5, 7, 8, 10, 11, 13, and 14 of the HDMI splitter chip 200 receive the signals input through the connector of HDMI_IN. After being processed by the HDMI splitter chip 200, the signals are divided into two output paths. One path is output through pins 36, 37, 39, 40, 41, 42, 44, and 45 to U68 (LT6911) and then processed and calculated by the CPU 400 of X86. The other path is connected to the output value display of the HDMI3 connector through pins 54, 55, 57, 58, 59, 60, 62, and 63 to achieve the loop-out function. Among them, C978, X1, and C3 form a crystal oscillator circuit to provide the operating frequency required by the HDMI splitter chip 200, and R34 is a compensation resistor to adjust the operating parameters of the HDMI splitter chip 200. Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0031] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. An integrated HDMI loop-out circuit, characterized in that, Including: HDMI IN interface, HDMI splitter chip, loop-out HDMI OUT interface and CPU. The HDMI IN interface is connected to the HDMI splitter chip, and the HDMI splitter chip is connected to the loop-out HDMI OUT interface and the CPU.

2. The integrated HDMI loop-out circuit according to claim 1, wherein The HDMI splitter chip divides the HDMI signal received through the HDMI IN interface into two in-phase HDMI signals and transmits them to the loop-out HDMI OUT interface and the CPU.

3. The integrated HDMI loop-through circuit according to claim 2, wherein The model of the HDMI splitter chip is MS9332.

4. The integrated HDMI loop-out circuit according to claim 1, wherein It further includes a power module. The power module includes a power main chip PU6, an input filter circuit, an output filter circuit and a 5V power supply. The input end of the power main chip PU6 is connected to the 5V power supply through the input filter circuit, and the output end of the power main chip PU6 is connected to the output filter circuit.

5. The integrated HDMI loop-out circuit according to claim 4, wherein Resistor PR126 and signal GPP_H12 are connected to the enable terminal of the power main chip PU6 to form a power-on timing control. The other end of resistor PR126 is connected to the +V3.3S power supply terminal. Resistors PR157 and PR155 form an output voltage value control. Among them, resistor PR157 is arranged between the ADJ pin and the VOUT pin of the power main chip PU6, and resistor PR155 is arranged between the ADJ pin and the ground terminal. The input filter circuit is composed of capacitors PC128, PC127, PC127 and PC129, and the output filter circuit is composed of capacitors PC124, PC130, PC125 and PC123. The output filter circuit is connected to the +V1.2_LT power supply terminal.

6. The integrated HDMI loop-out circuit according to claim 1, wherein The AVDDT33 pin, AVDDR33 pin, DVDD33 pin and MV33 pin of the HDMI splitter chip are respectively connected to the +V3.3S power supply terminal through feedback resistors FB27, FB29, FB30 and FB28. The DVDD12 pin, AVDDT12 pin and AVDDR12 pin of the HDMI splitter chip are respectively connected to the +V1.2_LT power supply terminal through feedback resistors FB25, FB24 and FB26.

7. The integrated HDMI loop-out circuit according to claim 1, wherein It further includes an HDMI receiver chip. The HDMI receiver chip is connected to the HDMI splitter chip and the CPU. The model of the HDMI receiver chip is LT6911UXC.

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