Double CameraLink-to-HDMI (High-Definition Multimedia Interface) superposition display device

Abstract

The utility model discloses a double CameraLink to HDMI (High Definition Multimedia Interface) superposition display device. The device is a display device conforming to the 6U CPEX standard. The display device provided by the utility model can be conveniently applied to a standard 6U CPEX case to carry out double CameraLink to HDMI (High Definition Multimedia Interface) overlapping display. The device adopts a standard 6U CPEX structural design, and has excellent heat dissipation performance and environment protection design. According to the device, two paths of CameraLink input interfaces and one path of HDMI output interface are integrated, commands such as two paths of video zooming and superposition positions are issued through a serial port, and the master control module FPGA realizes analysis, zooming and superposition output display of two paths of CameraLink videos according to the commands. The device supports an IPMB bus, realizes temperature and voltage monitoring, supports online updating of an FPGA main control program through a serial port, avoids the complexity that a board card needs to be disassembled when a JTAG updates the program, and is high in universality and low in maintenance cost.

Description

Technical Field

[0001] The utility model belongs to the technical field of image and video processing, and particularly relates to a dual CameraLink to HDMI overlay display device. Background Art

[0002] With the rapid development of computer technology and the semiconductor industry, the demand for information is continuously increasing, and video overlay technology is widely used in places such as traffic monitoring, Internet of Things, and video conferencing. In the display control system, video overlay technology also plays an increasingly important role. It not only needs to process various information graphics and images received, but also needs to comprehensively process input signals and data of various video formats. This requires the design of a multi-format video overlay processor.

[0003] In China, with the continuous increase in environmental complexity and information volume, higher requirements are put forward for data transmission rate, transmission volume, and system reliability. The old architecture and bus transmission bandwidth are difficult to apply to the ever-changing modern places. The CPEX architecture that adopts the new generation of high-speed serial bus technology has a higher transmission bandwidth and more excellent structural performance. Therefore, the CPEX architecture will play a greater role. In addition, with the continuous improvement of production technology, FPGA has rich resources, low production cost, small volume, and low power consumption. High-end FPGAs are embedded with processors such as DSP and ARM, enabling them to not only complete logic control but also complete more complex algorithm implementations. Dedicated video chips have single functions, high prices, and high market risks, which are not conducive to wide application. Therefore, researching video overlay technology based on FPGA has become a new trend. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the problems raised in the background art, and provide a dual CameraLink to HDMI overlay display device with strong versatility and low cost, which conforms to the standard 6U CPEX structure, has two CameraLink Base video input interfaces, one HDMI output display interface, and simultaneously supports online updating of the FPGA program through a serial port, and has the advantages of high integration, easy maintenance and use, etc., meeting the requirements of the chassis and video overlay display function.

[0005] To achieve the above object, the present utility model provides the following technical solutions: A dual-Cameralink to HDMI superimposed display device, comprising: a CameraLink input module, an HDMI output module, an FPGA processing module, a BMC monitoring module, a serial port module, and an LED lighting module; wherein, the FPGA processing module is the main control module, responsible for the parsing, processing, superimposition of two-way CameraLink videos, and the realization of the HDMI output function; the CameraLink input module, the HDMI output module, the BMC monitoring module, the serial port module, and the LED lighting module are respectively connected to the FPGA processing module.

[0006] The model of the FPGA processing module is JFM7VX69T. According to the image scaling and superimposition instructions transmitted through the RS422 serial port 3, it parses, processes, scales, superimposes two-way CameraLink videos, and realizes HDMI output; the FPGA processing module is interconnected with the FLASH through the SPI interface. The model of the SPI FLASH is EFM25QL256, and the capacity of 256 Mbit can meet the requirements of program and related parameter solidification; the FPGA processing module is connected with two pieces of DDR3 memory for caching two-way CameraLink video images. The model of the DDR3 is SCB13H4G160AF-13KI. The two pieces of DDR3 are combined to form a cache with a bit width of 32 and a total capacity of 8 Gbit to meet the video image caching.

[0007] The CameraLink input module includes two B90CR286 chips; the B90CR286 chip realizes the conversion from the CameraLink interface to the 28-bit parallel port, and supports a maximum of 66Mhz CameraLink serial data input; the two B90CR286 chips are respectively introduced from the CPEX connector; the CameraLink input module and the FPGA processing module are connected through the 28-bit parallel port interface.

[0008] The HDMI output module includes two TVS diodes. The model of the TVS diode is AZ1045. The TVS diode mainly prevents external static electricity from damaging the FPGA chip; the HDMI output interface is led out from the P7 connector.

[0009] The BMC monitoring module includes a GD32F407 chip. The GD32F407 chip is interconnected with the EEPROM through the IIC interface. The GD32F407 chip is interconnected with the LTC4300A chip through the IPMB bus. The LTC4300A chip leads out the CPEX connector through the IPMB bus to complete the temperature and voltage monitoring functions of the IPMB bus. The BMC monitoring module and the FPGA processing module are connected through the IIC bus to obtain the temperature and voltage information of the FPGA chip in real time;

[0010] The serial port module includes three RS422 serial ports. One end of RS422 serial port 1 is connected to the GD32F407 chip through an SM3490 transceiver, and the other end is introduced into the front panel J30J connector for printing the serial port debugging information of the BMC monitoring module; One end of RS422 serial port 2 is connected to the FPGA chip through an SM3490 transceiver, and the other end is introduced into the front panel J30J connector for online updating of the FPGA program; One end of RS422 serial port 3 is connected to the FPGA chip through an SM3490 transceiver, and the other end is introduced into the CPEX P3 connector for receiving two image scaling and overlay instructions transmitted by the host.

[0011] The LED lighting module is connected to the FPGA through GPIO. After power-on, the LED lights flash at a specific frequency to indicate that the FPGA chip is working properly.

[0012] The FPGA processing module is connected to RS422 serial port 1 through an SM3490 chip, avoiding the cumbersome process of disassembling the board card required for JTAG program update, with strong versatility and low maintenance cost.

[0013] The FPGA processing module is connected to RS422 serial port 3 through an SM3490 chip to parse, scale, and overlay the output of two CameraLink images.

[0014] Compared with the prior art, the beneficial effects of the present utility model are as follows: 1) It conforms to the standard 6U CPEX structure, with strong versatility and low maintenance cost; 2) It has two CameraLink Base video input functions and one HDMI output display function. The FPGA realizes video parsing processing, overlay, and HDMI output functions, reducing the use of dedicated chips, with high integration and high reliability and adaptability; 3) For the traditional FPGA board card program update, a dedicated emulator and cable are required, and the board card needs to be disassembled. This device supports online updating of the FPGA program through the serial port, avoiding the cumbersome process brought by the dedicated cable and disassembling the board card, and greatly improving the convenience; 4) The BMC monitoring module can monitor voltage and temperature information in real time, obtain the health status of the board card in real time, make full use of the XADC inside the FPGA to obtain voltage and temperature information, reduce the use of voltage and temperature sensing chips, and further reduce costs.

[0015] To more clearly illustrate the functional characteristics and structural parameters of the present utility model, the following further description is provided in conjunction with the drawings and specific embodiments. Description of the Drawings

[0016] The accompanying drawings described herein are used to provide a further understanding of the present utility model and form a part of this application. The schematic embodiments of the present utility model and their descriptions are used to explain the present utility model and do not constitute an improper limitation of the present utility model. In the drawings:

[0017] Figure 1 It is a schematic diagram of the hardware structure of the present utility model. Specific implementation manners

[0018] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments; based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0019] A dual-CameraLink to HDMI overlay display device includes: a CameraLink input module, an HDMI output module, an FPGA processing module, a BMC monitoring module, a serial port module, and an LED lighting module;

[0020] The CameraLink input module, the HDMI output module, the serial port module, and the LED lighting module are respectively connected to the FPGA processing module.

[0021] The CameraLink input module mainly includes two B90CR286 chips; the B90CR286 chips implement the conversion from the CameraLink interface to a 28-bit parallel port, and support a maximum of 66Mhz CameraLink serial data input; the two B90CR286 chips are respectively introduced from the P5 and P6 connectors. The input resolutions of the two CameraLink interfaces are 1920*1080@50Hz and 640*512@50Hz respectively.

[0022] The HDMI output module mainly includes two TVS diodes, and the model of the TVS diodes is AZ1045. The TVS diodes mainly prevent external static electricity from damaging the FPGA chip; the HDMI output interface is led out from the P7 connector. The resolution of the HDMI output interface is 1920*1080@50Hz.

[0023] The FPGA processing module is model JFM7VX69T. According to the image scaling and overlay instructions transmitted through RS422 serial port 3, it parses, processes, scales, overlays two-way CameraLink videos and realizes HDMI output. The program of the FPGA processing module is solidified in the SPI FLASH. The SPI FLASH is model EFM25QL256 with a capacity of 256 Mbit, which can meet the requirements for solidifying the program and related parameters. The FPGA processing module is connected with two pieces of DDR3 for buffering two-way CameraLink video images. The DDR3 is model SCB13H4G160AF-13KI. The two pieces of DDR3 are used together to form a buffer with a bit width of 32 and a total capacity of 8 Gbit to meet the video image buffering requirements.

[0024] The BMC monitoring module includes a GD32F407 chip. The GD32F407 chip obtains the board number information through the EEPROM and communicates with the FPGA chip through the IIC bus to obtain temperature and voltage information. The BMC monitoring module includes a buffer chip LTC4303. The board card introduces the IPMB bus signal from the CPEX connector P1. These signals are connected to the GD32F407 chip after passing through the buffer chip LTC4303 to complete the temperature and voltage monitoring functions of the IPMB bus.

[0025] The serial port module mainly has three RS422 serial ports. One end of RS422 serial port 1 is connected to the GD32F407 chip through an SM3490 transceiver, and the other end is introduced into the front panel J30J connector for printing the serial port debugging information of the BMC monitoring module. One end of RS422 serial port 2 is connected to the FPGA chip through an SM3490 transceiver, and the other end is introduced into the front panel J30J connector for online updating the FPGA program. One end of RS422 serial port 3 is connected to the FPGA chip through an SM3490 transceiver, and the other end is introduced into the CPEX P3 connector for receiving the two-way image scaling and overlay instructions transmitted by the host.

[0026] The LED lighting module is driven by the GPIO of the FPGA chip. After power-on, the LED lights flash at a frequency of 1 Hz to indicate that the FPGA module is working properly.

[0027] The utility model has the advantages of strong versatility and low cost, and can conveniently realize the overlay display from two-way CameraLink to HDMI.

[0028] In the utility model, each module adopts the devices in the prior art, and this application does not include the improvement of the above devices themselves and the computer programs therein.

[0029] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0030] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A dual CameraLink to HDMI overlay display device, characterized in that It includes a CameraLink input module, an HDMI output module, an FPGA processing module, a BMC monitoring module, a serial port module, and an LED lighting module; the FPGA processing module is the main control module, and the CameraLink input module, the HDMI output module, the BMC monitoring module, the serial port module, and the LED lighting module are electrically connected to the FPGA processing module respectively.

2. The dual CameraLink to HDMI overlay display device according to claim 1, wherein The model of the FPGA processing module is JFM7VX69T, and the FPGA processing module is interconnected with the FLASH through the SPI interface; the program of the FPGA processing module is solidified in the SPI FLASH, the model of the SPI FLASH is EFM25QL256, and the capacity is 256 Mbit; the FPGA processing module is connected with two DDR3 memories, the model of the DDR3 memory is SCB13H4G160AF-13KI, and the two DDR3 memories are combined to form a cache with a bit width of 32 and a total capacity of 8 Gbit.

3. The dual CameraLink to HDMI overlay display device according to claim 1, characterized in that, The CameraLink input module includes two B90CR286 chips; the two B90CR286 chips are respectively introduced from the CPEX connector; the CameraLink input module and the FPGA processing module are connected through a 28-bit parallel port interface.

4. A dual CameraLink to HDMI overlay display device according to claim 1, wherein, The HDMI output module includes two TVS diodes, and the model of the TVS diode is AZ1045; the HDMI output interface is led out from the P7 connector.

5. A dual CameraLink to HDMI overlay display device according to claim 1, characterized in that, The BMC monitoring module includes a GD32F407 chip, and the GD32F407 chip is interconnected with the EEPROM through the IIC interface; the GD32F407 chip is interconnected with the LTC4300A chip through the IPMB bus; the LTC4300A chip leads out the CPEX connector through the IPMB bus; the BMC monitoring module and the FPGA processing module are connected through the IIC bus.

6. A dual CameraLink to HDMI overlay display device according to claim 1, wherein The serial port module includes three RS422 serial ports, namely RS422 serial port 1, RS422 serial port 2, and RS422 serial port 3. One end of RS422 serial port 1 is connected to the GD32F407 chip through the SM3490 transceiver, and the other end is introduced into the front panel J30J connector; one end of RS422 serial port 2 is connected to the FPGA chip through the SM3490 transceiver, and the other end is introduced into the front panel J30J connector; one end of RS422 serial port 3 is connected to the FPGA chip through the SM3490 transceiver, and the other end is introduced into the CPEX P3 connector.

7. A dual CameraLink to HDMI overlay display device according to claim 1, wherein The LED lighting module is connected to the FPGA through GPIO.

8. A dual CameraLink to HDMI overlay display device according to claim 6, characterized in that, The FPGA processing module is connected to RS422 serial port 1 through the SM3490 chip.

9. A dual CameraLink to HDMI overlay display device according to claim 6, characterized in that, The FPGA processing module is connected to RS422 serial port 3 through the SM3490 chip.

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