Display device

Abstract

The utility model discloses a display device. The display device includes: a base layer in which a display area and a non-display area are defined; a plurality of pixels arranged on the base layer in a manner corresponding to the display area; a plurality of signal lines arranged on the base layer in a manner corresponding to the display area and connected to the plurality of pixels; and a fan-out wiring portion disposed on the base layer so as to correspond to the non-display area and connected to the plurality of signal lines. Wherein the fan-out wiring portion includes: a plurality of first fan-out wirings arranged at a first interval; and a plurality of second fan-out wires extending from the plurality of first fan-out wires and arranged at a second interval larger than the first interval. At least one of the plurality of first fan-out wires defines an opening.

Description

Technical Field

[0001] The utility model relates to a display device, in particular to a display device with improved reliability. Background Art

[0002] A display device provides information to a user by displaying various images on a display screen. Generally, the display device displays information within a configured screen.

[0003] The display device includes a display area for displaying information and a non-display area surrounding the display area.

[0004] Recently, with the enlargement of the display device, in order to increase the size of the panel and achieve high resolution, the number of signal lines arranged in the non-display area has increased. Accordingly, there are problems that the resistance value of the signal lines increases and the image quality characteristics deteriorate.

[0005] Multiple signal lines are arranged, resulting in a decrease in display quality due to the resistance difference between the signal lines. To solve this problem, a method for measuring the thickness of the signal lines that generate the resistance difference is required. Summary of the Utility Model

[0006] An object of the utility model is to form the fan-out wiring so that the thickness of the fan-out wiring arranged in the non-display area can be easily measured.

[0007] A display device according to an embodiment of the utility model includes: a base layer defining a display area and a non-display area; a plurality of pixels arranged on the base layer corresponding to the display area; a plurality of signal lines arranged on the base layer corresponding to the display area and connected to the plurality of pixels; and a fan-out wiring portion arranged on the base layer corresponding to the non-display area and connected to the plurality of signal lines. The fan-out wiring portion includes: a plurality of first fan-out wirings arranged at a first interval; and a plurality of second fan-out wirings extending from the plurality of first fan-out wirings and arranged at a second interval greater than the first interval. An opening is defined in at least one of the plurality of first fan-out wirings.

[0008] The plurality of first fan-out wirings may include: a plurality of connection wirings connected to the plurality of signal lines; and a plurality of dummy wirings not connected to the plurality of signal lines.

[0009] The opening may be defined in at least one of the plurality of dummy wirings.

[0010] The dummy wiring in which the opening is defined may be arranged on the outermost contour of the plurality of first fan-out wirings.

[0011] The plurality of first fan-out wirings include a plurality of first connection wirings and a plurality of second connection wirings that are alternately arranged with each other on a plane, and the layer on which the plurality of first connection wirings are arranged may be different from the layer on which the plurality of second connection wirings are arranged.

[0012] The plurality of first connection wirings may be arranged on a first insulating layer, and the plurality of second connection wirings may be arranged on a second insulating layer arranged on the first insulating layer.

[0013] The plurality of first connection wirings may include: a plurality of first sub-connection wirings connected to a part of the plurality of signal lines; and a plurality of first dummy wirings not connected to the plurality of signal lines, wherein the plurality of second connection wirings may include: a plurality of second sub-connection wirings connected to another part of the plurality of signal lines; and a plurality of second dummy wirings not connected to the plurality of signal lines.

[0014] The opening may include: a first opening formed in at least one of the plurality of first dummy wirings; and a second opening formed in at least one of the plurality of second dummy wirings.

[0015] The first opening and the second opening may not overlap on the plane.

[0016] The first opening includes a first sub-opening and a second sub-opening defined respectively in two first dummy wirings adjacent to one second sub-connection wiring among the plurality of second sub-connection wirings, and the first sub-opening and the second sub-opening may separate one second sub-connection wiring among the plurality of second sub-connection wirings therebetween.

[0017] The second opening includes a third sub-opening and a fourth sub-opening defined respectively in two second dummy wirings adjacent to one first sub-connection wiring among the plurality of first sub-connection wirings, and the third sub-opening and the fourth sub-opening may separate one first sub-connection wiring among the plurality of first sub-connection wirings therebetween.

[0018] The plurality of first fan-out wirings each have a first width, and the plurality of second fan-out wirings each have a second width, and the first width may be different from the second width.

[0019] The first width and the second width are each constant in the direction in which the plurality of first fan-out wirings and the plurality of second fan-out wirings extend, and the second width may be greater than the first width.

[0020] The non-display area includes a bent area where the base layer is bent, the plurality of first fan-out wirings may be arranged between the bent area and the display area, and the plurality of second fan-out wirings may be arranged in the bent area.

[0021] A display device according to an embodiment of the present invention includes: a base layer defining a display area and a non-display area; a plurality of pixels arranged on the base layer corresponding to the display area; a plurality of signal lines arranged on the base layer corresponding to the display area and connected to the plurality of pixels; and a fan-out wiring portion arranged on the base layer corresponding to the non-display area and connected to the plurality of signal lines. The fan-out wiring portion includes: a plurality of first connection wirings arranged on a first insulating layer and connected to a part of the plurality of signal lines; and a plurality of second connection wirings arranged on a second insulating layer and connected to another part of the plurality of signal lines. At least one of the plurality of first connection wirings and the plurality of second connection wirings defines an opening.

[0022] The plurality of first connection wirings and the plurality of second connection wirings are alternately arranged with each other in a plane.

[0023] The plurality of first connection wirings may include: a plurality of first sub-connection wirings connected to the part of the plurality of signal lines; and a plurality of first dummy wirings not connected to the plurality of signal lines, wherein the plurality of second connection wirings may include: a plurality of second sub-connection wirings connected to the another part of the plurality of signal lines; and a plurality of second dummy wirings not connected to the plurality of signal lines.

[0024] The opening may include: a first opening formed in at least one of the plurality of first dummy wirings; and a second opening formed in at least one of the plurality of second dummy wirings.

[0025] The fan-out wiring portion includes: a plurality of first fan-out wirings arranged at a first interval; and a plurality of second fan-out wirings extending from the plurality of first fan-out wirings and arranged at a second interval greater than the first interval, wherein at least one of the plurality of first fan-out wirings defines an opening.

[0026] The non-display area includes a bent area where the base layer is bent. The plurality of first fan-out wirings may be arranged between the bent area and the display area, and the plurality of second fan-out wirings may be arranged in the bent area.

[0027] The display device of the present invention may include fan-out wiring arranged in the non-display area. The fan-out wiring may include connection wiring connected to the signal line and dummy wiring not connected to the signal line. When measuring the width of the connection wiring, an opening may be defined in the dummy wiring adjacent to the connection wiring to be measured. Accordingly, a display device can be provided: by removing the lower interference that may be caused by the dummy wiring adjacent to the connection wiring whose width is to be measured, the width of the connection wiring can be accurately measured and has reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1Is a perspective view of a display device according to an embodiment of the present utility model.

[0029] Figure 2a Is an exploded perspective view of a display device according to an embodiment of the present utility model.

[0030] Figure 2b Is an exploded perspective view of a display device according to an embodiment of the present utility model.

[0031] Figure 3 Is a cross-sectional view of a display module according to an embodiment of the present utility model.

[0032] Figure 4 Is a plan view of a part included in a display module according to an embodiment of the present utility model.

[0033] Figure 5 Is a cross-sectional view of a display panel according to an embodiment of the present utility model.

[0034] Figure 6 Is an enlarged Figure 4 An enlarged view of the AA' region shown.

[0035] Figure 7a Is along Figure 6 A cross-sectional view taken along the I-I' line shown.

[0036] Figure 7b Is along Figure 6 A cross-sectional view taken along the II-II' line shown.

[0037] Figure 7c Is an enlarged Figure 6 An enlarged view of the BB' region.

[0038] Figure 8a Is an enlarged view of a part of a display panel according to an embodiment of the present utility model.

[0039] Figure 8b Is an enlarged Figure 8a An enlarged view of the CC' region.

[0040] Figure 8c Is along Figure 8b A cross-sectional view taken along the III-III' line shown.

[0041] Figure 9a Is a view showing a display panel and a marking portion according to an embodiment of the present utility model.

[0042] Figure 9b Is an enlarged Figure 9a An enlarged view of the DD' region shown.

[0043] Explanation of reference numerals

[0044] Detailed implementation manners

[0045] The present utility model can be subjected to various changes and can have various forms. Specific embodiments are illustrated in the drawings and are described in detail in the text. However, this does not limit the present utility model to the specific disclosed forms, and it should be understood to include all changes, equivalents, and alternatives included in the concept and technical scope of the present utility model.

[0046] In this specification, when it is mentioned that a certain component (or region, layer, part, etc.) is "on", "connected to", or "coupled to" another component, it means that the component (or region, layer, part, etc.) can be directly arranged on the other component, connected to / coupled to the other component, or a third component can also be arranged between them.

[0047] The same reference numerals refer to the same components. Moreover, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for effective illustration of the technical content.

[0048] The term "and / or" includes all one or more combinations that can be defined by the related components.

[0049] Terms such as "first", "second", etc. can be used to describe various components, but the components are not limited to these terms. These terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the rights of the present utility model, the first component can be named the second component, and similarly, the second component can also be named the first component. Unless the context clearly indicates otherwise, the singular expression also includes the plural expression.

[0050] In addition, terms such as "below", "under", "above", "on the upper side", etc. are used to describe the relative relationship of the components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0051] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as that commonly understood by those skilled in the technical field to which the present utility model belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as idealized or overly formal meanings unless clearly defined herein.

[0052] Terms such as "comprising" or "having" shall be understood as specifying the presence of the features, numbers, steps, operations, components, parts, or combinations thereof recited in the specification, rather than precluding the presence or additional possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of a display device according to an embodiment of the present invention. Figure 2a and Figure 2b is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 2b shows a state in which the display panel DP in the display device DD is bent. In this specification, a mobile terminal is exemplarily shown as the display device DD. The display device DD according to the present invention can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablet computers, car navigation devices, game consoles, and smart watches.

[0055] Referring to Figure 1 , the display device DD can display an image IM through a display surface DD-IS. As an example of the image IM, an icon image is shown. The display surface DD-1S is parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DD-1S (i.e., the thickness direction of the display device DD) is indicated by the third direction DR3.

[0056] The display surface DD-1S includes a display area DD-DA for displaying the image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is an area where no image is displayed. However, it is not limited thereto, and the non-display area DD-NDA can be adjacent to any side of the display area DD-DA, or can be omitted.

[0057] In this specification, the meaning of "when viewed from a plane or on a plane" can represent the case of viewing from the third direction DR3. The front surface (or upper surface) and the back surface (or lower surface) of each layer or unit described below are distinguished by the third direction DR3. However, the combination of the first direction DR1 to the third direction DR3 can be changed to other combinations.

[0058] Referring to Figure 2a and Figure 2b , the display device DD can include a window WM, a display module DM, and a housing member BC.

[0059] The window WM is arranged on the upper part of the display module DM, allowing the image provided by the display module DM to be transmitted to the outside. The window WM includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA overlaps with the Figure 1 display area DD-DA shown, and may have a shape corresponding to the display area DD-DA. The window WM may include a base layer and a functional layer disposed on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM may be made of glass, sapphire, plastic, etc. The base layer of the window WM may include an optically transparent insulating material. For example, the base layer of the window WM may include glass or plastic. The base layer of the window WM may have a multi-layer structure or a single-layer structure. For example, the base layer of the window WM may include a plurality of plastic films bonded by an adhesive, or may include a glass substrate and a plastic film bonded by an adhesive.

[0060] The non-transmissive area NTA may overlap with the non-display area DD-NDA and may have a shape corresponding to the non-display area DD-NDA. The non-transmissive area NTA may be an area with a relatively low light transmittance compared to the transmissive area TA. The non-transmissive area NTA may be defined by arranging a border pattern in a part of the base layer of the window WM, and the area where the border pattern is not arranged may be defined as the transmissive area TA. However, the technical concept of the present utility model is not limited thereto, and the non-transmissive area NTA may also be omitted.

[0061] Although not shown, an anti-reflection layer may be disposed between the window WM and the display module DM. The anti-reflection layer may reduce the reflectance of external light incident from the outside of the display device DD. The anti-reflection layer may include a color filter. The color filter may have a predetermined arrangement. For example, the color filter may be arranged in consideration of the light-emitting colors of the pixels in the display panel DP to be described later. In addition, the anti-reflection layer may further include a black matrix adjacent to the color filter.

[0062] According to an embodiment of the present utility model, the display module DM may include a display panel DP and an input sensor ISU.

[0063] The display panel DP can be any one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, an electrowetting display panel, an organic light emitting display panel, an inorganic light emitting display panel, and a quantum dot light emitting display panel. However, it is not particularly limited thereto. Hereinafter, the display panel DP is described as an organic light emitting display panel.

[0064] The input sensor ISU can include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensor ISU can be formed on the display panel DP by a continuous process, or can be attached to the upper side of the display panel DP through an adhesive layer after being separately manufactured, not limited to a certain embodiment.

[0065] The display module DM can include a printed circuit board CF and a driving chip DC. Although not shown, the main circuit board can be arranged on one side of the printed circuit board CF. The printed circuit board CF can electrically connect the display panel DP to the main circuit board. Figure 2a An embodiment in which the driving chip DC is mounted on the display panel DP is shown, but it is not limited thereto. The driving chip DC can generate a driving signal required to operate the display panel DP based on a control signal transmitted from the printed circuit board CF.

[0066] The display panel DP can include a bending region BA, a first non-bending region NBA1, and a second non-bending region NBA2, wherein the first non-bending region NBA1 and the second non-bending region NBA2 are arranged at intervals along the second direction DR2 with the bending region BA therebetween.

[0067] The bending region BA can be defined as the region where the display panel DP bends along a virtual bending axis BX extending in the first direction DR1. The first non-bending region NBA1 can be defined as the region overlapping with the transmissive region TA, and the second non-bending region NBA2 can be defined as the region connected to the printed circuit board CF. When the bending region BA of the display panel DP bends with the bending axis BX as a reference, the printed circuit board CF and the driving chip DC can be arranged below the back surface of the display panel DP. Although not shown, an additional structure for compensating the step difference between the printed circuit board CF and the back surface of the display panel DP generated by the bending region BA can be arranged.

[0068] According to an embodiment, the width of the first non-bending region NBA1 in the second direction DR2 can be greater than the widths of the bending region BA and the second non-bending region NBA2 in the second direction DR2. However, this is not limited thereto, and the width of the bending region BA in the second direction DR2 can be set to a shape that narrows from the first non-bending region NBA1 toward the second non-bending region NBA2, not limited to any one embodiment.

[0069] As Figure 2b shown, as a part of the display panel DP is bent, the printed circuit board CF electrically connected to the display panel DP can be arranged on the back surface of the display panel DP.

[0070] The housing member BC can house the display module DM and be combined with the window WM. The printed circuit board CF can be arranged at one end of the display panel DP and electrically connected to the circuit element layer DP-CL (refer to Figure 3 ). Although not shown, the display device DD can further include a main board, an electronic module mounted on the main board, a camera module, a power module, etc.

[0071] Above, a mobile phone terminal has been described as an example of the display device DD, but in this specification, the display device DD can include two or more electrically connected electronic components. The display panel DP and the driving chip DC mounted on the display panel DP respectively correspond to different electronic components, and the display device DD can also be constituted only by them, not limited to any one embodiment.

[0072] In an embodiment, the display device DD can be constituted only by the display panel DP and the printed circuit board CF connected to the display panel DP, or can be constituted only by the main board and the electronic module mounted on the main board. Hereinafter, the display device DD according to the present utility model will be described centering on the bonding structure of the display panel DP and the driving chip DC mounted on the display panel DP.

[0073] Figure 3 is a cross-sectional view of a display module according to an embodiment of the present utility model. Figure 4It is a plan view formed by a part included in a display module according to an embodiment of the present utility model.

[0074] Referring to Figure 3 , the display panel DP includes a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and an upper insulating layer TFL. The input sensor ISU can be disposed on the upper insulating layer TFL.

[0075] The display panel DP includes a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP corresponds to Figure 1 the display area DD-DA shown in Figure 2a or the transmissive area TA shown in Figure 1 , and the non-display area DP-NDA corresponds to Figure 2a the non-display area DD-NDA shown in

[0076] or the non-transmissive area NTA shown in

[0077] The non-display area DP-NDA can be referred to as a border area. The base layer BL may include at least one plastic film. As a flexible substrate, the base layer BL may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc.

[0078] The circuit element layer DP-CL includes at least one intermediate insulating layer and circuit elements. The intermediate insulating layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements include signal lines, driving circuits of pixels, etc.

[0079] The display element layer DP-OLED includes a plurality of organic light-emitting diodes. The display element layer DP-OLED may further include an organic layer such as a pixel defining film.

[0080] In an embodiment of the present invention, a packaging substrate may be provided to replace the upper insulating layer TFL. In this case, the packaging substrate may face the base layer BL, and the circuit element layer DP-CL and the display element layer DP-OLED may be disposed between the packaging substrate and the base layer BL.

[0081] The input sensor ISU may be directly disposed on the display panel DP. In this specification, "A is directly disposed on B" means that no separate layer is disposed between A and B. In this embodiment, the input sensor ISU and the display panel DP may be manufactured by a continuous process. However, the technical concept of the present invention is not limited thereto, and the input sensor ISU may be provided as a separate panel and may be bonded to the display panel DP through an adhesive layer. As an example, the input sensor ISU may be omitted.

[0082] Referring to Figure 4 , the display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, a fan-out wiring portion FOP, and a plurality of display pads SD.

[0083] The pixels PX are disposed in the display area DP-DA. Each of the pixels PX includes an organic light-emitting diode and a pixel driving circuit connected thereto. The gate driving circuit GDC and the signal lines SGL may be included in the Figure 3 circuit element layer DP-CL shown.

[0084] The gate driving circuit GDC sequentially outputs gate signals to a plurality of gate lines GL. The gate driving circuit GDC may include a plurality of thin film transistors formed by the same process as the driving circuit of the pixel PX (for example, a low temperature polycrystalline silicon (LTPS: Low Temperature Polycrystalline Silicon) process or a low temperature polycrystalline oxide (LTPO: Low Temperature Polycrystalline Oxide) process). The display panel DP may further include another driving circuit that provides a light emission control signal to the pixels PX.

[0085] The signal lines SGL include gate lines GL, data lines DL, power supply lines PL, and control signal lines CSL. The gate lines GL are respectively connected to the corresponding pixels PX in the pixels PX, and the data lines DL are respectively connected to the corresponding pixels PX in the pixels PX. The power supply lines PL are connected to the pixels PX. The control signal lines CSL may provide control signals to the scan driving circuit.

[0086] The signal line SGL can be arranged in the display area DP-DA. The control signal line CSL in the signal line SGL overlaps with the non-display area DP-NDA. The fan-out wiring part FOP can be provided in the non-display area DP-NDA. The fan-out wiring part FOP can be in contact with the pad part described later to electrically connect the pad part and the signal line SGL.

[0087] The fan-out wiring part FOP can include a connection wiring CNL connected to the signal line SGL and a dummy wiring DML not connected to the signal line SGL. The connection wiring CNL can be connected to at least one of the gate line GL, data line DL, and power line PL in the signal line SGL to be electrically connected to the pad part described later.

[0088] The display panel DP can include a plurality of display pads SD. Each of the plurality of display pads SD can be arranged at a predetermined interval. The plurality of display pads SD according to an embodiment can be arranged to overlap with the second non-bending area NBA2. The plurality of display pads SD can be arranged in the connection area CA of the second non-bending area NBA2. The connection area CA, as the area in the second non-bending area NBA2 where the display pads SD are arranged, can be defined as the area where the printed circuit board CF is attached.

[0089] The display pads SD can be arranged to overlap with the connection area CA. A driving chip DC can be mounted on the second non-bending area NBA2. The display pads SD are electrically connected to the driving chip DC, so that the electrical signals received from the driving chip DC can be transmitted to the signal line SGL.

[0090] The printed circuit board CF can include a substrate pad CF-PD electrically connected to the display panel DP. The substrate pads CF-PD can be arranged along the first direction DR1.

[0091] The display pads SD are electrically connected to the substrate pads CF-PD included in the printed circuit board CF, so as to transmit the electrical signals received from the printed circuit board CF to the display panel DP. The printed circuit board CF can be rigid or flexible.

[0092] The printed circuit board CF can include a timing control circuit for controlling the operation of the display panel DP. The timing control circuit can be mounted on the printed circuit board CF in the form of an integrated chip. In addition, although not shown, the printed circuit board CF can include an input sensing circuit for controlling the input sensor ISU (refer to Figure 2a )).

[0093] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0094] Refer to Figure 5, the display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA. Each of the pixels PX includes an organic light-emitting diode OLED and a pixel driving circuit connected thereto. Specifically, the pixel PX may include a transistor TR and an organic light-emitting diode OLED. A part of the transistors TR in the pixel driving circuit is shown.

[0095] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layer, semiconductor layer, and conductive layer are formed by coating, deposition, etc. Then, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned by photolithography. In this way, the semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED are formed.

[0096] The base layer BL may include a synthetic resin film. The base layer BL may have a multi-layer structure. For example, the base layer BL may also have a three-layer structure of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc.

[0097] At least one inorganic layer is disposed on the upper surface of the base layer BL. The inorganic layer may be formed into multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In this embodiment, it is shown as a case where the display panel DP includes a buffer layer BFL.

[0098] A semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide.

[0099] Figure 5 Only a part of the semiconductor pattern is shown, and semiconductor patterns may also be disposed in other areas of the pixels PX on the plane. The semiconductor patterns may be arranged in a specific rule in the pixels. The electrical properties of the semiconductor patterns are different depending on whether they are doped or not. The semiconductor pattern may include a first region and a second region. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant.

[0100] The conductivity of the first region is greater than that of the second region, and it substantially functions as an electrode or a signal line. The second region may be a low-doping concentration region or a non-doped region, and it substantially corresponds to the channel region of the transistor. In other words, a part of the semiconductor pattern may be the channel region of the transistor, another part may be the source or drain of the transistor, and still another part may be the connection electrode or the connection signal line.

[0101] AsFigure 5 As shown, the source S, channel region A, and drain D of the transistor TR are formed of a semiconductor pattern.

[0102] Figure 5 A part of the connection signal line SCL formed of the semiconductor pattern is shown. Although not shown separately, the connection signal line SCL can be electrically connected to the drain D of the transistor TR on the plane. Another transistor can be arranged between the connection signal line SCL and the drain D of the transistor TR.

[0103] A first insulating layer 10 is arranged on the buffer layer BFL. The first insulating layer 10 commonly overlaps a plurality of pixels PX and covers the semiconductor pattern. A gate G is arranged on the first insulating layer 10. The gate G can be a part of a metal pattern. The gate G overlaps the channel region A. In the process of doping the semiconductor pattern, the gate G acts as a mask.

[0104] A second insulating layer 20 covering the gate G is arranged on the first insulating layer 10. The second insulating layer 20 commonly overlaps the pixels PX. An upper electrode UE can be arranged on the second insulating layer 20. The upper electrode UE can overlap the gate G of the transistor TR. The upper electrode UE can be a part of a metal pattern. A part of the gate G and the upper electrode UE overlapping therewith can define a capacitor.

[0105] Although not shown, a first gate wiring formed by the same process as the gate G and a second gate wiring formed by the same process as the upper electrode UE can be defined. The first gate wiring and the second gate wiring can form a part of the fan-out wiring portion FOP (refer to Figure 6 ).

[0106] A third insulating layer 30 covering the upper electrode UE is arranged on the second insulating layer 20. The first connection electrode CNE1 arranged on the third insulating layer 30 can be connected to the connection signal line SCL through a contact hole CNT-1 penetrating the first insulating layer 10 to the third insulating layer 30.

[0107] A fourth insulating layer 40 covering the first connection electrode CNE1 is arranged on the third insulating layer 30. The first insulating layer 10 to the fourth insulating layer 40 can be an inorganic layer and / or an organic layer and can have a single-layer or multi-layer structure.

[0108] A fifth insulating layer 50 is arranged on the fourth insulating layer 40. The fifth insulating layer 50 can be an organic layer. A second connection electrode CNE2 can be arranged on the fifth insulating layer 50. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50.

[0109] On the fifth insulating layer 50, a sixth insulating layer 60 covering the second connection electrode CNE2 is disposed. The sixth insulating layer 60 may be an organic layer. On the sixth insulating layer 60, a first electrode AE is disposed. The first electrode AE is connected to the second connection electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60.

[0110] In the pixel defining film PDL, a pixel opening OPN is defined. The pixel opening OPN of the pixel defining film PDL exposes at least a part of the first electrode AE. In the present embodiment, the light emitting region PXA is defined to correspond to a part of the region of the first electrode AE exposed through the pixel opening OPN.

[0111] The hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer HCL includes a hole transport layer and may further include a hole injection layer. On the hole control layer HCL, a light emitting layer EML is disposed. The light emitting layer EML may be disposed in a region corresponding to the pixel opening OPN. That is, the light emitting layer EML may be separately formed in each of the pixels. However, not limited thereto, the light emitting layer EML may also be commonly formed in a plurality of pixels PX using an opening mask.

[0112] On the light emitting layer EML, an electron control layer ECL is disposed. The electron control layer ECL includes an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly formed in a plurality of pixels using an opening mask. On the electron control layer ECL, a second electrode CE is disposed. The second electrode CE has an integral shape and is commonly disposed in a plurality of pixels PX (refer to Figure 4 ). On the second electrode CE, an upper insulating layer TFL is disposed. The upper insulating layer TFL may include a plurality of thin films.

[0113] Figure 6 is an enlarged Figure 4 view of the AA' region shown. Figure 7a is a cross-sectional view taken along the Figure 6 I-I' line shown. Figure 7b is a cross-sectional view taken along the Figure 6 II-II' line shown. Specifically, Figure 6 is a view showing Figure 4 a part of the fan-out wiring portion FOP shown, Figure 7a is a cross-sectional view taken of a plurality of first fan-out wirings FOL1, Figure 7b is a cross-sectional view taken of a plurality of second fan-out wirings FOL2. Figure 7c is an enlarged Figure 6 view of the BB' region.

[0114] Refer to Figure 6, the fan-out wiring portion FOP may include a plurality of first fan-out wirings FOL1 and a plurality of second fan-out wirings FOL2 extending from the plurality of first fan-out wirings FOL1.

[0115] Referring to Figure 4 and Figure 6 , the plurality of first fan-out wirings FOL1 may be wirings extending from the signal line SGL. For example, the plurality of first fan-out wirings FOL1 may be wirings extending from the data line DL in the signal line SGL. The plurality of first fan-out wirings FOL1 may extend in an oblique direction DR4 with respect to the first direction DR1 and the second direction DR2. The oblique direction (hereinafter referred to as the fourth direction) DR4 may be a direction further biased toward the first direction DR1. The plurality of second fan-out wirings FOL2 may extend from the plurality of first fan-out wirings FOL1. The plurality of second fan-out wirings FOL2 may extend parallel to the second direction DR2 and be arranged along the first direction DR1.

[0116] The non-display area DP-NDA may include a bending area BA. According to an embodiment of the present invention, the plurality of first fan-out wirings FOL1 may be arranged between the bending area BA and the display area DP-DA, and the plurality of second fan-out wirings FOL2 may overlap with the bending area BA of the non-display area DP-NDA.

[0117] Referring to Figure 6 and Figure 7a , the plurality of first fan-out wirings FOL1 may include a plurality of first connection wirings CL1 and a plurality of second connection wirings CL2 alternately arranged with each other on a plane. According to an embodiment of the present invention, the layers on which the plurality of first connection wirings CL1 and the plurality of second connection wirings CL2 are arranged may be different from each other. For example, the plurality of first connection wirings CL1 may be arranged on the first insulating layer 10, and the plurality of second connection wirings CL2 may be arranged on the second insulating layer 20.

[0118] The plurality of first connection wirings CL1 may be formed by the same process as the gate G shown in Figure 5 . And, the plurality of second connection wirings CL2 may be formed by the same process as the upper electrode UE shown in Figure 5 . That is, the gate G and the plurality of first connection wirings CL1 may be components included in the first gate wiring, and the upper electrode UE and the plurality of second connection wirings CL2 may be components included in the second gate wiring.

[0119] Referring to Figure 6 and Figure 7b, a plurality of second fan-out wirings FOL2 may include a plurality of third connection wirings CL3 and a plurality of fourth connection wirings CL4 that are alternately arranged with each other on a plane. According to an embodiment of the present invention, the layers on which the plurality of third connection wirings CL3 and the plurality of fourth connection wirings CL4 are arranged may be different from each other. For example, the plurality of third connection wirings CL3 may be arranged on the first insulating layer 10, and the plurality of fourth connection wirings CL4 may be arranged on the second insulating layer 20. The plurality of third connection wirings CL3 extend from Figure 7a the plurality of first connection wirings CL1 shown, and the plurality of fourth connection wirings CL4 extend from Figure 7a the plurality of second connection wirings CL2 shown.

[0120] The plurality of third connection wirings CL3 may be formed by the same process as the Figure 5 gate G shown. And, the plurality of fourth connection wirings CL4 may be formed by the same process as the Figure 5 upper electrode UE shown. That is, the plurality of third connection wirings CL3 may be included in the first gate wiring like the plurality of first connection wirings CL1, and the plurality of fourth connection wirings CL4 may be included in the second gate wiring like the second connection wiring CL2.

[0121] Referring to Figures 6 to 7b , the width of each of the plurality of first connection wirings CL1 and the plurality of second connection wirings CL2 may be the same, and the width of each of the plurality of third connection wirings CL3 and the plurality of fourth connection wirings CL4 may be the same. The width of each of the plurality of first connection wirings CL1 and the plurality of second connection wirings CL2 may be defined as a first width W1, and the width of each of the plurality of third connection wirings CL3 and the plurality of fourth connection wirings CL4 may be defined as a second width W2. According to an embodiment of the present invention, the first width W1 and the second width W2 may be different from each other. For example, the second width W2 may be greater than the first width W1.

[0122] The interval D1 between the plurality of first connection wirings CL1 and the adjacent plurality of second connection wirings CL2 may be the same for each, and the interval D2 between the plurality of third connection wirings CL3 and the adjacent plurality of fourth connection wirings CL4 may be the same for each. The interval D1 between the plurality of first connection wirings CL1 and the adjacent plurality of second connection wirings CL2 may be defined as a first interval D1. The interval D2 between the plurality of third connection wirings CL3 and the adjacent plurality of fourth connection wirings CL4 may be defined as a second interval D2. According to an embodiment of the present invention, the first interval D1 and the second interval D2 may be different from each other. For example, the second interval D2 may be greater than the first interval D1.

[0123] Referring again to Figure 7a, a plurality of first connection wirings CL1 and a plurality of second connection wirings CL2 can be arranged on different layers from each other and do not overlap with each other in a plane, and are alternately arranged with each other in the plane. Accordingly, a large number of the plurality of first connection wirings CL1 and the plurality of second connection wirings CL2 can be arranged in the same area, and the width of each of the plurality of first connection wirings CL1 and the plurality of second connection wirings CL2 can be increased. When the widths of the connection wirings CL1 and CL2 are increased, the resistance of the connection wirings CL1 and CL2 is reduced, and the scanning speed of the signal lines is increased, thereby improving the quality of the display device DD (refer to Figure 1 ).

[0124] Refer to Figure 7c , a plurality of first fan-out wirings FOL1 can include a plurality of connection wirings CNL connected to a signal line SGL (refer to Figure 4 ) and a first dummy wiring DMLa to a third dummy wiring DMLc not connected to the signal line SGL. According to an embodiment of the present invention, openings OP can be defined in the first dummy wiring DMLa and the third dummy wiring DMLc. The opening OP can include a first sub-opening SOP1 and a second sub-opening SOP2 that face each other with the second dummy wiring DMLb therebetween. Without being limited thereto, the second dummy wiring DMLb can be one of the plurality of connection wirings CNL. The first sub-opening SOP1 and the second sub-opening SOP2 can be respectively formed in the first dummy wiring DMLa and the third dummy wiring DMLc. The first sub-opening SOP1 and the second sub-opening SOP2 can separate the second dummy wiring DMLb therebetween.

[0125] The width W3 of the first sub-opening SOP1 and the width W4 of the second sub-opening SOP2 can be the same as each other. For example, the lengths of the width W3 of the first sub-opening SOP1 and the width W4 of the second sub-opening SOP2 can be 4 μm or more. Specifically, the lengths of the width W3 of the first sub-opening SOP1 and the width W4 of the second sub-opening SOP2 can be 4 μm or more and 6 μm or less.

[0126] As Figure 7c shown, the first dummy wiring DMLa and the third dummy wiring DMLc in which the opening OP is defined can be arranged on the outermost contour of the plurality of first fan-out wirings FOL1. However, without being limited thereto, the dummy wirings DMLa and DMLc in which the opening OP is defined can be arranged in the middle of the first fan-out wirings FOL1, not limited to this embodiment.

[0127] Refer to together Figure 7a and Figure 7c, the first dummy wiring DMLa and the third dummy wiring DMLc may be included in the first gate wiring, and the second dummy wiring DMLb may be included in the second gate wiring. That is, the first dummy wiring DMLa and the third dummy wiring DMLc may be disposed on the first insulating layer 10, and the second dummy wiring DMLb may be disposed on the second insulating layer 20. Substantially, the widths of the plurality of connection wirings CNL and the first dummy wiring DMLa to the third dummy wiring DMLc are the same. Therefore, the width of the plurality of connection wirings CNL can be measured by measuring the width of the second dummy wiring DMLb. Openings OP may be defined in the first dummy wiring DMLa and the third dummy wiring DMLc disposed adjacent to the second dummy wiring DMLb. Accordingly, when measuring the width of the second dummy wiring DMLb, lower interference that may be caused by the first dummy wiring DMLa and the third dummy wiring DMLc is removed, so that the width of the second dummy wiring DMLb can be accurately measured, and the width of the plurality of connection wirings CNL can be indirectly measured through the width of the second dummy wiring DMLb. As a result, a reliable display device DD (refer to Figure 1 ). In this embodiment, the width of the connection wiring CNL included in the second gate wiring is measured. This is because the connection wiring CNL included in the first gate wiring can be measured before the connection wiring CNL included in the second gate wiring is formed.

[0128] Figure 8a is an enlarged view of a part of a display panel according to an embodiment of the present invention. Figure 8b is an enlarged Figure 8a of the CC' region. Figure 8c is a cross-sectional view taken along the Figure 8b shown III-III' line. Figure 8a is a view showing another embodiment of enlarging the Figure 4 AA' region.

[0129] Refer to Figures 8a to 8c , a plurality of first fan-out wirings FOL1a may include a plurality of first connection wirings CL1a and a plurality of second connection wirings CL2a that are alternately arranged with each other on a plane. The plurality of first connection wirings CL1a may include a plurality of first sub-connection wirings SCL1a, SCL1b that are connected to a part of the signal lines SGL (refer to Figure 4 ), and a plurality of first dummy wirings DML1a, DML1b that are not connected to the signal lines SGL. The plurality of first sub-connection wirings SCL1a, SCL1b and the plurality of first dummy wirings DML1a, DML1b may be disposed on the first insulating layer 10 and included in the first gate wiring.

[0130] A plurality of second connection wirings CL2a may include a plurality of second sub-connection wirings SCL2a, SCL2b connected to a part of the signal lines SGL, and a plurality of second dummy wirings DML2a, DML2b not connected to the signal lines SGL. The plurality of second sub-connection wirings SCL2a, SCL2b and the plurality of second dummy wirings DML2a, DML2b may be disposed on the second insulating layer 20 and included in the second gate wiring.

[0131] According to an embodiment of the present invention, a first opening OP1 may be formed in the first dummy wirings DML1a, DML1b, and a second opening OP2 may be formed in the second dummy wirings DML2a, DML2b. The first opening OP1 and the second opening OP2 may not overlap with each other in a plane.

[0132] The first opening OP1 may include a first sub-opening SOP1a and a second sub-opening SOP2a formed in the first dummy wirings DML1a, DML1b. The first sub-opening SOP1a and the second sub-opening SOP2a may face each other with the second sub-connection wiring SCL2b therebetween. For example, the first sub-opening SOP1a and the second sub-opening SOP2a may be spaced apart with the second sub-connection wiring SCL2b therebetween.

[0133] The second opening OP2 may include a third sub-opening SOP3 and a fourth sub-opening SOP4 formed in the second dummy wirings DML2a, DML2b. The third sub-opening SOP3 and the fourth sub-opening SOP4 may face each other with the first sub-connection wiring SCL1a therebetween. For example, the third sub-opening SOP3 and the fourth sub-opening SOP4 may be spaced apart with the first sub-connection wiring SCL1a therebetween.

[0134] The first opening OP1 and the second opening OP2 may be arranged spaced apart from each other in the fourth direction DR4. Specifically, the second sub-opening SOP2a and the third sub-opening SOP3 may be arranged spaced apart from each other in the fourth direction DR4. For example, the interval D3 between the second sub-opening SOP2a and the third sub-opening SOP3 spaced apart from each other in the fourth direction DR4 may be 8 μm or more and 10 μm or less. When measuring the widths of the first sub-connection wiring SCL1a and the second sub-connection wiring SCL2b by an inspection device, the widths of the first sub-connection wiring SCL1a and the second sub-connection wiring SCL2b may be measured by one inspection image. At this time, the maximum distance between the first sub-connection wiring SCL1a and the second sub-connection wiring SCL2b that can be measured by one inspection image may be 10 μm or less. Therefore, when the interval D3 between the second sub-opening SOP2a and the third sub-opening SOP3 spaced apart from each other in the fourth direction DR4 is formed to be 8 μm or more and 10 μm or less, since the widths of the second sub-connection wiring SCL2b and the first sub-connection wiring SCL1a can be measured by one inspection, the inspection efficiency can be improved.

[0135] Figure 9a FIG. is a diagram showing a display panel and a marking portion according to an embodiment of the present invention. Figure 9b is an enlarged Figure 9a enlarged view of the DD' area shown.

[0136] Referring to Figure 9a , a marking portion TGP may be arranged on the lower side of the display panel DP. Specifically, the marking portion TGP may be arranged adjacent to the second non-bending area NBA2 of the display panel DP. A marking wiring portion TLP may be arranged in the marking portion TGP. The marking portion TGP, as a portion provided for inspecting the display panel DP of the present invention, may be truncated from the display panel DP after the inspection of the display panel DP is completed.

[0137] Figure 9a The fan-out wiring portion FOP shown may not be defined with an opening OP as Figure 7c . The marking wiring portion TLP may function to measure Figure 6 the width of the first fan-out wiring FOL1 of the fan-out wiring portion FOP shown.

[0138] Referring to Figure 9b , the marking wiring portion TLP may include a plurality of marking wirings. A marking opening TOP may be defined in a part of the plurality of marking wirings. For ease of explanation, three of the plurality of marking wirings are respectively referred to as a first marking wiring TLa, a second marking wiring TLb, and a third marking wiring TLc.

[0139] The width of each of the first to third mark wirings TLa to TLc and the distance between the first to third mark wirings TLa to TLc can be the same as Figure 8a the width of the first fan-out wiring FOL1 shown and the distance between the first fan-out wirings FOL1. The first mark wiring TLa and the third mark wiring TLc are arranged on the same layer as Figure 7a the plurality of first connection wirings CL1, and the second mark wiring TLb is arranged on the same layer as Figure 7a the plurality of second connection wirings CL2.

[0140] The mark opening TOP may include a first sub-mark opening STOP1 and a second sub-mark opening STOP2 formed in the first mark wiring TLa and the third mark wiring TLc, respectively. When measuring the width of the second mark wiring TLb, based on the formation of the first sub-mark opening STOP1 and the second sub-mark opening STOP2 in the first mark wiring TLa and the third mark wiring TLc, respectively, the width of the second mark wiring TLb between the first sub-mark opening STOP1 and the second sub-mark opening STOP2 can be accurately measured. That is, the width of Figure 8a the plurality of first fan-out wirings FOL1 shown can be indirectly measured by measuring the width of the second mark wiring TLb.

[0141] As described above, the preferred embodiments of the present invention have been described. However, it can be understood by those skilled in the art of the present invention or those with ordinary knowledge in the technical field of the present invention that various modifications and changes can be made to the present invention without departing from the concept and technical field of the present invention described in the claims.

[0142] Therefore, the technical scope of the present invention should be determined only by the claims and is not limited to the content described in the detailed description of the specification.

Claims

1. A display device, characterized in that, Comprising: A base layer, which defines a display area and a non-display area; A plurality of pixels, arranged on the base layer in a manner corresponding to the display area; A plurality of signal lines, arranged on the base layer in a manner corresponding to the display area and connected to the plurality of pixels; And A fan-out wiring portion, arranged on the base layer in a manner corresponding to the non-display area and connected to the plurality of signal lines, wherein the fan-out wiring portion includes: A plurality of first fan-out wirings, arranged at a first interval; and A plurality of second fan-out wirings, extending from the plurality of first fan-out wirings and arranged at a second interval greater than the first interval, An opening is defined in at least one of the plurality of first fan-out wirings.

2. The display device according to claim 1, characterized in that The plurality of first fan-out wirings include: A plurality of connection wirings, connected to the plurality of signal lines; and A plurality of dummy wirings, not connected to the plurality of signal lines.

3. The display device according to claim 2, characterized in that The opening is defined in at least one of the plurality of dummy wirings.

4. The display device according to claim 3, characterized in that The dummy wiring in which the opening is defined is arranged on the outermost contour of the plurality of first fan-out wirings.

5. The display device according to claim 1, characterized in that The plurality of first fan-out wirings include a plurality of first connection wirings and a plurality of second connection wirings alternately arranged with each other in a plane, The layer on which the plurality of first connection wirings are arranged is different from the layer on which the plurality of second connection wirings are arranged.

6. The display device according to claim 5, characterized in that The plurality of first connection wirings are arranged on a first insulating layer, The plurality of second connection wirings are arranged on a second insulating layer arranged on the first insulating layer.

7. The display device according to claim 5, characterized in that The plurality of first connection wirings include: A plurality of first sub-connection wirings, connected to a part of the plurality of signal lines; and A plurality of first dummy wirings, not connected to the plurality of signal lines, The plurality of second connection wirings include: A plurality of second sub-connection wirings, connected to another part of the plurality of signal lines; and A plurality of second dummy wirings, not connected to the plurality of signal lines.

8. The display device according to claim 7, characterized in that The opening includes: A first opening, formed in at least one of the plurality of first dummy wirings; and A second opening, formed in at least one of the plurality of second dummy wirings.

9. The display device according to claim 8, characterized in that The first opening and the second opening do not overlap in a plane.

10. The display device according to claim 8, characterized in that The first opening includes a first sub-opening and a second sub-opening defined in two first dummy wirings adjacent to one second sub-connection wiring among the plurality of second sub-connection wirings respectively, The first sub-opening and the second sub-opening separate the one second sub-connection wiring among the plurality of second sub-connection wirings therebetween.

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