Display device

Abstract

A display device includes a display panel including a display area in which a light emitting element and a signal line are disposed, and a non-display area adjacent to the display area and in which a pad connected to the signal line is disposed. The pad includes: a first conductive pattern at which the pad is connected to the signal line; an insulating pattern on the first conductive pattern and defining protrusions adjacent to each other in a direction along the first conductive pattern; a second conductive pattern on the insulating pattern and electrically connected to the first conductive pattern; and a conductive member between the protrusions and at least partially in the second conductive pattern.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0113040, filed on August 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device and a method for providing (or manufacturing) a display device. More specifically, embodiments relate to a display device including pads with improved bonding reliability and a method for providing (or manufacturing) the display device. Background Art

[0003] A display device includes a display area activated in response to an electrical signal. The display device can sense an input applied from outside the display device through the display area while displaying various images to be provided to a user in the display area.

[0004] A display device includes a display panel and a circuit board. The display panel can be connected to a main board through the circuit board. A driving circuit chip can be mounted on the display panel. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display device with improved bonding reliability and a method for providing (or manufacturing) the display device.

[0006] According to an embodiment of the present disclosure, a display device includes: a display panel including a display area and a non-display area adjacent to the display area; an insulating layer disposed on a base layer; a light-emitting element disposed in the display area; a pad disposed in the non-display area; and a signal line connected to the pad. The pad includes: a first conductive pattern connected to the signal line and disposed on the insulating layer; an insulating pattern including a protrusion protruding in a direction away from the first conductive pattern and disposed on the first conductive pattern; a second conductive pattern disposed on the insulating pattern; and a conductive member disposed between the protrusions. At least a portion of the conductive member can be inserted into the second conductive pattern such that the conductive member is at least partially within the second conductive pattern.

[0007] The insulating pattern may have a continuous integral form, the protrusion may include a first protrusion and a second protrusion connected to the first protrusion, and a recess may be defined between the first protrusion and the second protrusion.

[0008] Each of the protrusions may have a width in the direction in which the protrusions are arranged that decreases in a direction away from the first conductive pattern.

[0009] At least a portion of the conductive member can be inserted into the insulating pattern.

[0010] The second conductive pattern may include a 2-1 pattern layer, a 2-2 pattern layer disposed on the 2-1 pattern layer, and a 2-3 pattern layer disposed on the 2-2 pattern layer. The 2-1 pattern layer and the 2-3 pattern layer may include titanium (Ti), and the 2-2 pattern layer may include aluminum (Al).

[0011] The thickness of the 2-3 pattern layer may be less than the thickness of the 2-2 pattern layer, and a portion of the conductive member inserted into the second conductive pattern may be exposed from a part of the 2-3 pattern layer by passing through the 2-3 pattern layer.

[0012] The second conductive pattern may include a 2-1 pattern layer and a 2-2 pattern layer disposed on the 2-1 pattern layer. The 2-1 pattern layer may include copper (Cu), and the 2-2 pattern layer may include indium tin oxide (ITO).

[0013] The first conductive pattern may include a top surface on which an insulating pattern is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The second conductive pattern may be in contact with a part of the top surface and the side surface exposed from the insulating pattern.

[0014] A driving chip disposed in the non-display area and bumps overlapping with the pads may be further included. The bumps and the second conductive pattern may be at least partially in contact with each other.

[0015] At least a part of the conductive member protruding from the second conductive pattern may be in contact with the bumps.

[0016] The conductive member may include conductive particles, and the conductive particles may be randomly arranged in the second conductive pattern.

[0017] The conductive member may include spherical conductive particles having an uneven outer surface.

[0018] The conductive member may include a metal paste, and at least a part of the metal paste may be inserted into the first conductive pattern.

[0019] The insulating pattern may include a polymer.

[0020] Each of the protrusions may include a first side surface facing an adjacent protrusion and a second side surface facing the first side surface when viewed in a cross-sectional view. The conductive member may be disposed between the first side surfaces, and the pad may further include an additional conductive member disposed on at least one of the second side surfaces.

[0021] The protrusion may include a first protrusion, a second protrusion connected to the first protrusion, and a third protrusion connected to the second protrusion and spaced apart from the first protrusion while the second protrusion is disposed between the first protrusion and the third protrusion. The insulating pattern may include recesses defined between the first protrusion and the second protrusion and between the second protrusion and the third protrusion.

[0022] It may further include a metal layer disposed on the second conductive pattern, and the metal layer may cover the second conductive pattern.

[0023] According to an embodiment of the present disclosure, a method for manufacturing (or providing) a display device may include: providing a preliminary display device including a base layer and an insulating layer disposed on the base layer, wherein the base layer includes a display area and a non-display area adjacent to the display area; forming (or providing) a first conductive pattern in the non-display area of the base layer; forming a preliminary insulating pattern on the first conductive pattern; forming an insulating pattern including protrusions protruding in a direction away from the first conductive pattern; forming a conductive member between the protrusions, and forming a second conductive pattern on the insulating pattern.

[0024] At least a part of the conductive member may be inserted into the second conductive pattern.

[0025] Forming the conductive member may include disposing a discharge member on the insulating pattern and discharging the conductive member from the discharge member.

[0026] The method may further include disposing bumps on the second conductive pattern and pressing the second conductive pattern by moving the bumps toward the second conductive pattern.

[0027] In the pressing of the second conductive pattern, the part of the conductive member inserted into the second conductive pattern may be at least partially exposed from the second conductive pattern.

[0028] After forming the second conductive pattern, the method may further include forming a metal layer on the second conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects and features of the present disclosure will become apparent by describing its embodiments in detail with reference to the accompanying drawings.

[0030] Figure 1 A perspective view of an electronic device according to an embodiment of the present disclosure.

[0031] Figure 2 An exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0032] Figure 3 A cross-sectional view of a display device according to an embodiment of the present disclosure.

[0033] Figure 4 A plan view of a display panel according to an embodiment of the present disclosure.

[0034] Figure 5 A cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0035] Figure 6ACross-sectional view of an input sensing unit according to an embodiment of the present disclosure.

[0036] Figure 6B Planar view of an input sensing unit according to an embodiment of the present disclosure.

[0037] Figure 6C Is a cross-sectional view of a part of a display device taken along the line Figure 6B I-I'.

[0038] Figure 7 Exploded perspective view of a pad area of a display device according to an embodiment of the present disclosure.

[0039] Figure 8 Is a cross-sectional view of a part of a display device taken along the line Figure 7 II-II'.

[0040] Figures 9A to 9H Cross-sectional views sequentially illustrating structures and processes in a method for providing (or manufacturing) a display device according to an embodiment of the present disclosure.

[0041] Figure 9I Is an enlarged view of the area Figure 9H AA' of.

[0042] Figure 9J Cross-sectional view of a conductive member according to an embodiment of the present disclosure.

[0043] Figure 10A Cross-sectional view of a part of a display device according to an embodiment of the present disclosure.

[0044] Figure 10B Cross-sectional view of a part of a display device according to an embodiment of the present disclosure.

[0045] Figure 10C Cross-sectional view of a part of a display device according to an embodiment of the present disclosure.

[0046] Figure 10D Cross-sectional view of a part of a display device according to an embodiment of the present disclosure. Detailed Description

[0047] Although the present disclosure is susceptible to various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the intention is not to limit the present disclosure to the particular forms disclosed, but on the contrary, the present disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0048] In the specification, statements related to a first component (or region, layer, part, portion, etc.) and another element, such as "on" a second component, "connected to" or "coupled to" the second component, mean that the first component is directly on, connected to, or coupled to the second component, or that a third component is disposed therebetween. In contrast, statements related to a first component (or region, layer, part, portion, etc.) and another element, such as "directly on" the second component, "directly connected to" or "directly coupled to" the second component, mean that no third component is disposed therebetween.

[0049] The same or similar reference numerals will be assigned to the same components. In the drawings and text of the present disclosure, reference numerals indicating the singular form of an element may also be used to refer to a plurality of singular elements. Additionally, in the drawings, the thickness, scale, and dimensions of components may be enlarged to effectively describe technical features.

[0050] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a," "the," and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Thus, a reference to "a" element after a reference to "the" element in the claims includes one element and a plurality of the elements. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element." "At least one" is not to be construed as limited to "one." "Or" means "and / or." The term "and / or" includes any and all combinations of one or more of the associated components.

[0051] Although terms such as "first," "second," etc. may be used to describe various components, the components should not be construed as being limited by these terms. Each term is only used to distinguish one component from another. For example, without departing from the scope and spirit of the present disclosure, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

[0052] The singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0053] Additionally, the terms "below," "at the lower part," "above," "at the upper part" are used to describe the relationship between components illustrated in the drawings. Each term is relative and is described with reference to the directions indicated in the drawings.

[0054] It will be further understood that the terms "comprises," "comprising," or "having" specify the presence of the recited features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, the illustrated shapes are expected to change due to, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of the regions illustrated herein but include, for example, deviations in shapes due to manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Also, the illustrated sharp corners may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims.

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of an electronic device ED according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device ED according to an embodiment of the present disclosure.

[0059] The electronic device ED may be activated in response to an electrical signal. According to an embodiment, by way of example, the electronic device ED is provided in the form of a smart phone. However, the present disclosure is not limited thereto, and the electronic device ED according to an embodiment may have various forms. For example, the electronic device ED may be applied to a personal computer, a laptop computer, a television, a personal digital terminal, a car navigation system, a game console, a smart phone, a tablet computer, or a camera.

[0060] The electronic device ED may display an image IM through a display plane ED-IS as a display surface. Figure 1 An icon image is illustrated as an example of the image IM. The display plane ED-IS is parallel to a plane defined by a first direction DR1 and a second direction DR2 that intersect each other.

[0061] Figure 1 And the subsequent drawings illustrate a first direction DR1 to a third direction DR3, and the directions indicated by the first direction DR1 to the third direction DR3 described in this specification may be relative concepts and may be converted to other directions.

[0062] For convenience of explanation in this specification, a third direction DR3 is defined as a direction for providing an image IM, such as a direction for providing the image IM to the outside of the electronic device ED and / or to its user. Additionally, a first direction DR1 and a second direction DR2 may be perpendicular to each other. The third direction DR3 may be a direction perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The thickness of the electronic device ED and its various components or layers may be defined along the third direction DR3 (e.g., the thickness direction).

[0063] A display plane ED-IS includes a display area ED-DA for displaying an image IM and a non-display area ED-NDA adjacent to the display area ED-DA. The non-display area ED-NDA may be an area (or a region of the plane) where the image IM is not displayed. However, the present disclosure is not limited thereto. The non-display area ED-NDA may be adjacent to any side of the display area ED-DA or may be omitted.

[0064] Reference Figure 2 , according to an embodiment, the electronic device ED may include a window WM, a display device DD, and a receiving member BC.

[0065] The window WM may be disposed on or face the display device DD, and may transmit the image IM provided from the display device DD to the outside (e.g., the outside of the window WM, the outside of the electronic device ED, etc.). The window WM may include a transmissive area TA and a non-transmissive area NTA.

[0066] The transmissive area TA may overlap with the display area ED-DA illustrated in Figure 1 , and may have a form (or a planar shape) corresponding to the display area ED-DA. The transmissive area TA may be an area where the image IM provided from the display device DD (see Figure 1 ) is transmitted to the outside.

[0067] The non-transmissive area NTA may overlap with the non-display area ED-NDA illustrated in Figure 1 , and may have a form corresponding to the non-display area ED-NDA. The non-transmissive area NTA has a lower light transmittance than the transmissive area TA. The non-transmissive area NTA may be defined by a border pattern provided in a partial area of the base layer of the window WM. An area where the border pattern is not provided (e.g., excluded or absent) is defined as the transmissive area TA. However, the present disclosure is not limited thereto, and the non-transmissive area NTA may be omitted such that the transmissive area TA extends to the outer edge of the electronic device ED in a plan view.

[0068] Although not illustrated, the window WM may include a base layer and a functional layer disposed on the base layer. The functional layer may include a protective layer and an anti-fingerprint layer. The base layer of the window WM may include glass, sapphire, or plastic. The base layer of the window WM may include an optically transparent material. For example, the base layer of the window WM may include a glass or a plastic film, or may include a glass substrate and a plastic film coupled to each other by an adhesive.

[0069] Although not illustrated, an anti-reflection layer may be disposed between the window WM and the display device DD. The anti-reflection layer may reduce the reflectance of external light incident from outside the display device DD. The anti-reflection layer may include a color filter. The color filter may have a specific array. For example, the color filter may be arranged based on the emission color of pixels PX (see Figure 4 ) included in the display panel DP to be described below. Additionally, the anti-reflection layer may further include a black matrix adjacent to the color filter.

[0070] Reference Figure 2 , according to an embodiment, the display device DD may include a display panel DP and an input sensing unit ISU.

[0071] The display panel DP may be a liquid crystal display panel or an emissive display panel. For example, the display panel DP may include a liquid crystal display panel including liquid crystal elements, an organic light emitting display panel including organic electroluminescent elements, or a quantum dot light emitting display panel including quantum dot light emitting elements. However, the embodiments are not limited thereto. Hereinafter, the display panel DP may be described as an organic light emitting display panel.

[0072] The input sensing unit ISU as an input sensing layer may be disposed on the display panel DP. The input sensing unit ISU may include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensing unit ISU may be formed on (or provided on) the display panel DP through a subsequent process in a method of providing an electronic device ED. Alternatively, the input sensing unit ISU may be separately manufactured and may be bonded to the display panel DP through an adhesive layer.

[0073] The display device DD may further include a driving chip DC and a circuit board PB disposed on the display panel DP.

[0074] According to an embodiment, the circuit board PB may be a flexible circuit board. In the following description, although the circuit board PB is described as a flexible circuit board and the same reference numerals are assigned to the circuit board, the present disclosure is not limited thereto. For example, the circuit board PB may be rigid. The flexible circuit board PB may electrically connect the display panel DP to a main circuit board (not shown) which is a component outside the display panel DP.

[0075] Although Figure 2The exemplary driving chip DC is mounted on the display panel DP, but the present disclosure is not limited thereto. For example, the driving chip DC can be mounted on the flexible circuit board PB. The driving chip DC can include driving elements, such as data driving circuits, to drive the pixels PX of the display panel DP. According to an embodiment, the driving chip DC directly mounted on the display panel DP and the flexible circuit board PB can be collectively referred to as electronic components. Hereinafter, the bonding structure between the display panel DP and the flexible circuit board PB can be similarly applied to another electronic component such as the driving chip DC in addition to the flexible circuit board PB.

[0076] Figure 2 The exemplary circuit board PB is bendable to be bent and disposed on the rear surface of the display panel DP. However, the present disclosure is not limited thereto. For example, a part of the display panel DP can be bendable to be bent such that the driving chip DC faces the lower part of the display device DD. In this case, the display panel DP can be bent in the non-display area DP-NDA (see Figure 3 ). The circuit board PB can be disposed at one end portion of the base layer BL of the display panel DP (see Figure 3 ), and can be connected to the circuit element layer DP-CL (see Figure 3 ) at the one end portion of the display panel DP.

[0077] The receiving member BC can receive the display device DD and can be coupled to the window WM. The flexible circuit board PB can be disposed at one end portion of the display panel DP, and can be electrically connected to the display panel DP at the circuit element layer DP-CL which will be described with reference to Figure 3 . Although not illustrated, the display device DD can further include a main board, an electronic module, a camera module, or a power module mounted on the main board.

[0078] Although the above description has been made for the electronic device ED in the form of a mobile phone, the electronic device ED can include a device formed by combining at least two electronic components with each other. For example, the electronic device ED can represent the display panel DP and the driving chip DC mounted on the display panel DP.

[0079] Figure 3 FIG. is a cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0080] The display panel DP includes a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a packaging layer TFL disposed on the display element layer DP-OLED.

[0081] The display panel DP can include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP can correspond to the referenceFigure 1 The display area ED-DA of the described electronic device ED and a reference Figure 2 described transmissive area TA. The non-display area DP-NDA of the display panel DP may correspond to the reference Figure 1 non-display area ED-NDA of the described electronic device ED and a reference Figure 2 described non-transmissive area NTA.

[0082] The base layer BL may be provided at the lowest part of the display panel DP to provide a base surface for setting components or layers of the display panel DP. The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a silicone resin, a polyamide resin, and a perylene resin. Additionally, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0083] The base layer BL may be provided in a form in which organic layers and inorganic layers are alternately stacked. For example, the base layer BL may be provided as a structure in which a first organic layer including polyimide, a first inorganic layer provided on the first organic layer, a second organic layer provided on the first inorganic layer, and a second inorganic layer provided on the second organic layer are stacked, and the present disclosure is not limited to any one embodiment.

[0084] The circuit element layer DP-CL may include a plurality of insulating layers and circuit elements. The insulating layers may include at least one inorganic layer and at least one organic layer. The circuit elements may include signal lines and driving circuits. The insulating layers and circuit elements may be formed by processes such as a coating process and a deposition process to form insulating layers, semiconductor layers, and conductive layers and then selectively patterning the resulting structure by photolithography and etching processes. Accordingly, semiconductor patterns, conductive patterns, and signal lines may be formed in the circuit element layer DP-CL.

[0085] Patterns may be formed in the same layer as another pattern by the same process. In the present specification, forming patterns by the same process may mean that the patterns include the same materials and have the same stacking structure. Since in the same layer, each element may be formed in the same process and / or include the same materials as each other, each element may be a respective part or pattern of the same material layer, each element may be on the same layer by forming an interface with the same underlying layer or overlying layer, and so on, without being limited thereto.

[0086] The display element layer DP-OLED may include a pixel defining layer PDL (see Figure 5 ) and an organic light emitting element OLED as a light emitting element (see Figure 5 ).

[0087] The encapsulation layer TFL may be disposed on the display element layer DP-OLED to cover the display element layer DP-OLED. The encapsulation layer TFL may prevent moisture / oxygen from penetrating into the display element layer DP-OLED. The encapsulation layer TFL may include a stacked structure of an inorganic layer / an organic layer / an inorganic layer.

[0088] The input sensing unit ISU may be disposed on the display panel DP. In this specification, the phrase "component A is directly disposed on component B" means that there is no other component intervening between component A and component B.

[0089] Figure 4 It is a plan view of the display panel DP according to an embodiment of the present disclosure.

[0090] Reference Figure 4 , according to an embodiment, the display panel DP may include pixels PX, a gate driving circuit GDC, signal lines SGL, and pads DP-PD.

[0091] The pixels PX may be disposed in the display area DP-DA, and each of the pixels PX may include a light-emitting element and a pixel driving circuit connected to the light-emitting element. According to an embodiment, the light-emitting element may be an organic light-emitting element.

[0092] The gate driving circuit GDC may be disposed in the non-display area DP-NDA of the display panel DP. The gate driving circuit GDC may sequentially output gate signals to the gate lines GL. The circuit transistors of the gate driving circuit GDC may be formed by the same process as the transistors TR of the pixels PX, such as a low-temperature polysilicon (LTPS) process, a low-temperature polycrystalline oxide (LTPO) process, or a hybrid oxide and polysilicon (HOP) process.

[0093] However, the driving circuits included in the display panel DP are not limited to the gate driving circuit GDC. For example, the display panel DP may further include another driving circuit for applying a light emission control signal to the pixels PX. For example, the display panel DP may include a scan driving circuit.

[0094] The signal lines SGL may be disposed in the display area DP-DA and may extend from the display area DP-DA to the non-display area DP-NDA. The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. The gate lines GL may be respectively connected to the relevant pixels PX in the pixels PX, and the data lines DL may be respectively connected to the relevant pixels PX in the pixels PX. The power lines PL may be connected to the pixels PX. The control signal lines CSL may provide control signals to the scan driving circuit.

[0095] Each of the signal lines SGL may include a line portion LP. Although not illustrated, the signal line SGL may further include a pad portion. The line portion LP may overlap with the display area DP-DA and the non-display area DP-NDA. The pad portion may be connected to an end portion (e.g., a distal end) of the line portion LP.

[0096] The pad DP-PD serving as a pad of the display panel DP may be provided in a plurality, including a first pad PD1, a second pad PD2, and a third pad PD3.

[0097] The non-display area DP-NDA may include a first pad area PA1 and a second pad area PA2. The first pad area PA1 may be an area in which the first pad PD1 and the second pad PD2 are provided and overlap with the driving chip DC (see Figure 2 ). The second pad area PA2 may be an area in which the third pad PD3 is provided and overlaps with the circuit board PB.

[0098] The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in a first direction DR1 (or along the first direction DR1).

[0099] The first pad area PA1 may include a first area B1 as a first sub-area in which the first pad PD1 is provided and a second area B2 as a second sub-area in which the second pad PD2 is provided.

[0100] The area in which the first pad PD1 and the second pad PD2 are provided may be collectively defined as the first pad area PA1, and the area in which the third pad PD3 is provided may be defined as the second pad area PA2.

[0101] According to an embodiment, the first pad PD1 may be arranged in a row in the first area B1. However, the manner of arranging the first pad PD1 in the first area B1 is not limited thereto. According to an embodiment, the first pad PD1 may be arranged in at least two rows in the first area B1.

[0102] Reference Figure 4 , the second area B2 may be provided below the first area B1, that is, closer to the end portion of the display panel DP than the first area B1. The second pad PD2 provided in the second area B2 may be connected to the third pad PD3 provided in the second pad area PA2 through a connection signal line S-CL. The first pad PD1 provided in the first pad area PA1 may not be connected to the second pad PD2 in the first pad area PA1 through a connection line. For example, the first pad PD1 and the second pad PD2 may be connected to each other via the driving chip DC, but are not limited thereto.

[0103] The circuit board PB may include substrate bumps PB-BP. The substrate bumps PB-BP serving as circuit board bumps may be arranged in the second direction DR2. The substrate bumps PB-BP of the circuit board PB may be connected to the display panel DP at the third pad PD3 in the second pad region PA2 while being in contact with the third pad PD3. Due to the contact, the respective elements may be physically in contact with each other, such as forming an interface therebetween.

[0104] Figure 5 FIG. is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 5 Illustrate a cross-section corresponding to the light-emitting region PXA and the non-light-emitting region NPXA adjacent to the light-emitting region PXA. The definition of the light-emitting region PXA and the non-light-emitting region NPXA will be described below.

[0105] The display panel DP includes a base layer BL, a circuit element layer DP-CL provided on the base layer BL, a display element layer DP-OLED provided on the circuit element layer DP-CL, and a encapsulation layer TFL provided on the display element layer DP-OLED.

[0106] For convenience of explanation, although Figure 5 only one transistor TR is illustrated as an example of the pixel driving circuit, the embodiments of the present disclosure are not limited thereto. For example, the pixel PX may include a plurality of transistors TR.

[0107] According to an embodiment, the circuit element layer DP-CL may include an isolation layer BRL, a buffer layer BFL, and first to fifth insulating layers 10 to 50, a transistor TR, a signal line SGL, a first connection electrode CNE1, and a second connection electrode CNE2. However, the embodiments of the present disclosure are not limited thereto. For example, the isolation layer BRL or the buffer layer BFL may be omitted, or any one of the insulating layers in the range from the first insulating layer 10 to the fifth insulating layer 50 may be omitted, or another insulating layer may be further inserted into the first insulating layer 10 to the fifth insulating layer 50.

[0108] The isolation layer BRL is provided on the base layer BL. The isolation layer BRL prevents foreign substances from being introduced from the outside into the layers above the isolation layer BRL. The isolation layer BRL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may include a plurality of silicon oxide layers, the silicon nitride layer may include a plurality of silicon nitride layers, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0109] The buffer layer BFL is provided on the isolation layer BRL. The buffer layer BFL may improve the bonding force between the base layer BL and the overlying layers (such as semiconductor patterns and / or conductive patterns). The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked, and a plurality of such layers may be alternately stacked.

[0110] A semiconductor pattern is disposed on a buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present disclosure is not limited thereto. For example, the semiconductor pattern may include amorphous silicon or metal oxide.

[0111] A part of the semiconductor pattern is illustrated in Figure 5 and when viewed in a plan view, the semiconductor pattern may extend along a circuit element layer DP-CL to be further disposed in another region of the display panel DP. The semiconductor pattern may include a first region and a second region. The first region may be doped with an N-type dopant or a P-type dopant and may have a greater conductivity (e.g., conductance) than that of the second region. The first region substantially corresponds to an electrode element or a conductive signal line and serves as an electrode element or a conductive signal line. The second region may have a lower doping concentration or may be an undoped region and substantially corresponds to an active portion (or channel portion) of a transistor TR.

[0112] A drain D, an active portion A, and a source S may be defined or disposed on the buffer layer BFL. The drain D, the active portion A, and the source S may define a transistor TR together with a gate G described later. When the display panel DP further includes another transistor in addition to the transistor TR, the another transistor may include a material different from that of the transistor TR and may be disposed in a layer different from that of the transistor TR. The source S, the active portion A, and the drain D of the transistor TR may be formed or defined by the semiconductor pattern.

[0113] A first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the semiconductor pattern. The first insulating layer 10 may commonly overlap with a plurality of pixels PX. A gate G is disposed on the first insulating layer 10. The gate G may be a part of a metal pattern or a conductive material layer. The gate G may overlap with the active portion A. In a process of doping the semiconductor pattern, the gate G may be used as a mask in a process of providing the display panel DP.

[0114] The gate G may include titanium (Ti), silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum (Mo), aluminum (Al), an alloy containing aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), and the present disclosure is not particularly limited thereto.

[0115] A second insulating layer 20 covering the gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may commonly overlap with the pixel PX. Although not illustrated, an upper electrode overlapping with the gate G may be disposed on the second insulating layer 20. A first connection electrode CNE1 disposed on the second insulating layer 20 may be connected to a signal line SGL through a first contact hole CNT-1 formed (or extended) through the first insulating layer 10 and the second insulating layer 20.

[0116] The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode and the first connection electrode CNE1.

[0117] The first insulating layer 10 to the third insulating layer 30 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. One or more of the first insulating layer 10 to the fifth insulating layer 50 may be referred to as an "insulating layer", but is not limited thereto.

[0118] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be an organic layer. The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 by forming a second contact hole CNT-2 passing through the third insulating layer 30 and the fourth insulating layer 40.

[0119] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer. The first electrode AE may be disposed on the fifth insulating layer 50. The first electrode AE may be connected to the second connection electrode CNE2 by forming a third contact hole CNT-3 passing through the fifth insulating layer 50.

[0120] The display element layer DP-OLED may include a pixel defining layer PDL and an organic light-emitting element OLED. A pixel opening OPN is defined in the pixel defining layer PDL, such as being defined by portions (e.g., materials or solid portions) spaced apart from each other. The pixel opening OPN of the pixel defining layer PDL may expose at least a part of the first electrode AE to the outside of the pixel defining layer PDL. According to an embodiment, a light-emitting region PXA may be defined corresponding to the portion region of the first electrode AE exposed by the pixel opening OPN. For example, the planar region of the light-emitting region PXA may correspond to the exposed planar region of the first electrode AE.

[0121] The hole control layer HCL may be commonly disposed in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer.

[0122] The light-emitting layer EML is disposed on the hole control layer HCL. The light-emitting layer EML may be disposed in a region corresponding to the pixel opening OPN. In other words, the light-emitting layer EML may be separately formed as a discrete pattern in each of the pixels PX. However, the present disclosure is not limited thereto. For example, the light-emitting layer EML may be commonly formed in a plurality of pixels PX.

[0123] The electron control layer ECL may be disposed on the light-emitting layer EML. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly formed in a plurality of pixels PX through an opening mask.

[0124] The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may have an integral form and may be commonly disposed in a plurality of pixels PX.

[0125] The encapsulation layer TFL may be disposed on the second electrode CE. The encapsulation layer TFL may include a plurality of thin films. The encapsulation layer TFL may prevent moisture / oxygen from penetrating into the display element layer DP-OLED.

[0126] Figure 6A A cross-sectional view of an input sensing unit ISU according to an embodiment of the present disclosure.

[0127] The input sensing unit ISU may include a first sensing insulating layer IS-IL1, a first sensing conductive layer IS-CL1 disposed on the first sensing insulating layer IS-IL1, a second sensing insulating layer IS-IL2 disposed on the first sensing conductive layer IS-CL1, a second sensing conductive layer IS-CL2 disposed on the second sensing insulating layer IS-IL2, and a third sensing insulating layer IS-IL3 disposed on the second sensing conductive layer IS-CL2. The first sensing insulating layer IS-IL1 may be directly disposed on the encapsulation layer TFL.

[0128] However, the present disclosure is not limited thereto, and the first sensing insulating layer IS-IL1 and / or the third sensing insulating layer IS-IL3 may be omitted. When the first sensing insulating layer IS-IL1 is omitted, the first sensing conductive layer IS-CL1 may be directly disposed on the encapsulation layer TFL. The third sensing insulating layer IS-IL3 may be replaced by an adhesive layer or an insulating layer of an antireflection member of the input sensing unit ISU.

[0129] Each of the first to third sensing insulating layers IS-IL1, IS-IL2, and IS-IL3 may include an inorganic layer or an organic layer. The inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride, and the organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin.

[0130] According to an embodiment, at least one of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may be an organic layer. For example, the third sensing insulating layer IS-IL3 may include an organic layer.

[0131] In Figure 6AIn [the figure], each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 is illustrated in the form of a layer (e.g., a single layer) overlapping the entire portion of the display panel DP, to schematically represent the stacked structure. However, embodiments of the present disclosure are not limited thereto, and each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 may be patterned to include discrete shapes or discrete patterns along the encapsulation layer TFL.

[0132] Figure 6B FIG. [is] a plan view of an input sensing unit ISU according to an embodiment of the present disclosure. Figure 6C is along Figure 6B a cross-sectional view of a part of the display device DD taken along line I-I'.

[0133] Referring to Figure 6B , the input sensing unit ISU may include a sensing region IS-DA and a non-sensing region IS-NDA adjacent to the sensing region IS-DA, and the sensing region IS-DA and the non-sensing region IS-NDA may respectively correspond to a display region DP-DA (see Figure 3 ) and a non-display region DP-NDA (see Figure 3 ).

[0134] Referring to Figure 6B , the input sensing unit ISU may include first electrodes E1-1 to E1-5, second electrodes E2-1 to E2-4, a first signal line SL1, and a second signal line SL2.

[0135] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may be disposed in the sensing region IS-DA. The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may be insulated from each other (e.g., electrically insulated) while crossing each other in the plan view.

[0136] The first signal line SL1 and the second signal line SL2 may be disposed in the non-sensing region IS-NDA. The first signal line SL1 may be electrically connected to the first electrodes E1-1 to E1-5 respectively, and the second signal line SL2 may be electrically connected to the second electrodes E2-1 to E2-4 respectively.

[0137] The first electrodes E1-1 to E1-5, the second electrodes E2-1 to E2-4, the first signal line SL1, and the second signal line SL2 may be part of the first sensing conductive layer IS-CL1 or the second sensing conductive layer IS-CL2.

[0138] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include a plurality of wires that cross each other. The plurality of wires may be spaced apart from each other to define a plurality of openings therebetween, and the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a mesh form through the wires and the openings therebetween. Each of the plurality of openings may be defined to correspond to Figure 5 the pixel opening OPN of the pixel defining layer PDL illustrated in

[0139] The first electrodes E1-1 to E1-5 may include a sensing part ST1 and an intermediate part LP1 that extends from the sensing part ST1 while being formed integrally or as a monolithic structure with the sensing part ST1. In other words, although the sensing part ST1 and the intermediate part LP1 connected to the sensing part ST1 have a monolithic pattern formed by the same process as a part of the same material layer, for convenience of explanation, the sensing part ST1 and the intermediate part LP1 will be described separately.

[0140] The second electrodes E2-1 to E2-4 may include a sensing pattern ST2 and a bridging pattern LP2 (or a connecting pattern).

[0141] Referring to Figure 6B and Figure 6C , two adjacent sensing patterns ST2 may be connected to each other by the bridging pattern LP2 at or through a contact hole CH-I formed through the second sensing insulating layer IS-IL2.

[0142] One of the first signal line SL1 and the second signal line SL2 transmits a transmission signal for sensing an external input from an external circuit, and the other of the first signal line SL1 and the second signal line SL2 transmits a capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 as a reception signal to the external circuit.

[0143] The first signal line SL1 and the second signal line SL2 may have a multilayer structure, and the first layer line and the second layer line may be connected to each other through a contact hole CH-I formed through the second sensing insulating layer IS-IL2 (see Figure 6A ).

[0144] Figure 7 A exploded perspective view of the pad regions PA1, PA2 of a display device DD according to an embodiment of the present disclosure. In Figure 7 , the driving chip DC and the circuit board PB are exploded from the display panel DP. Since the layout relationship and the connection relationship between the first pad region PA1 and the second pad region PA2 have been described above with reference to Figure 4 , the details thereof will be omitted hereinafter.

[0145] Referring to Figure 7, the driving chip DC can be bonded to the display panel DP through the first bonding layer CF1 at the first pad area PA1. The circuit board PB can be bonded to the display panel DP through the second bonding layer CF2 at the second pad area PA2.

[0146] According to an embodiment, the first bonding layer CF1 and the second bonding layer CF2 may include a non-conductive film (NCF) instead of an anisotropic conductive film (ACF). Therefore, the first bonding layer CF1 and the second bonding layer CF2 may include a synthetic resin having adhesive properties, and may not include a conductive material or a conductive element such as a conductive ball in the non-conductive film (NCF).

[0147] The driving chip DC may include a driving integrated circuit D-IC and driving bumps DC-BP mounted in the driving chip DC.

[0148] The driving integrated circuit D-IC may include a top surface DC-US and a bottom surface DC-DS opposite to the top surface DC-US. The bottom surface DC-DS of the driving integrated circuit D-IC may be the surface facing the first pad PD1 and the second pad PD2 along the thickness direction.

[0149] The driving bumps DC-BP may be disposed on the bottom surface DC-DS of the driving integrated circuit D-IC. The driving bumps DC-BP may include a first bump BP1 electrically connected to the display panel DP at the first pad PD1 respectively and a second bump BP2 electrically connected to the display panel DP at the second pad PD2 respectively. The first bump BP1 may be arranged in the second direction DR2, and the second bump BP2 may be spaced apart from the first bump BP1 in the first direction DR1 and may be arranged in the second direction DR2. Although Figure 7 the first bump BP1 is illustrated as being arranged in a row and the second bump BP2 is illustrated as being arranged in a row, the embodiments of the present disclosure are not limited thereto. For example, the first bump BP1 may be arranged in at least two rows, and the second bump BP2 may be arranged in at least two rows.

[0150] The driving chip DC can receive a first signal at the second bump BP2 through the second pad PD2. The driving chip DC can provide a second signal generated based on the first signal to the first pad PD1 through the first bump BP1. For example, the driving chip DC may include a data driving circuit and generate a second signal based on the first signal through the data driving circuit.

[0151] The first signal may be an image signal as a digital signal applied from the outside, and the second signal may be a data signal as an analog signal. The driving chip DC can generate an analog voltage corresponding to the gray value of the image signal. The data signal can be provided to the pixel PX through the data line DL (see Figure 4 ).

[0152] Although not illustrated, the first bump BP1 and the second bump BP2 may protrude from the bottom surface DC-DS of the driving integrated circuit D-IC or be exposed at the bottom surface DC-DS of the driving integrated circuit D-IC and may be exposed to the outside of the driving integrated circuit D-IC. In the method of providing the display device DD, when the uncured material for providing the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed in place relative to each other (e.g., in one or all of the first direction DR1 to the third direction DR3) while contacting each other, and the second pad PD2 and the second bump BP2 may be fixed in place relative to each other while contacting each other.

[0153] The circuit board PB may include a base layer P-BS and substrate bumps PB-BP mounted in or on the base layer P-BS. The circuit board PB may include a top surface PB-US and a bottom surface PB-DS opposite to the top surface PB-US, and the bottom surface PB-DS of the circuit board PB may be the surface facing the third pad PD3.

[0154] The substrate bumps PB-BP may be provided on the bottom surface PB-DS of the base layer P-BS. The substrate bumps PB-BP may be electrically connected to the display panel DP at the third pads PD3 respectively. The substrate bumps PB-BP may be arranged in the second direction DR2. Although Figure 7 the substrate bumps PB-BP are illustrated as being arranged in a row, embodiments of the present disclosure are not limited thereto. For example, the substrate bumps PB-BP may be arranged in at least two rows.

[0155] The circuit board PB may provide an image signal, a driving voltage, and other control signals to the driving chip DC.

[0156] Although not illustrated, the substrate bumps PB-BP may protrude from or be exposed from the bottom surface PB-DS of the base layer P-BS and be exposed to the outside of the circuit board PB. When the second adhesive layer CF2 is cured, the third pads PD3 and the substrate bumps PB-BP may be fixed in place relative to each other (e.g., in one or all of the first direction DR1 to the third direction DR3) while contacting each other.

[0157] Figure 8 For Figure 7 a cross-sectional view of a part of the display device DD taken along the line II-II'.

[0158] The bonding structure between electronic components will be described with reference to Figure 8 wherein the pads DP-PD provided in the first region B1 (see Figure 4 ) are bonded to the first bump BP1.

[0159] Figure 8The pad DP-PD illustrated above may be any one of the first pad PD1 to the third pad PD3 described above with reference to Figure 4 and Figure 7 . Although Figure 8 the end portion DL-E of the illustrated data line DL (see Figure 4 ) is the signal line SGL (see Figure 4 ), embodiments of the present disclosure are not limited thereto. The end portion DL-E may be the end portion of another signal line SGL other than the data line DL. The end portion DL-E may correspond to the pad portion described above with reference to Figure 4 .

[0160] Hereinafter, the bonding structure of the pad DP-PD will be described while focusing on the bonding between the display panel DP and the first bump BP1 of the driving chip DC at the first pad PD1 (see Figure 4 ) that overlaps the end portion DL-E of the data line DL (see Figure 4 ). The second pad PD2 and the third pad PD3 may overlap the end portion of the connection signal line S-CL (see Figure 4 ) instead of the end portion DL-E of the data line DL. The second pad PD2 may be bonded to the second bump BP2 of the driving chip DC (see Figure 2 ), and the third pad PD3 may be bonded to the substrate bump PB-BP of the circuit board PB (refer to Figure 7 ).

[0161] With reference to Figure 8 , the end portion DL-E may be provided on the first insulating layer 10. The end portion DL-E may be provided in the same layer as the gate G (see Figure 5 ). The end portion DL-E may be formed by the same process as the gate G. The end portion DL-E may include the same material as the gate G.

[0162] However, the position of the end portion DL-E is not limited thereto. For example, the end portion DL-E may be located in the same layer as the upper electrode described above with reference to Figure 5 , may include the same material as the upper electrode, and may have the same stacking structure as the upper electrode. Some signal lines SGL (refer to Figure 4 ) may be formed by the same process as the gate G (refer to Figure 5 ), and other signal lines SGL may be formed by the same process as the upper electrode described above with reference to Figure 5 .

[0163] With reference to Figure 8 , the display device DD may include a base layer BL, an isolation layer BRL, a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, pads DP-PD, a first adhesive layer CF1, and a driving chip DC in the first region B1.

[0164] It can be formed by the same process as the isolation layer BRL, buffer layer BFL, first insulating layer 10, and second insulating layer 20 exemplified in Figure 5 In Figure 8 the isolation layer BRL, buffer layer BFL, first insulating layer 10, and second insulating layer 20 exemplified in Figure 8 In other words, the stacked structure of the base layer BL, isolation layer BRL, buffer layer BFL, first insulating layer 10, and second insulating layer 20 exemplified in Figure 5 can vary according to the stacked structure of the circuit element layer DP-CL (see

[0165] The pad DP-PD can be disposed on the second insulating layer 20. The pad DP-PD can include a first conductive pattern CL1, an insulating pattern SP, a second conductive pattern CL2, and a conductive member CP.

[0166] The first conductive pattern CL1 can be disposed on the second insulating layer 20. Although not illustrated, the first conductive pattern CL1 can contact the end portion DL-E by forming a contact hole through the second insulating layer 20. Accordingly, the first conductive pattern CL1 and the end portion DL-E can be electrically connected to each other.

[0167] The insulating pattern SP can be disposed on the first conductive pattern CL1. Referring to Figure 8 , the insulating pattern SP and the first conductive pattern CL1 can be in contact with each other. However, embodiments of the present disclosure are not limited thereto. For example, an insulating layer can be further disposed between the insulating pattern SP and the first conductive pattern CL1. Accordingly, the insulating pattern SP and the first conductive pattern CL1 can be not in contact with each other.

[0168] The insulating pattern SP can have a continuous integral form. The insulating pattern SP can include a first protrusion SP1 and a second protrusion SP2 connected to the first protrusion SP1. A portion where the first protrusion SP1 is connected to the second protrusion SP2 in the insulating pattern SP can be defined as a connection portion BR. A boundary between the first protrusion SP1 and the second protrusion SP2 or a region where the first protrusion SP1 and the second protrusion SP2 intersect each other can define the connection portion BR. According to an embodiment, the first protrusion SP1 and the second protrusion SP2 can be adjacent to each other in a direction along the first conductive pattern CL1.

[0169] When viewed in a cross-sectional view, the insulating pattern SP may have a thickness at a position along the first conductive pattern CL1. The thickness SH of the insulating pattern SP (hereinafter, "connection portion thickness") is defined at the connection portion BR. The connection portion thickness SH may have a value greater than "0". In other words, the first protrusion SP1 and the second protrusion SP2 may be connected to each other through the connection portion BR with a certain thickness of the insulating pattern SP. Accordingly, the insulating pattern SP may have a continuous integral form by being connected to each other through the first protrusion SP1 and the second protrusion SP2.

[0170] The first protrusion SP1 and the second protrusion SP2 may protrude in a direction away from the first insulating layer 10 and the second insulating layer 20. Referring Figure 8 , the first protrusion SP1 and the second protrusion SP2 may protrude in the third direction DR3.

[0171] A portion of the first protrusion SP1 defined at a position farthest from the first insulating layer 10 and the second insulating layer 20 may be defined as the upper portion of the first insulating layer pattern SP1U. A portion of the second protrusion SP2 defined at a position farthest from the first insulating layer 10 and the second insulating layer 20 may be defined as the upper portion of the second insulating layer pattern SP2U. The upper portion of the first insulating layer pattern SP1U and the upper portion of the second insulating layer pattern SP2U may correspond to the uppermost portions of the first protrusion SP1 and the second protrusion SP2 in the insulating pattern SP in the third direction DR3. The uppermost portions of the first protrusion SP1 and the second protrusion SP2 may include points, edges, or planes that are farthest from the insulating layer.

[0172] The insulating pattern SP has a width at a position along its thickness. The width of each of the protrusions SP1, SP2 in the direction in which the protrusions SP1, SP2 are arranged, for example, in the direction along the first conductive pattern CL1, may decrease as the distance from the first conductive pattern CL1 increases. According to an embodiment, the width of each of the protrusions SP1, SP2 in the second direction DR2 may decrease in the third direction DR3.

[0173] A recess ANK (see Figure 9D ) may be defined between the first protrusion SP1 and the second protrusion SP2 in the insulating pattern SP. The recess ANK may correspond to a portion where the insulating pattern SP is recessed in a direction opposite to the direction in which the first protrusion SP1 and the second protrusion SP2 protrude. When viewed in a cross-sectional view, the recess ANK may be defined between the upper portion of the first insulating layer pattern SP1U and the upper portion of the second insulating layer pattern SP2U in the second direction DR2 and extend to the connection portion BR. The upper portions SP1U, SP2U may include the peaks of the respective protrusions, and the recess ANK is defined between the peaks.

[0174] The second conductive pattern CL2 may be disposed on the insulating pattern SP. The first conductive pattern CL1 may include a top surface CU adjacent to the insulating pattern SP, such as the top surface on which the insulating pattern SP is disposed, a bottom surface CB opposite to the top surface CU (see Figure 9D ), and a side surface CLC connecting the top surface CU and the bottom surface CB. The bottom surface SB of the insulating pattern SP may be coplanar with the top surface CU of the first conductive pattern CL1. The top surface CU may extend more than the insulating pattern SP to define an exposed portion of the top surface CU. The second conductive pattern CL2 may be in contact with a portion CUC of the top surface CU and the side surface CLC exposed from the insulating pattern SP. Accordingly, the second conductive pattern CL2 and the first conductive pattern CL1 may be electrically connected to each other at the exposed portion of the first conductive pattern CL1.

[0175] The second conductive pattern CL2 has a multilayer structure. According to an embodiment, the second conductive pattern CL2 may include a 2-1 pattern or pattern layer CL2a, a 2-2 pattern or pattern layer CL2b disposed on the 2-1 pattern CL2a, and a 2-3 pattern or pattern layer CL2c disposed on the 2-2 pattern CL2b (see Figure 9I ).

[0176] The 2-3 pattern CL2c may include a material different from that of the 2-2 pattern CL2b. The 2-3 pattern CL2c may include a material having a lower reactivity than that of the material of the 2-2 pattern CL2b. For example, the 2-3 pattern CL2c may include a material having a lower oxygen reactivity than that of the material of the 2-2 pattern CL2b. The 2-3 pattern CL2c may prevent the 2-2 pattern CL2b from being exposed to oxygen to prevent the 2-2 pattern CL2b from being corroded by oxygen. According to an embodiment, the thickness of the 2-3 pattern CL2c may be less than the thickness of the 2-2 pattern CL2b.

[0177] For example, the 2-1 pattern CL2a and the 2-3 pattern CL2c may include titanium (Ti), and the 2-2 pattern CL2b may include aluminum (Al). However, the stacked structure and materials of the second conductive pattern CL2 are not limited thereto. For example, the second conductive pattern CL2 may include a 2-1 pattern CL2a including copper (Cu) and a 2-2 pattern CL2b including indium tin oxide (ITO).

[0178] Although not illustrated, the first conductive pattern CL1 has the same stacked structure as that of the second conductive pattern CL2 and may include the same materials as those of the second conductive pattern CL2.

[0179] According to an embodiment, the conductive member CP may be disposed between the protrusions SP1 and SP2. The region for the conductive member CP may be defined as the conductive member region SPA. The conductive member region SPA may be disposed between the upper portion SP1U of the first insulating layer pattern and the upper portion SP2U of the second insulating layer pattern in the second direction DR2.

[0180] The conductive member CP may be randomly arranged. However, the present disclosure is not limited thereto. The conductive member CP may be arranged according to a specific rule.

[0181] At least a part of the conductive member CP may extend into the main body of the second conductive pattern CL2. At least a part of the conductive member CP may extend into the main body of the insulating pattern SP. The conductive member CP may be in contact with the top surface SU of the insulating pattern SP and may be disposed on the top surface SU of the insulating pattern SP. The conductive member CP may penetrate the top surface SU of the insulating pattern SP opposite to its bottom surface SB. A process of inserting a part of the conductive member CP into the second conductive pattern CL2 and / or the insulating pattern SP will be described later with reference to Figures 9A to 9G a process of inserting a part of the conductive member CP into the second conductive pattern CL2 and / or the insulating pattern SP will be described later with reference to

[0182] The first bump BP1 may be disposed on the second conductive pattern CL2. The first bump BP1 and the second conductive pattern CL2 may be at least partially in contact with each other. Referring to Figure 8 Since the first bump BP1 and the second conductive pattern CL2 are in contact with each other, the contact point CTP may be defined between the first bump BP1 and the second conductive pattern CL2. In the method of providing the display panel DP, when the first bump BP1 moves downward toward the pad DP-PD, the first bump BP1 may apply pressure to the second conductive pattern CL2 by contacting the second conductive pattern CL2. The pressure applied by the first bump BP1 to the second conductive pattern CL2 may be transmitted through the contact point CTP.

[0183] The contact point CTP may include the first contact CTP1, the second contact CTP2, the third contact CTP3 (see Figure 10C ) etc. between the same bump of the pad DP-PD and the driving chip DC, corresponding to the number of protrusions in the pad DP-PD. The contact point may be defined at a point or a discrete region, may be defined along an edge formed by points extending in the planar direction, etc., without being particularly limited thereto.

[0184] The second conductive pattern CL2 and the first conductive pattern CL1 may be at least partially in contact with each other. Figure 8 For example, a part of the top surface CU of the first conductive pattern CL1 and the side surface CLC of the first conductive pattern CL1 are covered by the second conductive pattern CL2. However, the embodiments of the present disclosure are not limited thereto, as long as the second conductive pattern CL2 is in contact with the first conductive pattern CL1 to be electrically connected thereto.

[0185] According to an embodiment, the conductive member CP may include conductive particles having a spherical shape with a non-uniform outer surface. For example, the conductive member CP may include a metal layer having a non-uniform pattern along an upper portion of a spherical polymer layer. However, the present disclosure is not limited thereto. The conductive member CP may include a metal paste including conductive particles. According to an embodiment, the conductive member CP may include conductive particles randomly arranged in the second conductive pattern CL2.

[0186] According to an embodiment, the insulating pattern SP may include a polymer. Thus, the insulating pattern SP may have insulating properties. Additionally, since the insulating pattern SP has a polymer, the insulating pattern SP has an elastic modulus. Accordingly, the insulating pattern SP receives pressure from the outside and deforms in response to the pressure. Thus, the bonding reliability of the pad DP-PD can be improved.

[0187] According to an embodiment, since the pad DP-PD includes the conductive member CP between the first protrusion SP1 and the second protrusion SP2, the conductive member CP may aggregate in the recess ANK. Accordingly, since the conductive member CP is not disposed between the pad DP-PD and another adjacent pad, an accidental electrical short circuit between adjacent pads can be prevented. Thus, the reliability of the electrical connection for each component within the display device DD can be ensured.

[0188] Figures 9A to 9H Cross-sectional views for sequentially illustrating operations and structures in a method for providing (or manufacturing) a display device DD according to an embodiment of the present disclosure. Figure 9I For Figure 9H an enlarged view of the region AA'.

[0189] Referring to Figures 9A to 9H , according to an embodiment of the present disclosure, a method for providing (or manufacturing) a display device DD may include: providing a preliminary display device P-DD including a base layer BL and insulating layers 10, 20 disposed on the base layer BL, the base layer BL including a display region DP-DA (see Figure 3 ) and a non-display region DP-NDA adjacent to the display region DP-DA (see Figure 3 ); providing (or forming) a first conductive pattern CL1 in the non-display region DP-NDA of the base layer BL; forming a preliminary insulating pattern P-SP on the first conductive pattern CL1; forming, by etching the preliminary insulating pattern P-SP, an insulating pattern SP including protrusions SP1, SP2 protruding in a direction away from the insulating layers 10, 20; forming a conductive member CP between the protrusions SP1, SP2; and forming a second conductive pattern CL2 on the insulating pattern SP. Additionally, at least a portion of the conductive member CP may be inserted into or extend into the second conductive pattern CL2.

[0190] Referring to Figure 9A, the preliminary display device P-DD may include a base layer BL including a display area DP-DA (see Figure 3 ) and a non-display area DP-NDA adjacent to the display area DP-DA (see Figure 3 ), and insulating layers 10 and 20 provided on the base layer BL.

[0191] An end portion DL-E of a data line DL (see Figure 4 ) may be provided on the first insulating layer 10. The second insulating layer 20 may cover the end portion DL-E of the data line DL.

[0192] Thereafter, referring to Figure 9B and Figure 9C , after a first conductive pattern CL1 is formed in the non-display area DP-NDA of the base layer BL, a preliminary insulating pattern P-SP may be formed on a top surface CU of the first conductive pattern CL1. Accordingly, the top surface CU of the first conductive pattern CL1 may be in contact with a bottom surface SB of the preliminary insulating pattern P-SP (see Figure 9D ). Although the preliminary insulating pattern P-SP may include the same material as the insulating pattern SP (see Figure 9D ), the preliminary insulating pattern P-SP may be a member that is not patterned before the insulating pattern SP is formed by an etching process.

[0193] Thereafter, referring to Figure 9D , the insulating pattern SP including protrusions SP1 and SP2 protruding in a direction away from the insulating layers 10 and 20 may be formed by patterning (such as etching) the preliminary insulating pattern P-SP (see Figure 9C ). In the etching of the preliminary insulating pattern P-SP, a mask may overlap the preliminary insulating pattern P-SP, and the resulting structure may be etched by a photoresist process.

[0194] When performing this process, etching may be performed so as not to completely penetrate the thickness of the preliminary insulating pattern P-SP corresponding to the boundary between the first protrusion SP1 and the second protrusion SP2. In other words, the first protrusion SP1 and the second protrusion SP2 may be connected to each other at a lower thickness portion of the preliminary insulating pattern P-SP by a connecting portion BR, and the insulating pattern SP may have a continuous integral form without being disconnected or separated into discrete parts.

[0195] Referring to Figure 9E , a conductive member CP may be formed between the first protrusion SP1 and the second protrusion SP2. Providing the conductive member CP may include disposing a discharge member NZ on the insulating pattern SP, and discharging the material of the conductive member CP from the discharge member NZ to the insulating pattern SP, where the insulating pattern SP is partially separated between the first protrusion SP1 and the second protrusion SP2.

[0196] When the material of the insulating pattern SP is not fully cured, a part of the conductive member CP discharged from the discharging member NZ may be at least partially inserted into or extend into the uncured insulating pattern SP.

[0197] The conductive member CP discharged from the discharging member NZ may be captured and aggregated into the recess ANK defined above the connecting portion BR of the insulating pattern SP. Since the not fully cured material of the insulating pattern SP has the conductive member CP provided thereon, the conductive member CP may penetrate the top surface SU of the insulating pattern SP due to the penetration force (e.g., by the weight of the member, by gravity, etc.) provided by the conductive member CP being greater than the resistance of the not cured insulating pattern.

[0198] The discharging member NZ is spaced apart from the insulating pattern SP by a specific distance, and the conductive member CP discharged from the discharging member NZ moves downward through this distance and is disposed on the insulating pattern SP. Therefore, due to the discharge of the conductive member material into the recess ANK, the conductive members CP may be randomly arranged without a specific arrangement rule. However, embodiments of the present disclosure are not limited thereto. For example, when rules for discharging the conductive member CP from the discharging member NZ are established, the conductive members CP may be arranged according to the rules.

[0199] Referring to the stacked structure having the insulating pattern SP and the conductive member CP between the protrusions SP1, SP2 ( Figure 9E , once the discharging member NZ is removed), a second conductive pattern CL2 is provided on the insulating pattern SP. At least a part of the conductive members CP aggregated in the recess ANK of the insulating pattern SP may be inserted into the second conductive pattern CL2. Here, the lower surface of the second conductive pattern CL2 may be penetrated by the conductive members CP, such as merely due to the low resistance of the second conductive pattern CL2 to the conductive members CP (e.g., by the weight of the second conductive pattern CL2, by gravity, by the shape of the conductive members CP, etc.).

[0200] Thereafter, referring to Figure 9F and Figure 9G , after forming the second conductive pattern CL2, a first bump BP1 may be provided on the second conductive pattern CL2 and pressure may be applied to the second conductive pattern CL2 by moving the first bump BP1 toward the second conductive pattern CL2.

[0201] However, embodiments of the present disclosure are not limited thereto. For example, the pad DP-PD may be moved toward the first bump BP1 to apply pressure to the second conductive pattern CL2.

[0202] In one embodiment, an adhesive material layer may be applied to the Figure 9F structure in. As Figure 9GAs shown, pressing the driving chip DC onto the display panel DP at the pad DP-PD can shift the adhesive material layer and bring the first bump BP1 into contact with the second conductive pattern CL2, but is not limited thereto. In one embodiment, as Figure 9G shown, pressing the driving chip DC onto the display panel DP to bring the first bump BP1 into contact with the second conductive pattern CL2 may occur first, and then an adhesive material layer may be provided around the contact element.

[0203] Referring to Figure 9G , a contact point CTP may be formed between the same bump of the pad DP-PD and the driving chip DC, corresponding to the number of protrusions in the pad DP-PD. As an initial contact, the contact point CTP may provide the minimum planar area of contact between the pad DP-PD and the driving chip DC.

[0204] Referring to Figure 9H , as the first bump BP1 applies more pressure to the second conductive pattern CL2, the planar area of the contact point CTP increases to provide a contact surface CTL between the first bump BP1 and the second conductive pattern CL2.

[0205] Since the insulating pattern SP including a polymer is elastic, the insulating pattern SP may be deformed by the pressure applied by the first bump BP1. However, Figure 9H the deformation of the pad DP-PD illustrated in is provided for illustrative purposes, but the embodiments of the present disclosure are not limited thereto. Here, the second conductive pattern CL2 is deformed together with the insulating pattern SP to substantially flatten the upper portion of the second conductive pattern CL2.

[0206] Referring to Figure 9I , when pressing the second conductive pattern CL2, a portion of the conductive member CP inserted into the second conductive pattern CL2 may be at least partially exposed from the deformed second conductive pattern CL2. In other words, after forming a through-hole CL-OP in the 2-3 pattern CL2c by applying pressure to the conductive member CP, the conductive member CP may be exposed from the 2-3 pattern CL2c at the through-hole CL-OP of the 2-3 pattern CL2c. Here, the through-hole CL-OP may be provided by the penetration force of the conductive member CP through the thickness of the 2-3 pattern CL2c.

[0207] The exposed portion of the conductive member CP that penetrates further than the outer surface of the 2-3 pattern CL2c may contact the first bump BP1 and the second conductive pattern CL2. Therefore, the conductive member CP may transmit the electrical signal applied to the first bump BP1 to the second conductive pattern CL2. In other words, the electrical signal may be transmitted sequentially from the first bump BP1, to the conductive member CP, and then to the second conductive pattern CL2.

[0208] When the first bump BP1 applies pressure to the second conductive pattern CL2, the first bump BP1 may not contact the entire outer surface of the upper portion of the second conductive pattern CL2. In other words, a non-contact space NCTP may be formed as a gap between the first bump BP1 and the second conductive pattern CL2.

[0209] However, referring to Figure 9I , the first conductive member CPa may protrude from the second conductive pattern CL2. The exposed portion of the first conductive member CPa protruding from the second conductive pattern CL2 may contact the first bump BP1. In contrast, the second conductive particle CPb does not penetrate the outer surface of the second conductive pattern CL2. Therefore, the first conductive member CPa may contact both the first bump BP1 and the second conductive pattern CL2. The second conductive pattern CL2 may be electrically connected to the first bump BP1. In other words, according to the present disclosure, since the pad DP-PD includes the first conductive member CPa, the reliability of the electrical connection can be ensured.

[0210] In addition, when the conductivity of the 2-2 pattern CL2b is higher than the conductivity of the 2-3 pattern CL2c, the first conductive member CPa may ensure the electrical connection between the 2-2 pattern CL2b and the first bump BP1. For example, when the 2-3 pattern CL2c includes titanium (Ti) and the 2-2 pattern CL2b may include aluminum (Al), the conductivity of the 2-2 pattern CL2b may be higher than the conductivity of the 2-3 pattern CL2c. When a through portion CL-OP is formed in the 2-3 pattern CL2c, the first conductive member CPa may electrically connect the 2-2 pattern CL2b to the first bump BP1 by contacting the first bump BP1. Therefore, according to the present disclosure, since the pad DP-PD includes the first conductive member CPa in the conductive member CP, the reliability of the electrical connection can be ensured.

[0211] Figure 9J A cross-sectional view of a conductive member CP according to an embodiment of the present disclosure.

[0212] According to an embodiment, the conductive member CP may include spherical conductive particles having an uneven outer surface.

[0213] Each of the conductive particles may have a core portion CPC and a coating CPS surrounding the core portion CPC. The core portion CPC may have a spherical shape, and the coating CPS as an outer layer may have an uneven outer surface. Due to the uneven shape of the coating CPS defining the outer surface of the conductive member CP, the bonding force can be maintained between the first bump BP1 (see Figure 9J ) and the second conductive pattern CL2. Therefore, the reliability of the electrical connection between the first bump BP1 and the second conductive pattern CL2 can be increased.

[0214] The core CPC may include a polymer resin. The coating CPS may include a conductive material. For example, the coating CPS may include metal particles, and the metal particles include at least one of silver (Ag), copper (Cu), bismuth (Bi), zinc (Zn), indium (In), tin (Sn), nickel (Ni), cobalt (Co), chromium (Cr), and iron (Fe). Thus, the conductive member CP may have conductivity.

[0215] Figure 10A A cross-sectional view of a first region that is part of a display device DD-1 according to an embodiment of the present disclosure. The same / similar reference numerals will be assigned to Figure 7 and Figure 8 as well as Figures 9A to 9J the components described, and redundant repetitions will be omitted. Additionally, the following description will be made while focusing on the differences between the components described with reference to Figure 7 and Figure 8 as well as Figures 9A to 9J the components described.

[0216] Reference will be made to Figure 10A to describe the bonding structure in which the pad DP-PD1 disposed in the first region B1 (see Figure 4 ) is bonded to the first bump BP1.

[0217] Referring to Figure 10A , the display device DD-1 may include a base layer BL, an isolation layer BRL, a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, a pad DP-PD1, a first adhesive layer CF1, and a driving chip DC in the first region B1.

[0218] The pad DP-PD1 may be disposed on the second insulating layer 20. The pad DP-PD1 may include a first conductive pattern CL1, an insulating pattern SP, a second conductive pattern CL2, and a conductive member MTP.

[0219] The conductive member MTP may include a metal paste as a single main body of the conductive material. The metal paste may include conductive particles. The conductive particles may include a metal. For example, the conductive particles may include silver particles.

[0220] Referring to Figure 10A , at least a part of the metal paste may be inserted (or extended) into the second conductive pattern CL2. Additionally, the metal paste may penetrate into the first outer surface SU1 and / or the second outer surface SU2 of each of the first protrusion SP1 and the second protrusion SP2. At least a part of the metal paste may be inserted into the first conductive pattern CL1.

[0221] According to one embodiment, since the conductive member MTP includes a metal paste in a single body form, the reliability of electrical connection can be ensured through a plurality of conductive contact points similar to the conductive contact points provided by the discrete conductive member CP.

[0222] Figure 10B FIG. is a cross-sectional view of a first region that is part of a display device DD-2 according to an embodiment of the present disclosure. The same / similar reference numerals will be assigned to components that are the same / similar as those Figure 7 and Figure 8 and Figures 9A to 9J described in the reference, and redundant repetitions will be omitted. Additionally, the following description will be made while focusing on the differences between components that are the same / similar as those Figure 7 and Figure 8 and Figures 9A to 9J described in the reference.

[0223] Reference will be made to Figure 10B to describe the bonding structure in which the pad DP-PD2 provided in the first region B1 (see Figure 4 ) is bonded to the first bump BP1.

[0224] Referring to Figure 10B , the display device DD-2 may include a base layer BL, an isolation layer BRL, a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, a pad DP-PD2, a first adhesive layer CF1, and a driving chip DC in the first region B1.

[0225] The pad DP-PD2 may be provided on the second insulating layer 20. The pad DP-PD2 may include a first conductive pattern CL1, an insulating pattern SP, a second conductive pattern CL2, and a plurality of provided conductive members CP.

[0226] The insulating pattern SP may include a first protrusion SP1 and a second protrusion SP2. The first protrusion SP1 and the second protrusion SP2 may include a first outer surface SU1 and a second outer surface SU2, respectively. According to one embodiment, each of the first outer surface SU1 and the second outer surface SU2 may include a first side surface facing an adjacent protrusion and a second side surface facing the first side surface when viewed in a cross-sectional view.

[0227] The conductive members CP may be provided on opposite sides of the outer surface of the insulating pattern SP, respectively. Among the conductive members CP, each individual conductive member CP as a whole may be adjacent to the outer surfaces SU1, SU2 without penetrating the respective outer surfaces.

[0228] The conductive member CP may include: a plurality of first conductive members CP1 provided entirely on the first side of the outer surfaces SU1 and SU2, i.e., within the main body of the insulating pattern SP; and a plurality of second conductive members CP2 provided entirely on the second side of the outer surfaces SU1 and SU2, i.e., outside the main body of the insulating pattern SP. According to an embodiment, the conductive member CP may be disposed between the first side surfaces of the protrusions SP1 and SP2, and the pads DP - PD2 may further include additional conductive members provided on at least one of the second side surfaces of the protrusions SP1 and SP2.

[0229] Figure 10C A cross-sectional view of a first region that is part of a display device DD - 3 according to an embodiment of the present disclosure. The same / similar reference numerals will be assigned to components that are the same / similar as those Figure 7 and Figure 8 as well as Figures 9A to 9J described components, and redundant repetitions will be omitted. Additionally, the following description will be made while focusing on the differences between components that are the same / similar as those Figure 7 and Figure 8 as well as Figures 9A to 9J described components.

[0230] Reference will be made to Figure 10C to describe the bonding structure in which the pads DP - PD3 provided in the first region B1 (see Figure 4 ) are bonded to the first bump BP1.

[0231] Referring to Figure 10C , the display device DD - 3 may include a base layer BL, an isolation layer BRL, a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, pads DP - PD3, a first adhesive layer CF1, and a driving chip DC in the first region B1.

[0232] The pads DP - PD3 may be provided on the second insulating layer 20. The pads DP - PD3 may include a first conductive pattern CL1, an insulating pattern SP, a second conductive pattern CL2, and a conductive member CP.

[0233] The insulating pattern SP may include a plurality of protrusions SP1, SP2, and SP3. Referring to Figure 10C , the protrusions SP1, SP2, and SP3 may include a first protrusion SP1, a second protrusion SP2 connected to the first protrusion SP1, and a third protrusion SP3 connected to the second protrusion SP2 and spaced apart from the first protrusion SP1, with the second protrusion SP2 disposed between the first protrusion SP1 and the third protrusion SP3. According to an embodiment, the protrusions SP1, SP2, and SP3 may define a single main body of the insulating pattern SP, and may be adjacent to and connected to each other in the direction along the first conductive pattern CL1.

[0234] The insulating pattern SP may include recesses ANK between the first protrusion SP1 and the second protrusion SP2 and recesses ANK between the second protrusion SP2 and the third protrusion SP3. Accordingly, a part of the conductive member CP may be disposed between the first protrusion SP1 and the second protrusion SP2, and the remaining part of the conductive member CP may be disposed between the second protrusion SP2 and the third protrusion SP3. The first conductive member region SPA1 may be disposed between the first protrusion SP1 and the upper part of the insulating layer pattern of the second protrusion SP2 in the second direction DR2. The second conductive member region SPA2 may be disposed between the second protrusion SP2 and the upper part of the insulating layer pattern of the third protrusion SP3 in the second direction DR2.

[0235] When viewed in a cross-sectional view, the insulating pattern SP may have a thickness at a position along the first conductive pattern CL1. A first connection portion thickness SH1 and a second connection portion thickness SH2 are defined at each connection portion BR. The value of the connection portion thickness may have a value exceeding "0". In other words, the first protrusion SP1, the second protrusion SP2, and the third protrusion SP3 may be connected to each other with a certain thickness of the insulating pattern SP through the connection portion BR. Accordingly, the insulating pattern SP may be formed as a single body by connecting the first protrusion SP1, the second protrusion SP2, and the third protrusion SP3 to each other.

[0236] Figure 10D A cross-sectional view of a first region that is a part of the display device DD-4 according to an embodiment of the present disclosure. The same / similar reference numerals will be assigned to components that are the same / similar as those described with reference Figure 7 and Figure 8 as well as Figures 9A to 9J and redundant repetitions will be omitted. Additionally, the following description will be made while focusing on the differences between components that are the same / similar as those described with reference Figure 7 and Figure 8 as well as Figures 9A to 9J described.

[0237] Reference will be made to Figure 10D describe a bonding structure in which a pad DP-PD4 provided in the first region B1 (see Figure 4 ) is bonded to the first bump BP1.

[0238] Reference Figure 10D , the display device DD-4 may include a base layer BL in the first region B1 (see Figure 4 ), an isolation layer BRL, a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, a pad DP-PD4, a first adhesive layer CF1, and a driving chip DC.

[0239] The pad DP-PD4 may be disposed on the second insulating layer 20. The pad DP-PD4 may include a first conductive pattern CL1, an insulating pattern SP, a second conductive pattern CL2, a conductive member CP, and a metal layer MTL.

[0240] The metal layer MTL may be disposed on the second conductive pattern CL2. The metal layer MTL may cover the second conductive pattern CL2.

[0241] The metal layer MTL may be formed by the same process as the first sensing conductive layer IS-CL1. In other words, the metal layer MTL may include the same material as the first sensing conductive layer IS-CL1 and may have the same stacked structure as the first sensing conductive layer IS-CL1.

[0242] The metal layer MTL may be in contact with the first bump BP1. Thus, the metal layer MTL may transmit an electrical signal applied to the first bump BP1 to the conductive member CP or the second conductive pattern CL2. The electrical signal transmitted from the metal layer MTL to the conductive member CP may be transmitted to the second conductive pattern CL2. In other words, the electrical signal may be sequentially transmitted to the first bump BP1, the metal layer MTL, the conductive member CP, and the second conductive pattern CL2, or may be sequentially transmitted to the first bump BP1, the metal layer MTL, and the second conductive pattern CL2. The electrical signal transmitted to the second conductive pattern CL2 may be sequentially transmitted to the first conductive pattern CL1 and the end portion DL-E of the data line DL (see Figure 4 ).

[0243] According to an embodiment of the present disclosure, after the step of forming the second conductive pattern CL2 described in the reference Figure 9F , the display device DD-4 may be manufactured by performing the step of forming the metal layer MTL on the second conductive pattern CL2, and redundant repetitions will be omitted.

[0244] According to an embodiment of the present disclosure, since the pad included in the display device includes an insulating pattern including a protrusion, the reliability of the bonding between the pad and the bump may be improved.

[0245] In one embodiment, for example, the display device includes: a base layer including a display area in which a light-emitting element and a signal line are disposed and a non-display area adjacent to the display area and including a pad connected to the signal line. The pad includes a first conductive pattern to which the pad is connected to the signal line, an insulating pattern on the first conductive pattern and defining protrusions adjacent to each other in a direction along the first conductive pattern, a second conductive pattern on the insulating pattern and electrically connected to the first conductive pattern, and a conductive member between the protrusions and in the second conductive pattern.

[0246] Within the insulating pattern, the protrusions may define a single body of the insulating pattern. The insulating pattern includes a first protrusion and a second protrusion that are adjacent to and connected to each other in a direction along the first conductive pattern, and a recess may be defined between the first protrusion and the second protrusion.

[0247] Each of the protrusions may have a width in a direction along the first conductive pattern, and the width may decrease in a direction away from the first conductive pattern.

[0248] The first conductive pattern may include: a top surface, adjacent to the insulating pattern and extending further than the insulating pattern to define an exposed portion of the top surface; a bottom surface, opposite to the top surface; and a side surface, connecting the top surface to the bottom surface. The second conductive pattern is electrically connected to the first conductive pattern at the exposed portion of the top surface.

[0249] The conductive member may further include a first conductive member and a second conductive member. The first conductive member is entirely within the second conductive pattern and outside the insulating pattern, and the second conductive member is entirely within the insulating pattern.

[0250] In one embodiment, for example, a method for providing a display device includes: providing a preliminary display device, the preliminary display device including a base layer, the base layer including a display area in which a light-emitting element and a signal line are disposed and a non-display area adjacent to the display area and including a pad area; providing a first conductive pattern of a pad in the pad area; providing a preliminary insulating pattern on the first conductive pattern; providing an insulating pattern of the pad by etching the preliminary insulating pattern, the insulating pattern including protrusions adjacent to each other in a direction along the first conductive pattern; providing a conductive member of the pad between the protrusions; and providing a second conductive pattern of the pad on the insulating pattern having the protrusions. The conductive member is within the second conductive pattern.

[0251] In this method, providing the conductive member may include providing the conductive member from an emission member and directly between the protrusions of the insulating pattern.

[0252] The method may further include providing a bump facing the pad, and pressing the second conductive pattern having the conductive member therein onto the bump to expose the conductive member outside the second conductive pattern.

[0253] Although embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will recognize that various modifications and substitutions are possible without departing from the scope and spirit of the present disclosure as disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0254] Although the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, characterized in that, Comprising: A display panel, comprising: A display area in which light-emitting elements and signal lines are provided, and A non-display area adjacent to the display area and in which pads connected to the signal lines are provided, the pads comprising: A first conductive pattern to which the pad is connected to the signal line at the first conductive pattern; An insulating pattern on the first conductive pattern and defining protrusions adjacent to each other in a direction along the first conductive pattern; A second conductive pattern on the insulating pattern and electrically connected to the first conductive pattern; and A conductive member between the protrusions and at least partially in the second conductive pattern.

2. The display device according to claim 1, wherein Within the insulating pattern: The protrusions define a single body of the insulating pattern, the protrusions comprising a first protrusion and a second protrusion adjacent to each other and connected to each other in the direction along the first conductive pattern; and A recess is defined between the first protrusion and the second protrusion.

3. The display device according to claim 1, wherein Each of the protrusions has a width in the direction along the first conductive pattern; and The width decreases in a direction away from the first conductive pattern.

4. The display device according to claim 1, wherein The conductive member extends from the second conductive pattern and extends into the insulating pattern.

5. The display device according to claim 1, wherein The second conductive pattern comprises: A 2-1 pattern layer comprising titanium; A 2-2 pattern layer comprising aluminum, on the 2-1 pattern layer comprising titanium; and A 2-3 pattern layer comprising titanium, on the 2-2 pattern layer comprising aluminum, wherein the thickness of the 2-3 pattern layer is less than the thickness of the 2-2 pattern layer, and wherein the conductive member extends through the 2-3 pattern layer and is exposed outside the pad.

6. The display device according to claim 1, characterized in that, The second conductive pattern comprises: A 2-1 pattern layer comprising copper; and A 2-2 pattern layer comprising indium tin oxide, on the 2-1 pattern layer comprising copper.

7. The display device according to claim 1, wherein The first conductive pattern comprises: A top surface close to the insulating pattern and extending more than the insulating pattern to define an exposed portion of the top surface; A bottom surface opposite to the top surface; and A side surface connecting the top surface to the bottom surface, and The second conductive pattern is electrically connected to the first conductive pattern at the exposed portion of the top surface, wherein the display device further comprises: a driving chip in the non-display area and comprising bumps overlapping with the pads, wherein the bumps of the driving chip and the second conductive pattern of the pad are in contact with each other, and wherein the conductive member extends to the outside of the second conductive pattern and contacts the bumps.

8. The display device according to claim 1, wherein The conductive member comprises conductive particles randomly arranged in the second conductive pattern, and wherein the conductive particles comprise spherical conductive particles having an uneven outer surface.

9. The display device according to claim 1, wherein Each of the protrusions comprises: A first side surface facing an adjacent protrusion when viewed in a cross-sectional view; and A second side surface facing the first side surface, wherein the conductive member is disposed between the first side surfaces, wherein the pad further includes: an additional conductive member disposed on at least one of the second side surfaces, and wherein the pad further includes a metal layer covering the second conductive pattern.

10. The display device according to claim 1, wherein, Within the insulating pattern: the protrusions define a single body of the insulating pattern, the protrusions including a first protrusion, a second protrusion, and a third protrusion that are adjacent to and connected to each other in a direction along the first conductive pattern; and recesses are defined between the first protrusion and the second protrusion and between the second protrusion and the third protrusion.

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