Data recorder

Abstract

The utility model relates to the technical field of recorders, in particular to a data recorder which comprises a shell, a mainboard, an XJ4 connector, an AD acquisition daughter card, a 1553 communication daughter card, an interface assembly and a signal conditioning daughter card, the rear end of the mainboard is provided with a plurality of daughter card slots, the XJ4 connector is fixedly connected with the mainboard and located at the right end of the mainboard, the 1553 communication daughter card is connected with the corresponding daughter card slots in a clamped mode, and the interface assembly is connected with the 1553 communication daughter card in a clamped mode. The AD acquisition daughter cards are connected with the corresponding daughter card slots in a clamped mode, the signal conditioning daughter cards are connected with the corresponding daughter card slots in a clamped mode, and the interface assembly is arranged on the left side of the main board. The 1553 communication daughter card provides a path of dual-redundancy multifunctional 1553 communication protocol and exchanges information with the main collector through a PCI bus. A microcode controller is realized in a single-chip FPGA to process BC, RT and BM protocols, and the GJB289A requirement is met; through the application of the SoC technology, the number of devices is reduced, the reliability of the product is greatly improved, the power consumption of the product is reduced, and the device can be connected with a power supply of a case through an XJ4 connector.

Description

Technical Field

[0001] The utility model relates to the technical field of recorders, in particular to a data recorder. Background Art

[0002] Data recorders are essential equipment in the aviation field. The GJB1188A standard specifies the interface requirements between aircraft and data recorders, enabling compatibility between one aircraft and multiple data recorders, as well as between one data recorder and multiple aircraft.

[0003] In the existing technology, different problems are inevitable during the compatibility debugging and testing process between different aircraft and different data recorders. Recording the information exchange, power status, etc. between the aircraft and the data recorder can assist in the debugging and testing between the corresponding interface of the aircraft and the interface of the data recorder, and improve the research and development efficiency of the data recorder equipment. The test system for the data recorder can record the information exchange between the test system and the data recorder, and improve the research and development efficiency and testing efficiency of the test system. The same recorder can be adapted to multiple occasions, improving the efficiency of the equipment itself.

[0004] However, in the aforementioned prior art, the data recorder has too many components, which increases the power consumption of the product and reduces the reliability of the product. The device is also inconvenient to connect to the power interface of the chassis. Utility Model Content

[0005] The purpose of the utility model is to provide a data recorder, which solves the problems in the prior art that the number of components in the data recorder is too large, the power consumption of the product is increased, the reliability of the product is reduced, and the device is not convenient to connect to the chassis power interface.

[0006] To achieve the above-mentioned purpose, the present invention provides a data recorder, including a shell, a mainboard, an XJ4 connector, an AD acquisition sub-card, a 1553 communication sub-card, an interface component and a signal conditioning sub-card. The rear end of the mainboard has multiple sub-card slots, the XJ4 connector is fixedly connected to the mainboard and is located at the right end of the mainboard, the 1553 communication sub-card is engaged and connected with the corresponding sub-card slot, the AD acquisition sub-card is engaged and connected with the corresponding sub-card slot, the signal conditioning sub-card is engaged and connected with the corresponding sub-card slot, the interface component is arranged on the left side of the mainboard, and the mainboard is arranged inside the shell.

[0007] Among them, the interface component includes a bolt, a front panel, a signal recording interface and a debugging interface. The front panel is arranged on the left side of the main board. The bolt passes through the front panel and is located on the main board. The signal recording interface is arranged on the front panel. The debugging interface is arranged on the front panel and is located below the signal recording interface.

[0008] The data recorder further includes an ejector, which is fixedly connected to the front panel and located on the left side of the front panel.

[0009] The data recorder has a plurality of mounting posts and a cold plate, wherein the plurality of mounting posts are fixedly connected to the rear end of the cold plate, and the rear ends of the plurality of mounting posts are fixedly connected to the front end of the mainboard.

[0010] The mainboard has a plurality of first openings, the AD acquisition sub-card, the 1553 communication sub-card and the signal conditioning sub-card respectively have second openings, and the plurality of first openings are respectively adapted to the corresponding second openings.

[0011] The utility model relates to a data recorder. The 1553 communication daughter card provides a dual-redundant multifunctional 1553 communication protocol, exchanging information with the main acquisition unit via the PCI bus. A microcode controller is implemented in a single-chip FPGA to process the BC, RT, and BM protocols, complying with the requirements of GJB289A. The application of SoC technology reduces the number of components, greatly improving product reliability and reducing product power consumption. Furthermore, the XJ4 connector enables connection to the chassis power supply. The signal conditioning card completes signal conditioning for power supply voltage and current acquisition. The conditioned signal is sent to the AD acquisition daughter card for signal acquisition. For current signal acquisition of three power supplies (115V, 270V, and 28.5V), the Hall effect sensor MT9221CT12UR5 from MagnTek is used to convert the current signal into a voltage signal, which is then sent to the AD acquisition daughter card for signal acquisition. The current is then reversely calculated based on the acquired voltage. The input voltage is adjusted to the range of 0-5V by using precision electrical components for splitting, and then sent to the AD acquisition sub-card for signal acquisition. The voltage is then reversely calculated based on the collected voltage. The AD acquisition sub-card can acquire a total of 14 analog quantities. All signals are conditioned and the voltage range is 0-10V. Therefore, the AD acquisition sub-card provides 14 channels of 10V range analog quantity acquisition and communicates with the FPGA through the PCI bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art.

[0013] Figure 1 It is a schematic diagram of the overall structure of the utility model.

[0014] Figure 2 It is an overall exploded view of the present invention.

[0015] Figure 3 It is a principle block diagram of the utility model.

[0016] Figure 4 It is a principle block diagram of the mainboard of the utility model.

[0017] Figure 5 It is a schematic diagram of the relationship between the LS2K1000 interface of the present utility model.

[0018] Figure 6 It is a connection diagram of the power supply of the utility model.

[0019] Figure 7 This is a principle block diagram of the AD acquisition daughter card of the present utility model.

[0020] Figure 8 This is a principle block diagram of the signal conditioning of the present utility model.

[0021] Figure 9 This is a principle block diagram of the 1553 communication daughter card of the utility model.

[0022] Figure 10 It is a schematic diagram of the overall external structure of the utility model.

[0023] 1- Mainboard, 2- XJ4 connector, 3- AD acquisition daughter card, 4- 1553 communication daughter card, 5- Signal conditioning daughter card, 6- Daughter card slot, 7- Bolt, 8- Front panel, 9- Signal recording interface, 10- Debug interface, 11- Puller, 12- Mounting column, 13- Cold plate, 14- First opening, 15- Second opening, 16- Housing. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, but should not be understood as limiting the present invention.

[0025] See also Figures 1 to 10 ,in, Figure 1 It is a schematic diagram of the overall structure of the utility model. Figure 2 It is an exploded view of the entire utility model. Figure 3 This is a principle block diagram of the utility model. Figure 4 This is a principle block diagram of the mainboard 1 of the present utility model. Figure 5 This is a schematic diagram of the relationship between the LS2K1000 interface of the utility model. Figure 6 This is a schematic diagram of the connection of the power supply of the utility model. Figure 7 This is the principle block diagram of the AD acquisition sub-card 3 of the utility model. Figure 8 This is the principle block diagram of the signal conditioning of this utility model. Figure 9 This is the principle block diagram of the 1553 communication daughter card 4 of the utility model. Figure 10It is a schematic diagram of the overall external structure of the utility model.

[0026] The utility model provides a data recorder, including a shell 16, a mainboard 1, an XJ4 connector 2, an AD acquisition daughter card 3, a 1553 communication daughter card 4, an interface component and a signal conditioning daughter card 5. The rear end of the mainboard 1 has a plurality of daughter card slots 6, the XJ4 connector 2 is fixedly connected to the mainboard 1 and is located at the right end of the mainboard 1, the 1553 communication daughter card 4 is engaged and connected with the corresponding daughter card slot 6, the AD acquisition daughter card 3 is engaged and connected with the corresponding daughter card slot 6, the signal conditioning daughter card 5 is engaged and connected with the corresponding daughter card slot 6, the interface component is arranged on the left side of the mainboard 1, and the mainboard 1 is arranged inside the shell 16.

[0027] In this embodiment, the device offers multiple power supply options when plugged into a PXI chassis. Power is supplied via the 5V input of the J1 connector; when plugged into a PXIe chassis, it receives 12V power via the XJ4 connector 2. As a single board, it receives 12V power from an external input via the two-pin auxiliary power interface. Three power lines are fed into the board, each equipped with anti-backfeed diodes to ensure the safety of other power supplies and devices. The input power is converted to 5V DC via an isolated DC-DC converter and supplied to the mainboard 1. The 1553 communication daughter card 4 provides a dual-redundant multi-function 1553 communication protocol, exchanging information with the main acquisition unit via the PCI bus. A microcode controller is implemented in a single-chip FPGA to process BC, RT and BM protocols, which complies with the requirements of GJB289A. The application of SoC technology reduces the number of devices, greatly improves product reliability and reduces product power consumption, and can be connected to the power supply of the chassis through the XJ4 connector 2. The signal conditioning card completes the signal conditioning of the power supply voltage and current acquisition, and the conditioned signal is sent to the AD acquisition daughter card 3 for signal acquisition. For the current signal acquisition of the three power supplies of 115V, 270V and 28.5V, MagnTek's Hall sensor MT9221CT12UR5 is used to convert the current signal into a voltage signal, which is sent to the AD acquisition daughter card 3 for signal acquisition, and then the current is reversely calculated based on the acquired voltage. A precision electronic component is used to divide and adjust the input voltage to a range of 0-5V. This voltage is then fed into the AD acquisition daughter card 3 for signal acquisition. The voltage is then reverse-calculated based on the acquired voltage. The AD acquisition daughter card 3 collects a total of 14 analog signals. All signals undergo signal conditioning, with a voltage range of 0-10V. Therefore, the AD acquisition daughter card 3 provides 14 channels of 10V analog signal acquisition, communicating with the FPGA via the PCI bus. The motherboard 1 includes the Loongson 2K1000 core processing unit. The 1553B communication unit, operating in BM mode, monitors the communication data of the test interface 1553B. This is achieved through the 1553B communication daughter card and interacts with the motherboard 1 via the PCI bus. The AD acquisition unit records the output voltage and current of the MSI interface power supply. This is then processed by the signal conditioning daughter card 5 and then by the AD acquisition daughter card 3. Information is then exchanged with the motherboard 1 via the PCI bus. The Loongson 2K1000 processor is primarily targeted at network applications, with consideration also given to tablet and industrial control applications. The chip uses a 40nm process and integrates two GS264 processor cores with a main frequency of 1GHz, a 64-bit DDR3 controller, and various device I / O interfaces. Its main technical features are as follows:

[0028] The chip integrates two 64-bit dual-issue superscalar GS264 processor cores with a main frequency of 1GHz; a shared 1MB L2 cache; an integrated GPU; an integrated 64-bit 533MHz DDR3 controller; one SATA2.0 interface; two x4 PCIE2.0 interfaces on the chip, which can be split into six independent x1 interfaces; four USB2.0 interfaces on the chip; two RGMII Gigabit Ethernet interfaces on the chip; HDA / AC97 / I2S interfaces on the chip; an RTC / HPET module on the chip; 12 UART controllers on the chip; The Loongson LS2K1000 integrates one NAND controller, two CAN controllers, one SDIO controller, two I2C controllers, one LIO controller, one temperature sensor, one SPI interface (with four chip select signals), and a dynamic power consumption control module. The Loongson 2K1000 supports the following firmware and operating devices: BIOS: Loongson PMON; Operating System: Loongson Embedded Linux, Kylin. The Loongson LS2K1000 uses a 100MHz clock, a built-in 64-bit DDR3 controller, and 1GB of DDR3 RAM. The hard drive uses an onboard SATA NANDrive embedded solid-state drive with a capacity of 128GB, connected via a SATA interface, for signal acquisition programs and recorded data storage. The Loongson 2K1000 provides two GMAC controllers, which, when connected to an external network PHY chip, can implement two Gigabit / 100M adaptive network interfaces. The processor provides an EJTAG interface for debugging, downloading and upgrading PMON programs; and an RS232 interface for terminal information printing and program debugging.

[0029] Furthermore, the interface assembly includes a bolt 7, a front panel 8, a signal recording interface 9 and a debugging interface 10, the front panel 8 is arranged on the left side of the main board 1, the bolt 7 passes through the front panel 8 and is located on the main board 1, the signal recording interface 9 is arranged on the front panel 8, and the debugging interface 10 is arranged on the front panel 8 and is located below the signal recording interface 9.

[0030] In this embodiment, the signal recording interface 9 and the debugging interface 10 use lightweight quick-insert rectangular connectors J30JA-66ZK and J303JA-15ZK, and are connected to external data transmission equipment through the signal recording interface 9 and the debugging interface 10.

[0031] Furthermore, the data recorder further includes an extraction aid 11 , which is fixedly connected to the front panel 8 and is located on the left side of the front panel 8 .

[0032] In this embodiment, the extraction aid 11 is used for plugging and unplugging modules, which is convenient for operators to operate.

[0033] Furthermore, the data recorder has multiple mounting posts 12 and cold plates 13 , and the multiple mounting posts 12 are fixedly connected to the rear ends of the cold plates 13 , and the rear ends of the multiple mounting posts 12 are fixedly connected to the front ends of the mainboard 1 .

[0034] In this embodiment, the cold plate 13 is used to dissipate heat from electronic components with high heat generation, such as processors and power chips, and is mounted on the mainboard 1 via a plurality of mounting posts 12 .

[0035] Furthermore, the main board 1 has a plurality of first openings 14 , and the AD acquisition sub-card 3 , the 1553 communication sub-card 4 and the signal conditioning sub-card 5 respectively have a second opening 15 , and the plurality of first openings 14 are respectively adapted to the corresponding second openings 15 .

[0036] In this embodiment, external screws pass through the corresponding first opening 14 and the corresponding second opening 15, thereby fixing the AD acquisition sub-card 3, the 1553 communication sub-card 4 and the signal conditioning sub-card 5 on the main board 1 respectively; the software development environment of the device adopts the upper and lower computer working modes, and the recorder adopts the embedded operating system based on Loongson as the lower computer. The upper computer compiles the application through the cross-compilation tool, and then downloads the application to the processor through the network and loads it for operation; the upper computer can use an X86 architecture PC or laptop, which needs to be configured with at least one network port and one USB interface.

[0037] The above disclosure is merely one or more preferred embodiments of the present application and is not intended to limit the scope of the present application. A person skilled in the art will understand that all or part of the processes of the above embodiments and equivalent changes made in accordance with the claims of the present application are still within the scope of the present application.

Claims

1. A data recorder, characterized in that: Including housing, mainboard, XJ4 connector, AD acquisition daughter card, 1553 communication daughter card, interface components and signal conditioning daughter card; The rear end of the mainboard has multiple sub-card slots, the XJ4 connector is fixedly connected to the mainboard and is located at the right end of the mainboard, the 1553 communication sub-card is engaged with the corresponding sub-card slot, the AD acquisition sub-card is engaged with the corresponding sub-card slot, and the signal conditioning sub-card is engaged with the corresponding sub-card slot. The interface component is arranged on the left side of the mainboard, and the mainboard is arranged inside the shell.

2. The data recorder according to claim 1, wherein The interface assembly includes a bolt, a front panel, a signal recording interface and a debugging interface. The front panel is arranged on the left side of the main board. The bolt passes through the front panel and is located on the main board. The signal recording interface is arranged on the front panel. The debugging interface is arranged on the front panel and is located below the signal recording interface.

3. The data recorder according to claim 2, wherein: The data recorder further includes an ejection aid, which is fixedly connected to the front panel and located on the left side of the front panel.

4. The data recorder according to claim 3, wherein: The data recorder has a plurality of mounting posts and a cold plate, wherein the plurality of mounting posts are respectively fixedly connected to the rear end of the cold plate, and the rear ends of the plurality of mounting posts are respectively fixedly connected to the front end of the mainboard.

5. The data recorder according to claim 4, wherein: The mainboard has a plurality of first openings, the AD acquisition daughter card, the 1553 communication daughter card and the signal conditioning daughter card respectively have a second opening, and the plurality of first openings are respectively adapted to the corresponding second openings.

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