Display device

Abstract

Provided is a display device including: a substrate; a circuit layer; and an element layer. The circuit layer includes: a first light emitting pixel driver and a second light emitting pixel driver adjacent to each other in a second direction; a third light-emitting pixel driver and a fourth light-emitting pixel driver adjacent to the first light-emitting pixel driver and the second light-emitting pixel driver, respectively, in the first direction; and a first direction line extending in the first direction and adjacent to a boundary between the first light emitting pixel driver and the second light emitting pixel driver and adjacent to a boundary between the third light emitting pixel driver and the fourth light emitting pixel driver. The one first direction line includes: a first main extension portion extending in a first direction; and a bypass portion connected to the first main extension portion and bypassing the light transmissive region.

Description

Technical Field

[0001] Aspects of one or more embodiments of the present disclosure relate to a display device. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Here, the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and an ultra-small light-emitting display device including an ultra-small light-emitting element.

[0004] Organic light-emitting display devices use light-emitting elements, each of which includes a light-emitting layer of organic light-emitting material, to display images. Because organic light-emitting display devices use self-luminous elements to achieve image display, they can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0005] The surface of the display device may be a display surface including a display area displaying an image and a non-display area disposed around the display area. An emission area emitting light having corresponding brightness and color may be arranged in the display area.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Utility Model Content

[0007] An electronic device equipped with a display device may include optical sensors such as a camera, an illuminance sensor, and a distance sensor.

[0008] If the optical sensors are arranged below the display surface of the display device, they can overlap with the non-display area of the display device to ensure its optical path. However, in this case, the width of the non-display area increases due to the arrangement of the optical sensors.

[0009] To address this issue, a portion of the display area of the display device may include both an emissive area and a light-transmitting area, and the optical sensor may overlap with this portion of the display area. In this case, due to the presence of the light-transmitting area, the portion of the display area overlapping the optical sensor may have a lower resolution than other portions, resulting in degraded display quality.

[0010] Aspects of some embodiments of the present disclosure relate to a display device in which degradation of display quality can be reduced or prevented if a portion of a display area overlaps with an optical sensor.

[0011] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0012] According to some aspects of the present disclosure, a display device is provided, comprising: a substrate including a display area including an emission area; a circuit layer on the substrate; and an element layer on the circuit layer and including light-emitting elements, respectively, in the emission area. The circuit layer includes light-emitting pixel drivers, each electrically connected to the light-emitting elements, and arranged side by side in a first direction and in a second direction intersecting the first direction. The light-emitting pixel drivers include: a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the second direction; and a third light-emitting pixel driver and a fourth light-emitting pixel driver adjacent to the first light-emitting pixel driver and the second light-emitting pixel driver, respectively, in the first direction. The circuit layer further includes: a first direction line extending in the first direction and adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver and adjacent to a boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver. The first direction line includes: a first main extension portion extending in the first direction; and a bypass portion connected to the first main extension portion and bypassing a light-transmitting area of the display area including contact points where the first, second, third, and fourth light-emitting pixel drivers contact each other.

[0013] The first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver and the fourth light-emitting pixel driver can be electrically connected to the one first direction line; and the one first direction line can be a bias voltage line among a plurality of bias voltage lines configured to transmit a bias voltage to the light-emitting pixel driver.

[0014] The circuit layer may further include an anode initialization voltage line configured to transmit an anode initialization voltage to the light-emitting pixel driver. The anode initialization voltage line may include: a second main extension portion adjacent to the first main extension portion and extending in the first direction; and a first sub-protrusion portion protruding from the second main extension portion to extend in the second direction and intersecting the first direction line. The second main extension portion may overlap the first light-emitting pixel driver; and an end portion of the first sub-protrusion portion may overlap the second light-emitting pixel driver.

[0015] The circuit layer may further include: a first anode initialization voltage line adjacent to one side of the bias voltage line among the plurality of bias voltage lines in the second direction, extending in the first direction, and configured to transmit a first anode initialization voltage; and a second anode initialization voltage line adjacent to the other side of the bias voltage line among the plurality of bias voltage lines in the second direction, extending in the first direction, and configured to transmit a second anode initialization voltage having a voltage level different from that of the first anode initialization voltage. The first anode initialization voltage line may overlap with the first light-emitting pixel driver and may be electrically connected to the first light-emitting pixel driver and the second light-emitting pixel driver; and the second anode initialization voltage line may overlap with the fourth light-emitting pixel driver and may be electrically connected to the third light-emitting pixel driver and the fourth light-emitting pixel driver.

[0016] The circuit layer may further include a bias control line configured to transmit a bias control signal to a light-emitting pixel driver. The bias control line may include: a third main extension portion adjacent to one side of the bias voltage line among the plurality of bias voltage lines in the second direction and extending in the first direction; and a second sub-protrusion portion protruding from the third main extension portion to extend in the second direction and intersect the one first-direction line. The third main extension portion may overlap the first light-emitting pixel driver; and an end portion of the second sub-protrusion portion may overlap the second light-emitting pixel driver.

[0017] The circuit layer may further include: an emission control line, adjacent to the bias control line, extending in the first direction and overlapping with the first light-emitting pixel driver and the third light-emitting pixel driver, the emission control line being configured to transmit an emission control signal to the light-emitting pixel driver; an emission control auxiliary line, extending in the first direction, spaced apart from the emission control line in the second direction and overlapping with the second light-emitting pixel driver and the fourth light-emitting pixel driver; and an emission control connection line, extending in the second direction, electrically connected to the emission control line and the emission control auxiliary line and crossing the one first direction line.

[0018] The circuit layer may further include a gate initialization voltage line configured to transmit a gate initialization voltage to the light-emitting pixel driver. The light-emitting pixel driver may further include a fifth light-emitting pixel driver adjacent to the first light-emitting pixel driver in the second direction. The first light-emitting pixel driver may be located between the second light-emitting pixel driver and the fifth light-emitting pixel driver in the second direction; and the first light-emitting pixel driver and the fifth light-emitting pixel driver may be electrically connected to the gate initialization voltage line arranged adjacent to the boundary between the first light-emitting pixel driver and the fifth light-emitting pixel driver.

[0019] The circuit layer may further include a scan initialization line configured to transmit a scan initialization signal to the light-emitting pixel driver. The scan initialization line may include: a fourth main extension portion adjacent to the gate initialization voltage line and extending in the first direction; and a third sub-protrusion portion protruding from the fourth main extension portion and extending in the second direction. The fourth main extension portion may overlap with the fifth light-emitting pixel driver, and an end portion of the third sub-protrusion portion may overlap with the first light-emitting pixel driver.

[0020] The circuit layer may further include: a gate control line extending in the first direction, overlapping the fifth light-emitting pixel driver and configured to transmit a gate control signal to the light-emitting pixel driver; a gate control auxiliary line spaced apart from the gate control line in the second direction, extending in the first direction and overlapping the first light-emitting pixel driver; and a gate control connection line extending in the second direction, electrically connected to the gate control line and the gate control auxiliary line and crossing the gate initialization voltage line.

[0021] The circuit layer may include: a first semiconductor layer on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the second interlayer insulating layer; a first planarizing layer covering the first source-drain conductive layer; a second source-drain conductive layer on the first planarizing layer; and a second planarizing layer covering the second source-drain conductive layer. Each of the light-emitting pixel drivers may include: a first transistor electrically connected between a first node and a second node; a pixel capacitor electrically connected between a first power line and a third node, the first power line being configured to transmit a voltage of a first power source; a second transistor electrically connected between a data line and the first node, the data line being configured to transmit a data signal; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a gate initialization voltage line and the third node, the gate initialization voltage line being configured to transmit a gate initialization voltage; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between the second node and the fourth node; a seventh transistor electrically connected between an anode initialization voltage line and the fourth node, the anode initialization voltage line being configured to transmit an anode initialization voltage; and an eighth transistor electrically connected between the one of the plurality of bias voltage lines and the first node. The first node may be electrically connected to a first electrode of the first transistor; the second node may be electrically connected to a second electrode of the first transistor; the third node may be electrically connected to a gate electrode of the first transistor; and the fourth node may be electrically connected to one of the light-emitting elements. Each of the first, second, fifth, sixth, seventh, and eighth transistors may include: a gate electrode; a channel portion overlapping the gate electrode; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion. Each of the third and fourth transistors may include: a first gate electrode and a second gate electrode at least partially overlapping each other; a channel portion between the first and second gate electrodes; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion. The channel portion, the first electrode portion, and the second electrode portion of each of the first, second, fifth, sixth, seventh, and eighth transistors may be portions of the first semiconductor layer; and the channel portion, the first electrode portion, and the second electrode portion of each of the third and fourth transistors may be portions of the second semiconductor layer.

[0022] The first and second semiconductor layers of the first light emitting pixel driver may be symmetrical to the first and second semiconductor layers of the third light emitting pixel driver with respect to a boundary between the first and third light emitting pixel drivers.

[0023] The first semiconductor layer of the first light emitting pixel driver may be symmetrical to the first semiconductor layer of the second light emitting pixel driver with respect to a boundary between the first light emitting pixel driver and the second light emitting pixel driver.

[0024] A channel portion of the first transistor of the first light-emitting pixel driver may be congruent with a channel portion of the first transistor of the second light-emitting pixel driver.

[0025] According to some aspects of the present disclosure, a display device is provided, comprising: a substrate comprising a display area including an emission area; a circuit layer on the substrate; and an element layer on the circuit layer and comprising light-emitting elements respectively in the emission area, wherein the circuit layer comprises: light-emitting pixel drivers respectively electrically connected to the light-emitting elements and arranged side by side with each other in a first direction and a second direction intersecting the first direction; wherein the circuit layer comprises: a first semiconductor layer on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; and a second interlayer insulating layer covering the third gate conductive layer. Each of the light-emitting pixel drivers includes: a first transistor electrically connected between a first node and a second node; a pixel capacitor electrically connected between a first power line and a third node, the first power line configured to transmit a voltage of a first power source; a second transistor electrically connected between a data line and the first node, the data line configured to transmit a data signal; a third transistor electrically connected between the second node and the third node; and a fourth transistor electrically connected between a gate initialization voltage line and a third node, the gate initialization voltage line configured to transmit a gate initialization voltage. The first node is electrically connected to a first electrode of the first transistor; the second node is electrically connected to a second electrode of the first transistor; and the third node is electrically connected to a gate electrode of the first transistor. Each of the first and second transistors includes: a gate electrode; a channel portion overlapping the gate electrode; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion. Each of the third and fourth transistors includes: a first gate electrode and a second gate electrode at least partially overlapping each other; a channel portion between the first and second gate electrodes; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion. The channel portion, first electrode portion, and second electrode portion of each of the first and second transistors are part of the first semiconductor layer; and the channel portion, first electrode portion, and second electrode portion of each of the third and fourth transistors are part of the second semiconductor layer. The light-emitting pixel driver includes a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in a second direction. The channel portion of the first transistor of the first light-emitting pixel driver is congruent with the channel portion of the first transistor of the second light-emitting pixel driver.

[0026] The light-emitting pixel driver may further include a third light-emitting pixel driver and a fourth light-emitting pixel driver respectively adjacent to the first light-emitting pixel driver and the second light-emitting pixel driver in the first direction; the circuit layer may further include: a first direction line, extending in the first direction, and adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver and adjacent to the boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver; the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver and the fourth light-emitting pixel driver may be electrically connected to the one first direction line; and the one first direction line may include: a first main extension portion, extending in the first direction; and a bypass portion, connected to the first main extension portion, and bypassing a light-transmitting area of the display area including a contact point at which the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver and the fourth light-emitting pixel driver contact each other.

[0027] Each of the light-emitting pixel drivers may further include: a fifth transistor electrically connected between the first power supply line and the first node; a sixth transistor electrically connected between the second node and the fourth node; a seventh transistor electrically connected between an anode initialization voltage line and the fourth node, the anode initialization voltage line configured to transmit an anode initialization voltage; and an eighth transistor electrically connected between a bias voltage line and the first node, the bias voltage line configured to transmit a bias voltage. The fourth node may be electrically connected to one of the light-emitting elements, and the one first direction line may be a bias voltage line.

[0028] The anode initialization voltage line may include: a second main extension portion adjacent to the first main extension portion of the bias voltage line and extending in a first direction; and a first sub-protrusion portion protruding from the second main extension portion to extend in a second direction and intersecting the first direction line. The second main extension portion may overlap with the first light-emitting pixel driver; and an end portion of the first sub-protrusion portion may overlap with the second light-emitting pixel driver.

[0029] The circuit layer may further include: a first anode initialization voltage line adjacent to one side of the bias voltage line in the second direction, extending in the first direction, and configured to transmit a first anode initialization voltage; and a second anode initialization voltage line adjacent to the other side of the bias voltage line in the second direction, extending in the first direction, and configured to transmit a second anode initialization voltage having a voltage level different from that of the first anode initialization voltage. The first anode initialization voltage line may overlap with the first light-emitting pixel driver and may be electrically connected to the first light-emitting pixel driver and the second light-emitting pixel driver; and the second anode initialization voltage line may overlap with the fourth light-emitting pixel driver and may be electrically connected to the third light-emitting pixel driver and the fourth light-emitting pixel driver.

[0030] The circuit layer may further include a bias control line configured to transmit a bias control signal to the light-emitting pixel driver; the seventh transistor and the eighth transistor may be configured to be turned on by the bias control signal; the bias control line may include: a third main extension portion, adjacent to one side of the bias voltage line in the second direction and extending in the first direction; and a second sub-protrusion portion, protruding from the third main extension portion to extend in the second direction and crossing the one first direction line; the third main extension portion may overlap with the first light-emitting pixel driver; and an end portion of the second sub-protrusion portion may overlap with the second light-emitting pixel driver.

[0031] The light-emitting pixel driver may further include a fifth light-emitting pixel driver adjacent to the first light-emitting pixel driver in the second direction. The first light-emitting pixel driver may be located between the second light-emitting pixel driver and the fifth light-emitting pixel driver in the second direction, and the first light-emitting pixel driver and the fifth light-emitting pixel driver may be electrically connected to a gate initialization voltage line adjacent to a boundary between the first light-emitting pixel driver and the fifth light-emitting pixel driver.

[0032] According to some embodiments, even if the number of light-emitting pixel drivers is not reduced, a light-transmitting area for providing a light path for the optical sensor can be ensured. Accordingly, even if a portion of the display area overlaps with the optical sensor, degradation of display quality can be reduced or prevented.

[0033] According to some embodiments, because one bias voltage line does not extend in a straight line in the first direction but includes a bypass portion that bypasses the light-transmitting area, a wider light-transmitting area can be ensured.

[0034] However, the effects according to some embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are also included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] These and / or other aspects will become apparent and more readily understood from the following description of some embodiments taken in conjunction with the accompanying drawings, in which:

[0036] Figure 1 is a perspective view of an electronic device according to some embodiments;

[0037] Figure 2 yes Figure 1 An exploded perspective view of an electronic device;

[0038] Figure 3 yes Figure 2 A plan view of a display device;

[0039] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA';

[0040] Figure 5 yes Figure 3 a layout diagram of part B;

[0041] Figure 6 yes Figure 5 Equivalent circuit diagram of the light-emitting pixel driver in FIG;

[0042] Figure 7 yes Figure 3 a layout diagram of part C;

[0043] Figure 8 According to some embodiments Figure 7 A plan view of the circuit layer in section D;

[0044] Figure 9 Graphic Figure 8 a first semiconductor layer, a first gate conductive layer, and a bias voltage line in a plan view;

[0045] Figure 10 It is along Figure 8 A cross-sectional view taken along line F-F';

[0046] Figure 11 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first semiconductor layer, the first gate conductive layer, the bias voltage line, and the first source and drain conductive layer in portion D;

[0047] Figure 12 FIGURE 1 shows a diagram according to some embodiments Figure 7 The first semiconductor layer, the first gate conductive layer and the anode initialization voltage line in the portion D;

[0048] Figure 13 According to some embodiments Figure 7 A plan view of the circuit layer in section E;

[0049] Figure 14 It is along Figure 13 A cross-sectional view taken along line G-G';

[0050] Figure 15 FIGURE 1 shows a diagram according to some embodiments Figure 7 The first semiconductor layer, the first gate conductive layer and the bias voltage line in the portion D;

[0051] Figure 16 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first semiconductor layer, the first gate conductive layer, and the third gate conductive layer in portion D';

[0052] Figure 17is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first gate conductive layer, the second gate conductive layer, the second semiconductor layer and the third gate conductive layer in part E;

[0053] Figure 18 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first gate conductive layer, the second gate conductive layer, the second semiconductor layer and the third gate conductive layer in part E;

[0054] Figure 19 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first gate conductive layer, the second gate conductive layer, the second semiconductor layer and the third gate conductive layer in part E;

[0055] Figure 20 is a plan view illustrating a first semiconductor layer and a second semiconductor layer of each of a first light emitting pixel driver, a second light emitting pixel driver, a third light emitting pixel driver, and a fourth light emitting pixel driver according to some embodiments; and

[0056] Figure 21 is a plan view illustrating a first semiconductor layer and a second semiconductor layer of each of a first light emitting pixel driver, a second light emitting pixel driver, a third light emitting pixel driver, and a fourth light emitting pixel driver according to some embodiments.

[0057] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings. DETAILED DESCRIPTION

[0058] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, some embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, like reference numerals denote like components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0059] For the purpose of describing the embodiments of the present disclosure, some of parts irrelevant to the description may not be provided.

[0060] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0061] Further, the phrase "in a plan view" means when an object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting an object portion is viewed from the side. The term "overlapping" or "overlapping" means that a first object can be above or below or to the side of a second object, and / or vice versa. In addition, the term "overlapping" can include layer, stack, facing or facing, extending above, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will recognize and understand. The expression "not overlapping with..." can include meanings such as "separated from..." or "separated from..." or "deviated from..." and any other suitable equivalents that a person of ordinary skill in the art will recognize and understand. The terms "facing" and "facing" can mean that a first object can be directly or indirectly opposite to a second object. In the case where a third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, although still facing each other.

[0062] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," or "upper" may be used herein to describe the relationship between one element or component and another element or component illustrated in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the devices illustrated in the accompanying drawings are flipped over, a device that is "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0063] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprises,” “comprising,” “having,” and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0064] It will be understood that although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and illustration thereof. For example, when a "first element" is discussed in the description, it may be referred to as a "second element" or a "third element," and the "second element" and "third element" may be referred to in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0065] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0066] Throughout the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in either a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or." Throughout the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0067] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0068] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0069] Figure 1 is a perspective view of an electronic device 10 according to some embodiments. Figure 2 yes Figure 1 1 is an exploded perspective view of the electronic device 10.

[0070] refer to Figure 1The electronic device 10 according to some embodiments is a device having a function of displaying an image in a display area. The electronic device 10 may be portable. For example, the electronic device 10 may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra-mobile PC (UMPC).

[0071] However, the electronic device 10 according to some embodiments is not limited to a portable electronic device and may also be a large device such as a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IOT) device.

[0072] The electronic device 10 may include a display device 100 (see Figure 2 )'s housing provides a cover window 11 and a bottom cover 12.

[0073] refer to Figure 2 The electronic device 10 according to some embodiments may further include a display device 100 , a bracket 13 , one or more optical devices 18 , and a main circuit board 14 accommodated between the cover window 11 and the bottom cover 12 .

[0074] In the following description, a first direction DR1 may be a direction parallel to a short side of the electronic device 10 in a plan view, that is, a horizontal direction of the electronic device 10. A second direction DR2 may be a direction parallel to a long side of the electronic device 10 in a plan view, that is, a vertical direction of the electronic device 10. A third direction DR3 may be a thickness direction of the electronic device 10.

[0075] The electronic device 10 may have a rectangular shape in a plan view. For example, the electronic device 10 may be shaped like a rectangular plane having short sides in the first direction DR1 and long sides in the second direction DR2. Each corner where the short sides extending in the first direction DR1 intersect the long sides extending in the second direction DR2 may be rounded with a predetermined curvature or may be a right angle. The planar shape of the electronic device 10 is not limited to a rectangular shape, but may also be other polygonal shapes, a circular shape, or an elliptical shape.

[0076] The electronic device 10 may include a display surface on which a display area DA displaying an image is provided.

[0077] The display device 100 may include a display area DA that emits light toward a display surface of the electronic device 10 and a non-display area NDA (see FIG. Figure 3 ). In addition, the display device 100 may further include a non-display area NDA (see Figure 3) of the display area DA adjacent to the short side of the portion of the protruding sub-area SBA (see Figure 3 ).

[0078] The display device 100 may further include a sub-area SBA (see Figure 3 ) in the display driving circuit 200, fastened to the sub-area SBA (see Figure 3 ), a display circuit board 300 at an edge thereof, a touch driving circuit 400 mounted on the display circuit board 300, and a wire 500 extending from one side of the display circuit board 300.

[0079] The display area DA may include a main display area MDA provided in most of the display area DA and one or more sub display areas SBDA surrounded by the main display area MDA and overlapping with the optical device 18 .

[0080] The cover window 11 may be provided on the display device 100 . Thus, a surface of the display device 100 from which light is emitted may be covered by the cover window 11 .

[0081] The cover window 11 may protect the upper surface of the display device 100 .

[0082] The cover window 11 may include a transparent light-transmitting portion and an opaque light-shielding portion.

[0083] The light-transmitting portion may overlap with the display area DA of the display device 100 in the third direction DR3, and the light-shielding portion may overlap with the non-display area NDA (see FIG. 1 ) of the display device 100 in the third direction DR3. Figure 3 )overlapping.

[0084] The cover window 11 may include an upper surface portion forming an upper surface of the electronic device 10, a left surface portion forming a left side surface of the electronic device 10, and a right surface portion forming a right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the upper surface portion, and the right surface portion may extend from the right side of the upper surface portion.

[0085] Each of the upper surface portion, the left side surface portion, and the right side surface portion of the cover window 11 may include a light transmitting portion and a light shielding portion.

[0086] The light transmitting portion of the cover window 11 may be provided in most of each of the upper, left, and right surface portions of the cover window 11 .

[0087] The light shielding portion of the cover window 11 can be set at the upper edge and lower edge of the upper surface portion of the cover window 11, at the upper edge, left edge and lower edge of the left surface portion of the cover window 11, and at the upper edge, right edge and lower edge of the right surface portion of the cover window 11.

[0088] The bracket 13 may be disposed under the display device 100 .

[0089] The bracket 13 may include plastic, metal, or both. The bracket 13 may include a first camera hole CMH1 into which the camera device 16 is inserted, a battery hole BH into which the battery 19 is fixed, a light-transmitting hole SH into which the optical device 18 is inserted, and a wire hole CAH through which the wires 500 connected to the display circuit board 300 pass.

[0090] The main circuit board 14 and the battery 19 may be disposed under the bracket 13. The main circuit board 14 may be a printed circuit board or a flexible printed circuit board.

[0091] The main processor 15 , the camera device 16 , the main connector 17 and the optical device 18 may be mounted on the main circuit board 14 .

[0092] The camera device 16 may be provided on both the upper and lower surfaces of the main circuit board 14. The main processor 15 may be provided on the upper surface of the main circuit board 14, and the main connector 17 may be provided on the lower surface of the main circuit board 14.

[0093] The main processor 15 may control substantially all functions of the electronic device 10 .

[0094] For example, the main processor 15 can output digital video data to the display driver circuit 200 via the display circuit board 300 so that the display panel 100 can display an image. In addition, the main processor 15 can receive touch data including the user's touch coordinates from the touch driver circuit 400, determine whether the user has touched the display device 100 or is close to the display device 100, and perform an operation corresponding to the user's touch input or proximity input. For example, the main processor 15 can execute an application or perform an operation indicated by an icon touched by the user.

[0095] The main processor 15 may be an application processor, a central processing unit, or a system chip formed as an integrated circuit, etc.

[0096] The camera device 16 may process image frames such as still images or moving images obtained by an image sensor in a camera mode and may output the processed image frames to the main processor 15 .

[0097] The electric wires 500 passing through the electric wire holes CAH of the bracket 13 may be connected to the main connector 17. Accordingly, the main circuit board 14 may be electrically connected to the display circuit board 300.

[0098] The optical device 18 may include a proximity sensor, an illumination sensor, an iris sensor, a second camera sensor, and the like.

[0099] Optical devices 18 such as a proximity sensor, an illumination sensor, an iris sensor, and a second camera sensor may be disposed on the upper surface of the main circuit board 14 and in the light-transmitting hole SH of the bracket 13 .

[0100] The proximity sensor is a sensor for detecting an object positioned near the front surface of the electronic device 10. The proximity sensor may include a light source that outputs light and a light receiving unit (e.g., a light receiver) that receives light reflected by the object. The proximity sensor may generate a sensing signal corresponding to the amount of light reflected by the object. Based on the sensing signal from the proximity sensor, it may be determined whether an object is positioned near the front surface of the electronic device 10.

[0101] The illuminance sensor is a sensor for detecting the brightness of the front surface of the electronic device 10. The illuminance sensor may include a resistor whose resistance value (eg, resistance) varies according to the brightness of incident light.

[0102] The iris sensor is a sensor for capturing the user's iris. Whether the user is a pre-registered user can be verified based on whether the image captured by the iris sensor is substantially the same as the iris image pre-stored in the memory.

[0103] The second camera sensor may process image frames such as still images or moving images obtained by the image sensor and may output the processed image frames to the main processor 15. The second camera sensor may be a CMOS image sensor or a CCD sensor. The number of pixels of the second camera sensor may be less than the number of pixels of the camera device 16, and the size of the second camera sensor may be smaller than the size of the camera device 16.

[0104] The battery 19 may be spaced apart from the main circuit board 14. For example, the battery 19 may not overlap with the main circuit board 14 in the third direction DR3. The battery 19 may be disposed in the battery hole BH of the bracket 13 in the third direction DR3.

[0105] In addition, the main circuit board 14 may further include a mobile communication module that can transmit wireless signals to at least one of a base station, an external terminal, and a server through a mobile communication network and receive wireless signals from at least one of the base station, the external terminal, and the server. The wireless signals may include voice signals, video call signals, or various types of data generated by the transmission / reception of text / multimedia messages.

[0106] The bottom cover 12 may be disposed below the main circuit board 14 and the battery 19. The bottom cover 12 may be fastened and fixed to the bracket 13. The bottom cover 12 may form an upper side surface, a lower side surface, and a lower surface of the electronic device 10. The bottom cover 12 may include plastic, metal, or both plastic and metal.

[0107] The bottom cover 12 may include a second camera hole CMH2 exposing a lower surface of the camera device 16 .

[0108] However, the positions of the light transmission hole SH, the first camera hole CMH1 and the second camera hole CMH2 are not limited to Figure 2 The location shown in the figure.

[0109] Figure 3 yes Figure 2 100 is a plan view of the display device 100. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'.

[0110] refer to Figure 3 , the substrate 110 of the display device 100 may include a display area DA and a non-display area NDA provided on a display surface, and a sub-area SBA protruding from one side of the non-display area NDA.

[0111] The display area DA may be provided on most of the display surface.The display area DA may be provided in the center of the display surface.

[0112] The display area DA may include a main display area MDA provided in most part of the display area DA and one or more subsidiary display areas SBDA surrounded by the main display area MDA.

[0113] The auxiliary display area SBDA can be connected to the optical device 18 (see Figure 2 )overlapping.

[0114] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be an edge area of the display surface.

[0115] The sub area SBA may protrude from a portion of the non-display area NDA adjacent to a short side of the display area DA in the second direction DR2 .

[0116] Since a portion of the sub area SBA is bent, another portion of the sub area SBA may overlap the display area DA and the non-display area NDA in the third direction DR3 .

[0117] The display device 100 may include an upper surface portion facing an upper surface portion of the cover window 11, a left surface portion facing a left surface portion of the cover window 11, and a right surface portion facing a right surface portion of the cover window 11. The left surface portion of the display device 100 may extend from a left side of the upper surface portion, and the right surface portion may extend from a right side of the upper surface portion.

[0118] Each of the upper surface portion, the left side surface portion, and the right side surface portion of the display device 100 may include a display area DA and / or a non-display area NDA.

[0119] The display area DA may be provided on most of an upper surface portion, a left side surface portion, and / or a right side surface portion of the display device 100 .

[0120] The non-display area NDA may be disposed at an edge of the main area MA to surround the display area DA.

[0121] The sub-area SBA may be a region protruding from the non-display area NDA of the main area MA to one side in the second direction DR2 .

[0122] Since a portion of the sub area SBA is bent, another portion of the sub area SBA may be disposed on the rear surface of the display device 100 .

[0123] Figure 3 and Figure 4 The display device 100 is illustrated in which a portion of the sub area SBA is bent.

[0124] refer to Figure 4 , the display device 100 according to some embodiments may include a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0125] The display device 100 according to some embodiments may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140 .

[0126] In addition, the display device 100 according to some embodiments may further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0127] The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, rolled, etc.

[0128] In some embodiments, the substrate 110 may be made of an insulating material such as glass.

[0129] The substrate 110 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0130] The element layer 130 may include a layer disposed in the emission area EA (see Figure 5 ) in the light emitting element LE (see Figure 6 ).

[0131] The circuit layer 120 may include a light emitting element LE electrically connected to the element layer 130 (see Figure 6) of the light-emitting pixel driver EPD (see Figure 5 ).

[0132] The sealing layer 140 may cover the element layer 130 and extend to the non-display area NDA to contact the circuit layer 120. The sealing layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0133] The touch sensor layer 150 may be provided on the sealing layer 140 and may correspond to the main area MA. The touch sensor layer 150 may include a touch electrode for detecting a touch of a person or an object.

[0134] The polarizing layer 160 may block or reduce external light reflected from the touch sensor layer 150 , the sealing layer 140 , the element layer 130 , the circuit layer 120 and / or their interfaces to reduce or prevent degradation of image visibility due to reflection of external light.

[0135] The cover window 11 of the electronic device 10 may be disposed on the polarizing layer 160. The cover window 11 may be attached to the polarizing layer 160 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR).

[0136] The cover window 11 may be an inorganic material such as glass, or may be an organic material such as plastic or polymer material.

[0137] The cover window 11 may protect the touch sensor layer 150 , the sealing layer 140 , the element layer 130 , and the circuit layer 120 from electrical and physical shocks on the display surface.

[0138] Figure 5 yes Figure 3 Layout diagram of part B.

[0139] refer to Figure 5 , the display area DA of the display device 100 according to some embodiments may include the emission areas EA. In addition, the display area DA may further include a non-emission area provided in a space between the emission areas EA.

[0140] The light emitting pixel drivers EPD corresponding to the emission areas EA may be arranged side by side with each other in the first direction DR1 and the second direction DR2 in the display area DA. The light emitting pixel drivers EPD may be electrically connected to the light emitting elements LE of the element layer 130 in the emission area EA (see FIG. Figure 6 ).

[0141] The emission area EA may have a rhombus plane shape or a rectangular plane shape. However, this is only an example, and the plane shape of the emission area EA according to some embodiments is not limited to Figure 5For example, the emission area EA may also have a polygonal shape such as a quadrangle, a pentagon, or a hexagon, or may have a circular or elliptical plane shape including curved edges.

[0142] The emission area EA may include a first emission area EA1 that emits a first color light in a preset band, a second emission area EA2 that emits a second color light in a band lower than the first color band, and a third emission area EA3 that emits a third color light in a band lower than the second color band.

[0143] For example, the first color may be red in a wavelength range of about 600 nm to about 750 nm, the second color may be green in a wavelength range of about 480 nm to about 560 nm, and the third color may be blue in a wavelength range of about 370 nm to about 460 nm.

[0144] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0145] The second emission regions EA2 may be arranged side by side with each other in at least one of the first direction DR1 and the second direction DR2.

[0146] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in diagonal directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2 .

[0147] Pixels PX displaying corresponding brightness and color may be provided by the first, second, and third emission areas EA1, EA2, and EA3 that are adjacent to each other among the emission areas EA.

[0148] The pixel PX may be a basic unit that displays various colors including white at a preset brightness level.

[0149] Each of the pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Therefore, each of the pixels PX may display various colors by mixing the colors of light emitted from the first to third emission areas EA1, EA2, and EA3 adjacent to each other.

[0150] Figure 6 yes Figure 5 Equivalent circuit diagram of the light-emitting pixel driver EPD in .

[0151] refer to Figure 6, one of the light emitting elements LE of the element layer 130 may be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power source ELVSS.

[0152] For example, an anode of the light emitting element LE may be electrically connected to the light emitting pixel driver EPD, and a cathode of the light emitting element LE may be electrically connected to the second power source ELVSS having a lower voltage level than the first power source ELVDD.

[0153] The capacitor Cel connected in parallel to the light emitting element LE may represent a parasitic capacitance between the anode and the cathode.

[0154] The circuit layer 120 may further include a first power line VDL transmitting a voltage of a first power source ELVDD, a gate initialization voltage line VGIL transmitting a gate initialization voltage VGINT, an anode initialization voltage line VAIL transmitting an anode initialization voltage VAINT, and a bias voltage line VBL transmitting a bias voltage VBS.

[0155] The circuit layer 120 may further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0156] The light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 generating a driving current for driving the light emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1 , and at least one capacitor PC1 .

[0157] The first transistor T1 may be connected in series to the light emitting element LE between the first power source ELVDD and the second power source ELVSS.

[0158] The first transistor T1 may be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first electrode (eg, a source electrode) of the first transistor T1. The second node N2 is electrically connected to a second electrode (eg, a drain electrode) of the first transistor T1.

[0159] The first electrode (eg, source electrode) of the first transistor T1 can be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 can be electrically connected to the anode of the light emitting element LE through the sixth transistor T6.

[0160] The first pixel capacitor PC1 may be electrically connected between the first power line VDL and a third node N3. The third node N3 may be electrically connected to the gate electrode of the first transistor T1.

[0161] For example, the gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1 .

[0162] Accordingly, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged in the first power line VDL.

[0163] The second transistor T2 may be electrically connected between the data line DL and the first node N1 .

[0164] For example, the second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0165] For example, the first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0166] The fifth transistor T5 may be electrically connected between the first node N1 and the first power line VDL.

[0167] The sixth transistor T6 may be electrically connected between the second node N2 and a fourth node N4. The fourth node N4 may be electrically connected to the anode of the light emitting element LE.

[0168] For example, the fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0169] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode of the light emitting element LE.

[0170] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0171] If the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may be the voltage difference between the first power source ELVDD and the data signal Vdata.

[0172] If the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (ie, the gate-source voltage difference) is equal to or greater than the threshold voltage, the first transistor T1 may be turned on. Accordingly, a drain-source current corresponding to the data signal Vdata of the first transistor T1 may be generated.

[0173] If the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series to the light emitting element LE between the first power line VDL and the second power line. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0174] Therefore, the light emitting element LE may emit light with brightness corresponding to the data signal Vdata.

[0175] The third transistor T3 may be electrically connected between the second node N2 and the third node N3. For example, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of a gate control line GCL.

[0176] A voltage difference between the second node N2 and the third node N3 may be initialized by the turned-on third transistor T3 .

[0177] The fourth transistor T4 may be electrically connected between the gate initialization voltage line VGIL and the third node N3. For example, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL. The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0178] The potential of the third node N3 may be initialized by the turned-on fourth transistor T4.

[0179] The third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0180] The seventh transistor T7 can be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. For example, the seventh transistor T7 can be electrically connected between the anode of the light emitting element LE and the anode initialization voltage line VAIL. The seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL.

[0181] The potential of the fourth node N4 may be initialized by the turned-on seventh transistor T7.

[0182] The eighth transistor T8 may be electrically connected between the first node N1 and the bias voltage line VBL. For example, the eighth transistor T8 may be electrically connected between the first electrode of the first transistor T1 and the bias voltage line VBL. The eighth transistor T8 may be turned on by a bias control signal GB of a bias control line GBL.

[0183] The potential of the first node N1 may be initialized by the turned-on eighth transistor T8 .

[0184] The transistors T1 , T2 , T5 , T6 , T7 , and T8 may be provided as P-type MOSFETs.

[0185] For example, among the first to eighth transistors T1 to T8 included in the light emitting pixel driver EPD, the third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs, and the transistors T1, T2, T5, T6, T7, and T8 may be provided as P-type MOSFETs.

[0186] Therefore, according to some embodiments, the circuit layer 120 (see Figure 4 ) may include a first semiconductor layer and a second semiconductor layer.

[0187] The first semiconductor layer may include a channel portion, a first electrode portion, and a second electrode portion of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. In each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, the channel portion may overlap with the gate electrode. In addition, in each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, the first electrode portion and the second electrode portion may be connected to both ends of the channel portion. The first electrode portion may become the first electrode, and the second electrode portion may become the second electrode.

[0188] The second semiconductor layer may include a channel portion, a first electrode portion, and a second electrode portion of each of the third transistor T3 and the fourth transistor T4. In each of the third transistor T3 and the fourth transistor T4, the channel portion may be disposed between the first gate electrode and the second gate electrode that overlap each other, and may overlap the first gate electrode and the second gate electrode. In each of the third transistor T3 and the fourth transistor T4, the first electrode portion and the second electrode portion may be connected to both ends of the channel portion. The first electrode portion may become the first electrode, and the second electrode portion may become the second electrode.

[0189] Figure 7 yes Figure 3 Layout diagram of part C.

[0190] refer to Figure 7 , the light emitting pixel driver EPD of the circuit layer 120 of the display device 100 according to some embodiments may include a first light emitting pixel driver EPD1 and a second light emitting pixel driver EPD2 adjacent to each other in the second direction DR2 .

[0191] The second light emitting pixel driver EPD2 may be adjacent to one side of the first light emitting pixel driver EPD1 in the second direction DR2 .

[0192] According to some embodiments, the light emitting pixel driver EPD may further include a third light emitting pixel driver EPD3 adjacent to the first light emitting pixel driver EPD1 in the first direction DR1 and a fourth light emitting pixel driver EPD4 adjacent to the second light emitting pixel driver EPD2 in the first direction DR1.

[0193] According to some embodiments, the light emitting pixel driver EPD may further include a fifth light emitting pixel driver EPD5 adjacent to the other side of the first light emitting pixel driver EPD1 in the second direction DR2 .

[0194] In addition, the light emitting pixel driver EPD may further include a sixth light emitting pixel driver EPD6 adjacent to the fifth light emitting pixel driver EPD5 in the first direction DR1 .

[0195] Figure 7 The first to sixth light-emitting pixel drivers EPD1 to EPD6 are shown as being arranged in a matrix in a portion of the sub-display area SBDA of the display area DA. However, this is only an example, and the embodiment is not limited thereto. Figure 3 and Figure 7 For example, the first to sixth light-emitting pixel drivers EPD1 to EPD6 may also be arranged in a matrix in a portion of the main display area MDA.

[0196] Figure 8 According to some embodiments Figure 7 FIG. 1 is a plan view of the circuit layer 120 in section D. FIG. Figure 9 Graphic Figure 8 The first semiconductor layer, the first gate conductive layer and the bias voltage line VBL in the plan view. Figure 10 It is along Figure 8 A cross-sectional view taken along line FF'.

[0197] like Figure 6 As shown in FIG. 1 , the circuit layer 120 may include a bias voltage line VBL that transmits a bias voltage VBS to the light-emitting pixel driver EPD.

[0198] like Figure 8 、 Figure 9 and Figure 10 As shown in FIG. 1 , according to some embodiments, the first and second light-emitting pixel drivers EPD1 and EPD2 adjacent to each other in the second direction DR2 may be electrically connected to a bias voltage line VBL disposed adjacent to a boundary between the first and second light-emitting pixel drivers EPD1 and EPD2 .

[0199] One bias voltage line VBL may extend in the first direction DR1 and may be disposed adjacent to a boundary between the third and fourth light-emitting pixel drivers EPD3 and EPD4, which are adjacent to the first and second light-emitting pixel drivers EPD1 and EPD2 in the first direction DR1. The third and fourth light-emitting pixel drivers EPD3 and EPD4 may be electrically connected to the one bias voltage line VBL.

[0200] For example, the first to fourth light-emitting pixel drivers EPD1 to EPD4 adjacent to each other in the first direction DR1 and the second direction DR2 may share one bias voltage line VBL.

[0201] In this case, the number of bias voltage lines VBL arranged in the main area MA may be reduced by about half compared to a structure in which two light emitting pixel drivers EPD1 and EPD2 or EPD3 and EPD4 adjacent to each other in the second direction DR2 are connected to two bias voltage lines VBL.

[0202] For example, a space may be provided between two light-emitting pixel drivers EPD1 and EPD2 or EPD3 and EPD4 adjacent to each other in the second direction DR2. Therefore, a portion of the display area DA including contact points between the first to fourth light-emitting pixel drivers EPD1 to EPD4 adjacent to each other in the first and second directions DR1 to DR2 may be provided as a light-transmitting region TRA in which no conductive layer is provided.

[0203] Because the light-transmitting region TRA may provide a light path for the display device 100 , even if the optical device 18 disposed under the display device 100 overlaps the display area DA, the function of the optical device 18 may be performed by the light-transmitting region TRA.

[0204] Therefore, in the display area DA, the resolution of the sub-display area SBDA overlapping with the optical device 18 can be maintained to be the same as the resolution of the main display area MDA, thereby reducing or preventing the degradation of display quality due to the arrangement of the optical device 18.

[0205] like Figure 8 As shown in FIG. , according to some embodiments, the anode initialization voltage line VAIL may extend in the first direction DR1. One anode initialization voltage line VAIL may overlap the first and third light-emitting pixel drivers EPD1 and EPD3 that are adjacent to each other in the first direction DR1, and another anode initialization voltage line VAIL may overlap the second and fourth light-emitting pixel drivers EPD2 and EPD4 that are adjacent to each other in the first direction DR1.

[0206] The bias control line GBL may also extend in the first direction DR1. One bias control line GBL may overlap the first and third light-emitting pixel drivers EPD1 and EPD3 that are adjacent to each other in the first direction DR1. Another bias control line GBL may overlap the second and fourth light-emitting pixel drivers EPD2 and EPD4 that are adjacent to each other in the first direction DR1.

[0207] The anode initialization voltage line VAIL and the bias control line GBL may be disposed adjacent to the bias voltage line VBL in the second direction DR2 .

[0208] In each of the light emitting pixel drivers EPD, a channel portion CH7 of the seventh transistor T7 and a channel portion CH8 of the eighth transistor T8 may be disposed at an intersection of the bias control line GBL and the first semiconductor layer.

[0209] The seventh transistor T7 may be electrically connected to the anode initialization voltage line VAIL through the anode initialization voltage connection hole.

[0210] The eighth transistor T8 may be electrically connected to the bias voltage line VBL through the bias voltage connection hole VBCH.

[0211] The data lines DL and the first power lines VDL may extend in the second direction DR2 .

[0212] like Figure 10 As shown in FIG. 1 , a display device 100 according to some embodiments (see Figure 2 ) may include a first semiconductor layer (CH8, S8, and D8) disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer (G8 and Figure 14 G41), a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer ( Figure 14 G31 and VGIL of the gate conductive layer), a first interlayer insulating layer 124 covering the second gate conductive layer, and a second semiconductor layer ( Figure 14 CH3, S3, D3, CH4, S4 and D4), a third gate insulating layer 125 covering the second semiconductor layer, a third gate conductive layer (VBL, Figure 14 G32 and G42 of the gate conductive layer, a second interlayer insulating layer 126 covering the third gate conductive layer, and a first source-drain conductive layer (VAIL, Figure 14CNE1, CNE2 and CNE3, a first planarization layer 127 covering the first source-drain conductive layer, a second source-drain conductive layer (DL and CNE3) disposed on the first planarization layer 127, Figure 14 VDL) and a second planarization layer 128 covering the second source and drain conductive layer.

[0213] According to some embodiments, the circuit layer 120 may further include a buffer layer 121 covering the substrate 110. In this case, the first semiconductor layer may be provided on the buffer layer 121.

[0214] like Figure 9 and Figure 10 As illustrated in FIG, the seventh transistor T7 may include a channel portion CH7 provided as the first semiconductor layer, a first electrode portion S7 and a second electrode portion D7, and may include a gate electrode G7 provided as a portion of the bias control line GBL overlapping the channel portion CH7.

[0215] The eighth transistor T8 may include a channel portion CH8 provided as the first semiconductor layer, a first electrode portion S8 and a second electrode portion D8, and may include a gate electrode G8 provided as another portion of the bias control line GBL overlapping the channel portion CH8.

[0216] According to some embodiments, the first electrode portion S8 of the eighth transistor T8 of the first light emitting pixel driver EPD1 and the first electrode portion S8 of the eighth transistor T8 of the second light emitting pixel driver EPD2 may be connected to each other and may be connected through the bias voltage connection hole VBCH (see Figure 8 ) is electrically connected to a bias voltage line VBL.

[0217] like Figure 10 As illustrated in FIG, the first semiconductor layer on the buffer layer 121 may include a channel portion CH8, a first electrode portion S8, and a second electrode portion D8 of the eighth transistor T8.

[0218] refer to Figure 9 , the first semiconductor layer on the buffer layer 121 may further include a channel portion CH7 of the seventh transistor T7 , a first electrode portion S7 , and a second electrode portion D7 .

[0219] refer to Figure 6 , since the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be provided as P-type MOSFETs, like the seventh transistor T7 and the eighth transistor T8, the first semiconductor layer on the buffer layer 121 can further include a channel portion, a first electrode portion, and a second electrode portion of each of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6.

[0220] refer to Figure 10 , the first gate conductive layer on the first gate insulating layer 122 may include a gate electrode G8 of the eighth transistor T8.

[0221] refer to Figure 9 Since the gate electrode G7 of the seventh transistor T7 and the gate electrode G8 of the eighth transistor T8 are parts of the bias control line GBL, the first gate conductive layer on the first gate insulating layer 122 may include the bias control line GBL.

[0222] The third gate conductive layer on the third gate insulating layer 125 may include a bias voltage line VBL.

[0223] The first source-drain conductive layer on the second interlayer insulating layer 126 may include an anode initialization voltage line VAIL.

[0224] The second source-drain conductive layer on the first planarization layer 127 may include a data line DL.

[0225] like Figure 9 As illustrated in FIG. 2 , according to some embodiments, one bias voltage line VBL may include a first main extension portion MEX1 extending in a first direction DR1 and a bypass portion DET connected to the first main extension portion MEX1 and bypassing the light-transmitting region TRA.

[0226] The first main extension portion MEX1 may be disposed adjacent to a boundary between two light emitting pixel drivers EPD1 and EPD2 or EPD3 and EPD4 that are adjacent to each other in the second direction DR2 .

[0227] The bias voltage connection hole VBCH may overlap with the first main extension MEX1.

[0228] The light-transmitting area TRA may be a portion of the display area DA including contact points between the first to fourth light-emitting pixel drivers EPD1 to EPD4 adjacent to each other in the first and second directions DR1 and DR2 .

[0229] The bypass portion DET may be provided in a 'U' shape protruding from the first main extension portion MEX1 to one side in the second direction DR2 .

[0230] According to some embodiments, since the bias voltage line VBL includes not only the first main extension portion MEX1 but also the bypass portion DET as described above, a wider light transmission area TRA may be provided.

[0231] Figure 11 is a diagram illustrating a method according to some embodiments Figure 7 1. A plan view of the first semiconductor layer, the first gate conductive layer, the bias voltage line VBL and the first source-drain conductive layer in portion D of FIG.

[0232] Except that the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 adjacent to each other in the second direction DR2 share one anode initialization voltage line VAIL, Figure 11 The display device 100 of some embodiments shown in FIG. Figures 1 to 10 The display devices 100 of some embodiments illustrated in FIG. 1 are substantially the same. Therefore, any redundant description will be omitted below.

[0233] according to Figure 11 In some embodiments, the anode initialization voltage line VAIL may include a second main extension portion MEX2 disposed adjacent to the first main extension portion MEX1 of the bias voltage line VBL and extending in the first direction DR1, and a first sub-protrusion portion SPR1 protruding from the second main extension portion MEX2 and extending in the second direction DR2.

[0234] The second main extension portion MEX2 may overlap the first light emitting pixel driver EPD1 .

[0235] The first sub-protrusion portion SPR1 may cross the bias voltage line VBL.

[0236] An end portion of the first sub-protrusion portion SPR1 may overlap with the second light emitting pixel driver EPD2 .

[0237] Accordingly, the first electrode portion S7 of the seventh transistor T7 of the first light emitting pixel driver EPD1 may be electrically connected to the anode initialization voltage line VAIL through the first anode initialization connection hole VAICH1 overlapping the second main extension portion MEX2 .

[0238] In addition, the first electrode portion S7 of the seventh transistor T7 of the second light emitting pixel driver EPD2 may be electrically connected to the anode initialization voltage line VAIL through the second anode initialization connection hole VAICH2 overlapping the first sub-protrusion portion SPR1 .

[0239] In addition, because the second main extension portion MEX2 extends in the first direction DR1, the third light-emitting pixel driver EPD3 adjacent to the first light-emitting pixel driver EPD1 in the first direction DR1 can be electrically connected to the anode initialization voltage line VAIL through the first anode initialization connection hole VAICH1, and the fourth light-emitting pixel driver EPD4 adjacent to the second light-emitting pixel driver EPD2 in the first direction DR1 can be electrically connected to the anode initialization voltage line VAIL through the second anode initialization connection hole VAICH2.

[0240] Accordingly, according to some embodiments, since the first to fourth light-emitting pixel drivers EPD1 to EPD4 adjacent to each other in the first direction DR1 and the second direction DR2 share one anode initialization voltage line VAIL, the number of anode initialization voltage lines VAIL arranged in the main area MA can be reduced by approximately half.

[0241] Therefore, without changing the number of pixel drivers EPD, a wider light-transmitting area TRA including contact points between the first to fourth pixel drivers EPD1 to EPD4 can be ensured according to the reduction in the number of anode initialization voltage lines VAIL.

[0242] Figure 12 FIGURE 1 shows a diagram according to some embodiments Figure 7 The first semiconductor layer, the first gate conductive layer and the anode initialization voltage lines VAIL1 and VAIL2 in portion D of FIG.

[0243] Except that the circuit layer 120 may include first and second anode initialization voltage lines VAIL1 and VAIL2 alternately arranged in the second direction DR2 instead of the anode initialization voltage lines VAIL, Figure 12 The display device 100 of some embodiments shown in FIG. Figures 1 to 10 The display devices 100 of some embodiments illustrated in FIG. 1 are substantially the same. Therefore, any redundant description will be omitted below.

[0244] like Figure 5 As illustrated in , the emission area EA may include a first emission area EA1 , a second emission area EA2 , and a third emission area EA3 .

[0245] The first emission region EA1, the second emission region EA2, and the third emission region EA3 may be arranged side by side in the second direction DR2.

[0246] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in the first direction DR1.

[0247] The second emission region EA2 may be arranged side by side in the first direction DR1 and adjacent to the first and third emission regions EA1 and EA3 in a fourth direction DR4 or a fifth direction DR5 inclined to the first and second directions DR1 and DR2.

[0248] Since the second emission area EA2 has a width smaller than the first emission area EA1 and the third emission area EA3, if the light-emitting elements of the second emission area EA2 are initialized to substantially the same voltage level as the light-emitting elements of the first emission area EA1 and the third emission area EA3, it may be difficult to display the brightness corresponding to the data signal Vdata.

[0249] Therefore, according to Figure 12 In some embodiments, the circuit layer 120 may include a first anode initialization voltage line VAIL1 for transmitting a first anode initialization voltage for initializing the light-emitting elements of the first emission area EA1 and the third emission area EA3, and a second anode initialization voltage line VAIL2 for transmitting a second anode initialization voltage for initializing the light-emitting elements of the second emission area EA2.

[0250] A voltage level of the second anode initialization voltage may be different from a voltage level of the first anode initialization voltage.

[0251] For example, each of the first and second light-emitting pixel drivers EPD1 and EPD2 may be electrically connected to the light-emitting element LE of one of the first and third emission areas EA1 and EA3 .

[0252] Each of the third and fourth light-emitting pixel drivers EPD3 and EPD4 may be electrically connected to the light-emitting elements LE of the second emission area EA2 .

[0253] according to Figure 12 In some embodiments, the first anode initialization voltage line VAIL1 may extend in the first direction DR1 and may be disposed adjacent to one side of the bias voltage line VBL in the second direction DR2.

[0254] The second anode initialization voltage line VAIL2 may extend in the first direction DR1 and may be disposed adjacent to the other side of the bias voltage line VBL in the second direction DR2.

[0255] For example, the first anode initialization voltage line VAIL1 may overlap the first and third light-emitting pixel drivers EPD1 and EPD3 , and the second anode initialization voltage line VAIL2 may overlap the second and fourth light-emitting pixel drivers EPD2 and EPD4 .

[0256] according to Figure 12In some embodiments illustrated in FIG, the first electrode portion S7 of the seventh transistor T7 of the first light-emitting pixel driver EPD1 and the first electrode portion S7 of the seventh transistor T7 of the second light-emitting pixel driver EPD2 can be connected to each other and can be electrically connected to the first anode initialization voltage line VAIL1 through the third anode initialization connection hole VAICH3.

[0257] Likewise, the first electrode portion S7 of the seventh transistor T7 of the third light-emitting pixel driver EPD3 and the first electrode portion S7 of the seventh transistor T7 of the fourth light-emitting pixel driver EPD4 may be connected to each other and may be electrically connected to the second anode initialization voltage line VAIL2 through the fourth anode initialization connection hole VAICH4.

[0258] In this case, even if the circuit layer 120 includes first and second anode initialization voltage lines VAIL1 and VAIL2 instead of a single anode initialization voltage line VAIL, the number of lines transmitting the anode initialization voltage does not double, thereby reducing or preventing a reduction in the width of the light-transmitting area TRA.

[0259] Figure 13 According to some embodiments Figure 7 FIG. 1 is a plan view of the circuit layer 120 in section E. FIG. Figure 14 It is along Figure 13 A cross-sectional view taken along line G-G'.

[0260] like Figure 13 As shown in FIG. 1 , according to some embodiments, the first light-emitting pixel driver EPD1 and the fifth light-emitting pixel driver EPD5 adjacent to each other in the second direction DR2 may be electrically connected to a gate initialization voltage line VGIL disposed adjacent to a boundary between the first light-emitting pixel driver EPD1 and the fifth light-emitting pixel driver EPD5. The first light-emitting pixel driver EPD1 may be disposed on one side ( Figure 7 The lower side in the second direction DR2) is adjacent to the second light-emitting pixel driver EPD2, and can be Figure 7 The upper side in the middle) is adjacent to the fifth light-emitting pixel driver EPD5.

[0261] One gate initialization voltage line VGIL may extend in the first direction DR1 and may be disposed adjacent to a boundary between the third and sixth pixel drivers EPD3 and EPD6. The third and sixth pixel drivers EPD3 and EPD6 may be electrically connected to one gate initialization voltage line VGIL.

[0262] For example, the fifth light emitting pixel driver EPD5 , the first light emitting pixel driver EPD1 , the sixth light emitting pixel driver EPD6 , and the third light emitting pixel driver EPD3 adjacent to each other in the first direction DR1 and the second direction DR2 may share one gate initialization voltage line VGIL.

[0263] In this case, the number of gate initialization voltage lines VGIL arranged in the main area MA may be reduced by about half compared to a structure in which two light emitting pixel drivers EPD1 and EPD5 adjacent to each other in the second direction DR2 are connected to two gate initialization voltage lines VGIL.

[0264] Therefore, without changing the number of light-emitting pixel drivers EPD, a wider light-transmitting area TRA in the display area DA can be ensured according to the reduction in the number of gate initialization voltage lines VGIL.

[0265] like Figure 13 As illustrated in FIG. 2 , according to some embodiments, the scan write line GWL, the gate control line GCL, and the scan initialization line GIL may extend in the first direction DR1 and may be sequentially farther from the gate initialization voltage line VGIL.

[0266] like Figure 13 and Figure 14 As illustrated in FIG. 1 , in each light emitting pixel driver EPD, a channel portion CH3 of the third transistor T3 may be disposed at an intersection of the second semiconductor layer on the first interlayer insulating layer 124 and the gate control line GCL.

[0267] The third transistor T3 may include a channel portion CH3 provided as a second semiconductor layer on the first interlayer insulating layer 124, a first electrode portion S3 and a second electrode portion D3, a first gate electrode G31 which is part of the gate control line GCL and provided as a second gate conductive layer on the second gate insulating layer 123, and a second gate electrode G32 provided as a third gate conductive layer on the third gate insulating layer 125.

[0268] In each light emitting pixel driver EPD, a channel portion CH4 of the fourth transistor T4 may be disposed at an intersection of the second semiconductor layer on the first interlayer insulating layer 124 and the scan initialization line GIL.

[0269] The fourth transistor T4 may include a channel portion CH4 provided as a second semiconductor layer on the first interlayer insulating layer 124, a first electrode portion S4 and a second electrode portion D4, a first gate electrode G41 which is part of the scan initialization line GIL and provided as a first gate conductive layer on the first gate insulating layer 122, and a second gate electrode G42 provided as a third gate conductive layer on the third gate insulating layer 125.

[0270] like Figure 14 As shown in FIG. 1 , the second gate conductive layer on the second gate insulating layer 123 may include a gate initialization voltage line VGIL.

[0271] The first source-drain conductive layer on the second interlayer insulating layer 126 may include a first connection electrode CNE1 , a second connection electrode CNE2 , and a third connection electrode CNE3 .

[0272] like Figure 13 As shown, according to some embodiments, the first electrode portion S4 of the fourth transistor T4 of the first light-emitting pixel driver EPD1 and the first electrode portion S4 of the fourth transistor T4 of the fifth light-emitting pixel driver EPD5 can be connected to each other and can be electrically connected to a gate initialization voltage line VGIL.

[0273] For example, the gate initialization voltage line VGIL may be electrically connected to the first electrode portion S4 of the fourth transistor T4 through the first connection electrode CNE1 .

[0274] The first connection electrode CNE1 may be electrically connected to the gate initialization voltage line VGIL through the first gate initialization connection hole VGICH1 and may be electrically connected to the first electrode portion S4 of the fourth transistor T4 through the second gate initialization connection hole VGICH2 .

[0275] The second electrode portion D3 of the third transistor T3 and the second electrode portion D4 of the fourth transistor T4 may be connected to each other and may be electrically connected to the gate electrode of the first transistor T1 through the second connection electrode CNE2. For example, the second connection electrode CNE2 may be connected to the third node N3 (see Figure 6 ) corresponding to.

[0276] The second connection electrode CNE2 may be electrically connected to the second electrode portion D4 of the fourth transistor T4 through the gate connection hole GTCH.

[0277] The first electrode portion S3 of the third transistor T3 may be electrically connected to the second electrode of the first transistor T1 through the third connection electrode CNE3. For example, the third connection electrode CNE3 may be connected to the second node N2 (see Figure 6 ) corresponding to.

[0278] The third connection electrode CNE3 may be electrically connected to the first electrode portion S3 of the third transistor T3 through the drain connection hole DRCH.

[0279] Figure 15 FIGURE 1 shows a diagram according to some embodiments Figure 7 The first semiconductor layer, the first gate conductive layer and the bias voltage line VBL in portion D are formed.

[0280] Except that the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 adjacent to each other in the second direction DR2 share one bias control line GBL, Figure 15 The display device 100 of some embodiments shown in FIG. Figures 1 to 14 The display devices 100 of some embodiments illustrated in FIG. 1 are substantially the same. Therefore, redundant descriptions will be omitted below.

[0281] As reference Figure 10 As described above, the first gate conductive layer on the first gate insulating layer 122 may include a bias control line GBL for transmitting the bias control signal GB to the light-emitting pixel driver EPD.

[0282] according to Figure 15 In some embodiments, the bias control line GBL may include a third main extension portion MEX3 disposed adjacent to the first main extension portion MEX1 of the bias voltage line VBL and extending in the first direction DR1, and a second sub-protrusion portion SPR2 protruding from the third main extension portion MEX3 to extend in the second direction DR2 and crossing the bias voltage line VBL.

[0283] The third main extension portion MEX3 may overlap the first light emitting pixel driver EPD1 .

[0284] An end portion of the second sub-protrusion portion SPR2 may overlap with the second light emitting pixel driver EPD2 .

[0285] The second sub-protrusion portion SPR2 overlapping the second light emitting pixel driver EPD2 and the second sub-protrusion portion SPR2 overlapping the fourth light emitting pixel driver EPD4 may extend toward each other in the first direction DR1 and may be connected to each other.

[0286] For example, the gate electrode G7 of the seventh transistor T7 of the first light-emitting pixel driver EPD1, the gate electrode G8 of the eighth transistor T8 of the first light-emitting pixel driver EPD1, the gate electrode G7 of the seventh transistor T7 of the third light-emitting pixel driver EPD3, and the gate electrode G8 of the eighth transistor T8 of the third light-emitting pixel driver EPD3 can be provided as part of the third main extension portion MEX3 and can be connected to each other.

[0287] The gate electrode G7 of the seventh transistor T7 of the second light-emitting pixel driver EPD2, the gate electrode G8 of the eighth transistor T8 of the second light-emitting pixel driver EPD2, the gate electrode G7 of the seventh transistor T7 of the fourth light-emitting pixel driver EPD4, and the gate electrode G8 of the eighth transistor T8 of the fourth light-emitting pixel driver EPD4 may be provided as part of an extension of the second sub-protrusion SPR2 in the first direction DR1 and may be connected to each other.

[0288] In this case, since the first and second light emitting pixel drivers EPD1 and EPD2 adjacent to each other in the second direction DR2 share one bias control line GBL, the number of bias control lines GBL arranged in the main area MA may be reduced by about half.

[0289] Therefore, without changing the number of light-emitting pixel drivers EPD, a wider light-transmitting area TRA in the display area DA can be ensured according to the reduction in the number of bias control lines GBL.

[0290] Figure 16 is a diagram illustrating a method according to some embodiments Figure 7 FIG. 1 is a plan view of the first semiconductor layer, the first gate conductive layer, and the third gate conductive layer in portion D′ of FIG.

[0291] Except that the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 adjacent to each other in the second direction DR2 share one emission control line ECL, Figure 16 The display device 100 of some embodiments shown in FIG. Figures 1 to 15 The display devices 100 of some embodiments illustrated in FIG. 1 are substantially the same. Therefore, redundant descriptions will be omitted below.

[0292] refer to Figure 16 and Figure 12 , the gate electrode G5 of the fifth transistor T5 and the gate electrode G6 of the sixth transistor T6 may be provided in the same layer as the bias control line GBL.

[0293] For example, the first gate conductive layer on the first gate insulating layer 122 may include a bias control line GBL, a gate electrode G5 of the fifth transistor T5 , and a gate electrode G6 of the sixth transistor T6 .

[0294] The emission control line ECL, which transmits the emission control signal EC to the light-emitting pixel driver EPD, may be disposed in the same layer as the bias voltage line VBL.

[0295] For example, the third gate conductive layer on the third gate insulating layer 125 may include a bias voltage line VBL and an emission control line ECL.

[0296] according to Figure 16 In some embodiments, the third gate conductive layer may include a bias voltage line VBL, an emission control line ECL arranged adjacent to the bias control line GBL, extending in the first direction DR1 and transmitting the emission control signal EC to the light-emitting pixel driver EPD, and an emission control auxiliary line ECAL extending in the first direction DR1 and spaced apart from the emission control line ECL in the second direction DR2.

[0297] The emission control auxiliary line ECAL may be electrically connected to the emission control line ECL through an emission control link line ECCL extending in the second direction DR2 .

[0298] The emission control connection line ECCL may cross the bias control line GBL and the bias voltage line VBL. Accordingly, the emission control connection line ECCL may be disposed in a gate conductive layer different from the bias control line GBL and the bias voltage line VBL among the first, second, and third gate conductive layers.

[0299] For example, the bias control line GBL may be provided in the first gate conductive layer, the bias voltage line VBL may be provided in the third gate conductive layer, and the emission control connection line ECCL may be provided in the second gate conductive layer.

[0300] For example, the second gate conductive layer on the second gate insulating layer 123 may include the emission control link line ECCL.

[0301] However, this is merely an example, and as long as the bias control line GBL, the bias voltage line VBL, and the emission control link line ECCL are provided in different gate conductive layers, the arrangement structure of the lines may be changed as needed.

[0302] The emission control line ECL may overlap the first light emitting pixel driver EPD1 .

[0303] The emission control auxiliary line ECAL may overlap with the second light emitting pixel driver EPD2.

[0304] For example, the gate electrode G5 of the fifth transistor T5 of the first light-emitting pixel driver EPD1 and the gate electrode G6 of the sixth transistor T6 of the first light-emitting pixel driver EPD1 may overlap with the emission control line ECL. The gate electrode G5 of the fifth transistor T5 of the first light-emitting pixel driver EPD1 and the gate electrode G6 of the sixth transistor T6 of the first light-emitting pixel driver EPD1 may be electrically connected to the emission control line ECL through connection holes, respectively.

[0305] In addition, the gate electrode G5 of the fifth transistor T5 of the second light-emitting pixel driver EPD2 and the gate electrode G6 of the sixth transistor T6 of the second light-emitting pixel driver EPD2 may overlap with the emission control auxiliary line ECAL. The gate electrode G5 of the fifth transistor T5 of the second light-emitting pixel driver EPD2 and the gate electrode G6 of the sixth transistor T6 of the second light-emitting pixel driver EPD2 may be electrically connected to the emission control auxiliary line ECAL through connection holes, respectively, and may be electrically connected to the emission control line ECL through the emission control auxiliary line ECAL and the emission control connection line ECCL.

[0306] In this case, since the first and second light emitting pixel drivers EPD1 and EPD2 adjacent to each other in the second direction DR2 share one emission control line ECL, the number of emission control lines ECL arranged in the main area MA may be reduced by about half.

[0307] Therefore, without changing the number of light-emitting pixel drivers EPD, a wider light-transmitting area TRA in the display area DA can be ensured according to the reduction in the number of emission control lines ECL.

[0308] Figure 17 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first gate conductive layer, the second gate conductive layer, the second semiconductor layer and the third gate conductive layer in part E of FIG.

[0309] Except that the first light emitting pixel driver EPD1 and the fifth light emitting pixel driver EPD5 adjacent to each other in the second direction DR2 share one scan initialization line GIL, Figure 17 The display device 100 of some embodiments shown in FIG. Figures 1 to 16 The display devices 100 of some embodiments illustrated in FIG. 1 are substantially the same. Therefore, redundant descriptions will be omitted below.

[0310] refer to Figure 17 and Figure 14 The first gate conductive layer on the first gate insulating layer 122 may include a scan initialization line GIL that transmits a scan initialization signal GI to the light-emitting pixel driver EPD.

[0311] The first gate conductive layer may further include a scanning write line GWL transmitting the scanning write signal GW to the light emitting pixel driver EPD.

[0312] The second gate conductive layer on the second gate insulating layer 123 may include a gate initialization voltage line VGIL and a gate control line GCL.

[0313] Each of the scan initialization line GIL, the scan write line GWL, the gate initialization voltage line VGIL, and the gate control line GCL may extend in the first direction DR1.

[0314] The third gate conductive layer on the third gate insulating layer 125 may include a second gate electrode G32 of the third transistor T3 and a second gate electrode G42 of the fourth transistor T4 .

[0315] according to Figure 17In some embodiments, the scan initialization line GIL may include a fourth main extension portion MEX4 disposed adjacent to the gate initialization voltage line VGIL and extending in the first direction DR1, and a third sub-protrusion portion SPR3 protruding from the fourth main extension portion MEX4 to extend in the second direction DR2 and crossing the gate initialization voltage line VGIL.

[0316] The fourth main extension portion MEX4 may overlap the fifth light emitting pixel driver EPD5 .

[0317] An end portion of the third sub-protrusion portion SPR3 may overlap with the first light emitting pixel driver EPD1 .

[0318] For example, the first gate electrode G41 of the fourth transistor T4 of the fifth light-emitting pixel driver EPD5 may be provided as a portion of the fourth main extension MEX4 , and the second gate electrode G42 of the fourth transistor T4 may overlap with the fourth main extension MEX4 .

[0319] The first gate electrode G41 of the fourth transistor T4 of the first light emitting pixel driver EPD1 may be provided as a portion of the third sub-protrusion portion SPR3 , and the second gate electrode G42 of the fourth transistor T4 of the first light emitting pixel driver EPD1 may overlap the third sub-protrusion portion SPR3 .

[0320] In this case, since the first and fifth light emitting pixel drivers EPD1 and EPD5 adjacent to each other in the second direction DR2 share one scan initialization line GIL, the number of scan initialization lines GIL arranged in the main area MA may be reduced by about half.

[0321] Therefore, without changing the number of light-emitting pixel drivers EPD, a wider light-transmitting area TRA in the display area DA can be ensured according to the reduction in the number of scanning initialization lines GIL.

[0322] Figure 18 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first gate conductive layer, the second gate conductive layer, the second semiconductor layer and the third gate conductive layer in part E of FIG.

[0323] Except that the first light emitting pixel driver EPD1 and the fifth light emitting pixel driver EPD5 adjacent to each other in the second direction DR2 share one gate control line GCL, Figure 18 The display device 100 of some embodiments shown in FIG. Figures 1 to 17 The display devices 100 of some embodiments illustrated in FIG. 1 are substantially the same. Therefore, redundant descriptions will be omitted below.

[0324] refer to Figure 18 and Figure 14 The first gate conductive layer on the first gate insulating layer 122 may include a scan initialization line GIL transmitting a scan initialization signal GI to the light-emitting pixel driver EPD and a scan write line GWL transmitting a scan write signal GW to the light-emitting pixel driver EPD.

[0325] according to Figure 18 In some embodiments, the second gate conductive layer on the second gate insulating layer 123 may include a gate initialization voltage line VGIL, a gate control line GCL disposed adjacent to the gate initialization voltage line VGIL, extending in the first direction DR1 and transmitting a gate control signal GC to the light-emitting pixel driver EPD, and a gate control auxiliary line GCAL extending in the first direction DR1 and spaced apart from the gate control line GCL in the second direction DR2.

[0326] The gate control auxiliary line GCAL may be electrically connected to the gate control line GCL through a gate control link line GCCL extending in the second direction DR2 .

[0327] The gate control connection line GCCL may cross the scan initialization line GIL and the gate initialization voltage line VGIL. Accordingly, the gate control connection line GCCL may be disposed in a gate conductive layer different from the scan initialization line GIL and the gate initialization voltage line VGIL among the first gate conductive layer, the second gate conductive layer, and the third gate conductive layer.

[0328] For example, the scan initialization line GIL may be disposed in the first gate conductive layer, the gate initialization voltage line VGIL may be disposed in the second gate conductive layer, and the gate control connection line GCCL may be disposed in the third gate conductive layer.

[0329] For example, the third gate conductive layer on the third gate insulating layer 125 may include a gate control connection line GCCL.

[0330] However, this is merely an example, and as long as the scan initialization line GIL, the gate initialization voltage line VGIL, and the gate control link line GCCL are provided in different gate conductive layers, the arrangement structure of the lines may be changed as needed.

[0331] In addition, the third gate conductive layer on the third gate insulating layer 125 may include a second gate electrode G32 of the third transistor T3 and a second gate electrode G42 of the fourth transistor T4 .

[0332] The gate control line GCL may overlap the fifth light emitting pixel driver EPD5 .

[0333] The gate control auxiliary line GCAL may overlap the first light emitting pixel driver EPD1 .

[0334] For example, the first gate electrode G31 of the third transistor T3 of the fifth light-emitting pixel driver EPD5 may be provided as part of the gate control line GCL, and the second gate electrode G32 of the third transistor T3 of the fifth light-emitting pixel driver EPD5 may overlap the gate control line GCL.

[0335] The first gate electrode G31 of the third transistor T3 of the first light emitting pixel driver EPD1 may be provided as a portion of the gate control auxiliary line GCAL, and the second gate electrode G32 of the third transistor T3 of the first light emitting pixel driver EPD1 may overlap the gate control auxiliary line GCAL.

[0336] In this case, since the first and fifth light emitting pixel drivers EPD1 and EPD5 adjacent to each other in the second direction DR2 share one gate control line GCL, the number of gate control lines GCL arranged in the main area MA may be reduced by about half.

[0337] Therefore, without changing the number of light-emitting pixel drivers EPD, a wider light-transmitting area TRA in the display area DA can be ensured according to the reduction in the number of gate control lines GCL.

[0338] Figure 19 is a diagram illustrating a method according to some embodiments Figure 7 A plan view of the first gate conductive layer, the second gate conductive layer, the second semiconductor layer and the third gate conductive layer in part E of FIG.

[0339] according to Figure 19 In some embodiments illustrated in FIG, the first light-emitting pixel driver EPD1 and the fifth light-emitting pixel driver EPD5 adjacent to each other in the second direction DR2 may share one scan initialization line GIL and one gate control line GCL.

[0340] For example, Figure 19 Some examples are Figure 17 Some embodiments and Figure 18 Therefore, redundant descriptions will be omitted below.

[0341] In this case, without changing the number of light emitting pixel drivers EPD, a wider light transmission area TRA in the display area DA can be ensured according to the reduction in the number of scanning initialization lines GIL and the number of gate control lines GCL.

[0342] Figure 20 is a plan view illustrating first and second semiconductor layers of each of the first, second, third, and fourth light-emitting pixel drivers EPD1, EPD2, EPD3, and EPD4 according to some embodiments.

[0343] like Figure 20 As shown in FIG, according to some embodiments, the first semiconductor layer SEL1 on the substrate 110 may include a channel portion CH1, CH2, CH5, CH6, CH7 and / or CH8 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8, and a first electrode portion and a second electrode portion connected to both ends of the channel portion CH1, CH2, CH5, CH6, CH7 and / or CH8.

[0344] The second semiconductor layer SEL2 may include a channel portion CH3 or CH4 of each of the third transistor T3 and the fourth transistor T4 and first and second electrode portions connected to both ends of the channel portion CH3 or CH4 .

[0345] refer to Figure 20 In the circuit layer 120 of the display device 100 according to some embodiments, the first semiconductor layer SEL11 and the second semiconductor layer SEL12 of the first light-emitting pixel driver EPD1 may be symmetrical with the first semiconductor layer SEL31 and the second semiconductor layer SEL32 of the third light-emitting pixel driver EPD3 relative to the boundary between the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3.

[0346] In addition, according to some embodiments, the first semiconductor layer SEL11 and the second semiconductor layer SEL12 of the first light-emitting pixel driver EPD1 can be symmetrical with the first semiconductor layer SEL21 and the second semiconductor layer SEL22 of the second light-emitting pixel driver EPD2 relative to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0347] In this case, a structure can be easily realized in which at least one of the bias voltage line VBL, the anode initialization voltage line VAIL, the bias control line GBL, the emission control line ECL, the gate initialization voltage line VGIL, the scan initialization line GIL, and the gate control line GCL, which are adjacent to the boundary between the light-emitting pixel drivers EPD adjacent to each other in the second direction DR2 and extend in the first direction DR1, is shared by the light-emitting pixel drivers EPD adjacent to each other in the second direction DR2.

[0348] Figure 21 is a plan view illustrating first and second semiconductor layers of each of the first, second, third, and fourth light-emitting pixel drivers EPD1, EPD2, EPD3, and EPD4 according to some embodiments.

[0349] Except that the channel portion CH1 of the first transistor T1 of the light emitting pixel driver EPD is identical, Figure 21 The display device 100 of some embodiments shown in FIG. Figure 20 The display devices 100 of some embodiments are substantially the same. Therefore, redundant descriptions will be omitted below.

[0350] according to Figure 21 In some embodiments, the first semiconductor layer SEL11 and the second semiconductor layer SEL12 of the first light-emitting pixel driver EPD1 that do not include the channel portion CH1 of the first transistor T1 may be symmetrical with the first semiconductor layer SEL21 and the second semiconductor layer SEL22 of the second light-emitting pixel driver EPD2 that do not include the channel portion CH1 of the first transistor T1 relative to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0351] In addition, the channel portion CH1 of the first transistor T1 of the first light-emitting pixel driver EPD1 may be congruent with the channel portion CH1 of the first transistor T1 of the second light-emitting pixel driver EPD2 .

[0352] For example, in all the light emitting pixel drivers EPD, the channel portion CH1 of the first transistor T1 may be disposed toward one side in the second direction DR2 ( Figure 21 However, Figure 21 The illustration in is only an example, and the channel portion CH1 of the first transistor T1 may also be modified into other shapes.

[0353] In this case, during the process of crystallizing the first semiconductor layers SEL11, SEL21, SEL31, and SEL41 using a laser beam, the channel portion CH1 of the first transistor T1 of the light-emitting pixel driver EPD can be similarly irradiated with the laser beam. Therefore, the uniformity of the semiconductor characteristics of the channel portion CH1 of the first transistor T1 can be improved. This, in turn, can reduce color spot defects, thereby improving the display quality of the display device 100.

[0354] A display device according to some embodiments may include a substrate, a circuit layer, and an element layer. The substrate may include a display area in which emission regions are arranged. The element layer may include light-emitting elements respectively arranged in the emission regions.

[0355] The circuit layer may include light emitting pixel drivers respectively electrically connected to the light emitting elements of the element layer and arranged side by side with each other, data lines transmitting data signals to the light emitting pixel drivers, and bias voltage lines extending in a first direction crossing the data lines.

[0356] The light emitting pixel driver includes a first light emitting pixel driver and a second light emitting pixel driver adjacent to each other in a second direction crossing the first direction.

[0357] The first light emitting pixel driver and the second light emitting pixel driver may be electrically connected to one bias voltage line disposed adjacent to a boundary between the first light emitting pixel driver and the second light emitting pixel driver.

[0358] For example, according to some embodiments, the first and second light-emitting pixel drivers may not be electrically connected to two bias voltage lines, but may share a single bias voltage line. Accordingly, because one bias voltage line is removed, the area between the first and second light-emitting pixel drivers can be provided as a light-transmitting area in which no conductive layer is provided.

[0359] Therefore, even if the number of pixel drivers is not reduced, a light-transmitting area for providing a light path for the optical sensor can be ensured. Accordingly, even if a portion of the display area overlaps with the optical sensor, degradation of display quality can be reduced or prevented.

[0360] Additionally, according to some embodiments, the light emitting pixel driver may further include a third light emitting pixel driver and a fourth light emitting pixel driver respectively adjacent to the first light emitting pixel driver and the second light emitting pixel driver in the first direction.

[0361] A bias voltage line arranged adjacent to a boundary between a first light-emitting pixel driver and a second light-emitting pixel driver may include a first main extension portion extending in a first direction and a bypass portion connected to the first main extension portion and bypassing a light-transmitting area including contact points at which the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver contact each other.

[0362] For example, according to some embodiments, because one bias voltage line does not extend in a straight line in the first direction but includes a bypass portion that bypasses the light-transmitting area, a wider light-transmitting area can be ensured.

[0363] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

[0364] The foregoing is an illustration of some embodiments of the present disclosure and should not be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made in some embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the claims and their equivalents.

Claims

1. A display device comprising: a substrate including a display region including an emission region; a circuit layer on the substrate; as well as an element layer on the circuit layer and including light emitting elements respectively in the emission regions, Wherein, the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements, respectively, and arranged side by side in a first direction and in a second direction intersecting the first direction, the light-emitting pixel drivers comprising: a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the second direction; and a third light-emitting pixel driver and a fourth light-emitting pixel driver adjacent to the first light-emitting pixel driver and the second light-emitting pixel driver, respectively, in the first direction; and a first direction line extending in the first direction and adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver and adjacent to a boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver, Wherein, the first direction line includes: a first main extension extending in the first direction; and a bypass portion connected to the first main extension portion and bypassing a light-transmitting area of the display area including contact points at which the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver contact one another, in: The first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver are electrically connected to the one first direction line; and The first direction line is a bias voltage line among a plurality of bias voltage lines configured to transmit a bias voltage to the light-emitting pixel driver.

2. The display device according to claim 1, wherein The circuit layer further includes an anode initialization voltage line configured to transmit an anode initialization voltage to the light-emitting pixel driver. Wherein, the anode initialization voltage line includes: a second main extension portion adjacent to the first main extension portion and extending in the first direction; and a first sub-protrusion portion protruding from the second main extension portion to extend in the second direction and crossing the one first direction line, and in: The second main extension portion overlaps the first light-emitting pixel driver; and An end portion of the first sub-protrusion portion overlaps with the second light-emitting pixel driver.

3. The display device according to claim 1, wherein: The circuit layer further includes a gate initialization voltage line configured to transmit a gate initialization voltage to the light-emitting pixel driver; The light-emitting pixel driver further includes a fifth light-emitting pixel driver adjacent to the first light-emitting pixel driver in the second direction; The first light-emitting pixel driver is located between the second light-emitting pixel driver and the fifth light-emitting pixel driver in the second direction; and The first light emitting pixel driver and the fifth light emitting pixel driver are electrically connected to the gate initialization voltage line disposed adjacent to a boundary between the first light emitting pixel driver and the fifth light emitting pixel driver.

4. The display device according to claim 3, wherein The circuit layer further includes a scan initialization line configured to transmit a scan initialization signal to the light-emitting pixel driver. Wherein, the scan initialization line includes: a fourth main extension portion adjacent to the gate initializing voltage line and extending in the first direction; and a third sub-protrusion portion protruding from the fourth main extension portion and extending in the second direction, and in: The fourth main extension portion overlaps the fifth light-emitting pixel driver; and An end portion of the third sub-protrusion portion overlaps with the first light-emitting pixel driver.

5. The display device according to claim 3, wherein The circuit layer further comprises: a gate control line extending in the first direction, overlapping the fifth light-emitting pixel driver, and configured to transmit a gate control signal to the light-emitting pixel driver; a gate control auxiliary line spaced apart from the gate control line in the second direction, extending in the first direction and overlapping the first light-emitting pixel driver; and A gate control connection line extends in the second direction, is electrically connected to the gate control line and the gate control auxiliary line, and crosses the gate initialization voltage line.

6. The display device according to claim 1, in, The circuit layer includes: a first semiconductor layer on the substrate; a first gate insulating layer, covering the first semiconductor layer; a first gate conductive layer, on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer, on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer, covering the second semiconductor layer; a third gate conductive layer, on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer, on the second interlayer insulating layer; a first planarization layer, covering the first source-drain conductive layer; a second source-drain conductive layer on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer; Wherein, each of the light-emitting pixel drivers includes: a first transistor electrically connected between the first node and the second node; a pixel capacitor electrically connected between a first power line and a third node, wherein the first power line is configured to transmit a voltage of a first power source; a second transistor electrically connected between a data line and the first node, the data line being configured to transmit a data signal; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a gate initialization voltage line and the third node, the gate initialization voltage line being configured to transmit a gate initialization voltage; a fifth transistor electrically connected between the first power line and the first node; a sixth transistor electrically connected between the second node and a fourth node; a seventh transistor electrically connected between an anode initialization voltage line and the fourth node, the anode initialization voltage line being configured to transmit an anode initialization voltage; and an eighth transistor electrically connected between the one bias voltage line among the plurality of bias voltage lines and the first node, in: The first node is electrically connected to the first electrode of the first transistor; the second node being electrically connected to the second electrode of the first transistor; The third node is electrically connected to the gate electrode of the first transistor; and The fourth node is electrically connected to one of the light emitting elements, Wherein, each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor comprises: gate electrode; a channel portion overlapping the gate electrode; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion, Wherein, each of the third transistor and the fourth transistor includes: a first gate electrode and a second gate electrode at least partially overlapping each other; a channel portion between the first gate electrode and the second gate electrode; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion, and in: the channel portion, the first electrode portion, and the second electrode portion of each of the first, second, fifth, sixth, seventh, and eighth transistors are portions of the first semiconductor layer; and The channel portion, the first electrode portion, and the second electrode portion of each of the third transistor and the fourth transistor are portions of the second semiconductor layer.

7. The display device according to claim 6, wherein: The first and second semiconductor layers of the first light-emitting pixel driver are symmetrical to the first and second semiconductor layers of the third light-emitting pixel driver with respect to a boundary between the first and third light-emitting pixel drivers.

8. The display device according to claim 7, wherein: The first semiconductor layer of the first light-emitting pixel driver is symmetrical to the first semiconductor layer of the second light-emitting pixel driver with respect to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

9. The display device according to claim 7, wherein: The channel portion of the first transistor of the first light-emitting pixel driver is congruent with the channel portion of the first transistor of the second light-emitting pixel driver.

10. A display device comprising: a substrate including a display region including an emission region; a circuit layer on the substrate; as well as an element layer on the circuit layer and including light-emitting elements respectively in the emission regions, wherein the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements, respectively, and arranged side by side with each other in a first direction and a second direction intersecting the first direction; Wherein, the circuit layer includes: a first semiconductor layer on the substrate; a first gate insulating layer, covering the first semiconductor layer; a first gate conductive layer, on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer, on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer, covering the second semiconductor layer; a third gate conductive layer, on the third gate insulating layer; and a second interlayer insulating layer covering the third gate conductive layer; Wherein, each of the light-emitting pixel drivers includes: a first transistor electrically connected between the first node and the second node; a pixel capacitor electrically connected between a first power line and a third node, wherein the first power line is configured to transmit a voltage of a first power source; a second transistor electrically connected between a data line and the first node, the data line being configured to transmit a data signal; a third transistor electrically connected between the second node and the third node; and a fourth transistor electrically connected between a gate initialization voltage line and the third node, wherein the gate initialization voltage line is configured to transmit a gate initialization voltage, in: The first node is electrically connected to the first electrode of the first transistor; The second node is electrically connected to the second electrode of the first transistor; and The third node is electrically connected to the gate electrode of the first transistor, Wherein, each of the first transistor and the second transistor comprises: gate electrode; a channel portion overlapping the gate electrode; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion, Wherein, each of the third transistor and the fourth transistor includes: a first gate electrode and a second gate electrode at least partially overlapping each other; a channel portion between the first gate electrode and the second gate electrode; a first electrode portion connected to one side of the channel portion; and a second electrode portion connected to the other side of the channel portion, in: the channel portion, the first electrode portion, and the second electrode portion of each of the first transistor and the second transistor are portions of the first semiconductor layer; and the channel portion, the first electrode portion, and the second electrode portion of each of the third transistor and the fourth transistor are portions of the second semiconductor layer, The light-emitting pixel driver includes a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the second direction, and The channel portion of the first transistor of the first light-emitting pixel driver is congruent with the channel portion of the first transistor of the second light-emitting pixel driver.

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