Display panel and display device

Abstract

The utility model discloses a display panel and a display device. The display panel comprises first light-emitting elements, second light-emitting elements and third light-emitting elements, the first light-emitting elements, the second light-emitting elements and the third light-emitting elements are different in light emitting color, the first unit column comprises the first light-emitting elements and the second light-emitting elements which are alternately arranged in the first direction, and the second unit column comprises a plurality of third light-emitting elements which are arranged in the first direction. The first unit columns and the second unit columns are alternately arranged in the second direction; the first circuit column comprises a plurality of first pixel circuits arranged in the first direction, the second circuit column comprises a plurality of second pixel circuits arranged in the first direction, the third circuit column comprises a plurality of third pixel circuits arranged in the first direction, the first pixel circuits are electrically connected with the first data lines and the first light-emitting elements, and the second pixel circuits are electrically connected with the second data lines and the second light-emitting elements. The second pixel circuit is electrically connected with the second data line and the second light-emitting element, and the third pixel circuit is electrically connected with the third data line and the third light-emitting element. The embodiment of the utility model can reduce the power consumption of the driving chip.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more common, and users have more and more requirements for the performance of display panels. For example, users hope that the power consumption of display products can be lower and lower. Therefore, how to reduce power consumption is an important problem that troubles those skilled in the art. Utility Model Content

[0003] Embodiments of the present application provide a display panel and a display device that can reduce power consumption.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: light-emitting elements, comprising a first light-emitting element, a second light-emitting element, and a third light-emitting element, the first light-emitting element, the second light-emitting element, and the third light-emitting element having different light-emitting colors, a first unit column comprising a first light-emitting element and a second light-emitting element alternately arranged in a first direction, a second unit column comprising a plurality of third light-emitting elements arranged in the first direction, the first unit column and the second unit column being alternately arranged in a second direction, and the first direction and the second direction intersecting; a first circuit column, a second circuit column, and a third circuit column, the first circuit column comprising a plurality of first pixel circuits arranged in the first direction, the second circuit column comprising a plurality of second pixel circuits arranged in the first direction, the third circuit column comprising a plurality of third pixel circuits arranged in the first direction, the first pixel circuit being electrically connected to a first data line and a first light-emitting element, the second pixel circuit being electrically connected to a second data line and a second light-emitting element, and the third pixel circuit being electrically connected to a third data line and a third light-emitting element.

[0005] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel as described in the embodiment of the first aspect.

[0006] According to the display panel and display device provided in the embodiments of the present application, one data line is used to provide the data signal required by the light-emitting elements of the same light-emitting color. In this way, when displaying an image, especially displaying a pure color picture, the data signal on the data line does not need to jump, thereby reducing the power consumption of the driver chip connected to the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0008] Figure 1A schematic diagram showing a structure of a display panel in a comparative example is shown;

[0009] Figure 2 Show Figure 1 Schematic diagram of signal timing on the data line;

[0010] Figure 3 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown;

[0011] Figure 4 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0012] Figure 5 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0013] Figure 6 Show Figure 3 A schematic diagram of a layout structure of a corresponding display panel;

[0014] Figure 7 Show Figure 6 Schematic diagram of the layout structure of the middle anode, the second metal layer, and the third metal layer;

[0015] Figure 8 Show Figure 6 Schematic diagram of the layout structure of the middle anode;

[0016] Figure 9 Show Figure 6 Schematic diagram of the layout structure of the third metal layer;

[0017] Figure 10 Show Figure 6 Schematic diagram of the layout structure of the second metal layer;

[0018] Figure 11 Show Figure 6 Schematic diagram of the layout structure of the first metal layer;

[0019] Figure 12 Show Figure 6 Schematic diagram of the corresponding layout structure of the second gate layer;

[0020] Figure 13 Show Figure 6 A schematic diagram of the corresponding layout structure of the second semiconductor layer;

[0021] Figure 14 Show Figure 6 Schematic diagram of the layout structure of the corresponding capacitor metal layer;

[0022] Figure 15 Show Figure 6 Schematic diagram of the corresponding layout structure of the first gate layer;

[0023] Figure 16 Show Figure 6 A schematic diagram of the corresponding layout structure of the first semiconductor layer;

[0024] Figure 17 Show Figure 6 Schematic diagram of the layout structure of the corresponding auxiliary metal layer;

[0025] Figure 18 A schematic diagram showing a cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0026] Figure 19 A schematic diagram showing a structure of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0027] Figure 20 Show Figure 3 A schematic diagram of another layout structure of the corresponding display panel;

[0028] Figure 21 Show Figure 20 Schematic diagram of the layout structure of the middle anode, the second metal layer, and the third metal layer;

[0029] Figure 22 Show Figure 20 Schematic diagram of the layout structure of the middle anode;

[0030] Figure 23 Show Figure 20 Schematic diagram of the layout structure of the third metal layer;

[0031] Figure 24 Show Figure 20 Schematic diagram of the layout structure of the second metal layer;

[0032] Figure 25 Show Figure 20 A schematic diagram of the corresponding layout structure of the first metal layer;

[0033] Figure 26 Show Figure 20 Schematic diagram of the layout structure of the corresponding capacitor metal layer;

[0034] Figure 27 Show Figure 20 Schematic diagram of the corresponding layout structure of the first gate layer;

[0035] Figure 28 Show Figure 20 A schematic diagram of the corresponding layout structure of the first semiconductor layer;

[0036] Figure 29 Another schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0037] Figure 30 Another structural schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0038] Figure 31 Show Figure 3 A schematic diagram of another layout structure of the corresponding display panel;

[0039] Figure 32 Show Figure 31 Schematic diagram of the layout structure of the middle anode, the second metal layer, and the third metal layer;

[0040] Figure 33 Show Figure 31 Schematic diagram of the layout structure of the middle anode;

[0041] Figure 34 Show Figure 31 Schematic diagram of the layout structure of the third metal layer;

[0042] Figure 35 Show Figure 31 Schematic diagram of the layout structure of the second metal layer;

[0043] Figure 36 Show Figure 4 A schematic diagram of a layout structure of a corresponding display panel anode;

[0044] Figure 37 Show Figure 5 A schematic diagram of a layout structure of a corresponding display panel;

[0045] Figure 38 Show Figure 37 Schematic diagram of the layout structure of the middle anode;

[0046] Figure 39 Show Figure 37 Schematic diagram of the layout structure of the third metal layer;

[0047] Figure 40 Show Figure 37 Schematic diagram of the layout structure of the second metal layer;

[0048] Figure 41 Show Figure 5 A schematic diagram of another layout structure of the corresponding display panel;

[0049] Figure 42 Show Figure 41 Schematic diagram of the layout structure of the middle anode, the second metal layer, and the third metal layer;

[0050] Figure 43 Show Figure 41 Schematic diagram of the layout structure of the middle anode;

[0051] Figure 44Show Figure 41 Schematic diagram of the layout structure of the third metal layer;

[0052] Figure 45 Show Figure 41 Schematic diagram of the layout structure of the second metal layer;

[0053] Figure 46 Show Figure 5 A schematic diagram of a layout structure of a corresponding display panel;

[0054] Figure 47 Show Figure 46 Schematic diagram of the layout structure of the middle anode;

[0055] Figure 48 Show Figure 46 Schematic diagram of the layout structure of the third metal layer;

[0056] Figure 49 Show Figure 46 Schematic diagram of the layout structure of the second metal layer;

[0057] Figure 50 Show Figure 5 A schematic diagram of a layout structure of a corresponding display panel;

[0058] Figure 51 Show Figure 50 Schematic diagram of the layout structure of the middle anode;

[0059] Figure 52 Show Figure 50 Schematic diagram of the layout structure of the third metal layer;

[0060] Figure 53 Show Figure 50 Schematic diagram of the layout structure of the second metal layer;

[0061] Figure 54 Show Figure 5 A schematic diagram of a layout structure of a corresponding display panel;

[0062] Figure 55 Show Figure 54 Schematic diagram of the layout structure of the middle anode;

[0063] Figure 56 Show Figure 54 Schematic diagram of the layout structure of the third metal layer;

[0064] Figure 57 Show Figure 54 Schematic diagram of the layout structure of the second metal layer;

[0065] Figure 58 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0066] Figure 59 Show Figure 58 A schematic diagram of a layout structure of a corresponding display panel;

[0067] Figure 60 Show Figure 59 Schematic diagram of the layout structure of the middle anode and the first metal layer;

[0068] Figure 61 Show Figure 59 Schematic diagram of the layout structure of the middle anode;

[0069] Figure 62 Show Figure 59 Schematic diagram of the layout structure of the first metal layer;

[0070] Figure 63 Show Figure 59 Schematic diagram of the layout structure of the capacitor metal layer;

[0071] Figure 64 Show Figure 59 Schematic diagram of the layout structure of the first gate layer;

[0072] Figure 65 Show Figure 59 Schematic diagram of the layout structure of the first semiconductor layer;

[0073] Figure 66 Show Figure 59 Schematic diagram of the layout structure of the first semiconductor layer, the first gate layer, and the capacitor metal layer;

[0074] Figure 67 Show Figure 59 Schematic diagram of the layout structure of the auxiliary metal layer;

[0075] Figure 68 A schematic diagram showing another cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0076] Figure 69 Another structural schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0077] Figure 70 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0078] Figure 71 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0079] Figure 72 Show Figure 71 A structural diagram of the power distribution line;

[0080] Figure 73 A schematic structural diagram of a display device provided in an embodiment of the present application is shown.

[0081] Description of some reference numerals:

[0082] 10, light-emitting element; 11, first light-emitting element; 12, second light-emitting element; 13, third light-emitting element; 10a, first unit column; 10b, second unit column; 10c, first unit row; 101, element unit;

[0083] 20, pixel circuit; 21, first pixel circuit; 22, second pixel circuit; 23, third pixel circuit; 20a, first circuit column; 20b, second circuit column; 20c, third circuit column;

[0084] 30. Data line; 31. First data line; 32. Second data line; 33. Third data line;

[0085] 41, first via hole; 41a, first via hole row; 42, second via hole; 42a, second via hole row; 43, third via hole;

[0086] 40. Via;

[0087] 51, first connecting line; 511, first section; 512, second section; 52, second connecting line; 523, third section; 524, fourth section; 53, third connecting line;

[0088] 54. Compensation line;

[0089] PVDD, power line;

[0090] 61, first power line; 611, first power branch line; 612, second power branch line; 617, seventh power branch line;

[0091] 62, second power line; 623, third power branch line; 624, fourth power branch line; 628, eighth power branch line;

[0092] 63, third power line; 635, fifth power branch line; 636, sixth power branch line; 639, ninth power branch line;

[0093] 70. Adapter cable; 71. First line segment; 72. Second line segment;

[0094] 81, first auxiliary line; 82, second auxiliary line; 83, third auxiliary line;

[0095] 91, first routing; 92, second routing; 93, third routing;

[0096] 100. Display panel;

[0097] 1000. Display device. DETAILED DESCRIPTION

[0098] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0099] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0100] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0101] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0102] In the embodiments of the present application, the term "electrically connected" may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components. The term "drive" may refer to "control" or "operate". The term "portion" may refer to "local". The term "pattern" may refer to "component". The term "end" may refer to "end segment" or "end edge". The display panel may be a display device or a module / portion of a display device.

[0103] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0104] Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first shows a comparative example. Figure 1 Figure 1 shows a schematic diagram of the structure of a display panel in a comparative example. The display panel includes red sub-pixels R, green sub-pixels G, and blue sub-pixels B. Data line DL1 connects the red sub-pixels R and blue sub-pixels B in the same column, and data line DL2 connects the green sub-pixels G in the same column. The data lines are used to provide data signals to the sub-pixels. The data lines are connected to a driver chip (not shown in the figure), which generates the data signals.

[0105] Take the display panel showing a pure color picture (such as a pure red picture or a pure blue picture) as an example. Figure 2 As shown, the voltage on the data line DL1 will jump back and forth, resulting in increased power consumption of the driver chip connected to the data line.

[0106] To solve the above technical problems, the embodiments of the present application provide a display panel and a display device. The embodiments of the present application are described below with reference to the accompanying drawings.

[0107] like Figures 3 to 5 As shown, the display panel provided by the embodiment of the present application includes a light-emitting element 10 , a pixel circuit 20 , and a data line 30 .

[0108] Exemplarily, the light emitting element 10 includes an organic light emitting diode (OLED). The light emitting element 10 includes an anode, a light emitting layer, and a cathode. The location of the light emitting element in the drawings of this application can be understood as the location of the anode of the light emitting element.

[0109] The data line 30 is electrically connected to the pixel circuit 20 and is used to provide a data signal to the pixel circuit 20. The pixel circuit 20 generates a certain driving current based on the data signal from the data line 30, and the driving current is used to drive the light emitting element 10.

[0110] The data line 30 is electrically connected to a driving chip (not shown in the figure). The driving chip is used to generate a data signal and transmit it to the data line 30 .

[0111] The light emitting element 10 includes a first light emitting element 11 , a second light emitting element 12 , and a third light emitting element 13 . The first light emitting element 11 , the second light emitting element 12 , and the third light emitting element 13 emit light of different colors.

[0112] The first unit column 10a includes first light-emitting elements 11 and second light-emitting elements 12 arranged alternately in a first direction X. The second unit column 10b includes a plurality of third light-emitting elements 13 arranged in the first direction X. The first unit column 10a and the second unit column 10b are arranged alternately in a second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X is a column direction, and the second direction Y is a row direction.

[0113] As an example, Figures 3 to 5 As shown, the first light emitting element 11 is a red light emitting element, the second light emitting element 12 is a blue light emitting element, and the third light emitting element 13 is a green light emitting element. In this example, the red light emitting elements and the blue light emitting elements are alternately arranged in one column, and the green light emitting elements are arranged in another column.

[0114] As another example, the first light-emitting element 11 is a red light-emitting element, the second light-emitting element 12 is a green light-emitting element, and the third light-emitting element 13 is a blue light-emitting element, which will be illustrated in subsequent figures. In this example, the red light-emitting elements and the green light-emitting elements are arranged alternately in one column, and the blue light-emitting elements are arranged in another column.

[0115] It should be noted that the light emitting colors of the first light emitting element and the second light emitting element are interchangeable.

[0116] Exemplarily, the stacked structures of different light-emitting elements are the same. For example, light-emitting elements of three colors all include a stacked anode, a light-emitting layer, and a cathode, wherein the anode of the light-emitting element is electrically connected to the pixel circuit through a via (one end of the via extends to the film layer where the anode is located and overlaps the anode, or the anode and the via are connected by a trace).

[0117] The pixel circuit 20 includes a first pixel circuit 21, a second pixel circuit 22, and a third pixel circuit 23. It should be noted that in the drawings marked with pixel circuits in this application, the approximate location of the pixel circuits is indicated by a dotted frame.

[0118] Multiple pixel circuits 20 constitute a first circuit column 20a, a second circuit column 20b and a third circuit column 20c. The first circuit column 20a includes a plurality of first pixel circuits 21 arranged in the first direction X, the second circuit column 20b includes a plurality of second pixel circuits 22 arranged in the first direction X, and the third circuit column 20c includes a plurality of third pixel circuits 23 arranged in the first direction X.

[0119] It is understood that the first circuit column 20a does not include the second pixel circuit 22 and the third pixel circuit 23, the second circuit column 20b does not include the first pixel circuit 21 and the third pixel circuit 23, and the third circuit column 20c does not include the first pixel circuit 21 and the second pixel circuit 22.

[0120] The first pixel circuit 21 is electrically connected to the first data line 31 and the first light emitting element 11 . The second pixel circuit 22 is electrically connected to the second data line 32 and the second light emitting element 12 . The third pixel circuit 23 is electrically connected to the third data line 33 and the third light emitting element 13 .

[0121] From the perspective of transmitting data signals, the first data line 31 is only used to transmit the data signal required by the first light-emitting element 11, the second data line 32 is only used to transmit the data signal required by the second light-emitting element 12, and the third data line 33 is only used to transmit the data signal required by the third light-emitting element 13.

[0122] For example, when displaying a solid-color image corresponding to the first light-emitting element 11, the first data line 31 only needs to transmit the data signal required by the first light-emitting element 11, without needing to transmit the data signal required by the second light-emitting element 12. Thus, the first data line 31 does not need to provide a variable data signal. Similarly, when displaying a solid-color image corresponding to the second light-emitting element 12, the second data line 32 only needs to transmit the data signal required by the second light-emitting element 12, without needing to transmit the data signal required by the first light-emitting element 11. Thus, the second data line 32 does not need to provide a variable data signal.

[0123] According to the display panel provided in the embodiment of the present application, one data line is used to provide the data signal required by the light-emitting elements of the same light-emitting color. In this way, when displaying a pure color picture, the data signal on the data line does not need to jump, thereby reducing the power consumption of the driver chip connected to the data line.

[0124] It should be noted that Figures 3 to 5In the figure, the first data line 31 overlaps with the first circuit column 20a to indicate that the first data line 31 is electrically connected to each first pixel circuit 21 in the first circuit column 20a. The second data line 32 overlaps with the second circuit column 20b to indicate that the second data line 32 is electrically connected to each second pixel circuit 22 in the second circuit column 20b. The third data line 33 overlaps with the third circuit column 20c to indicate that the third data line 33 is electrically connected to each third pixel circuit in the third circuit column 20c. One end of the trace 01 points to the first light-emitting element 11, and the other end points to the first data line 31. This indicates that the first data line 31 is used to provide the data signal required by the first light-emitting element 11, rather than limiting the electrical connection between the first light-emitting element 11 and the first data line 31 via trace 01. The same applies to traces 02 and 03, and will not be further described here. Furthermore, to distinguish between the traces and the structure of the display panel, the traces extending into the width of the dashed line are marked with arrows, for example, traces 11, 12, and 13 are marked with arrows.

[0125] As an example, Figure 3 As shown, (i) to (i+3) and (j) to (j+3) represent eight unit columns, and nine circuit columns are schematically illustrated. The (i), (i+1), (i+2), and (i+3)th unit columns constitute four first unit columns 10a, and the (j), (j+1), (j+2), and (j+3)th unit columns constitute four second unit columns 10b. Reference numerals 20a1, 20a2, and 20a3 represent three first circuit columns 20a, 20b1 and 20b2 represent two second circuit columns 20b, and 20c1, 20c2, 20c3, and 20c4 represent four third circuit columns 20c.

[0126] Figure 3 Relative to Figure 1 In the example shown, the relative positional relationship between the third light-emitting element 13 and the pixel circuit connected thereto remains unchanged, and the differences include:

[0127] The first pixel circuit 21 in the first first circuit column 20a1 is used to drive the first light-emitting element 21 in the (i)th first unit column 10a, the first pixel circuit 21 in the second first circuit column 20a2 is used to drive the first light-emitting element 21 in the (i+1)th and (i+2)th first unit columns 10a, and the first pixel circuit 21 in the third first circuit column 20a3 is used to drive the first light-emitting element 21 in the (i+3)th first unit column 10a.

[0128] The second pixel circuit 22 in the first second circuit column 20b1 is used to drive the second light-emitting element 22 in the (i)th and (i+1)th first unit columns 10a, and the second pixel circuit 22 in the second second circuit column 20b is used to drive the second light-emitting element 22 in the (i+2)th and (i+3)th first unit columns 10a.

[0129] Figure 3 The number of columns of pixel circuits is one more than the number of columns of light-emitting elements, wherein the first first circuit column 20a1 and the third first circuit column 20a3 include virtual pixel circuits dummy, which are not connected to the light-emitting elements, that is, the virtual pixel circuits dummy are not used to drive the light-emitting elements.

[0130] It should be noted that the number of pixel circuit columns here means that at least one pixel circuit in the pixel circuit column is connected to a light-emitting element. Exemplarily, the display panel may further include a dummy pixel circuit column, and none of the dummy pixel circuits in the dummy pixel circuit column is used to drive a light-emitting element.

[0131] As another example, Figure 4 As shown, Figure 4 and Figure 3 The differences are as follows:

[0132] The first pixel circuit 21 in the first first circuit column 20a1 is used to drive the first light-emitting element 11 in the (i)th and (i+1)th first unit columns 10a, and the first pixel circuit 21 in the second first circuit column 20a2 is used to drive the first light-emitting element 11 in the (i+2)th and (i+3)th first unit columns 10a.

[0133] The second pixel circuit 22 in the first second circuit column 20b1 is used to drive the second light-emitting element 12 in the (i)th first unit column 10a, the second pixel circuit 22 in the second second circuit column 20b2 is used to drive the second light-emitting element 12 in the (i+1)th and (i+2)th first unit columns 10a, and the second pixel circuit 22 in the third second circuit column 20b3 is used to drive the second light-emitting element 12 in the (i+3)th first unit column 10a.

[0134] Figure 4 The number of pixel circuit columns is one more than the number of light emitting element columns, wherein the first second circuit column 20b1 and the third second circuit column 20b3 include dummy pixel circuits.

[0135] As another example, Figure 5 As shown, Figure 5 and Figure 3 、 Figure 4The differences are as follows:

[0136] The first pixel circuit 21 in the first first circuit column 20a1 is used to drive the first light-emitting element 21 in the (i)th and (i+1)th first unit columns 10a, and the first pixel circuit 21 in the second first circuit column 20a2 is used to drive the first light-emitting element 21 in the (i+2)th and (i+3)th first unit columns 10a.

[0137] The second pixel circuit 22 in the first second circuit column 20b1 is used to drive the second light-emitting element 22 in the (i)th and (i+1)th first unit columns 10a, and the second pixel circuit 22 in the second second circuit column 20b2 is used to drive the second light-emitting element 22 in the (i+2)th and (i+3)th first unit columns 10a.

[0138] Figure 5 The number of columns of pixel circuits is equal to the number of columns of light-emitting elements. Figure 5 Each circuit column does not include a dummy pixel circuit.

[0139] It should be noted that Figures 3 to 5 This is not intended to limit the present application. In other embodiments, the arrangement structure of the light-emitting elements of the display panel may be other methods, or the arrangement structure of the pixel circuit may be other methods. As long as the same column of units includes light-emitting elements of different colors, the light-emitting elements of the same color can be connected through data lines to reduce the power consumption of the driver chip.

[0140] like Figures 3 to 5 As shown, for the first circuit column without a dummy pixel circuit dummy, the first circuit column needs to be electrically connected to the first light-emitting elements located in the two unit columns. In this way, for at least part of the first light-emitting elements, it is necessary to set a connecting line to connect the first light-emitting element and the first pixel circuit. The longer the connecting line, the greater the voltage drop, which will affect the driving ability of the first pixel circuit to the first light-emitting element. Similarly, the same situation exists for the second light-emitting element and the second pixel circuit electrically connected thereto. Therefore, while achieving reduced power consumption, how to take into account the driving ability of the pixel circuit is also relatively important.

[0141] To this end, in some embodiments, Figure 3 or Figure 4 As shown, the number of columns of pixel circuits in the display panel is greater than the number of columns of light-emitting elements, and some circuit columns include virtual pixel circuits. Figures 6 to 8 A schematic diagram showing the arrangement of connection vias between the light-emitting element and the pixel circuit is shown. Figure 6 、 Figure 7 、 Figure 8In the following schematic diagrams, vertical dotted lines are used to indicate the approximate positions of multiple circuit columns. In order to avoid too many dotted lines, the approximate position of each pixel circuit is not circled with a dotted box. It can be understood that a circuit column between two vertical dotted lines includes multiple pixel circuits.

[0142] Please refer to Figure 3 、 Figure 6 、 Figure 7 and Figure 8 , the first light-emitting element 11 is electrically connected to the first pixel circuit 21 through the first via 41. The first end of the first via 41 extends to the film layer where the anode of the first light-emitting element 11 is located, and the second end of the first via 41 is electrically connected to the first pixel circuit 21. The multiple first vias 41 corresponding to the same first circuit column 20a constitute a first via column 41a. For the first circuit column that does not include the virtual pixel circuit, in the second direction Y, the multiple first light-emitting elements 11 electrically connected to the first pixel circuit through the vias on the same first via column 41a are respectively located on both sides of the first via column 41a. In the figure, the multiple first vias located in the same column are circled with a dotted frame to represent the first via column, and the multiple second vias located in the same column are circled with another dotted frame to represent the second via column.

[0143] For example, Figure 7 The image processing apparatus includes four first unit columns 10a, from the i-th to the i+3-th, four second unit columns 10b, from the j-th to the j+3-th, eight pixel circuit columns, and eight circuit columns. The first unit columns 10a include first light-emitting elements 11 and second light-emitting elements 12 arranged alternately in a first direction X. For example, the first light-emitting elements 11 are red light-emitting elements, and the second light-emitting elements 12 are blue light-emitting elements. The second unit columns 10b are all arranged with third light-emitting elements 13, for example, green light-emitting elements.

[0144] The first circuit column 20a includes a plurality of first pixel circuits 21 arranged along a first direction, and the first pixel circuits 21 are used to drive the first light-emitting elements 11. The second circuit column 20b includes a plurality of second pixel circuits 22 arranged along the first direction, and the second pixel circuits 22 are used to drive the second light-emitting elements 12. The third circuit column 20c includes a plurality of third pixel circuits 23 arranged along the first direction, and the third pixel circuits 23 are used for the third light-emitting elements 13.

[0145] by Figure 6 and Figure 7Taking the second first circuit column 20a2 in the example, the second first circuit column 20a2 does not include a dummy pixel circuit. The second first circuit column 20a2 is used to drive the first light-emitting element 11 in the (i+1)th first unit column 10a and the (i+2)th first unit column 10a. The first via 41 of the first light-emitting element 11 in the (i+1)th first unit column 10a is located to the right of the first light-emitting element, while the first via 41 of the first light-emitting element 11 in the (i+2)th first unit column 10a is located to the left of the first light-emitting element. In other words, the first vias of the first light-emitting elements in the two first unit columns connected to the same first circuit column are both arranged toward the first circuit column. This shortens the length of the connecting line between the first light-emitting element and the first pixel circuit, thereby avoiding a large voltage drop caused by an excessively long connecting line. This reduces power consumption while also ensuring the driving capability of the first pixel circuit.

[0146] For example, please refer to Figures 6 to 8 For the first circuit column including the virtual pixel circuit, taking the first first circuit column 20a1 as an example, the first first circuit column 20a1 is used to drive the first light-emitting element 11 in the (i)th first unit column 10a, and the multiple first vias 41 of the (i)th first unit column 10a are located on the same side of the (i)th first unit column 10a.

[0147] The second light-emitting element 12 is electrically connected to the second pixel circuit 22 via a second via 42. The plurality of second vias 42 corresponding to the same second circuit column 20b constitute a second via column 42a. The first end of the second via 42 extends to the film layer where the anode of the second light-emitting element 12 is located, and the second end of the second via 42 is electrically connected to the second pixel circuit 22. For a second circuit column that does not include a dummy pixel circuit, in the second direction Y, the plurality of second light-emitting elements 12 electrically connected to the second pixel circuit 22 via vias in the same second via column 42a are located on either side of the second via column 42a.

[0148] For example, the first second circuit column 20b1 does not include a dummy pixel circuit. The first second circuit column 20b1 is used to drive the second light-emitting element 12 in the (i)th first unit column 10a and the (i+1)th first unit column 10a. The second via 42 of the second light-emitting element 12 in the (i)th first unit column 10a is located to the right of the second light-emitting element, while the second via 42 of the second light-emitting element 12 in the (i+1)th first unit column 10a is located to the left of the second light-emitting element. In other words, the second vias of the second light-emitting elements in the two first unit columns connected to the same second circuit column are both arranged toward the second circuit column. This shortens the length of the connecting line between the second light-emitting element and the second pixel circuit, thereby avoiding a large voltage drop caused by an excessively long connecting line. This reduces power consumption while also ensuring the driving capability of the second pixel circuit.

[0149] For a first circuit column including a dummy pixel circuit, the corresponding plurality of first vias are on the same side of the first circuit column. Figure 6 The first first circuit column 20a1 includes dummy pixel circuits, and the corresponding first via holes are approximately located on the left side thereof.

[0150] For the second circuit column including the dummy pixel circuit, the corresponding plurality of second via holes are located on the same side of the second circuit column.

[0151] In some embodiments, as Figures 6 to 8 As shown, for the same first unit column 10 a , in the second direction Y, the first via hole 41 and the second via hole 42 are respectively located on both sides of the first unit column 10 a .

[0152] For example, in the (i)th first unit column 10 a , the plurality of first vias 41 are all located on the left side of the (i)th first unit column 10 a , and the plurality of second vias 42 are all located on the right side of the (i)th first unit column 10 a .

[0153] For another example, in the (i+1)th first unit column 10a, the plurality of first vias 41 are all located on the right side of the (i+1)th first unit column 10a, and the plurality of second vias 42 are all located on the left side of the (i+1)th first unit column 10a.

[0154] Since the first light-emitting elements 11 and the second light-emitting elements 12 in the first unit column 10a are alternately distributed in the second direction Y, the first vias 41 and the second vias 42 are alternately distributed on both sides of the first unit column 10a. This avoids the vias corresponding to the first unit column 10a being distributed on the same side, which would cause the vias to be too dense. If the vias are too dense, more layout space would be required, which is not conducive to improving pixel density. Therefore, the embodiment of the present application is conducive to improving pixel density and can improve signal interference between different vias.

[0155] In some embodiments, please refer to Figure 8 The first light emitting elements 11 and the second light emitting elements 12 are alternately arranged in the second direction Y to form a first unit row 10c. Figure 8 In the figure, (e) to (e+3) are marked next to the mark 10c, where (e) represents the (e)th first unit row 10c, (e+1) represents the (e+1)th first unit row 10c, (e+2) represents the (e+2)th first unit row 10c, and (e+3) represents the (e+3)th first unit row 10c.

[0156] The plurality of third light emitting elements 13 are arranged in the second direction Y to form a second unit row. In the first direction, the first unit row and the second unit row are alternately arranged.

[0157] For the same first unit row 10c, in the second direction Y, the relative positional relationship between the first via 41 and the first light-emitting element 11 is the same as the relative positional relationship between the second via 42 and the second light-emitting element 12. That is, for the same unit row, the first via and the second via are both located on the same side of the first or second light-emitting element to which they are electrically connected.

[0158] For example, in the (e)th and (e+2)th first unit rows 10c, the first vias 41 are both located on the left side of the first light-emitting elements 11 to which they are connected. For another example, in the (e+1)th and (e+3)th first unit rows 10c, the first vias 41 are both located on the right side of the first light-emitting elements 11 to which they are connected.

[0159] In this example, in the same first unit row 10c, the first vias 41 and the first light-emitting elements 11 electrically connected thereto are arranged according to the same position rule, so that the driving capabilities of the first light-emitting elements 11 in the same row are equivalent, which is conducive to improving display uniformity.

[0160] For example, in the (e)th and (e+2)th first cell rows 10c, the second via 42 is located on the left side of the second light-emitting element 12 to which it is electrically connected. For another example, in the (e+1)th and (e+3)th first cell rows 10c, the second via 42 is located on the right side of the second light-emitting element 12 to which it is electrically connected.

[0161] Similarly, in the same first unit row 10c, the second vias 42 and the second light-emitting elements 12 electrically connected thereto are arranged according to the same position rule, so that the driving capabilities of the second light-emitting elements 12 in the same row are equivalent, which is conducive to improving display uniformity.

[0162] It should be noted that, in this document, “left side” and “right side” refer to different sides and are not used to absolutely limit the left side or the right side.

[0163] Furthermore, the relative positional relationship between the first via 41 and the first light-emitting element 11 and the relative positional relationship between the second via 42 and the second light-emitting element 12 are the same. This can prevent the first via and the second via from being adjacent to each other in the same first unit row, which would result in the vias being too dense. For adjacent first unit rows, the first via and the second via are located on different sides of the first light-emitting element and the second light-emitting element in different first unit rows. For example, Figure 8 In the (e)th first unit row 10c, the first via 41 and the second via 42 are both located on the first side of the first light-emitting element 11 and the second light-emitting element 12 electrically connected thereto, while in the (e+2)th first unit row 10c adjacent to the (e)th first unit row 10c, the first via 41 and the second via 42 are both located on the second side of the first light-emitting element 11 and the second light-emitting element 12 electrically connected thereto. This arrangement facilitates connecting the first light-emitting elements in adjacent first unit columns to the same circuit column.

[0164] In some embodiments, as Figures 6 to 18 As shown, the display panel may include at least two semiconductor layers. For example, refer to Figure 18 The display panel includes a first semiconductor layer B1 and a second semiconductor layer B2. As an example, the material of the first semiconductor layer B1 includes low-temperature polysilicon (LTPS), and the material of the second semiconductor layer B2 includes indium gallium zinc oxide (IGZO). The display panel is a low-temperature polycrystalline oxide (LTPO) type display panel. LTPS transistors have faster carrier mobility, while IGZO transistors have lower leakage current.

[0165] For example, the structure of the pixel circuit can be as follows Figure 19 As shown, the driving transistor T3 can be an LTPS transistor, and the threshold compensation transistor T4 and the reset transistor T5 can be an IGZO transistor. Figure 19 The structures of the pixel circuits shown in the subsequent figures are merely examples and are not intended to limit the present application.

[0166] like Figure 18 As shown, the display panel may further include an auxiliary metal layer M0, a first gate layer GAT, a capacitor metal layer MC, a second gate layer MG, a first metal layer SD1, a second metal layer SD2, a third metal layer SD3, and an anode layer RE. The relative position relationship of each film layer is referenced as follows: Figure 18, I will not go into details here. It should be noted that the auxiliary metal layer M0 can be set according to needs. In some examples, the auxiliary metal layer M0 may not be set. Similarly, the second metal layer SD2 and the third metal layer SD3 can be set according to needs. In some examples, the second metal layer SD2 and the third metal layer SD3 may not be set. It can be understood that the first gate layer GAT, the capacitor metal layer MC, and the second gate layer MG are also metal layers. The first metal layer, the second metal layer, and the third metal layer in this article are just names for different metal layers and are not used to limit the order of the metal layers.

[0167] Corresponding to Figure 18 The film structure shown and Figure 19 The circuit structure shown is Figures 8 to 17 The layout structure of each film layer is shown in order from top to bottom. Figure 8 It is a layout structure of the anode layer RE. The anode of the light-emitting element is arranged in the anode layer RE. The connection line between the light-emitting element and the pixel circuit can also be at least partially arranged in the anode layer RE. Figure 9 The third metal layer SD3 may include traces extending along the second direction Y, such as power branch lines 612 and 624 . Figure 10 The second metal layer SD2 may include traces extending along the first direction X, such as data lines 31 - 33 , power branch lines 611 , 623 , and 635 , and traces 91 and 92 . Figure 11 Schematic diagram of the layout structure of the first metal layer SD1 . The first metal layer SD1 may include a trace extending along the second direction, for example, a second trace segment 72 for connecting a data line. Figure 12 Γ is the layout of the second gate layer MG. The second gate layer MG may include scan lines S1N and S2N extending along the second direction. Figure 13 The second semiconductor layer B2 may include an active layer of a transistor, for example, Figure 19 The active layers of the transistors T4 and T5 are arranged in the second semiconductor layer B2. Figure 14 The layout structure of the capacitor metal layer MC includes scan lines S1N and S2N extending along the second direction, reset signal lines Vref1 and Vref2, and a plate of the storage capacitor. Figure 15 : is the layout structure of the first gate layer GAT. The first gate layer GAT includes scan lines SP and SP* extending along the second direction, and a light emitting control signal line EM. Figure 16 represents the layout structure of the first semiconductor layer B1, which may include an active layer of a transistor, for example, Figure 19 The active layers of the transistors T1 to T3 and T6 to T8 are arranged on the first semiconductor layer B1 . Figure 17It represents the layout structure of the auxiliary metal layer M0. The wiring structure in the auxiliary metal layer M0 can shield the active layer of the transistor from light to stabilize the characteristics of the transistor.

[0168] The anode of each light emitting element is arranged on the anode layer RE, the pixel definition layer PDL includes a pixel opening KK, and the light emitting layer ( Figure 18 Not shown) is correspondingly arranged at the opening KK, the cathode of the light emitting element ( Figure 18 (not shown) covers its light-emitting layer.

[0169] like Figure 8 and Figure 9 As shown, the anode of the first light-emitting element 11 is electrically connected to the first end of the first via 41 through the first connecting wire 51, and the second end of the first via 41 is electrically connected to the first pixel circuit. The first connecting wire 51 and the anode of the first light-emitting element 11 are located in the same film layer. Figure 18 The anode layer RE is shown. The anode of the first light-emitting element 11 is the light-emitting area of ​​the first light-emitting element, and the first connecting line 51 can be a non-light-emitting area. In other words, in the thickness direction of the display panel, the anode of the first light-emitting element 11 overlaps with the opening KK, and the first connecting line 51 does not overlap with the opening KK.

[0170] The anode of the second light emitting element 12 is electrically connected to the first end of the second via 42 through the second connecting wire 52, and the second end of the second via 42 is electrically connected to the second pixel circuit. The second connecting wire 52 and the anode of the second light emitting element 12 are located in the same film layer. Figure 18 The anode layer RE is shown. The anode of the second light-emitting element 12 is the light-emitting area of ​​the second light-emitting element, and the second connecting line 52 can be a non-light-emitting area. In other words, in the thickness direction of the display panel, the anode of the second light-emitting element 12 overlaps with the opening KK, and the second connecting line 52 does not overlap with the opening KK.

[0171] As described above, the multiple first light-emitting elements connected to the first circuit column are alternately distributed on both sides, so that the first light-emitting elements are relatively close to the first pixel circuit they need to connect to. In addition, in the LTPO pixel circuit, the two adjacent pixel circuits in the second direction adopt a mirror design. This design method ensures that the length of the first connecting line between the first light-emitting element and the first pixel circuit is not too long. Therefore, there is space for the first connecting line to be set in the film layer where the light-emitting element is located, without the need for line replacement, which can avoid increasing the difficulty of the process. The second connecting line is similarly designed and will not be repeated here.

[0172] In some embodiments, please refer to Figure 8The length of the first connecting wire 51 is less than the maximum width of the first light-emitting element 11 along the second direction Y, and the length of the second connecting wire 50 is less than the maximum width of the second light-emitting element 12 along the second direction Y. In other words, there is no need to set a winding around the anode in the module where the anode of the light-emitting element is located. The short length of the connecting wire can reduce the impact of voltage drop, and there is no need to wind the wire from one end of the light-emitting element to the other end, which can avoid problems such as short circuits caused by excessive length of the connecting wire on the anode layer.

[0173] In some embodiments, as Figure 8 As shown, for the same unit column, the first connecting line 51 and the second connecting line 52 extend in intersecting directions. For example, the first connecting line 51 and the second connecting line 52 corresponding to the (i)th first unit column 10a extend in intersecting directions. The intersection of the two connecting lines can help to shorten the length of the connecting lines.

[0174] Figure 3 The architecture shown can also be represented by Figures 20 to 30 The specific structure shown is implemented. Figures 20 to 30 The structure shown in FIG. 1 shows a display panel comprising a semiconductor layer. For example, Figure 29 As shown, the display panel includes a first semiconductor layer B1. For example, the material of the first semiconductor layer B1 includes LTPS, such as Figure 30 As shown, each transistor of the pixel circuit is an LTPS transistor. Figure 29 and Figure 18 , Figure 29 The film structure shown does not include the second semiconductor layer B2 and the second gate layer MG. Figure 29 The film structure shown and Figure 30 The circuit structure shown is Figures 22 to 27 The layout structure of each film layer is shown in order from top to bottom. Figure 22 It is a layout structure of the anode layer RE. The anode of the light-emitting element is arranged in the anode layer RE. The connection line between the light-emitting element and the pixel circuit can also be at least partially arranged in the anode layer RE. Figure 23 The third metal layer SD3 may include traces extending along the second direction Y, such as power branch lines 612 and 624 . Figure 24 The second metal layer SD2 may include wiring extending along the first direction X, such as data lines 31 - 33 and power branch lines 611 , 623 , and 635 . Figure 25 The first metal layer SD1 may include wiring extending along a first direction, for example, reset signal lines Vref1 and Vref2 , and power branch lines 617 , 628 , and 639 . Figure 26This is the layout structure of the capacitor metal layer MC. The capacitor metal layer MC includes reset signal lines Vref1 and Vref2 extending along the second direction, and a plate of the storage capacitor. Figure 27 Schematic diagram of the first gate layer GAT. The first gate layer GAT includes scan lines S1 and S2 extending along the second direction, and a light emitting control signal line EM. Figure 28 represents the layout structure of the first semiconductor layer B1, which may include an active layer of a transistor, for example, Figure 28 The active layers of the transistors M1 to M7 are arranged on the first semiconductor layer B1. It is understandable that Figure 29 A wiring structure may also be provided in the auxiliary metal layer M0 shown. The wiring structure in the auxiliary metal layer M0 shields the active layer of the transistor from light, so as to stabilize the characteristics of the transistor.

[0175] For LTPS display panels, a non-mirror design is adopted. Even if a design method is adopted in which the multiple first light-emitting elements connected to the first circuit column are alternately distributed on both sides so that the first light-emitting elements are relatively close to the first pixel circuit to which they are required to be connected, in the non-mirror design, there will still be some first light-emitting elements that are relatively far away from the first pixel circuit to which they are required to be connected. If the connecting line is still completely set on the anode film layer, the connecting line needs to bypass the anode of the light-emitting elements of other colors, which will make the length of the connecting line longer, which will increase the voltage drop of the connecting line, resulting in a weakening of the driving ability of the first pixel circuit to the first light-emitting element. In addition, if the connecting line is completely set on the anode, the distance between the connecting line and the anode of the other light-emitting elements will be close, which will increase the risk of short circuit between different light-emitting elements. The same is true for the second light-emitting element, which will not be repeated here.

[0176] To address this, the first connecting line and the second connecting line may be designed in a cross-line manner (cross-line includes routing lines arranged on at least two film layers).

[0177] For example, Figure 21 For example, the first light-emitting element 11 is provided with a first connection line 51 corresponding to the first light-emitting element 11, and the first connection line 51 is used to connect the first light-emitting element 11 and the first pixel circuit. The second light-emitting element 12 is provided with a second connection line 52 corresponding to the second light-emitting element 12, and the second connection line 52 is used to connect the second light-emitting element 12 and the second pixel circuit.

[0178] The first connecting line 51 includes a first section 511 and a second section 512 . The first section 511 is connected between the anode of the first light emitting element 11 and the first end of the first via 41 . The second section 512 is connected between the second end of the first via 41 and the first pixel circuit.

[0179] The second connecting line 52 includes a third section 523 and a fourth section 524 . The third section 523 is connected between the anode of the second light-emitting element 12 and the first end of the second via 42 . The fourth section 524 is connected between the second end of the second via 42 and the second pixel circuit.

[0180] The lengths of the first connection lines 51 corresponding to the (i)th and (i+2)th first unit columns 10a are smaller than the lengths of the first connection lines 51 corresponding to the (i+1)th and (i+3)th first unit columns 10a.

[0181] The lengths of the second connection lines 52 corresponding to the (i)th and (i+2)th first unit columns 10a are greater than the lengths of the second connection lines 52 corresponding to the (i+1)th and (i+3)th first unit columns 10a.

[0182] For details, please refer to Figure 21 、 22 and Figure 23 The display panel includes a first connecting line 51 and a second connecting line 52. The first connecting line 51 includes a first section 511 and a second section 512. The first section 511 is connected between the anode of the first light-emitting element 11 and the first end of the first via 41, and the second section 512 is connected between the second end of the first via 41 and the first pixel circuit. The first section 511 and the anode of the first light-emitting element 11 are located in the same film layer, and the second section 512 is located in the metal layer on the side of the anode of the first light-emitting element 11 facing the substrate.

[0183] The second connecting line 52 includes a third section 523 and a fourth section 524. The third section 523 is connected between the anode of the second light-emitting element 12 and the first end of the second via 42. The fourth section 524 is connected between the second end of the second via 42 and the second pixel circuit. The third section 523 and the anode of the second light-emitting element 12 are located in the same film layer. The fourth section 524 is located in the metal layer on the side where the anode of the second light-emitting element 12 faces the substrate.

[0184] In the embodiment of the present application, since the second section 512 and the fourth section 524 are located in the metal layer below the anode, the length of the connecting line in the anode film layer can be reduced, and the connecting line in the metal layer is less constrained by the anode, and the routing form of the connecting line can be set by connecting nearby. The second section 512 and the fourth section 524 are both straight lines and do not need to meander due to the constraint of the anode. Therefore, the total length of the first connecting line can be reduced as a whole, and the total length of the second connecting line can be reduced.

[0185] In some embodiments, please refer to Figure 22 、 Figure 23 、 Figure 24 and Figure 29The display panel includes data lines, including a first data line 31, a second data line 32, and a third data line 33. All three types of data lines are located in the same film layer. In the thickness direction of the display panel, the film layer containing the second segment 512 and the fourth segment 524 is located between the film layer containing the data lines and the anode of the light-emitting element.

[0186] For example, combined with reference Figure 24 and Figure 29 , the data lines 31, 32, 33 are located in the second metal layer SD2, combined with the reference Figure 23 and Figure 29 The second section 512 and the fourth section 524 are the third metal layer SD3, and the anodes of various light-emitting elements are located at Figure 29 In the anode layer RE shown, the third metal layer SD3 is located between the second metal layer SD2 and the anode layer RE. That is, in the thickness direction of the display panel, the second segment 512 and the fourth segment 524 are closer to the anode of the light-emitting element, which facilitates connecting the second segment 512 and the fourth segment 524 to the anode of the corresponding light-emitting element.

[0187] It should be noted that Figure 3 The implementation is not limited to Figures 6 to 30 The example shown, among other examples, Figure 3 The architecture shown can also be represented by Figures 31 to 35 The specific structure shown is implemented. For example, Figures 31 to 35 The cross-sectional structure of the display panel corresponding to the structure shown can also be as follows Figure 18 As shown, Figure 34 The structure in the layout shown is located in Figure 18 The third metal layer SD3 shown, Figure 35 The structure in the layout shown is located in Figure 18 The second metal layer SD2 is shown.

[0188] Figures 31 to 35 The structure shown is Figures 6 to 19 The similarities of the structures shown are not described in detail here, and the differences include: the routing of the second metal layer and the third metal layer are interchanged. Figures 6 to 19 In the structure shown, the wiring extending in the first direction X is set in the second metal layer SD2, and the wiring extending in the second direction Y is set in the third metal layer SD3. Figures 31 to 35 In the structure shown, the wiring extending in the first direction X is arranged in the third metal layer SD3, and the wiring extending in the second direction Y is arranged in the second metal layer SD2.

[0189] For example, Figure 8 、 Figure 22 、 Figure 33 As shown, the layout of the anode layer can be roughly similar. Figure 34The third metal layer SD3 may include traces extending along the first direction X, such as data lines 31 - 33 , power branch lines 611 , 623 , and 635 , and traces 91 and 92 . Figure 35 The second metal layer SD2 may include traces extending along the second direction Y, such as power branch lines 612 and 624 .

[0190] In some embodiments, please refer to Figure 6 、 Figure 20 or Figure 31 In the thickness direction of the display panel, the first circuit column 20a overlaps at least partially with the multiple first light-emitting elements 11 connected thereto, and the second circuit column 20b overlaps at least partially with the multiple second light-emitting elements 12 connected thereto.

[0191] For example, for the first circuit column 20a not including the dummy pixel circuit, the multiple first light-emitting elements 11 connected to the first circuit column 20a are roughly alternately distributed on both sides thereof, and the first circuit column 20a at least partially overlaps with the first light-emitting elements 11 on the second side.

[0192] For another example, the plurality of second light-emitting elements 12 connected to the second circuit column 20 b are substantially alternately distributed on both sides thereof, and the second circuit column 20 b at least partially overlaps with the second light-emitting elements 12 on the second side.

[0193] When the light-emitting element overlaps with the pixel circuit to which it is electrically connected, the distance between the light-emitting element and the pixel circuit will not be too far, so as to avoid the length of the connecting line between the light-emitting element and the pixel circuit being too long, thereby ensuring the pixel circuit's ability to drive the light-emitting element.

[0194] In some embodiments, please refer to Figure 7 or Figure 32 In the thickness direction of the display panel, a portion of the first unit column 10a at least partially overlaps with the first data line 31 and the third data line 33, another portion of the first unit column 10a at least partially overlaps with the second data line 32 and the third data line 33, and the second unit column 10b has no overlap with the data lines.

[0195] In some embodiments, Figure 4 The anode layout structure corresponding to the driving architecture shown can be as follows Figure 36 As shown, Figure 4 The layout structure of other film layers corresponding to the driving architecture shown can be as follows Figures 6 to 17 The structure shown, or Figures 20 to 28 The structure shown, or Figures 31 to 35 As shown, no further details are given here.

[0196] like Figure 5As shown, the number of columns of pixel circuits in the display panel is equal to the number of columns of light-emitting elements. In some embodiments, Figure 5 The driver architecture shown can be Figures 37 to 40 This is achieved by the design shown.

[0197] For details, please refer to Figures 37 to 40 Two adjacent first unit columns 10a constitute a first unit column group, and the display panel includes multiple first unit column groups. For example, the (i)th first unit column 10a and the (i+1)th first unit column 10a constitute a first unit column group 10_1, and the (i+2)th first unit column 10a and the (i+3)th first unit column 10a constitute another first unit column group 10_2.

[0198] Each first circuit column 20 a is electrically connected to the plurality of first light emitting elements 11 in the first unit cell column group, and each second circuit column 20 b is electrically connected to the plurality of second light emitting elements 12 in the first unit cell column group.

[0199] In other words, each first unit column group is provided with a first circuit column 20a and a second circuit column 20b. Each first circuit column 20a is used to connect the first light-emitting elements 11 located in two unit columns, and each second circuit column 20b is used to connect the second light-emitting elements 12 located in two unit columns. This ensures that the number of pixel circuit columns in the display panel is equal to the number of light-emitting element columns. This design eliminates the need for an additional column of pixel circuits and dummy pixel circuits, facilitating a narrow bezel.

[0200] When the number of pixel circuit columns is equal to the number of light-emitting element columns, each first circuit column needs to be electrically connected to the first light-emitting elements located in two unit columns. In this way, for at least some of the first light-emitting elements, it is necessary to set a connecting line to connect the first light-emitting element and the first pixel circuit. The longer the connecting line, the greater the voltage drop, which will affect the driving ability of the first pixel circuit to the first light-emitting element. Similarly, the second light-emitting element and the second pixel circuit electrically connected thereto also have the same situation. Therefore, for Figure 5 The design shown is important for achieving reduced power consumption while also taking into account the driving capability of the pixel circuit.

[0201] In this regard, in some embodiments, please refer to Figure 5 、 Figure 37 、 Figure 38The first light-emitting element 11 is electrically connected to the first pixel circuit 21 through a first via 41. The first end of the first via 41 extends to the film layer where the anode of the first light-emitting element 11 is located, and the second end of the first via 41 is electrically connected to the first pixel circuit 21. The second light-emitting element 12 is electrically connected to the second pixel circuit 22 through a second via 42. The multiple second vias 42 corresponding to the same second circuit column 20b constitute a second via column 42a. The first end of the second via 42 extends to the film layer where the anode of the second light-emitting element 12 is located, and the second end of the second via 42 is electrically connected to the second pixel circuit 22.

[0202] In the first unit column group, in the second direction Y, the first via 41 of one first unit column 10 a is on a first side of the first unit column 10 a, and the second via 42 is on a second side of the first unit column; the first via 41 and the second via 42 of another first unit column 10 a are distributed on the same side of the first unit column.

[0203] For example, the (i)th first unit column 10a and the (i+1)th first unit column 10a constitute a first unit column group 10_1, wherein, in the (i)th first unit column 10a, the first via 41 is on the left and the second via 42 is on the right; in the (i+1)th first unit column 10a, the first via 41 and the second via 42 are both on the left.

[0204] The (i+2)th first unit column 10a and the (i+3)th first unit column 10a constitute another first unit column group 10_2, wherein, in the (i+2)th first unit column 10a, the first via 41 is on the left and the second via 42 is on the right; in the (i+3)th first unit column 10a, the first via 41 and the second via 42 are both on the left.

[0205] It is understood that in this embodiment, the first vias of the first light-emitting elements located in the two first unit columns and connected to the same first circuit column are all arranged in a direction close to the first circuit column. This shortens the length of the connecting line between the first light-emitting element and the first pixel circuit, thereby avoiding the large voltage drop caused by an excessively long connecting line. This achieves the goal of reducing power consumption while also ensuring the driving capability of the first pixel circuit. The same principle applies to the second light-emitting element and will not be further described here.

[0206] In some embodiments, please refer to Figure 37 、 Figure 38 and Figure 39 The first light emitting element 11 is electrically connected to the first pixel circuit via a first connecting line 51 , and the first connecting line 51 and the data line of the display panel are located in different film layers.

[0207] For example, for the first light-emitting element 11 in the (i+1)th and (i+3)th first unit columns 10a, a first connecting wire 51 needs to be provided in the metal layer below the anode. The first connecting wire 51 is used to connect the first light-emitting element 11 to the first pixel circuit. Specifically, a first end of the first connecting wire 51 is connected to the first via 41, and the other end is connected to the first pixel circuit. The other end of the first via 41 is connected to the anode of the first light-emitting element 11.

[0208] In some embodiments, the first connecting line 51 at least partially overlaps the second light emitting element 12 in the thickness direction of the display panel. This design can avoid winding of the first connecting line, reduce the length of the first connecting line, and thus reduce voltage drop.

[0209] For example, Figures 37 to 40 The corresponding film structure can be as follows Figure 18 As shown, Figures 37 to 40 In the embodiment, the data lines include a first data line 31, a second data line 32, and a third data line 33. The first data line 31, the second data line 32, and the third data line 33 are located as shown in FIG. Figure 18 As shown, the first connection line 51 is provided in the second metal layer SD2 and the third metal layer SD3, so that the first connection line 51 and the data line are located in different film layers.

[0210] In some embodiments, please refer to Figure 5 、 Figure 37 and Figure 18 In the thickness direction of the display panel, at least some of the second light-emitting elements 12 and the second pixel circuits 22 electrically connected thereto at least partially overlap. The display panel includes at least two semiconductor layers, namely, a first semiconductor layer B1 and a second semiconductor layer B2. Here, "overlap" simply means that at least some of the second light-emitting elements 12 overlap in the thickness direction of the display panel.

[0211] For example, the second light-emitting element 12 in the (i+1)th first unit column 10a at least partially overlaps with the second pixel circuit in the first second circuit column 20b1. The first second circuit column 20b1 is also used to drive the second light-emitting element 12 in the (i)th first unit column 10a. For the (i)th first unit column 10a, the second via 42 is located on a side close to the first second circuit column 20b1. This eliminates the need for excessively long connecting wires to connect each second light-emitting element to the second pixel circuit.

[0212] If a connecting wire is provided in the metal layer below the anode, which is called a "pull wire" for the light-emitting element, then in this embodiment, only the first light-emitting element 11 in the (i+1)th and (i+3)th first unit columns 10a needs to be designed with a "pull wire," and no "pull wire" design is required for the second light-emitting element 12 and the third light-emitting element 13. From this perspective, the embodiment of the present application is equivalent to reducing the length of the connecting wire required for the second light-emitting element 12 and the third light-emitting element 13, and the anodes of some second light-emitting elements 12 or third light-emitting elements 13 are directly connected to the pixel circuit through vias instead of connecting wires.

[0213] In addition, as described above, it is necessary to perform a "pull line" design on the first light emitting element 11 in the (i+1)th and (i+3)th first unit columns 10a. Here, "pull line" refers to Figure 37 、 Figure 39 The first connecting line 51 shown. If a "pull wire" is not designed for the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a, the voltage drops (or loading) corresponding to different first light-emitting elements 11 will be different, affecting the display uniformity. To address this, a compensation line 54 can be provided for the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a. The compensation line 54 is connected to the first via hole of the first light-emitting element 11 in the (i)th and (i+2)th first unit columns 10a. Exemplarily, the other end of the compensation line 54 is left floating. The compensation line 54 is provided on the same layer as the first connecting line 51 located on the metal layer.

[0214] Exemplarily, the first connection lines 51 and the compensation lines 54 corresponding to the first light-emitting elements connected to the same first circuit column are alternately arranged in the first direction.

[0215] It should be noted that the above Figure 18 The structure shown in the figure has been introduced and will not be repeated here. Figures 37 to 40 In the corresponding design method, the structures of other film layers can be respectively as follows Figures 11 to 17 shown.

[0216] In other embodiments, Figure 5 The driver architecture shown can be Figures 41 to 45 This is achieved by the design shown.

[0217] Please refer to Figure 5 as well as Figures 41 to 45The first light-emitting element 11 is electrically connected to the first pixel circuit 21 through the first connecting line 51, and the second light-emitting element 12 is electrically connected to the second pixel circuit 22 through the second connecting line 52. At least part of the line segment of the first connecting line 51 and at least part of the line segment of the second connecting line 52 are located in different film layers from the data line of the display panel. The display panel includes a semiconductor layer.

[0218] For example, Figures 41 to 45 The corresponding film structure can be as follows Figure 29 As shown, Figures 41 to 45 In the embodiment, the data lines include a first data line 31, a second data line 32, and a third data line 33. The first data line 31, the second data line 32, and the third data line 33 are located as shown in FIG. Figure 29 As shown, at least a portion of the line segments of the first connecting line 51 and at least a portion of the line segments of the second connecting line 52 are provided in the second metal layer SD2 and the third metal layer SD3, so that at least a portion of the line segments of the first connecting line 51, at least a portion of the line segments of the second connecting line 52 and the data line are located in different film layers, thereby avoiding crosstalk between the connecting lines and the data lines.

[0219] For LTPS display panels, a non-mirror design is used. Even if the vias of the light-emitting elements are all located on the side of the light-emitting elements facing the pixel circuit to which they are connected, so that the light-emitting elements are as close as possible to the pixel circuit to which they are connected, in the non-mirror design, some light-emitting elements will still be relatively far away from the pixel circuit to which they are connected. If the connecting wires are still all arranged in the anode film layer, the connecting wires will also need to bypass the anodes of light-emitting elements of other colors, which will make the length of the connecting wires longer, increase the voltage drop of the connecting wires, and cause the first pixel circuit to have a weakened driving ability of the first light-emitting element. The second light-emitting element is similar and will not be described here.

[0220] To address this, at least a portion of the first connecting wires and at least a portion of the second connecting wires may be designed in a cross-line manner (cross-line includes routing on at least two film layers).

[0221] Specifically, please refer to Figure 43 and Figure 44 For the (i+1)th first unit column 10a and the (i+3)th first unit column 10a, the first connecting line 51 includes a first segment 511 and a second segment 512, the first segment 511 is connected between the anode of the first light-emitting element 11 and the first end of the first via 41, the second segment 512 is connected between the second end of the first via 41 and the first pixel circuit, the first segment 511 and the anode of the first light-emitting element 11 are located in the same film layer, and the second segment 512 is located in the metal layer on the side of the anode of the first light-emitting element 11 facing the substrate.

[0222] For the (i)th first unit column 10a and the (i+2)th first unit column 10a, the second connecting line 52 includes a third segment 523 and a fourth segment 524, the third segment 523 is connected between the anode of the second light-emitting element 12 and the first end of the second via 42, and the fourth segment 524 is connected between the second end of the second via 42 and the second pixel circuit. The third segment 523 and the anode of the second light-emitting element 12 are located in the same film layer, and the fourth segment 524 is located in the metal layer on the side of the anode of the second light-emitting element 12 facing the substrate.

[0223] In the embodiment of the present application, since the second segment 512 and the fourth segment 524 are located in the metal layer below the anode, the length of the connecting wire in the anode film layer can be reduced. Moreover, the connecting wire in the metal layer is less constrained by the anode, and the routing of the connecting wire can be arranged in a manner of connecting nearby. The second segment 512 and the fourth segment 524 do not need to meander excessively due to the constraint of the anode, thereby reducing the total length of the first connecting wire and the total length of the second connecting wire. In addition, the problem of short circuit caused by directly running the wire at the anode can be avoided.

[0224] For example, please refer to Figure 43 and Figure 44 For the (i+1)th first unit column 10a and the (i+3)th first unit column 10a, a connection line for connecting the second light-emitting element 12 and the second pixel circuit may be provided only on the anode film layer. For the (i)th first unit column 10a and the (i+2)th first unit column 10a, a connection line for connecting the first light-emitting element 11 and the first pixel circuit may be provided only on the anode film layer.

[0225] In other embodiments, Figure 5 The driver architecture shown can also be Figures 46 to 49 The design shown is implemented. For example, Figures 46 to 49 The cross-sectional structure of the display panel corresponding to the structure shown can also be as follows Figure 18 As shown, Figure 48 The structure in the layout shown is located in Figure 18 The second metal layer SD2 shown, Figure 49 The structure in the layout shown is located in Figure 18 The third metal layer SD3 is shown.

[0226] Figures 46 to 49 The structure shown is Figures 37 to 40 The similarities of the structures shown are not described in detail here, and the differences include: the routing of the second metal layer and the third metal layer are interchanged. Figures 37 to 40 In the structure shown, the wiring extending in the first direction X is set in the second metal layer SD2, and the wiring extending in the second direction Y is set in the third metal layer SD3. Figures 46 to 49In the structure shown, the wiring extending in the first direction X is arranged in the third metal layer SD3, and the wiring extending in the second direction Y is arranged in the second metal layer SD2.

[0227] For example, Figure 48 The third metal layer SD3 has a layout structure. The third metal layer SD3 includes data lines 31 - 33 extending along the first direction, power branch lines 611 , 623 , 635 , and traces 91 , 92 . Figure 49 This is the layout structure of the second metal layer SD2. The second metal layer SD2 includes power branch lines 612 and 624 extending along the second direction, a trace 72, and the like.

[0228] in addition, Figures 46 to 49 In the example, the first light emitting element 11 in the (i+1)th and (i+3)th first unit columns 10a needs to be designed with a “pull line”. Here, “pull line” refers to the following: Figure 46 、 Figure 49 The second segment 512 is shown. If a "pull wire" is not designed for the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a, the voltage drops (or loading) corresponding to different first light-emitting elements 11 will be different, affecting the display uniformity. To address this, a compensation line 54 can be provided for the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a. The compensation line 54 is connected to the first via hole of the first light-emitting element 11 in the (i)th and (i+2)th first unit columns 10a. Exemplarily, the other end of the compensation line 54 is left floating. The compensation line 54 is provided on the same layer as the second segment 512 located on the metal layer.

[0229] In other embodiments, Figure 5 The driver architecture shown can also be Figures 50 to 53 The design shown is implemented. For example, Figures 50 to 53 The cross-sectional structure of the display panel corresponding to the structure shown can also be as follows Figure 18 As shown, Figure 52 The structure in the layout shown is located in Figure 18 The second metal layer SD2 shown, Figure 53 The structure in the layout shown is located in Figure 18 The third metal layer SD3 is shown.

[0230] Figures 50 to 53 The structure shown is Figures 37 to 40 The similarities of the structures shown are not described in detail here, and the differences include: the routing of the second metal layer and the third metal layer are interchanged. Figures 37 to 40 In the structure shown, the wiring extending in the first direction X is set in the second metal layer SD2, and the wiring extending in the second direction Y is set in the third metal layer SD3. Figures 50 to 53In the structure shown, the wiring extending in the first direction X is arranged in the third metal layer SD3, and the wiring extending in the second direction Y is arranged in the second metal layer SD2.

[0231] For example, Figure 52 The third metal layer SD3 has a layout structure. The third metal layer SD3 includes data lines 31 - 33 extending along the first direction, power branch lines 611 , 623 , 635 , and traces 91 , 92 . Figure 53 This is the layout structure of the second metal layer SD2. The second metal layer SD2 includes power branch lines 612 and 624 extending along the second direction, a trace 72, and the like.

[0232] In some embodiments, please refer to Figure 5 as well as Figures 50 to 53 The first light emitting element 11 is electrically connected to the first pixel circuit 21 through the first via 41, and the second light emitting element 12 is electrically connected to the second pixel circuit 22 through the second via 42. In addition, the third light emitting element 13 is electrically connected to the third pixel circuit 23 through the third via 43.

[0233] In the second direction Y, the first via 41 of any first unit column 10 a is located on a first side of the first unit column 10 a , and the second via 42 is located on a second side of the first unit column 10 a .

[0234] For example, for the (i)th and (i+2)th first unit columns 10a, the first vias 41 are on the left side, and the second vias 42 are on the right side. For the (i+1)th and (i+3)th first unit columns 10a, the first vias 41 are on the right side, and the second vias 42 are on the left side.

[0235] Exemplarily, in the first direction X, the third via holes 43 are all on the same side of the third light-emitting elements 13 to which they are connected.

[0236] Please refer to Figure 51 In this embodiment, it is possible to avoid the vias corresponding to the first unit column 10a being distributed on the same side, which would cause the vias to be too dense. If the vias are too dense, they would occupy more layout space, which would be detrimental to improving pixel density. Therefore, the embodiment of the present application is conducive to improving pixel density and can improve signal interference between different vias.

[0237] As can be seen from the attached figure, Figures 50 to 53 The structure shown and Figures 46 to 49 In the structure shown, the distribution patterns of the second and third vias are the same, and the differences include: the distribution patterns of the first vias 41 in the (i)th and (i+2)th first unit columns 10a are different. Figures 46 to 49In the structure shown, the first via holes 41 of the (i)th and (i+2)th first unit columns 10a are both located on the left side of the first light emitting elements connected thereto. Figures 50 to 53 In the structure shown, the first via holes 41 of the (i)th and (i+2)th first unit columns 10a are both located on the right side of the first light emitting elements connected thereto.

[0238] The first pixel circuit to be connected to the first light-emitting element of the (i)th and (i+2)th first unit columns 10a is on its left side. When the first via 41 of the (i)th and (i+2)th first unit columns 10a is moved to the right side of the first light-emitting element to which it is connected, the distance between the first via 41 and the first pixel circuit to which it is electrically connected will increase. In this case, the length of the connecting line between the two can be lengthened.

[0239] In some embodiments, please refer to Figure 51 and Figure 53 The first light-emitting element 11 is electrically connected to the first pixel circuit via a first connecting line 51. The length of the first connecting line 51 between the first via 41 and the first pixel circuit in the second direction Y is L1. The width of the pixel circuit of the display panel in the second direction Y is L2, and 3*L2≤L1≤4*L2. The first, second, and third pixel circuits have the same width in the second direction. The width of the first, second, and third circuit columns in the second direction Y is approximately L2.

[0240] In this embodiment, the first connecting line 51 may also include a first segment 511 and a second segment 512. The first segment 511 is connected between the anode of the first light-emitting element 11 and the first end of the first via 41, and the second segment 512 is connected between the second end of the first via 41 and the first pixel circuit. The first segment 511 and the anode of the first light-emitting element 11 are located in the same film layer, and the second segment 512 is located in the metal layer on the side of the anode of the first light-emitting element 11 facing the substrate. In this embodiment, the second segment 512 is located in the second metal layer.

[0241] The length of the second segment 512 in the second direction Y is L1. Figure 52 As shown, in the second direction Y, the second segment 512 needs to span approximately 3 to 4 circuit rows.

[0242] In other embodiments, Figure 5 The driver architecture shown can also be Figures 54 to 57 The design shown is implemented. For example, Figures 54 to 57 The cross-sectional structure of the display panel corresponding to the structure shown can also be as follows Figure 18 As shown, Figure 56 The structure in the layout shown is located in Figure 18 The second metal layer SD2 shown, Figure 57The structure in the layout shown is located in Figure 18 The third metal layer SD3 is shown.

[0243] Figures 54 to 57 The structure shown is Figures 37 to 40 The similarities of the structures shown are not described in detail here, and the differences include: the routing of the second metal layer and the third metal layer are interchanged. Figures 37 to 40 In the structure shown, the wiring extending in the first direction X is set in the second metal layer SD2, and the wiring extending in the second direction Y is set in the third metal layer SD3. Figures 54 to 57 In the structure shown, the wiring extending in the first direction X is arranged in the third metal layer SD3, and the wiring extending in the second direction Y is arranged in the second metal layer SD2.

[0244] For example, Figure 56 The third metal layer SD3 has a layout structure. The third metal layer SD3 includes data lines 31 - 33 extending along the first direction, power branch lines 611 , 623 , 635 , and traces 91 , 92 . Figure 57 This is the layout structure of the second metal layer SD2. The second metal layer SD2 includes power branch lines 612 and 624 extending along the second direction, a trace 72, and the like.

[0245] In some embodiments, please refer to Figure 5 as well as Figures 54 to 57 The first light emitting element 11 is electrically connected to the first pixel circuit 21 through the first via 41, and the second light emitting element 12 is electrically connected to the second pixel circuit 22 through the second via 42. In addition, the third light emitting element 13 is electrically connected to the third pixel circuit 23 through the third via 43.

[0246] In the second direction Y, the first via holes 41 and the second via holes 42 of any first unit column 10 a are distributed on the same side of the first unit column 10 a.

[0247] For example, for the (i)th, (i+1)th, (i+2)th, and (i+3)th first unit columns 10 a , the first via holes 41 and the second via holes 42 are both on the left side.

[0248] Exemplarily, in the first direction X, the third via holes 43 are all on the same side of the third light-emitting elements 13 to which they are connected.

[0249] Please refer to Figure 55 In this embodiment, it is also possible to avoid the vias corresponding to the first unit column 10a being distributed on the same side, resulting in the vias being too dense. If the vias are too dense, they will occupy more layout space, which is not conducive to improving pixel density. Therefore, the embodiment of the present application is conducive to improving pixel density and can improve signal interference between different vias.

[0250] As can be seen from the attached figure, Figure 54 Figure 57 Show structure and Figures 46 to 49 The distribution patterns of the first and third vias in the structure shown are the same, and the differences include: the distribution pattern of the second via 42 is different. Figure 49 In the structure shown, the second vias 42 of the (i)th and (i+2)th first unit columns 10a are both on the right side of the second light-emitting elements to which they are connected, and the second vias 42 of the (i+1)th and (i+3)th first unit columns 10a are both on the left side of the second light-emitting elements to which they are connected. Figures 50 to 53 In the structure shown, the second via holes 42 of each first unit column 10 a are all located on the left side of the first light emitting element connected thereto.

[0251] The second pixel circuit to which the second light-emitting element in the (i)th and (i+2)th first unit columns 10a is connected is located to the right of the second light-emitting element. If the second via 42 in the (i)th and (i+2)th first unit columns 10a is moved to the left of the second light-emitting element to which it is connected, the distance between the second via 42 and the second pixel circuit to which it is electrically connected increases. In this case, the length of the connecting wire between the second via 42 and the second pixel circuit can be increased. Furthermore, connecting wires are also required to connect the first light-emitting element in the (i+1)th and (i+3)th first unit columns 10a to the first pixel circuit to which it is connected.

[0252] In some embodiments, please refer to Figure 55 and Figure 57 The first light-emitting element 11 is electrically connected to the first pixel circuit through the first connecting line 51, and the second light-emitting element 12 is electrically connected to the second pixel circuit through the second connecting line 52. The first connecting line 51 and the second connecting line 52 do not overlap.

[0253] In this embodiment, the first connecting line 51 may include a first section 511 and a second section 512, the first section 511 is connected between the anode of the first light-emitting element 11 and the first end of the first via 41, and the second section 512 is connected between the second end of the first via 41 and the first pixel circuit, the first section 511 and the anode of the first light-emitting element 11 are located in the same film layer, and the second section 512 is located in the metal layer on the side of the anode of the first light-emitting element 11 facing the substrate.

[0254] The second connecting line 52 includes a third section 523 and a fourth section 524. The third section 523 is connected between the anode of the second light-emitting element 12 and the first end of the second via 42. The fourth section 524 is connected between the second end of the second via 42 and the second pixel circuit. The third section 523 and the anode of the second light-emitting element 12 are located in the same film layer. The fourth section 524 is located in the metal layer on the side where the anode of the second light-emitting element 12 faces the substrate.

[0255] In this embodiment, the second segment 512 and the fourth segment 524 are located in the second metal layer.

[0256] The first segment 511 and the third segment 523 do not overlap, and the second segment 512 and the fourth segment 524 do not overlap.

[0257] In this embodiment, the lengths of the second segment 512 and the fourth segment 524 in the second direction Y are substantially equal. The lengths of the second segment 512 and the fourth segment 524 in the second direction Y are substantially equal to twice the width L2 of the pixel circuit.

[0258] In some embodiments, as Figure 54 As shown, the third light emitting element 13 is electrically connected to the third pixel circuit through the third via 43. Any third via 43 is on the same side of the connected third light emitting element 13. In other words, the distribution pattern of multiple third vias in the entire display panel is the same.

[0259] For example, Figure 6 、 Figure 31 、 Figure 37 、 Figure 46 、 Figure 50 、 Figure 54 As shown, in the first direction X, any third via hole 43 is located at the lower side of the third light emitting element 13 to which it is connected.

[0260] For example, Figure 20 、 Figure 41 As shown, in the second direction Y, any third via hole 43 is located on the left side of the third light emitting element 13 to which it is connected.

[0261] For example, Figure 59 As shown, in the first direction X, any third via hole 43 is located on the upper side of the third light emitting element 13 to which it is connected.

[0262] For example, Figure 6 、 Figure 31 、 Figure 37 、 Figure 46 、 Figure 50 、 Figure 54 The display panels shown are all LTPO type display panels. Figure 20 、 Figure 41 The display panels shown are all LTPS type display panels. Figure 59 The display panel shown is an LTPS type display panel, but this is not intended to limit the present application.

[0263] It should be noted that Figures 3 to 57In the drawings showing the light-emitting elements, the first light-emitting element 11 is a red light-emitting element and the second light-emitting element 12 is a blue light-emitting element for illustration, which is not intended to limit the present application. In other examples, for example, the first light-emitting element 11 is a blue light-emitting element and the second light-emitting element 12 is a red light-emitting element.

[0264] In some embodiments, the Figure 58 The design shown is to realize that light emitting elements of different colors are included in the same column of units, and light emitting elements of the same color are connected through data lines.

[0265] like Figure 58 As shown, a first light emitting element 11 , a second light emitting element 12 and a third light emitting element 13 adjacent to each other constitute an element unit 101 , and a plurality of element units 101 are arrayed in the first direction X and the second direction Y.

[0266] The first light-emitting element 11 is electrically connected to the first pixel circuit 21 through the first via 41, the second light-emitting element 12 is electrically connected to the second pixel circuit 22 through the second via 42, and the third light-emitting element 13 is electrically connected to the third pixel circuit 23 through the third via 43; in the first direction X, the first via 41, the second via 42, and the third via 43 of the element unit 101 are located on the same side of the element unit 101.

[0267] For example, Figure 58 In the embodiment, the first via hole 41 , the second via hole 42 , and the third via hole 43 are located on the upper side of the element unit 101 .

[0268] As an example, Figure 58 In the embodiment, the first light emitting element 11 is a red light emitting element, the second light emitting element 12 is a green light emitting element, and the third light emitting element 13 is a blue light emitting element. Figure 58 The red and green light emitting elements are interchangeable.

[0269] In some embodiments, as Figure 58 As shown, the adjacent first unit column 10a and the second unit column 10b constitute a second unit column group, and each second unit column group is correspondingly provided with three columns of pixel circuits.

[0270] For example, the (i)th first unit column 10a and the (j)th second unit column 10b constitute the second unit column group 10_3, and the 1st first circuit column 20a1, the 1st second circuit column 20b1, and the 1st third circuit column 20c1 are used to drive the (i)th first unit column 10a and the (j)th second unit column 10b. That is, the three columns of pixel circuits corresponding to the second unit column group 10_3 are distributed as follows: the 1st first circuit column 20a1, the 1st second circuit column 20b1, and the 1st third circuit column 20c1.

[0271] The (i+1)th first unit column 10a and the (j+1)th second unit column 10b constitute the second unit column group 10_4, and the second first circuit column 20a2, the second second circuit column 20b2, and the second third circuit column 20c2 are used to drive the (i+1)th first unit column 10a and the (j+1)th second unit column 10b. That is, the three columns of pixel circuits corresponding to the second unit column group 10_4 are distributed as follows: the second first circuit column 20a2, the second second circuit column 20b2, and the second third circuit column 20c2.

[0272] In this embodiment, if the total number of first unit columns and second unit columns is 2n, the total number of pixel circuit columns is 3n. Thus, in the second direction Y, the total width of the first unit columns and the second unit columns is approximately equal to the total width of three pixel circuit columns, thereby increasing the light-emitting area of ​​the light-emitting element.

[0273] In some embodiments, please refer to Figures 58 to 61 The anode of the second light-emitting element 12 is electrically connected to the second via 42 through a second connecting wire 52 . In a direction parallel to the light-emitting surface of the display panel, the second connecting wire 52 is located between the first light-emitting element 11 and the third light-emitting element 13 .

[0274] Exemplarily, the second connecting line 52 and the anode of the second light-emitting element 12 are located in the same film layer.

[0275] For the first light emitting element 11 , there is almost no need to provide a connecting wire between its anode and the first pixel circuit 21 , but they can be directly connected through the first via hole 41 .

[0276] As for the third light emitting element 13 , the distance between its anode and the third via hole 43 is also relatively short. Therefore, the length of the connection line between the anode of the third light emitting element 13 and the third via hole 43 can be relatively short.

[0277] Compared with the first and third light-emitting elements, the anode of the second light-emitting element 12 is farther away from the second via hole 42 . Therefore, a relatively long second connecting line may be provided to connect the second light-emitting element 12 and the second via hole 42 .

[0278] Figures 62 to 67 Shows the implementation Figure 58 The layout structures of some other film layers in the design shown are as follows: Figures 59 to 69 As shown in FIG, the display panel includes a semiconductor layer. Figure 68 As shown, the display panel includes a first semiconductor layer B1. For example, the material of the first semiconductor layer B1 includes LTPS, such as Figure 30As shown, each transistor of the pixel circuit is an LTPS transistor. In this embodiment, the structures of the first pixel circuit, the second pixel circuit and the third pixel circuit can be as follows: Figure 69 As shown, in Figure 69 In the structure shown, the pixel circuit includes six transistors and one capacitor, wherein the first electrode of the driving transistor M13 is connected to the power line PVDD.

[0279] In some embodiments, please refer to Figure 65 and Figure 69 The pixel circuit of the display panel includes a driving transistor M13 and a power line PVDD electrically connected to the driving transistor M13, and there is no connection between the active layers M13-p of adjacent driving transistors. Figure 65 In FIG, the active layer of the driving transistor in a pixel circuit is selected by a dotted box.

[0280] It can be understood that this example lays the foundation for realizing that light-emitting elements of different luminous colors are powered by different power lines.

[0281] It should be noted that there is no connection between the active layers M13-p of adjacent driving transistors, which means that there is no overlapping "semiconductor part" between the active layers M13-p of adjacent driving transistors, and the "semiconductor part" refers to the structure on the same layer as the active layer of the driving transistor.

[0282] For example, Figure 65 As shown, in the first semiconductor layer, the active layer M13 - p of the driving transistor is disconnected from the active layers of other transistors, and the active layers M13 - p of different driving transistors are disconnected from each other.

[0283] It should also be noted that although this application is only Figures 58 to 69 The corresponding example points out that: in the film layer where the active layer of the driving transistor is located, the active layer of the driving transistor is disconnected from the active layers of other transistors, and the active layers of different driving transistors are disconnected. This is not used to limit the present application. For example, in Figures 3 to 57 In any of the examples in the accompanying drawings, this can also be done. Figures 3 to 57 In any example corresponding to any of the figures, in the film layer where the active layer of the driving transistor is located, the active layer of the driving transistor may not be disconnected from the active layers of other transistors.

[0284] Please refer to Figure 62 and Figure 69In the same pixel circuit, the driving transistor M13 needs to be connected to other transistors. For example, the gate of the driving transistor M13 is connected to the first connection part N11, and the second electrode of the driving transistor M13 is connected to the third connection part N13. The first connection part N11 and the third connection part N13 are arranged on the metal layer. Figure 8 In addition, the other end of the capacitor Cst is connected to the second connection portion N12, which is located at Figure 8 The first metal layer SD1 is shown.

[0285] in addition, Figure 61 The layout structure shown is located in Figure 68 The anode layer RE shown, Figure 62 The layout structure shown is located in Figure 68 The first metal layer SD1 shown, Figure 63 The layout structure shown is located in Figure 68 The capacitor metal layer MC shown, Figure 64 The layout structure shown is located in Figure 68 The first gate layer GAT shown, Figure 65 The layout structure shown is located in Figure 68 The first semiconductor layer B1 shown, Figure 67 The layout structure shown is located in Figure 68 The auxiliary metal layer M0 is shown.

[0286] In some embodiments, as Figures 37 to 40 The example shown, or Figures 46 to 49 The example shown, or Figures 50 to 53 In the example shown, for some light-emitting elements, a "wire pulling" design is required on the metal layer to achieve the connection between the light-emitting element and the pixel circuit.

[0287] Specifically, Figure 47 and Figure 48 For explanation, the light-emitting element is electrically connected to the pixel circuit through a via. For the first light-emitting element 11 in the (i+1)th and (i+3)th first unit columns 10a, a "pull wire" design is required. The connecting vias between these first light-emitting elements 11 and the first pixel circuit are called first sub-vias 411, and the first connecting line between the first light-emitting element 11 and the first pixel circuit includes a second segment 512. In the thickness direction of the display panel, the first sub-via 411 and the first pixel circuit electrically connected thereto do not overlap. One end of the first sub-via 411 extends to the film layer where the anode of the first light-emitting element 11 is located, and the other end of the first sub-via 411 extends to the metal layer where the second segment 512 is located. The other end of the first sub-via 411 is connected to one end of the second segment 512, and the other end of the second segment 512 is electrically connected to the first pixel circuit.

[0288] In some embodiments, the light-emitting element is electrically connected to the pixel circuit through a via, and the via includes a first sub-via, and the first sub-via has no overlap with the pixel circuit electrically connected to it; the display panel also includes a connecting line, one end of the connecting line is connected to the first sub-via, and the other end is connected to the pixel circuit.

[0289] Still Figure 47 and Figure 48 For illustration, the display panel includes power branch lines extending along the second direction Y, such as the second power branch line 612 and the fourth power branch line 624. "Wire drawing" can be performed on the film layer where the second power branch line 612 and the fourth power branch line 624 are located. In other words, at least some segments of the connecting line between the light-emitting element and the pixel circuit are arranged on the same layer as the power branch lines extending in the second direction.

[0290] In this embodiment, although an additional "pull wire" design is required, the "pull wire" is set on the same layer as the power branch line, so there is no need to add an additional film layer, which is beneficial to taking into account the lightness and thinness of the display panel.

[0291] In some embodiments, the via includes a second sub-via, and the second sub-via at least partially overlaps with the pixel circuit electrically connected thereto; the display panel further includes a compensation line, one end of the compensation line is connected to the second sub-via.

[0292] Still Figure 47 and Figure 48 For illustration, for the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a, no "pull wire" design is required. The "pull wire" here refers to the connection wire used to connect the light-emitting element and the pixel circuit. The connection vias between these first light-emitting elements 11 and the first pixel circuit are called second sub-vias 412. One end of the second sub-via 412 extends to the film layer where the anode of the first light-emitting element 11 is located, and the other end of the second sub-via 412 extends to the film layer where the first pixel circuit is located. The other end of the second sub-via 412 is connected to the first pixel circuit.

[0293] In the thickness direction of the display panel, the second sub-via 412 at least partially overlaps the first pixel circuit to which it is electrically connected. In the metal layer where the second segment 512 is located, the other end of the first sub-via 411 is connected to one end of the second segment 512, and the other end of the second segment 512 is electrically connected to the first pixel circuit.

[0294] For the first light-emitting elements 11 in the (i+1)th and (i+3)th first unit columns 10a, a "pulling wire" design is required. For the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a, a "pulling wire" design is not required. The "pulling wire" here refers to the connecting wire used to connect the light-emitting element and the pixel circuit. In this way, the lengths of the connecting wires for different first light-emitting elements 11 are different, resulting in different voltage drops (or loading) corresponding to different first light-emitting elements 11, affecting display uniformity.

[0295] To this end, a compensation line 54 may be further provided for the first light emitting elements 11 in the (i)th and (i+2)th first unit columns 10 a , with one end of the compensation line 54 connected to the second sub-via 412 .

[0296] For example, the overall impedance of the compensation line 54 and the overall impedance of the second segment 512 may be substantially equal.

[0297] In some embodiments, the compensation line and the connection line of the metal layer are in the same film layer.

[0298] Still Figure 47 and Figure 48 For example, for the first light-emitting elements 11 in the (i)th and (i+2)th first unit columns 10a, the compensation line 54 and the second segment 512 are located in the same film layer. In this embodiment, although an additional "compensation line" design is required, the "compensation line" and the metal layer connection line or the anode of the light-emitting element are designed in the same film layer. This eliminates the need for additional film layers and facilitates a thinner and lighter display panel.

[0299] In some embodiments, the other end of the compensation line is suspended, thereby preventing other signals from crosstalking or interfering with the light-emitting element connected to the compensation line.

[0300] For example, Figure 48 In the embodiment, one end of the compensation line 54 is connected to the second sub-via 412, and the other end is left floating. "Left floating" means that the other end of the compensation line is not connected to other structures.

[0301] In order to provide the current source required for the light-emitting element to emit light, a power line PVDD and a common voltage line PVEE need to be set. The pixel circuit and the light-emitting element are connected in series between the power line PVDD and the common voltage line PVEE. When the pixel circuit electrically connects the light-emitting element and the power line PVDD, the light-emitting element can emit light.

[0302] A light-emitting element and its electrically connected pixel circuit constitute a subpixel. For example, the first light-emitting element and the first pixel circuit constitute a first subpixel, the second light-emitting element and the second pixel circuit constitute a second subpixel, and the third light-emitting element and the third pixel circuit constitute a third subpixel. The subpixels are connected between a power line PVDD and a common voltage line PVEE.

[0303] In related art, sub-pixels of different colors share a power line PVDD and a common voltage line PVEE. However, the voltages required between the power line PVDD and the common voltage line PVEE for sub-pixels of different colors can differ. In a design where the power line PVDD is shared, the voltage between the power line PVDD and the common voltage line PVEE must cover the maximum voltage required by each sub-pixel to ensure that all sub-pixels of each color operate in their saturation region. This results in unnecessary power consumption for sub-pixels requiring smaller voltages.

[0304] In the embodiment of the present application, while the data lines of the light-emitting elements of each color are independent, the power lines PVDD of the light-emitting elements of each color are also designed to be independent to further save power consumption.

[0305] Figures 6 to 69 In the examples shown, the power lines PVDD of the light-emitting elements of at least two colors are designed independently. The independent design of the power line PVDD is exemplarily described below using some drawings.

[0306] In some embodiments, please refer to Figure 7 、 Figure 9 、 Figure 10 The display panel further includes a power supply line PVDD, which includes at least a first power supply line 61 and a second power supply line 62. The first power supply line 61 is electrically connected to the first light-emitting element 11 and includes a first power branch line 611 and a second power branch line 612 electrically connected to each other. The first power branch line 611 extends along the first direction X, and the second power branch line 612 extends along the second direction Y. The second power supply line 62 is electrically connected to the second light-emitting element 12 and includes a third power branch line 623 and a fourth power branch line 624 electrically connected to each other. The third power branch line 623 extends along the first direction X, and the fourth power branch line 624 extends along the second direction Y.

[0307] For example, the first power branch line 611 and the second power branch line 612 may be located in different film layers and connected via vias. The third power branch line 623 and the fourth power branch line 624 may be located in different film layers and connected via vias.

[0308] It should be noted that the first power line 61 and the second power line 62 are not connected. In this way, when the voltages required by the first light-emitting element and the second light-emitting element are different, different power supply voltages can be provided respectively through the first power line 61 and the second power line 62. In this way, there is no need to set a large voltage across to cover the voltages required by all light-emitting elements, thereby saving power consumption of the display panel.

[0309] In addition, the first power branch line 611 and the second power branch line 612 extend in different directions and are electrically connected to each other. Multiple first power branch lines 611 and multiple second power branch lines 612 can form a grid-like first power line 61, thereby reducing the voltage drop of the first power line 61 and improving display uniformity.

[0310] Similarly, the third power branch line 623 and the fourth power branch line 624 extend in different directions and are electrically connected to each other. Multiple third power branch lines 623 and multiple fourth power branch lines 624 can form a grid-like second power line 62, thereby reducing the voltage drop of the second power line 62 and improving display uniformity.

[0311] For example, only the first power branch line 611 and the third power branch line 623 are alternately distributed in the second direction Y. Only the second power branch line 612 and the fourth power branch line 624 are alternately distributed in the first direction X. In this way, the area covered by a single grid of the first power line 61 and a single grid of the second power line 62 can be substantially the same, thereby reducing the voltage drop difference between the first power line 61 and the second power line 62.

[0312] In some embodiments, please refer to Figure 7 、 Figure 9 、 Figure 10 , or, please refer to Figure 62 and Figure 63 The display panel also includes a power line PVDD, which also includes a third power line 63. The third power line 63 is electrically connected to the third light-emitting element 13. The third power line 63 includes a fifth power branch line 635 and a sixth power branch line 636 that are electrically connected to each other. The fifth power branch line 635 extends along the first direction X, and the sixth power branch line 636 extends along the second direction Y.

[0313] One of the second power branch line and the fourth power branch line is electrically connected to the sixth power branch line.

[0314] As an example, please refer to Figure 7 、 Figure 9 、 Figure 10The second power branch line 612 and the sixth power branch line 636 can be the same line, that is, the line serves as both the second power branch line 612 and the sixth power branch line 636. This example reduces the number of power branches extending in the second direction, freeing up layout space. It is understood that in this example, the first and third light-emitting elements share a power signal.

[0315] It should be noted that Figures 6 to 57 Although the layout diagram in FIG. 1 shows that the second power branch line 612 and the sixth power branch line 636 are the same line, this is not applicable to the present application. For example, in other examples, the fourth power branch line 624 and the sixth power branch line 636 are the same line, or the second power branch line 612 and the sixth power branch line 636 are two lines connected to each other, or the second fourth power branch line 624 and the sixth power branch line 636 are two lines connected to each other.

[0316] As another example, refer to Figure 62 and Figure 63 The second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 are independent of each other. In other words, the second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 are not connected to each other, and the power lines of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all independent of each other, which can more flexibly match the voltage requirements of each light-emitting element.

[0317] It should be noted that Figure 63 Shows the layout structure corresponding to 6 rows of pixel circuits, Figures 58 to 62 ,as well as Figures 64 to 67 The layout structure of 2 rows of pixel circuits is shown.

[0318] Exemplarily, when the second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 are independent of each other, each second power branch line 612, a fourth power branch line 624, and a sixth power branch line 636 constitute a line group, and multiple such line groups are arranged in the first direction X.

[0319] It should be noted that Figures 6 to 57 In the layout diagram in , the second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 can also be designed in a manner that they are independent of each other.

[0320] In some embodiments, as Figure 7 、 Figure 21 、 Figure 32 、 Figure 37 、 Figure 42 、 Figure 46 、 Figure 50 、 Figure 54As shown, one of the first light-emitting element 11 and the second light-emitting element 12 is a red light-emitting element, the other is a blue light-emitting element, and the third light-emitting element 13 is a green light-emitting element; the first power branch line 611, the fifth power branch line 635, the third power branch line 623, and the fifth power branch line 635 constitute a first line group, and multiple first line groups are arranged in the second direction Y.

[0321] That is to say, in the second direction Y, the arrangement pattern of the power branch lines is: a first power branch line 611, a fifth power branch line 635, a third power branch line 623, a fifth power branch line 635, then, a first power branch line 611, a fifth power branch line 635, a third power branch line 623, a fifth power branch line 635, and so on.

[0322] In the second direction Y, the circuit rows are arranged in the following order: a first circuit row 20a, a third circuit row 20c, a second circuit row 20b, a third circuit row 20c, then a first circuit row 20a, a third circuit row 20c, a second circuit row 20b, a third circuit row 20c, and so on.

[0323] In the second direction Y, the arrangement pattern of the power branch lines matches the arrangement order of the circuit columns. Each circuit column is correspondingly arranged with a power branch line extending along the first direction. In this way, while achieving the independence of the power lines PVDD of light-emitting elements of different colors, each circuit column can be connected to its corresponding power line nearby. In this way, there is no need to set up additional wiring for connection between the power lines and the pixel circuits.

[0324] In other embodiments, please refer to Figure 60 and Figure 62 One of the first light-emitting element 11 and the third light-emitting element 13 is a red light-emitting element, the other is a blue light-emitting element, and the second light-emitting element 12 is a green light-emitting element; the first power branch line 611, the third power branch line 623, and the fifth power branch line 635 constitute a second line group, and multiple second line groups are arranged in the second direction Y.

[0325] That is to say, in the second direction Y, the arrangement pattern of the power branch lines is: a first power branch line 611, a third power branch line 623, a fifth power branch line 635, then a first power branch line 611, a third power branch line 623, a fifth power branch line 635, and so on.

[0326] In the second direction Y, the circuit rows are arranged in the following order: a first circuit row 20a, a second circuit row 20b, a third circuit row 20c, then a first circuit row 20a, a second circuit row 20b, a third circuit row 20c, and so on.

[0327] Similarly, in this example, in the second direction Y, the arrangement pattern of the power branch lines matches the arrangement order of the circuit columns, and each circuit column is correspondingly arranged with a power branch line extending along the first direction. In this way, while achieving the independence of the power lines PVDD of light-emitting elements of different colors, each circuit column can be connected to its corresponding power line nearby, so that there is no need to set up additional wiring for connection between the power lines and the pixel circuits.

[0328] In some embodiments, the plurality of pixel circuits of the display panel are arranged in n1 rows; the total number of the second power branch line, the fourth power branch line, and the sixth power branch line is n2; n1=n2. Both n1 and n2 are integers greater than 1.

[0329] For example, Figure 7 、 Figure 21 、 Figure 32 、 Figure 37 、 Figure 42 、 Figure 46 、 Figure 50 、 Figure 54 As shown, for every two adjacent pixel circuit rows, one pixel circuit row is correspondingly provided with a second power branch line 612 and a sixth power branch line 636 , and the other pixel circuit row is correspondingly provided with a fourth power branch line 624 .

[0330] In some other embodiments, the plurality of pixel circuits of the display panel are arranged in n1 rows; the total number of the second power branch line, the fourth power branch line, and the sixth power branch line is n2; n1=2*n2. Both n1 and n2 are integers greater than 1.

[0331] For example, for every two adjacent pixel circuit rows, two second power branch lines, one fourth power branch line, and one sixth power branch line may be provided.

[0332] In some embodiments, please refer to Figure 20 、 Figure 24 and Figure 25 The first power line 61 further includes a seventh power branch line 617 , which extends along the first direction X. The seventh power branch line 617 is electrically connected to the first power branch line 611 and is located in a different film layer.

[0333] The second power line 62 further includes an eighth power branch line 628 . The eighth power branch line 628 extends along the first direction X. The eighth power branch line 628 is electrically connected to the third power branch line 623 and is located in a different film layer.

[0334] The third power line 63 further includes a ninth power branch line 639 . The ninth power branch line 639 extends along the first direction X. The ninth power branch line 639 is electrically connected to the fifth power branch line 635 and is located in a different film layer.

[0335] This example is equivalent to increasing the grid density of the first power line 61 , the second power line 62 , and the third power line 63 , which can further reduce the voltage drop corresponding to each power line, thereby further improving display uniformity.

[0336] Exemplarily, the seventh power branch line 617, the eighth power branch line 628, and the ninth power branch line 639 are located on the first metal layer SD1. In this example, the first metal layer SD1 is also provided with reset lines extending along the first direction X. The reset lines include, for example, a first reset line Vref1 and a second reset line Vref2. For example, a power branch line is provided between every two reset lines.

[0337] For example, in the thickness direction of the display panel, the seventh power branch 617 at least partially overlaps with the first power branch 611, and / or the eighth power branch 628 at least partially overlaps with the third power branch 623, and / or the ninth power branch 639 at least partially overlaps with the fifth power branch 635. In this way, electrical connection between the corresponding power branches can be achieved through vias without setting up additional connecting lines, which can realize a dual longitudinal power branch design without occupying additional layout area, that is, it will not affect the realization of high resolution.

[0338] For example, the first reset line Vref1 and / or the second reset line Vref2 may also be designed in a grid pattern. Figure 10 In the embodiment, at least part of the second trace 92 can be reused as the first reset line Vref1. Figure 14 As shown, the capacitor metal layer includes a first reset line Vref1 extending along the second direction Y. Figure 10 and Figure 14 The first reset lines Vref1 in the circuit are electrically connected to each other, realizing a grid design of the first reset lines Vref1.

[0339] For example, Figure 10 In the embodiment, at least part of the second trace 92 can be reused as the second reset line Vref2. Figure 14 As shown, the capacitor metal layer includes a second reset line Vref2 extending along the second direction Y. Figure 10 and Figure 14 The second reset lines Vref2 in the circuit are electrically connected to each other, realizing a grid design of the second reset lines Vref2.

[0340] In some embodiments, the first power branch line, the third power branch line and the fifth power branch line are located in the first film layer of the display panel; and the first film layer includes the data line of the display panel; the second power branch line, the fourth power branch line and the sixth power branch line are located in the second film layer of the display panel; the first film layer and the second film layer are both film layers on the side of the semiconductor layer of the display panel facing the light-emitting surface.

[0341] That is, the first power branch line, the third power branch line, the fifth power branch line, and the data line are located in the same first film layer, the second power branch line, the fourth power branch line, and the sixth power branch line are located in the same second film layer, and the first film layer and the second film layer are different metal layers. The semiconductor layer is provided with an active layer of a transistor, and the active layer may undergo characteristic shifts under the influence of light. In the embodiment of the present application, the traces within the first film layer and the second film layer can block light from shining on the active layer within the semiconductor layer, thereby preventing characteristic shifts in the active layer due to light exposure, thereby improving the circuit reliability of the display panel.

[0342] The display panel may include one or more semiconductor layers, and the first film layer and the second film layer are located on a side of any semiconductor layer facing the light emitting surface.

[0343] As an example, Figure 9 、 Figure 10 As shown, in addition, Figure 23 、 Figure 24 In the example shown, Figure 39 、 Figure 40 In the example shown, Figure 44 、 Figure 43 In the example shown, the signal lines are located in the following film layers: the first power branch line 611, the third power branch line 623, the fifth power branch line 635, and the first data line 31, the second data line 32, and the third data line 33 are located in the second metal layer SD2. The second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 are located in the third metal layer SD3.

[0344] As another example, Figure 34 、 Figure 35 As shown, in addition, Figure 48 、 Figure 49 In the example shown, Figure 52 、 Figure 53 In the example shown, Figure 56 、 Figure 57 In the example shown, the signal lines are located in the following film layers: the first power branch line 611, the third power branch line 623, the fifth power branch line 635, and the first data line 31, the second data line 32, and the third data line 33 are located in the third metal layer SD3. The second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 are located in the second metal layer SD2.

[0345] As another example, see Figure 62 、 Figure 63 and Figure 68In this example, the second metal layer SD2 and the third metal layer SD3 are not included. In this example, the signal lines are located in the following layers: the first power branch line 611, the third power branch line 623, the fifth power branch line 635, and the first data line 31, the second data line 32, and the third data line 33 are located in the first metal layer SD1. The second power branch line 612, the fourth power branch line 624, and the sixth power branch line 636 are located in the capacitor metal layer MC.

[0346] In some examples, such as Figure 17 and Figure 18 As shown, or, as Figure 67 and Figure 68 As shown, the display panel further includes an auxiliary metal layer M0, which is located on the side of the semiconductor layer close to the substrate PI. The display panel may include one or more semiconductor layers, and the auxiliary metal layer M0 is located on the side of any semiconductor layer close to the substrate PI.

[0347] The auxiliary metal layer M0 includes a first auxiliary line 81, a second auxiliary line 82, and a third auxiliary line 83, which are disconnected from each other. The first auxiliary line 81 is electrically connected to the first power line 61, the second auxiliary line 82 is electrically connected to the second power line 62, and the third auxiliary line 83 is electrically connected to the third power line 63. This example is equivalent to increasing the grid density of the first power line 61, the second power line 62, and the third power line 63, which can further reduce the voltage drop corresponding to each power line, thereby further improving display uniformity.

[0348] The wiring in the auxiliary metal layer M0 can also be used to block the light from the bottom surface from reaching the active layer in the semiconductor layer, thereby preventing the active layer from undergoing characteristic transfer due to light exposure, thereby improving the circuit reliability of the display panel.

[0349] As an example, Figure 16 and Figure 17 As shown, the wiring pattern in the auxiliary metal layer M0 and the wiring pattern in the first semiconductor layer overlap in the thickness direction of the display panel.

[0350] As another example, Figure 65 and Figure 67 As shown, the wiring pattern in the auxiliary metal layer M0 at least overlaps with the active layer of the driving transistor.

[0351] In some embodiments, as Figure 70 As shown, a patch cable 70 is provided within the display area AA of the display panel. One end of the patch cable 70 is connected to the data line 30, and the other end of the patch cable 70 is connected to the wiring within the wiring area NA1. The wiring within the wiring area NA1 is connected to the driver chip. It can be understood that the patch cable 70 is used to transmit data signals from the driver chip to the data line 30.

[0352] This design approach can be called "FIAA" design, which can reduce the width of the routing area NA1 and achieve a narrow border.

[0353] Furthermore, in the embodiment of the present application, the "FIAA" design is combined with independent power lines of light-emitting elements of different colors and independent data lines of light-emitting elements of different colors, which can not only reduce power consumption but also achieve a narrow frame.

[0354] Exemplarily, the patch cord 70 includes a first line segment 71 and a second line segment 72 electrically connected to each other. The first line segment 71 extends along a first direction X, and the second line segment 72 extends along a second direction Y.

[0355] like Figure 10 As shown, the first line segment 71 and the first power branch line 611 are located in the same film layer. Figure 9 and Figure 11 As shown, the second line segment 72 and the second power branch line 612 are located in different film layers. Figure 11 and Figure 18 As shown, the second line segment 72 is located in the first metal layer SD1.

[0356] For example, Figure 10 As shown, the display area of ​​the display panel includes multiple first traces 91 extending along the first direction X. For example, the area where the adapter line 70 is located is called the "FIAA area", and the area outside the adapter line 70 is called the "non-FIAA area". The first traces 91 in the "FIAA area" are multiplexed into the first line segment 71, and the first traces 91 in the "non-FIAA area" can be multiplexed into the common voltage line PVEE. Alternatively, the first traces 91 in the "non-FIAA area" can be multiplexed into reset lines Vref1, Vref2 or other signal lines. It is understandable that when the first traces in the "FIAA area" and the "non-FIAA area" transmit different signals, the two are disconnected from each other.

[0357] For example, Figure 11 As shown, the display area of ​​the display panel includes multiple third traces 93 extending along the second direction Y. Here, the area where the adapter line 70 is located is still referred to as the "FIAA area", and the area outside the adapter line 70 is referred to as the "non-FIAA area". The third traces 93 in the "FIAA area" are multiplexed into the second line segment 72, and the third traces 93 in the "non-FIAA area" can be multiplexed into the common voltage line PVEE. Alternatively, the third traces 93 in the "non-FIAA area" can be multiplexed into reset lines Vref1, Vref2 or other signal lines. It is understandable that when the third traces in the "FIAA area" and the "non-FIAA area" transmit different signals, the two are disconnected from each other.

[0358] For example, Figure 10As shown, the display area of ​​the display panel further includes a plurality of second traces 92 extending along the first direction X. The first trace 91 and the second trace 92 are disposed adjacent to each other, and the first trace 91 and the second trace 92 are located between two data lines. For example, the first trace 91 and the second trace 92 are disposed between the first data line 31 and the third data line 33, and the first trace 91 and the second trace 92 are disposed between the second data line 32 and the third data line 33.

[0359] The above embodiment describes that the data lines of each color light emitting element are independent, and the power lines of each color light emitting element are independent. In other embodiments, the independent power lines of each color light emitting element can also be applied to: the data lines of at least two color light emitting elements are not independent.

[0360] For example, Figure 71 As shown, the first light-emitting element 11 is electrically connected to the first pixel circuit 21, the second light-emitting element 12 is electrically connected to the second pixel circuit 22, and the data line 31' is electrically connected to both the first pixel circuit 21 and the second pixel circuit 22 in the same column. In other words, the data line 31' is used to provide the data signals required by the two color light-emitting elements, and the first light-emitting element 11 and the second light-emitting element 12 share the data line. In addition, the third light-emitting element 13 is electrically connected to the third pixel circuit 23, and the data line 32' is electrically connected to multiple third pixel circuits 23 in the same column.

[0361] Figure 71 The approximate position of the pixel circuit is shown in a dotted box, and the first pixel circuit 21 is indicated by a dotted box filled with gray to distinguish the first pixel circuit 21 from the second pixel circuit 22.

[0362] The power line PVDD includes a first power line 61, a second power line 62, and a third power line 63. The first power line 61 is electrically connected to the first pixel circuit 21 and includes a first power branch line 611 and a second power branch line 612 electrically connected to each other. One of the first power branch line 611 and the second power branch line 612 can be electrically connected to the first pixel circuit 21 through a via. The second power line 62 is electrically connected to the second pixel circuit 22 and includes a third power branch line 623 and a fourth power branch line 624 electrically connected to each other. One of the third power branch line 623 and the fourth power branch line 624 can be electrically connected to the second pixel circuit 22 through a via. The third power line 63 is electrically connected to the third pixel circuit 23 and includes a fifth power branch line 635 and a sixth power branch line 636 electrically connected to each other. One of the fifth power branch line 635 and the sixth power branch line 636 can be electrically connected to the third pixel circuit 23 through a via.

[0363] For the features of each power branch line, please refer to the above embodiments and will not be described in detail here.

[0364] It should be noted that Figure 71 It is used to illustrate the electrical connection relationship between the data line, the power line, and the pixel circuit, and is not used to limit the relative position relationship between the data line and the power line. Figure 71 A solid black dot is used to indicate that two power branch lines are electrically connected to each other. However, the solid black dot is not used to limit the connection position of the two power branch lines, as long as the connection between the two power branch lines can be achieved.

[0365] For example, Figure 71 As shown, the power branch line extending along the first direction X may include a branch, and in the thickness direction of the display panel, the branch at least partially overlaps with the third light-emitting element 13, so that the surface where the third light-emitting element 13 is located can be made flat as much as possible, thereby ensuring the luminous effect of the third light-emitting element 13.

[0366] For example, Figure 72 As shown, at least a portion of the power branch line extending along the second direction Y may also include branches. The pixel circuit includes a driver transistor, and the gate of the driver transistor is connected to other transistors via a metal connection. In the thickness direction of the display panel, at least a portion of the branch line extending along the second direction Y overlaps with the metal connection. The branch transmits the power supply voltage, which is generally a fixed voltage. Therefore, the branch can be used to shield the gate potential of the driver transistor from the influence of other signals.

[0367] It should be noted that, in the absence of contradiction, the above embodiments can be combined with each other.

[0368] This application also provides a display device, including the display panel provided by this application. Figure 73 , Figure 73 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 73 The provided display device 1000 includes a display panel 100 , and the display panel 100 includes the display panel provided by any of the above embodiments of the present application. Figure 73 The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understandable that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0369] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: The light-emitting elements include a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors, a first unit column includes the first light-emitting elements and the second light-emitting elements arranged alternately in a first direction, a second unit column includes a plurality of the third light-emitting elements arranged in the first direction, the first unit column and the second unit column are arranged alternately in a second direction, and the first direction and the second direction intersect; A first circuit column, a second circuit column, and a third circuit column, wherein the first circuit column includes a plurality of first pixel circuits arranged in the first direction, the second circuit column includes a plurality of second pixel circuits arranged in the first direction, the third circuit column includes a plurality of third pixel circuits arranged in the first direction, the first pixel circuit is electrically connected to the first data line and the first light-emitting element, the second pixel circuit is electrically connected to the second data line and the second light-emitting element, and the third pixel circuit is electrically connected to the third data line and the third light-emitting element.

2. The display panel according to claim 1, wherein: The number of columns of pixel circuits in the display panel is greater than the number of columns of light-emitting elements, some circuit columns include dummy pixel circuits, the first light-emitting elements are electrically connected to the first pixel circuits through first vias, and a plurality of first vias corresponding to the same first circuit column constitute a first via column; for a first circuit column that does not include the dummy pixel circuits, in the second direction, the plurality of first light-emitting elements electrically connected to the first pixel circuits through the vias on the same first via column are respectively located on both sides of the first via column; The second light-emitting element is electrically connected to the second pixel circuit through a second via, and the multiple second vias corresponding to the same second circuit column constitute a second via column; for the second circuit column that does not include the virtual pixel circuit, in the second direction, the multiple second light-emitting elements electrically connected to the second pixel circuit through the vias on the same second via column are respectively located on both sides of the second via column.

3. The display panel according to claim 2, wherein: For the same first unit column, in the second direction, the first via hole and the second via hole are respectively located on two sides of the first unit column.

4. The display panel according to claim 2, wherein: The first light emitting elements and the second light emitting elements are alternately arranged in the second direction to form a first unit row, For the same first unit row, in the second direction, the relative positional relationship between the first via hole and the first light-emitting element is the same as the relative positional relationship between the second via hole and the second light-emitting element.

5. The display panel according to claim 2, wherein: The anode of the first light-emitting element is electrically connected to the first end of the first via hole through a first connecting wire, the second end of the first via hole is electrically connected to the first pixel circuit, and the first connecting wire and the anode of the first light-emitting element are located in the same film layer; The anode of the second light-emitting element is electrically connected to the first end of the second via hole through a second connecting wire, the second end of the second via hole is electrically connected to the second pixel circuit, and the second connecting wire and the anode of the second light-emitting element are located in the same film layer; The display panel includes at least two semiconductor layers.

6. The display panel according to claim 5, wherein: The length of the first connecting line is smaller than the maximum width of the first light emitting element along the second direction, and the length of the second connecting line is smaller than the maximum width of the second light emitting element along the second direction.

7. The display panel according to claim 6, wherein: For the same component column, the extending directions of the first connecting lines and the second connecting lines intersect with each other.

8. The display panel according to claim 2, wherein: The display panel includes a first connecting line and a second connecting line, the first connecting line includes a first section and a second section, the first section is connected between the anode of the first light-emitting element and the first end of the first via hole, the second section is connected between the second end of the first via hole and the first pixel circuit, the first section and the anode of the first light-emitting element are located in the same film layer, and the second section is located in the metal layer on the side of the anode of the first light-emitting element facing the substrate; The second connecting line includes a third section and a fourth section, the third section is connected between the anode of the second light-emitting element and the first end of the second via hole, and the fourth section is connected between the second end of the second via hole and the second pixel circuit, the third section and the anode of the second light-emitting element are located in the same film layer, and the fourth section is located in the metal layer on the side of the anode of the second light-emitting element facing the substrate; The display panel includes a semiconductor layer.

9. The display panel according to claim 8, wherein: The display panel includes a data line. In the thickness direction of the display panel, the film layer where the second segment and the fourth segment are located is located between the film layer where the data line is located and the anode of the light-emitting element.

10. The display panel according to claim 2, wherein: In the thickness direction of the display panel, the first circuit column overlaps at least partially with the first light-emitting elements connected thereto, and the second circuit column overlaps at least partially with the second light-emitting elements connected thereto.

11. The display panel according to claim 2, wherein: In the thickness direction of the display panel, a portion of the first unit column at least partially overlaps with the first data line and the third data line, another portion of the first unit column at least partially overlaps with the second data line and the third data line, and the second unit column does not overlap with the data line.

12. The display panel according to claim 1, wherein The number of columns of pixel circuits in the display panel is equal to the number of columns of light-emitting elements; two adjacent first unit columns constitute a first unit column group; the display panel includes a plurality of first unit column groups; the first circuit column is electrically connected to the plurality of first light-emitting elements in the first unit column group, and the second circuit column is electrically connected to the plurality of second light-emitting elements in the first unit column group.

13. The display panel according to claim 12, wherein: The first light-emitting element is electrically connected to the first pixel circuit through a first via hole, and the second light-emitting element is electrically connected to the second pixel circuit through a second via hole; In the first unit column group, in the second direction, the first vias of one of the first unit columns are on a first side of the first unit column, and the second vias are on a second side of the first unit column; and the first vias and the second vias of another first unit column are distributed on the same side of the first unit column.

14. The display panel according to claim 12, wherein: The first light-emitting element is electrically connected to the first pixel circuit via a first connecting line, and at least a portion of the first connecting line and the data line of the display panel are located in a different film layer.

15. The display panel according to claim 14, wherein: In the thickness direction of the display panel, at least a portion of the first connecting line overlaps with the second light-emitting element.

16. The display panel according to claim 14, wherein: In a thickness direction of the display panel, at least part of the second light emitting element and the second pixel circuit electrically connected thereto at least partially overlap, and the display panel includes at least two semiconductor layers.

17. The display panel according to claim 12, wherein: The first light-emitting element is electrically connected to the first pixel circuit through a first connecting line, and the second light-emitting element is electrically connected to the second pixel circuit through a second connecting line. At least part of the line segments of the first connecting line, at least part of the line segments of the second connecting line, and the data lines of the display panel are located in different film layers, and the display panel includes a semiconductor layer.

18. The display panel according to claim 12, wherein: The first light-emitting element is electrically connected to the first pixel circuit through a first via hole, and the second light-emitting element is electrically connected to the second pixel circuit through a second via hole; In the second direction, the first via hole of any one of the first unit columns is located on a first side of the first unit column, and the second via hole is located on a second side of the second unit column.

19. The display panel according to claim 18, wherein: The first light-emitting element is electrically connected to the first pixel circuit through a first connecting line. The length of the first connecting line connected between the first via hole and the first pixel circuit in the second direction is L1. The width of the pixel circuit of the display panel in the second direction is L2, and 3*L2≤L1≤4*L2.

20. The display panel according to claim 12, wherein: The first light-emitting element is electrically connected to the first pixel circuit through a first via hole, and the second light-emitting element is electrically connected to the second pixel circuit through a second via hole; In the second direction, the first via holes and the second via holes of any one of the first unit columns are distributed on the same side of the first unit column.

21. The display panel according to claim 20, wherein: The first light-emitting element is electrically connected to the first pixel circuit via a first connecting line, and the second light-emitting element is electrically connected to the second pixel circuit via a second connecting line. The first connecting line and the second connecting line do not overlap.

22. The display panel according to claim 1, wherein The third light-emitting element is electrically connected to the third pixel circuit through a third via hole. In the first direction, any third via hole is located on the same side of the third light-emitting element to which it is connected.

23. The display panel according to claim 1, wherein The element unit includes the first light-emitting element, the second light-emitting element and the third light-emitting element which are adjacent to each other; The first light-emitting element is electrically connected to the first pixel circuit through a first via hole, the second light-emitting element is electrically connected to the second pixel circuit through a second via hole, and the third light-emitting element is electrically connected to the third pixel circuit through a third via hole; In the first direction, the first via hole, the second via hole, and the third via hole of the component unit are located on the same side of the component unit.

24. The display panel according to claim 23, wherein: The adjacent first unit columns and second unit columns constitute a second unit column group, and each second unit column group is correspondingly provided with three columns of pixel circuits.

25. The display panel according to claim 23, wherein: The anode of the second light-emitting element is electrically connected to the second via hole through a second connecting line. In a direction parallel to the light-emitting surface of the display panel, the second connecting line is located between the first light-emitting element and the third light-emitting element.

26. The display panel according to claim 1, wherein The pixel circuit of the display panel includes a driving transistor and a power line electrically connected to the driving transistor, and active layers of adjacent driving transistors are not connected.

27. The display panel according to claim 1, wherein The light emitting element is electrically connected to the pixel circuit through a via hole, wherein the via hole includes a first sub-via hole, and the first sub-via hole is electrically connected to the pixel circuit without overlapping; The display panel further includes a connecting line, one end of which is connected to the first sub-via hole, and the other end of which is connected to the pixel circuit.

28. The display panel according to claim 27, wherein: The display panel includes a power branch line extending along the second direction, and the connecting line and the power branch line are located in the same film layer.

29. The display panel according to claim 28, wherein: The via hole includes a second sub-via hole, and the second sub-via hole at least partially overlaps the pixel circuit electrically connected thereto; The display panel further includes a compensation line, one end of which is connected to the second sub-via hole.

30. The display panel according to claim 29, wherein: The other end of the compensation line is suspended.

31. The display panel according to claim 29, wherein: The compensation line and the connecting line are in the same film layer.

32. The display panel according to claim 1, wherein: The display panel also includes power lines, including a first power line and a second power line, the first power line is electrically connected to the first light-emitting element, the first power line includes a first power branch line and a second power branch line electrically connected to each other, the first power branch line extends along a first direction, and the second power branch line extends along a second direction; the second power line is electrically connected to the second light-emitting element, the second power line includes a third power branch line and a fourth power branch line electrically connected to each other, the third power branch line extends along the first direction, and the fourth power branch line extends along the second direction.

33. The display panel according to claim 32, wherein: The power line also includes a third power line, which is electrically connected to the third light-emitting element. The third power line includes a fifth power branch and a sixth power branch that are electrically connected to each other. The fifth power branch extends along the first direction, and the sixth power branch extends along the second direction. One of the second power branch and the fourth power branch is electrically connected to the sixth power branch, or the second power branch, the fourth power branch, and the sixth power branch are independent of each other.

34. The display panel according to claim 33, wherein: One of the first light-emitting element and the second light-emitting element is a red light-emitting element, the other is a blue light-emitting element, and the third light-emitting element is a green light-emitting element; the first power branch line, the fifth power branch line, the third power branch line, and the fifth power branch line constitute a first line group, and multiple first line groups are arranged in the second direction.

35. The display panel according to claim 33, wherein: One of the first light-emitting element and the third light-emitting element is a red light-emitting element, the other is a blue light-emitting element, and the second light-emitting element is a green light-emitting element; The first power branch line, the third power branch line, and the fifth power branch line constitute a second line group, and a plurality of the second line groups are arranged in the second direction.

36. The display panel according to claim 33, wherein: The plurality of pixel circuits of the display panel are arranged in n1 rows; The total number of the second power branch line, the fourth power branch line and the sixth power branch line is n2; n1=n2, or n1=2*n2, where n1 and n2 are both integers greater than 1.

37. The display panel according to claim 33, wherein: The first power line further includes a seventh power branch line, the seventh power branch line extending along the first direction, the seventh power branch line being electrically connected to the first power branch line and being located in a different film layer; The second power line further includes an eighth power branch line, the eighth power branch line extends along the first direction, the eighth power branch line is electrically connected to the third power branch line and is located in a different film layer; The third power line further includes a ninth power branch line, which extends along the first direction. The ninth power branch line is electrically connected to the fifth power branch line and is located in a different film layer.

38. The display panel according to claim 33, wherein: The first power branch line, the third power branch line, and the fifth power branch line are located in a first film layer of the display panel; and the first film layer includes a data line of the display panel; The second power branch line, the fourth power branch line and the sixth power branch line are located on the second film layer of the display panel; The first film layer and the second film layer are both film layers on the side of the semiconductor layer of the display panel facing the light emitting surface.

39. The display panel according to claim 38, wherein: The display panel further comprises an auxiliary metal layer, wherein the auxiliary metal layer is located on a side of the semiconductor layer close to the substrate; The auxiliary metal layer includes a first auxiliary line, a second auxiliary line, and a third auxiliary line disconnected from each other, the first auxiliary line is electrically connected to the first power line, the second auxiliary line is electrically connected to the second power line, and the third auxiliary line is electrically connected to the third power line.

40. The display panel according to claim 38, wherein The display panel also includes a transfer line, which is located in the display area and connected to the data line. The transfer line includes a first line segment and a second line segment electrically connected to each other. The first line segment extends along the first direction and is located in the same film layer as the first power branch line. The second line segment extends along the second direction and is located in a different film layer from the second power branch line.

41. A display device, characterized in that: Comprising the display panel according to any one of claims 1-40.

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