Display panel and display device

Abstract

The utility model provides a display panel and a display device, relates to the technical field of display, and aims to improve the phenomenon that a display picture is abnormal. The display panel comprises a display area and a peripheral area surrounding the outer side of the display area. The display panel comprises an array substrate and a color film substrate which are oppositely arranged, and the array substrate comprises a first substrate, at least one conductive structure and at least one spacer. The at least one conductive structure is arranged on the side, close to the color film substrate, of the first substrate and located in the peripheral area. The at least one spacer is arranged on the side, away from the first substrate, of the conductive structure, and the orthographic projection of the spacer on the first substrate is at least partially overlapped with the orthographic projection of the at least one conductive structure on the first substrate. The display panel can be applied to the display device to realize picture display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the applications of Thin Film Transistor Liquid Crystal Display (TFT-LCD) are becoming more and more diversified.

[0003] However, during the long-term high-temperature and high-humidity reliability evaluation of thin-film transistor liquid crystal displays, conductive structures such as via structures, cross-line structures and device structures in the display panel are prone to defects such as via corrosion, cross-line burns and characteristic shifts due to water vapor intrusion, resulting in abnormal display images. Utility Model Content

[0004] The present application provides a display panel and a display device, aiming to improve the phenomenon of abnormal display images.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] In one aspect, a display panel is provided, comprising a display area and a peripheral area surrounding the display area. The display panel includes an array substrate and a color filter substrate disposed opposite each other. The array substrate includes a first substrate, at least one conductive structure, and at least one spacer. The at least one conductive structure is disposed on a side of the first substrate proximal to the color filter substrate and located in the peripheral area. The at least one spacer is disposed on a side of the conductive structure distal to the first substrate, with an orthographic projection of the spacer on the first substrate at least partially overlapping with an orthographic projection of the at least one conductive structure on the first substrate.

[0007] The display panel provided in the embodiment of the present application includes a display area and a peripheral area surrounding the outside of the display area. The display panel also includes an array substrate and a color filter substrate arranged relatively to each other. The array substrate includes a first substrate, a plurality of conductive structures located in the peripheral area arranged on the side of the first substrate close to the color filter substrate, and a plurality of spacers arranged on the side of the conductive structure away from the first substrate. The orthographic projection of a spacer on the first substrate at least partially overlaps with the orthographic projection of at least one conductive structure on the first substrate, that is, a spacer can cover part of at least one conductive structure. It can be understood that the part of the conductive structure covered by the spacer is the part of the conductive structure that is easily corroded by water vapor, such as the via structure, the cross-line structure, and the device structure. The spacer protects the part of the conductive structure covered by the spacer and isolates the part from the entry of water vapor, so as to improve the corrosion of the conductive structure and thus improve the abnormality of the display panel image.

[0008] In some embodiments, the display panel further includes a gate driving circuit disposed on the first substrate, the gate driving circuit includes a conductive structure, and the orthographic projection of the spacer on the first substrate at least partially overlaps with the orthographic projection of the gate driving circuit on the first substrate.

[0009] In some embodiments, the array substrate further includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer sequentially stacked on a first substrate, wherein the conductive structure includes a first signal line located in the first conductive layer, a second signal line located in the second conductive layer, and a connection pattern located in the third conductive layer. First vias are provided through the first and second dielectric layers, and the connection pattern is electrically connected to the first signal line via the first vias. Second vias are provided through the second dielectric layer, and the connection pattern is also electrically connected to the second signal line via the second vias. The orthographic projection of the spacer on the first substrate at least covers the orthographic projection of the first via on the first substrate, and at least covers the orthographic projection of the second via on the first substrate.

[0010] In some embodiments, the array substrate includes multiple conductive structures and multiple spacers, wherein the orthographic projections of the multiple spacers on the first substrate do not overlap. The orthographic projection of one spacer on the first substrate covers the orthographic projections of a first via and a second via of the same conductive structure on the first substrate, or the orthographic projection of one spacer on the first substrate covers the orthographic projections of the first via and the second via of multiple conductive structures on the first substrate.

[0011] In some embodiments, the conductive structure includes a third signal line and a fourth signal line, the fourth signal line crossing the third signal line, and an orthographic projection of the spacer on the first substrate at least partially overlaps with an orthographic projection of the third signal line on the first substrate, and at least partially overlaps with an orthographic projection of the fourth signal line on the first substrate.

[0012] In some embodiments, the array substrate includes multiple conductive structures and multiple spacers, wherein the orthographic projections of the multiple spacers on the first substrate do not overlap. The orthographic projection of one spacer on the first substrate covers the orthographic projections of the third signal line and the fourth signal line of one conductive structure on the first substrate, or the orthographic projection of one spacer on the first substrate covers the orthographic projections of the third signal line and the fourth signal line of multiple conductive structures on the first substrate.

[0013] In some embodiments, the conductive structure includes at least one component, and an orthographic projection of the spacer on the first substrate covers an orthographic projection of the at least one component on the first substrate.

[0014] In some embodiments, the array substrate includes multiple conductive structures and multiple spacers, wherein the orthographic projections of the multiple spacers on the first substrate do not overlap. The orthographic projection of one spacer on the first substrate covers the orthographic projection of a component of a conductive structure on the first substrate, or the orthographic projection of one spacer on the first substrate covers the orthographic projections of multiple components of the conductive structures on the first substrate.

[0015] In some embodiments, the array substrate includes a plurality of conductive structures, the plurality of conductive structures including a first conductive structure, a second conductive structure, and a third conductive structure. The first conductive structure includes a first signal line, a second signal line, and a connection pattern, the first signal line being electrically connected to the second signal line via the connection pattern. The second conductive structure includes a third signal line and a fourth signal line, the fourth signal line crossing the third signal line. The third conductive structure includes at least one component. The array substrate includes a plurality of spacers, the orthographic projections of the plurality of spacers on the first substrate do not overlap, and among the first conductive structure, the second conductive structure, and the third conductive structure, the orthographic projection of one spacer on the first substrate covers the orthographic projections of at least two conductive structures on the first substrate.

[0016] In some embodiments, the array substrate includes multiple conductive structures, including a first conductive structure, a second conductive structure, and a third conductive structure. The first conductive structure includes a first signal line, a second signal line, and a connection pattern, wherein the first signal line is electrically connected to the second signal line via the connection pattern. The second conductive structure includes a third signal line and a fourth signal line, wherein the fourth signal line crosses the third signal line. The third conductive structure includes at least one component. The spacer includes at least one first spacer, wherein the orthographic projection of the first spacer on the first substrate covers the orthographic projections of the first conductive structure, the second conductive structure, and the third conductive structure on the first substrate.

[0017] In some embodiments, the array substrate includes a plurality of spacers, the plurality of spacers including at least one first spacer and a plurality of second spacers. The orthographic projection of the second spacer on the first substrate is located within the outer contour of the orthographic projection of the first spacer on the first substrate. The height of the second spacer relative to the first substrate is greater than the height of the first spacer.

[0018] In some embodiments, the plurality of spacers further include a plurality of third spacers, wherein the orthographic projections of the third spacers on the first substrate do not overlap with the orthographic projections of the first spacers on the first substrate. Relative to the first substrate, the height of the third spacers is greater than that of the first spacers, and the height of the third spacers is less than that of the second spacers.

[0019] In some embodiments, the peripheral region includes a first area and a second area. The color filter substrate includes a second substrate and a virtual color resist layer disposed on a side of the second substrate proximate to the array substrate, wherein the virtual color resist layer is located in the first area. The array substrate includes a plurality of spacers, wherein the plurality of spacers include a fourth spacer and a fifth spacer. The orthographic projection of the fourth spacer on the second substrate overlaps with the orthographic projection of the virtual color resist layer on the second substrate, and the orthographic projection of the fifth spacer on the second substrate does not overlap with the orthographic projection of the virtual color resist layer on the second substrate. Relative to the first substrate, the height of the fifth spacer is greater than the height of the fourth spacer.

[0020] In some embodiments, the array substrate further includes a planarization layer, and the planarization layer is disposed between the conductive structure and the spacer.

[0021] In some embodiments, the material of the spacer includes a hydrophobic material.

[0022] In yet another aspect, a display device is provided. The display device includes the display panel according to the above embodiment, and a controller electrically connected to the display panel.

[0023] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application. For those skilled in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and do not represent the actual dimensions of the products or the actual processes of the methods involved in the embodiments of this application.

[0025] Figure 1 Schematic diagram of the structure of the peripheral area of ​​a thin film transistor liquid crystal display in the related art;

[0026] Figure 2 for Figure 1 Schematic diagram of the via structure in the middle and peripheral areas being corroded by water vapor;

[0027] Figure 3 for Figure 1 Schematic diagram of the cross-line structure in the middle and peripheral areas being corroded by water vapor;

[0028] Figure 4 for Figure 1 Schematic diagram of device structure in the middle and peripheral areas being corroded by water vapor;

[0029] Figure 5 A structural diagram of a display panel provided in an embodiment of the present application;

[0030] Figure 6 for Figure 5 A partial cross-sectional view of the display panel along the section line AA';

[0031] Figure 7 A structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0032] Figure 8 A structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0033] Figure 9 for Figure 8 A partial cross-sectional view of the gate drive circuit along section line BB';

[0034] Figure 10 A structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0035] Figure 11 A structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0036] Figure 12 for Figure 11 A partial cross-sectional view of the gate drive circuit along section line CC';

[0037] Figure 13 for Figure 11 A partial cross-sectional view of the gate drive circuit along section line DD';

[0038] Figure 14 A structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0039] Figure 15 A structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0040] Figure 16 A structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0041] Figure 17 for Figure 5 Another partial cross-sectional view of the display panel along the section line AA';

[0042] Figure 18 A schematic diagram of the structure of another spacer provided in an embodiment of the present application;

[0043] Figure 19 A schematic structural diagram of another spacer arrangement provided in an embodiment of the present application;

[0044] Figure 20A schematic structural diagram of another spacer arrangement provided in an embodiment of the present application;

[0045] Figures 21 to 24 Structural diagrams of via structures, cross-line structures, and device structures provided in embodiments of the present application;

[0046] Figure 25 This is a structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0051] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0052] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0053] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the areas of regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0054] With the diversification of Thin Film Transistor Liquid Crystal Display (TFT-LCD) products, the operating environment of TFT-LCD is becoming increasingly demanding, and the reliability requirements for these products under high temperature and high humidity conditions are becoming increasingly stringent. During the long-term high temperature and high humidity reliability evaluation (2000 hours+), abnormal screen display may occur.

[0055] Figure 1 Schematic diagram of the structure of the peripheral area of ​​a thin film transistor liquid crystal display in the related art; Figure 2 for Figure 1 Schematic diagram of the via structure in the middle and peripheral areas being corroded by water vapor; Figure 3 for Figure 1 Schematic diagram of the cross-line structure in the middle and peripheral areas being corroded by water vapor; Figure 4 for Figure 1 Schematic diagram of device structure in the mid-peripheral area being corroded by water vapor.

[0056] like Figure 1 As shown, the peripheral region 3' includes conductive structures such as a via structure 31', a cross-line structure 32' and a device structure 33'. Figures 2 to 4 As shown, the above three conductive structures are easily corroded by water vapor under high temperature and high humidity conditions, thereby causing abnormal display of the display screen.

[0057] Specifically, such as Figure 2 As shown, in the via structure 31', water vapor gathers at the via position of the gate driver on array (GOA), forming an electrolyte, which causes electrochemical corrosion of the indium tin oxide (ITO) conductive layer, resulting in via corrosion, abnormal signal transmission, and ultimately image abnormality, seriously affecting the reliability and life of the product. Figure 3As shown in FIG. 3 , in the cross-line structure 32 ′, if the passivation layer (PVX) has poor coverage, especially at the taper, PVX cracks are likely to occur. Water vapor enters the interface between the SD (Source / Drain) conductive layer and the PVX through the cross-line vias, causing corrosion of the signal line in the SD conductive layer. This causes an excessively large voltage difference at the cross-line, resulting in a short circuit (short) burn. Figure 4 As shown, in the device structure 33', long-term water vapor penetration under the action of the electric field will cause water to decompose into H+, O- and e-. These ions and electrons will enter the semiconductor device layer, causing the characteristics of the thin film transistor (TFT) to be negatively biased, thereby affecting the characteristics of the TFT.

[0058] To improve the above-mentioned problems in the related art, the embodiments of the present application provide the following technical solutions:

[0059] On the one hand, an embodiment of the present application provides a display panel, Figure 5 A structural diagram of a display panel provided in an embodiment of the present application; Figure 6 for Figure 5 A partial cross-sectional view of the display panel along the section line AA'; Figure 7 A structural diagram of a gate drive circuit provided in an embodiment of the present application.

[0060] See also Figure 5 The display panel 1 includes a display area (Active Area, AA) 2 and a peripheral area 3 surrounding the outside of the display area 2. Exemplarily, a power line is further provided on a side of the peripheral area 3 away from the display area 2 to provide power to the display area 2 and the conductive structures in the peripheral area 3. The power line includes, for example, a base power supply voltage (Vbb), a positive power supply (VDD) and a negative ground line (VSS). The display panel 1 can be applied to a thin film transistor liquid crystal display.

[0061] See also Figure 6 The display panel 1 includes an array substrate 11 and a color filter substrate 12 arranged opposite to each other. The array substrate 11 includes a first substrate 13, at least one conductive structure 14, and at least one spacer 15. The at least one conductive structure 14 is arranged on a side of the first substrate 13 close to the color filter substrate 12 and located in the peripheral area 3. Exemplarily, the conductive structure 14 includes one or more structures such as a via structure, a line-crossing structure, and a device structure in the peripheral area 3. The at least one spacer 15 is arranged on a side of the conductive structure 14 away from the first substrate 13. The orthographic projection of one spacer 15 on the first substrate 13 at least partially overlaps with the orthographic projection of the at least one conductive structure 14 on the first substrate 13.

[0062] The display panel 1 provided in the embodiment of the present application includes a display area 2 and a peripheral area 3 surrounding the outside of the display area 2. The display panel 1 also includes an array substrate 11 and a color filter substrate 12 arranged opposite to each other. The array substrate 11 includes a first substrate 13, a plurality of conductive structures 14 located in the peripheral area 3 and arranged on the side of the first substrate 13 close to the color filter substrate 12, and a plurality of spacers 15 arranged on the side of the conductive structure 14 away from the first substrate 13. The orthographic projection of one spacer 15 on the first substrate 13 at least partially overlaps with the orthographic projection of at least one conductive structure 14 on the first substrate 13, that is, one spacer 15 can cover a portion of at least one conductive structure 14. It can be understood that the portions of the conductive structure 14 that are easily corroded by water vapor, such as the via structure, the cross-line structure, and the device structure, can be isolated from the entry of water vapor by covering the portion of the conductive structure 14 with the spacer 15, thereby improving the corrosion of the conductive structure 14, thereby improving the abnormal image of the display panel 1 and improving the reliability of the display panel 1.

[0063] In some embodiments, see Figure 6 The material of the spacer 15 includes a hydrophobic material, which can further prevent water vapor from invading the conductive structure 14, thereby improving the corrosion of the conductive structure 14 and improving the abnormal image of the display panel 1.

[0064] In some embodiments, see Figures 5 to 7 The display panel 1 further includes a gate drive circuit 4 disposed on the first substrate 13. The conductive structure 14 described above may be a structure within the gate drive circuit 4, that is, the gate drive circuit 4 includes the conductive structure 14. For example, the conductive structure 14 may be a via structure, a cross-line structure, or a device structure within the gate drive circuit 4. The gate drive circuit 4 is electrically connected to a plurality of gate lines within the display panel 1 and is configured to transmit gate scanning signals to the plurality of gate lines.

[0065] The gate drive circuit 4 is located in the peripheral area 3 of the display panel 1. Since water vapor easily enters the peripheral area 3, the orthographic projection of the spacer 15 on the first substrate 13 is set to at least partially overlap with the orthographic projection of the gate drive circuit 4 on the first substrate 13. That is, the spacer 15 covers the structure in the gate drive circuit 4, preventing the conductive structure 14 in the gate drive circuit 4 from being corroded by water vapor, thereby improving the reliability of the gate drive circuit 4.

[0066] Figure 8 A structural diagram of another gate drive circuit provided in an embodiment of the present application; Figure 9 for Figure 8 A partial cross-sectional view of the gate drive circuit along section line BB'.

[0067] In some embodiments, see Figure 8 and Figure 9 In the case where the conductive structure 14 is a via structure 31, the array substrate 11 further includes a first conductive layer 141, a first dielectric layer 142, a second conductive layer 143, a second dielectric layer 144, and a third conductive layer 145, which are sequentially stacked on the first substrate 13. The conductive structure 14 includes a first signal line 146a located in the first conductive layer 141, a second signal line 146b located in the second conductive layer 143, and a connection pattern 145a located in the third conductive layer 145. First vias 147a are provided through the first and second dielectric layers 142 and 144, and the connection pattern 145a is electrically connected to the first signal line 146a via the first vias 147a. Second vias 147b are provided through the second dielectric layer 144, and the connection pattern 145a is also electrically connected to the second signal line 146b via the second vias 147b.

[0068] For example, see Figure 9 The first conductive layer 141 is a gate conductive layer (Gate), and the first signal line 146a is located in the gate conductive layer. The first signal line 146a can be, for example, a clock signal line (Clock Signal), which is used to provide a clock control signal for the gate driving circuit 4. The first dielectric layer 142 is a gate insulating layer (GI), which is used to isolate the first signal line 146a from the second signal line 146b to prevent the first signal line 146a and the second signal line 146b from short-circuiting. The second conductive layer 143 is a source-drain conductive layer (SD), and the second signal line 146b is located in the source-drain conductive layer. The second dielectric layer 144 is PVX, and the third conductive layer 145 is ITO. A connection pattern 145a is provided in the ITO. A first via 147a penetrates the first dielectric layer 142 and the second dielectric layer 144, and a second via 147b penetrates the second dielectric layer 144. The connection pattern 145a connects the first signal line 146a and the second signal line 146b through the first via 147a and the second via 147b to form a via structure 31.

[0069] Continue to see Figure 8 and Figure 9 The spacer 15 is disposed on a side of the connection pattern 145a away from the first substrate 13. The orthographic projection of the spacer 15 on the first substrate 13 at least covers the orthographic projection of the first via 147a on the first substrate 13, and at least covers the orthographic projection of the second via 147b on the first substrate. It is understood that the first via 147a and the second via 147b are weak points of the via structure 31. The spacer 15 covers at least the first via 147a and the second via 147b to isolate the first via 147a and the second via 147b from moisture, thereby improving the corrosion of the vias and enhancing the reliability of the display panel 1.

[0070] For example, see Figure 9 Along the direction Y, the two side edges of the spacer 15 extend beyond the two side edges of the first via 147a and the second via 147b by 13.5um (Mask value), and the single-side critical dimension deviation (CD Bais) of the spacer 15 is approximately 12μm (based on the data of HTM transmittance of 27%) to ensure that the spacer 15 completely covers the first via 147a and the second via 147b, thereby improving the corrosion of the vias.

[0071] Furthermore, both side edges of the spacer 15 extend beyond both side edges of the third conductive layer 145 by 5 μm (Mask value) to ensure that the spacer 15 completely covers the third conductive layer 145 , thereby improving the corrosion of the connection pattern 145 a .

[0072] In some embodiments, see Figure 8 and Figure 9 The array substrate 11 includes multiple conductive structures 14 and multiple spacers 15. The orthographic projections of the multiple spacers 15 on the first substrate 11 do not overlap, that is, the multiple spacers 15 are dispersed and non-overlapping on the plane XY, and the multiple spacers 15 are intermittently arranged to avoid the support height of the spacers 15 in the gate drive circuit 4 area being too large.

[0073] The orthographic projection of a spacer 15 on the first substrate 11 covers the orthographic projections of the first via 147a and the second via 147b of the same conductive structure 14 on the first substrate 13, that is, a fragmented spacer 15 is used to cover each via of the conductive structure 14, thereby improving the corrosion of the via.

[0074] Figure 10 This is a structural diagram of another gate drive circuit provided in an embodiment of the present application.

[0075] In some embodiments, see Figure 10 The orthographic projection of a spacer 15 on the first substrate 13 covers the orthographic projections of multiple conductive structures 14 on the first substrate 13, that is, using a large block of spacers 15 to cover the vias of multiple conductive structures 14 can prevent the intrusion of water vapor to a greater extent, avoid the accumulation of water vapor at the vias and cause electrochemical corrosion of ITO, thereby further improving the corrosion of the vias.

[0076] In some embodiments, see Figure 10 The array substrate 11 includes multiple conductive structures 14, and the multiple conductive structures 14 include a first conductive structure 141, a second conductive structure 142 and a third conductive structure 143. Exemplarily, the first conductive structure 141 is a via structure 31, the second conductive structure 142 is a cross-line structure 32, and the third conductive structure 143 is a device structure 33.

[0077] Continue to see Figure 10 The orthographic projections of the multiple spacers 15 on the first substrate 13 do not overlap. Among the first conductive structure 141, the second conductive structure 142, and the third conductive structure 143, the orthographic projection of one spacer 15 on the first substrate 13 covers the orthographic projections of at least two conductive structures 14 on the first substrate 13. The arrangement in which one spacer 15 covers two conductive structures 14 susceptible to water vapor corrosion prevents water vapor intrusion into the conductive structures 14 to a greater extent, improves any two of via corrosion, cross-line corrosion, and device corrosion, and further enhances the reliability of the display panel 1.

[0078] Illustratively, along a direction parallel to the plane XY, one spacer 15 covers the via structure 31 and the flyback structure 32 , or covers the flyback structure 32 and the device structure 33 , or covers the device structure 33 and the via structure 31 .

[0079] Figure 11 A structural diagram of another gate drive circuit provided in an embodiment of the present application; Figure 12 for Figure 11 A partial cross-sectional view of the gate drive circuit along section line CC'; Figure 13 for Figure 11 A partial cross-sectional view of the gate drive circuit along the section line DD'.

[0080] In some embodiments, see Figures 11 to 13 In the case where the conductive structure 14 is a cross-line structure 32, the array substrate 11 further includes a first conductive layer 141, a first dielectric layer 142, a second conductive layer 143, and a second dielectric layer 144 stacked in sequence on the first substrate 13. The conductive structure 14 includes a third signal line 146c located in the first conductive layer 142 and a fourth signal line 146d located in the second conductive layer 143. The fourth signal line 146d crosses the third signal line 146c.

[0081] Exemplarily, the first conductive layer 141 is a gate conductive layer (Gate), and the third signal line 146c is located in the gate conductive layer. The third signal line 146c can be, for example, a clock signal line for providing a clock control signal to the gate drive circuit 4. The first dielectric layer 142 is a gate insulating layer, which is used to isolate the third signal line 146c from the fourth signal line 146d to prevent the third signal line 146c and the fourth signal line 146d from shorting. The second conductive layer 143 is a source-drain conductive layer (SD), and the second signal line 146b is located in the source-drain conductive layer. Along the direction X, the fourth signal line 146d crosses the third signal line 146c to facilitate electrical connection with the target signal line.

[0082] like Figures 12 and 13As shown, the orthographic projection of the spacer 15 on the first substrate 13 at least partially overlaps with the orthographic projection of the third signal line 146c on the first substrate 13, and at least partially overlaps with the orthographic projection of the fourth signal line 146d on the first substrate 13. It can be understood that the spacer 15 covers at least the portion where the third signal line 146c and the fourth signal line 146d cross over, thereby isolating moisture from the crossover structure 32 and preventing moisture from entering through the holes at the interface between the source / drain conductive layer and the second dielectric layer 144, which could cause a short circuit across the lines. This improves the corrosion of the signal lines and enhances the reliability of the display panel 1.

[0083] In some embodiments, see Figures 11 to 13 The array substrate 11 includes multiple conductive structures 14 and multiple spacers 15. The orthographic projections of the multiple spacers 15 on the first substrate 11 do not overlap, that is, the multiple spacers 15 are dispersed and non-overlapping on the plane XY, and the multiple spacers 15 are intermittently arranged to avoid the support height of the spacers 15 in the gate drive circuit 4 area being too large.

[0084] The orthographic projection of a spacer 15 on the first substrate 13 covers the orthographic projections of the third signal line 146c and the fourth signal line 146d of a conductive structure 14 on the first substrate 13, that is, a fragmented spacer 15 is used to cover the cross-line structure 32 of each conductive structure 14, thereby improving the corrosion of the cross-line structure 32.

[0085] Figure 14 This is a structural diagram of another gate drive circuit provided in an embodiment of the present application.

[0086] In some embodiments, see Figure 14 The orthographic projection of a spacer 15 on the first substrate 13 covers the orthographic projections of the third signal line 146c and the fourth signal line 146d of the multiple conductive structures 14 on the first substrate 13. That is, using a large block of spacers 15 to cover the cross-line structure 32 of the multiple conductive structures 14 can prevent the intrusion of water vapor in this part to a greater extent, thereby further improving the corrosion of the cross-line structure 32.

[0087] Figure 15 This is a structural diagram of another gate drive circuit provided in an embodiment of the present application.

[0088] In some embodiments, see Figure 15In the case where the conductive structure 14 is a device structure 33, the conductive structure 14 includes at least one component 330, illustratively a TFT. The orthographic projection of the spacer 15 on the first substrate 13 covers the orthographic projection of the at least one component 330 on the first substrate 11. That is, by covering the component 330 with the spacer 15, moisture is isolated from the device structure 33, thereby improving the corrosion of the TFT device and preventing the negative characteristic bias caused by the invasion of H+, O-, and e-, thereby improving the reliability of the display panel 1.

[0089] For example, the orthographic projection of one spacer 15 on the first substrate 13 covers the orthographic projection of a component 330 of a device structure 33 on the first substrate 13, or the orthographic projection of one spacer 15 on the first substrate 13 covers the orthographic projection of components 330 of multiple device structures 33 on the first substrate 13. In the embodiments provided in the present application, Figure 15 The diagram shows a situation where a spacer 15 covers components 330 of a plurality of device structures 33 .

[0090] The array substrate 11 includes a plurality of main supports (Main PS) and a plurality of sub supports (Sub PS). The height of the sub supports (Sub PS) relative to the array substrate 11 is smaller than the height of the main supports (Main PS) relative to the array substrate 11 .

[0091] See also Figure 15 , wherein the spacer 15 is a sub-support (Sub PS), which prevents the height of the component 330 from being too high after the spacer 15 covers the component 330, thereby reducing the risk of over-support.

[0092] Figure 16 This is a structural diagram of another gate drive circuit provided in an embodiment of the present application.

[0093] In some embodiments, see Figure 16 The array substrate 11 includes multiple conductive structures 14, and the multiple conductive structures 14 include a first conductive structure 141, a second conductive structure 142 and a third conductive structure 143. Exemplarily, the first conductive structure 141 is a via structure 31, the second conductive structure 142 is a cross-line structure 32, and the third conductive structure 143 is a device structure 33.

[0094] The spacer 15 includes at least one first spacer 151, which serves as a sub-support (Sub PS). The orthographic projection of the first spacer 151 on the first substrate 13 covers the orthographic projections of the first conductive structure 141, the second conductive structure 142, and the third conductive structure 143 on the first substrate 13, that is, the first spacer 151 covers the three conductive structures 14. The first spacer 151 simultaneously protects the first conductive structure 141, the second conductive structure 142, and the third conductive structure 143 to prevent the above conductive structures 14 from being invaded by water vapor and corroded.

[0095] Figure 17 for Figure 5 Another partial cross-sectional view of the display panel along the section line AA'.

[0096] In some embodiments, see Figure 17 The array substrate 11 includes a plurality of spacers 15, including at least one first spacer 151 and a plurality of second spacers 152. The plurality of second spacers 152 serve as main supports (MainPS). Exemplarily, the first spacer 151 covers the entire gate drive circuit 4. The orthographic projection of the second spacer 152 on the first substrate 13 is located within the outer contour of the orthographic projection of the first spacer 151 on the first substrate 13. It can be understood that the second spacer 152 is embedded in the first spacer 151.

[0097] Relative to the first substrate 13, the height of the second spacer 152 is greater than the height of the first spacer 151, that is, it can be understood that along the direction Z, the support height of the multiple second spacers 152 is greater than the support height of the first spacer 151, and there is a certain distance between the second spacers 152 and the color filter substrate 12. When the display panel 1 is deformed, it can provide deformation space for the color filter substrate 12, and when the deformation of the color filter substrate 12 reaches a certain level, it will first contact the second spacer 152.

[0098] Figure 18 A schematic structural diagram of another spacer arrangement provided in an embodiment of the present application.

[0099] In some embodiments, see Figure 17 and Figure 18, the multiple spacers 15 also include multiple third spacers 153, the orthographic projection of the third spacer 153 on the first substrate 13 does not overlap with the orthographic projection of the first spacer 151 on the first substrate 13, that is, the third spacer 153 is not embedded in the first spacer 151, and the third spacer 153 serves as a single Main PS. Relative to the first substrate 13, the height of the third spacer 153 is greater than the height of the first spacer 151, and the height of the third spacer 153 is less than the height of the second spacer 152. Among them, the height of the second spacer 152 refers to the distance between the side surface of the second spacer 152 away from the conductive structure 14 and the side surface of the first spacer 151 close to the conductive structure 14. By forming multiple spacers 15 with a gradient support height in the peripheral area 3, the display unevenness (Mura) phenomenon of the display panel 1 can be improved.

[0100] For example, the height of the first spacer 151 is 2.62 μm, the height of the second spacer 152 is 3.17 μm, and the height of the third spacer 153 is 2.86 μm. The height of the second spacer 152 is about 0.3 μm higher than the height of the single third spacer 153 around it. After the display panel 1 is assembled into a box, under the action of atmospheric pressure, the second spacer 152 contacts the color film substrate 12 on the opposite side earlier, which is beneficial to reduce the peripheral warping of the display panel 1 and optimize the peripheral display unevenness (Mura) phenomenon.

[0101] Figure 19 A schematic structural diagram of another spacer arrangement provided in an embodiment of the present application; Figure 20 A structural schematic diagram of another spacer arrangement provided in an embodiment of the present application.

[0102] In some embodiments, see Figure 5 、 Figure 19 and Figure 20 The peripheral area 3 includes a first area 3a and a second area 3b. For example, the first area 3a is the area of ​​the peripheral area 3 close to the display area 2, and the second area 3b is located on the side of the first area 3a away from the display area 2. The second area 3b is located in the gate drive circuit 4.

[0103] See also Figure 19 The color filter substrate 12 includes a second substrate 121 and a dummy color resist layer 122 disposed on the side of the second substrate 121 near the array substrate 11. The dummy color resist layer 122 is located in the first region 3a. The first region 3a serves as a grayscale transition zone at the edge of the display, achieving a gradual transition from bright to dark brightness at the edge of the display. The dummy color resist layer 113 is disposed within the openings of the black matrix 123 of the color filter substrate 12.

[0104] See also Figure 19 and Figure 20The array substrate 11 includes a plurality of spacers 15, including a fourth spacer 154 and a fifth spacer 155. The orthographic projection of the fourth spacer 154 on the second substrate 121 overlaps with the orthographic projection of the dummy color-resist layer 122 on the second substrate 121, i.e., the fourth spacer 154 is positioned directly opposite the dummy color-resist layer 122. In other words, the fourth spacer 154 is disposed in the first region 3a. The orthographic projection of the fifth spacer 155 on the second substrate 121 does not overlap with the orthographic projection of the dummy color-resist layer 122 on the second substrate 121, i.e., the fifth spacer 155 does not directly face the dummy color-resist layer 122. The fifth spacer 155 may be disposed in the second region 3b. Relative to the first substrate 13, the height of the fifth spacer 155 is greater than the height of the fourth spacer 154.

[0105] It can be understood that a dummy color resist layer 122 is provided on the color filter substrate 12 corresponding to the first region 3a. However, no dummy color resist layer 122 is provided on the color filter substrate 12 in the second region 3b. Therefore, the thickness of the color filter substrate 12 in the first region 3a is greater than that in the second region 3b. Based on this, the support height of the fourth spacer 154 in the first region 3a is smaller than the support height of the fifth spacer 155 in the second region 3b. The lower support height of the fourth spacer 154 prevents the portion of the color filter substrate 12 in the first region 3a from contacting the fourth spacer 154 if the color filter substrate 12 deforms, thereby reducing the risk of the fourth spacer 154 over-supporting the color filter substrate 12.

[0106] For example, see Figure 5 、 Figure 19 and Figure 20 In the first region 3a, the conductive structure 14 may be a Gout via structure 311, and the spacer 15 may be a sub-support (Sub PS). In the second region 3b, when the conductive structure 14 is a TN via structure 312 or a CK via structure 313, the spacer 15 may be a main support (Main PS).

[0107] For example, in the manufacturing process of the display panel 1, the process flow on the color filter substrate 12 side is a traditional process. For the array substrate 11 side, the order of film formation is Gate→GI→IGZO→SD→PVX→ITO→PS, and finally the PS coating process, which is divided into coating, exposure and development, and baking. In the case of a small and crowded location of the cross-line structure 32, to prevent PS stacking, a half-tone exposure method or a strip mask exposure method can be used to reduce the volume of the PS and form an effective PS protection with a fragmented morphology.

[0108] Figures 21 to 24Structural diagram of the via structure, line-crossing structure and device structure provided in the embodiments of the present application.

[0109] In some embodiments, see Figures 21 to 24 The array substrate 11 further includes a planarization layer (ORG) 16, which is disposed between the conductive structure 14 and the spacer 15. For example, for the array substrate 11 including the planarization layer 16, the order of film formation is Gate → GI → IGZO → SD → PVX → ORG → ITO → PS, with PS coating forming the last step. The PS film formation method is consistent. The ORG does not significantly change the overall morphology of the conductive structure 14, but not only improves the flatness of the surface on which the PS is formed, but also works together with the spacer 15 to achieve double-layer protection for the conductive structure 14.

[0110] The embodiment of the present application further provides a display device, which may be a TFT-LCD. Figure 25 This is a structural diagram of a display device provided in an embodiment of the present application.

[0111] See also Figure 25 The display device 10 includes the display panel 1 in the above embodiment, and a controller 100 electrically connected to the display panel 1. The non-display side of the exemplary display panel 1 is provided with a circuit board 200, and the controller 100 is provided on the circuit board 200. The controller 100 is used to control the display panel 10 to display the picture.

[0112] The display device 10 described above can be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0113] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a peripheral area surrounding the display area; The display panel includes an array substrate and a color filter substrate that are arranged opposite to each other, and the array substrate includes: a first substrate; at least one conductive structure, disposed on a side of the first substrate close to the color filter substrate and located in the peripheral area; At least one spacer is disposed on a side of the conductive structure away from the first substrate, and an orthographic projection of one spacer on the first substrate at least partially overlaps with an orthographic projection of at least one conductive structure on the first substrate.

2. The display panel according to claim 1, wherein: The display panel further includes a gate driving circuit disposed on the first substrate, and the gate driving circuit includes the conductive structure; The orthographic projection of the spacer on the first substrate at least partially overlaps with the orthographic projection of the gate driving circuit on the first substrate.

3. The display panel according to claim 1, wherein: The array substrate further includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer stacked in sequence on the first substrate, the conductive structure including a first signal line located in the first conductive layer, a second signal line located in the second conductive layer, and a connection pattern located in the third conductive layer; A first via hole is provided in the first dielectric layer and the second dielectric layer, and the connection pattern is electrically connected to the first signal line through the first via hole; A second via hole is provided in the second dielectric layer, and the connection pattern is electrically connected to the second signal line through the second via hole; The orthographic projection of the spacer on the first substrate at least covers the orthographic projection of the first via hole on the first substrate, and at least covers the orthographic projection of the second via hole on the first substrate.

4. The display panel according to claim 3, wherein: The array substrate includes a plurality of the conductive structures and a plurality of the spacers, and the orthographic projections of the plurality of the spacers on the first substrate do not overlap; an orthographic projection of a spacer on the first substrate, covering the orthographic projections of the first via hole and the second via hole of the same conductive structure on the first substrate; Alternatively, the orthographic projection of a spacer on the first substrate covers the orthographic projections of the first via holes and the second via holes of the plurality of conductive structures on the first substrate.

5. The display panel according to claim 1, wherein: The conductive structure includes a third signal line and a fourth signal line, wherein the fourth signal line crosses the third signal line; The orthographic projection of the spacer on the first substrate at least partially overlaps with the orthographic projection of the third signal line on the first substrate, and at least partially overlaps with the orthographic projection of the fourth signal line on the first substrate.

6. The display panel according to claim 5, wherein: The array substrate includes a plurality of the conductive structures and a plurality of the spacers, and the orthographic projections of the plurality of the spacers on the first substrate do not overlap; an orthographic projection of a spacer on the first substrate, covering an orthographic projection of a third signal line and a fourth signal line of the conductive structure on the first substrate; Alternatively, an orthographic projection of a spacer on the first substrate covers the orthographic projections of the third signal lines and the fourth signal lines of the plurality of conductive structures on the first substrate.

7. The display panel according to claim 1, wherein: The conductive structure includes at least one component, and the orthographic projection of the spacer on the first substrate covers the orthographic projection of the at least one component on the first substrate.

8. The display panel according to claim 7, wherein: The array substrate includes a plurality of the conductive structures and a plurality of the spacers, and the orthographic projections of the plurality of the spacers on the first substrate do not overlap; An orthographic projection of a spacer on the first substrate covers an orthographic projection of a component of the conductive structure on the first substrate; Alternatively, the orthographic projection of one of the spacers on the first substrate covers the orthographic projections of a plurality of components of the conductive structure on the first substrate.

9. The display panel according to claim 1, wherein: The array substrate includes a plurality of conductive structures, and the plurality of conductive structures include a first conductive structure, a second conductive structure and a third conductive structure; The first conductive structure includes a first signal line, a second signal line, and a connection pattern, wherein the first signal line is electrically connected to the second signal line through the connection pattern; the second conductive structure includes a third signal line and a fourth signal line, wherein the fourth signal line crosses the third signal line; and the third conductive structure includes at least one component; The array substrate includes a plurality of spacers, and the orthographic projections of the plurality of spacers on the first substrate do not overlap; Among the first conductive structure, the second conductive structure, and the third conductive structure, an orthographic projection of one spacer on the first substrate covers an orthographic projection of at least two conductive structures on the first substrate.

10. The display panel according to claim 1, wherein The array substrate includes a plurality of conductive structures, and the plurality of conductive structures include a first conductive structure, a second conductive structure and a third conductive structure; The first conductive structure includes a first signal line, a second signal line, and a connection pattern, wherein the first signal line is electrically connected to the second signal line through the connection pattern; the second conductive structure includes a third signal line and a fourth signal line, wherein the fourth signal line crosses the third signal line; and the third conductive structure includes at least one component; The spacers include at least one first spacer, and the orthographic projection of the first spacer on the first substrate covers the orthographic projections of the first conductive structure, the second conductive structure, and the third conductive structure on the first substrate.

11. The display panel according to claim 10, wherein: The array substrate includes a plurality of spacers, and the plurality of spacers include at least one first spacer and a plurality of second spacers; The orthographic projection of the second spacer on the first substrate is located within the outer contour of the orthographic projection of the first spacer on the first substrate; relative to the first substrate, the height of the second spacer is greater than that of the first spacer.

12. The display panel according to claim 11, wherein: The plurality of spacers further include a plurality of third spacers, and the orthographic projections of the third spacers on the first substrate do not overlap with the orthographic projections of the first spacers on the first substrate; With respect to the first substrate, the height of the third spacer is greater than that of the first spacer, and the height of the third spacer is less than that of the second spacer.

13. The display panel according to claim 1, wherein The peripheral area includes a first area and a second area; the color filter substrate includes a second substrate and a virtual color resist layer provided on a side of the second substrate close to the array substrate, and the virtual color resist layer is located in the first area; The array substrate includes a plurality of spacers, the plurality of spacers include a fourth spacer and a fifth spacer, an orthographic projection of the fourth spacer on the second substrate overlaps with an orthographic projection of the virtual color resist layer on the second substrate, and an orthographic projection of the fifth spacer on the second substrate does not overlap with an orthographic projection of the virtual color resist layer on the second substrate; Relative to the first substrate, a height of the fifth spacer is greater than a height of the fourth spacer.

14. The display panel according to claim 1, wherein The array substrate further includes a planarization layer, and the planarization layer is arranged between the conductive structure and the spacer.

15. The display panel according to claim 1, wherein The spacer is made of a hydrophobic material.

16. A display device, characterized in that: include: The display panel according to any one of claims 1 to 15; A controller is electrically connected to the display panel.

Images