Sub-pixel and display device

Abstract

The utility model relates to a sub-pixel and a display device. The sub-pixel includes: a fourth transistor including a first electrode connected to a third node, a second electrode connected to a second power supply line to which a reference voltage is applied, and a gate electrode connected to a first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to the fourth node, and a gate electrode connected to a second emission control line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light emitting element including a first electrode connected to the fourth node and a second electrode connected to a fourth power supply line to which a second driving voltage is applied.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0136078, filed on October 12, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a sub-pixel, a display device including the sub-pixel, and a driving method of the display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. Therefore, various types of display devices such as liquid crystal display devices and organic light emitting diode display devices are widely used in various fields.

[0005] Recently, head-mounted display (HMD) devices have been developed. A head-mounted display device is a display device that a user wears in the form of glasses or a helmet to achieve virtual reality (VR) or augmented reality (AR) focused at a distance close to the eyes. High-resolution panels can be used in head-mounted display devices, and therefore, pixels that can be applied to high-resolution panels are desired. Utility Model Content

[0006] Embodiments of the present invention provide a sub-pixel applicable to a high-resolution panel, a display device including the sub-pixel, and a driving method of the display device.

[0007] A sub-pixel according to an embodiment of the present invention includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a first power line to which a first driving voltage is applied, and a gate electrode connected to a second node; a second transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to a first sub-gate line; a third transistor including a first electrode connected to one of a plurality of data lines, a second electrode connected to a third node, and a gate electrode connected to a second sub-gate line; a fourth transistor including a first electrode connected to the third node, a second electrode connected to a second power line to which a reference voltage is applied, and a gate electrode connected to a first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to a fourth node, and a gate electrode connected to a second emission control line; a sixth transistor including a first electrode connected to the fourth node, a second electrode connected to a third power line to which an initialization voltage is applied, and a gate electrode connected to a third sub-gate line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light-emitting element including a first electrode connected to the fourth node and a second electrode connected to the fourth power line to which a second driving voltage is applied.

[0008] In an embodiment, the emission control signal input to the second emission control line may be a signal whose phase is delayed by one horizontal period from the emission control signal input to the first emission control line.

[0009] In an embodiment, the capacitor may be a first capacitor, and the subpixel may further include a second capacitor including a first electrode connected to the second node and a second electrode connected to the first power line.

[0010] In an embodiment, each of the first to sixth transistors may be a P-type transistor.

[0011] In an embodiment, a voltage level of the first driving voltage may be higher than a voltage level of the second driving voltage.

[0012] In an embodiment, each of the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be turned on during the first period, and the third transistor may be turned off during the first period.

[0013] In an embodiment, during the first period, an initialization voltage may be applied to the second node, and a reference voltage may be applied to the third node.

[0014] In an embodiment, each of the first transistor, the second transistor, and the third transistor may be turned on during a second period following the first period, and each of the fourth transistor and the fifth transistor may be turned off during the second period.

[0015] In an embodiment, the first driving voltage may be applied to the second node during the second period, and the voltage of the data signal may be applied to the third node during the second period.

[0016] In an embodiment, each of the first transistor, the fourth transistor, and the fifth transistor may be turned on during a third period after the second period, and each of the third transistor and the sixth transistor may be turned off during the third period.

[0017] In an embodiment, current may flow through the first transistor and the fifth transistor during the third period, and a reference voltage may be applied to the third node during the third period.

[0018] A display device according to an embodiment of the present invention includes: a display panel including a plurality of sub-pixels and a plurality of data lines, a plurality of sub-gate lines and a plurality of emission control lines connected to the plurality of sub-pixels; a data driver providing data signals to the plurality of data lines; a gate driver providing gate signals to the plurality of sub-gate lines, and the gate driver providing emission control signals to the plurality of emission control lines; and a voltage generator applying an initialization voltage, a reference voltage, a first driving voltage and a second driving voltage to the plurality of sub-pixels, wherein the plurality of sub-gate lines include a first sub-gate line, a second sub-gate line and a third sub-gate line, the plurality of emission control lines include a first emission control line and a second emission control line, and the sub-pixels in the plurality of sub-pixels include: a first transistor including a first electrode connected to a first node, a second electrode connected to a first power line to which the first driving voltage is applied and a gate electrode connected to a second node; a second transistor including a first electrode connected to the first node, a second electrode connected to the second node a second electrode and a gate electrode connected to the first sub-gate line; a third transistor including a first electrode connected to a corresponding one of the plurality of data lines, a second electrode connected to the third node, and a gate electrode connected to the second sub-gate line; a fourth transistor including a first electrode connected to the third node, a second electrode connected to the second power line to which a reference voltage is applied, and a gate electrode connected to the first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to the fourth node, and a gate electrode connected to the second emission control line; a sixth transistor including a first electrode connected to the fourth node, a second electrode connected to the third power line to which an initialization voltage is applied, and a gate electrode connected to the third sub-gate line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light-emitting element including a first electrode connected to the fourth node and a second electrode connected to the fourth power line to which a second driving voltage is applied.

[0019] In an embodiment, the emission control signal input to the second emission control line may be a signal whose phase is delayed by one horizontal period from the emission control signal input to the first emission control line.

[0020] In an embodiment, the capacitor may be a first capacitor, and the subpixel may further include a second capacitor including a first electrode connected to the second node and a second electrode connected to the first power line.

[0021] In an embodiment, the gate driver may provide a gate signal at an on level to each of the second, fourth, fifth, and sixth transistors during the first period, and provide a gate signal at an off level to the third transistor during the first period.

[0022] In an embodiment, the gate driver may provide a gate signal at a turn-on level to each of the first transistor, the second transistor, and the third transistor during a second period following the first period, and may provide a gate signal at a turn-off level to each of the fourth transistor and the fifth transistor during the second period.

[0023] In an embodiment, the gate driver may provide a gate signal at a turn-on level to each of the first transistor, the fourth transistor, and the fifth transistor during a third period after the second period, and may provide a gate signal at a turn-off level to each of the third transistor and the sixth transistor during the third period.

[0024] A driving method for a sub-pixel (which includes a first transistor and a capacitor) includes: during a first cycle, supplying an initialization voltage to a second node connected to the first electrode of the capacitor and the gate electrode of the first transistor, and supplying a reference voltage to a third node connected to the second electrode of the capacitor; during a second cycle, floating the third node; during a third cycle, supplying a first driving voltage to the second node, and supplying a data signal to the third node; during a fourth cycle and a fifth cycle, floating the second node and the third node; during a sixth cycle, floating the second node and supplying a reference voltage to the third node; and during a seventh cycle, allowing current to flow in the first transistor based on the voltage applied to the second node.

[0025] In an embodiment, the sub-pixel further includes a light emitting element, and the initialization voltage may be supplied to the light emitting element during the third period.

[0026] In an embodiment, during the first period, a first gate signal at an on level may be supplied to the second transistor of the subpixel connecting the first node connected to the first electrode of the first transistor and the second node.

[0027] According to the embodiments of the present invention, a sub-pixel applicable to a high-resolution panel, a display device including the sub-pixel, and a driving method of the display device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0029] Figure 2 It shows Figure 1 Block diagram of an embodiment of one of the sub-pixels.

[0030] Figure 3 It shows Figure 2 A circuit diagram of an embodiment of a sub-pixel is shown in FIG.

[0031] Figure 4 It shows Figure 3 1 is a signal timing diagram of an embodiment of a sub-pixel driving method shown in FIG.

[0032] Figures 5 to 11 It shows Figure 3 The sub-pixel is based on Figure 4 Circuit diagram of the signal operation process.

[0033] Figure 12 It shows Figure 2 A circuit diagram of another embodiment of a sub-pixel is shown in FIG.

[0034] Figures 13 to 19 It shows Figure 12 The sub-pixel is based on Figure 4 Circuit diagram of the signal operation process.

[0035] Figure 20 It shows Figure 1 A plan view of an embodiment of a display panel.

[0036] Figure 21 It shows Figure 20 An exploded perspective view of a portion of a display panel.

[0037] Figure 22 It shows Figure 21 A plan view of an embodiment of one of the pixels.

[0038] Figure 23 It is along Figure 22 A cross-sectional view taken along line II'.

[0039] Figure 24 It shows Figure 21 A plan view of another embodiment of one of the pixels.

[0040] Figure 25 It shows Figure 21A plan view of another embodiment of one of the pixels.

[0041] Figure 26 is a block diagram illustrating an embodiment of a display system.

[0042] Figure 27 It shows Figure 26 A perspective view of an embodiment of a display system.

[0043] Figure 28 It shows Figure 27 A view of an embodiment of a head-mounted display device worn by a user. DETAILED DESCRIPTION

[0044] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals represent like elements throughout.

[0045] Throughout the specification, when one component is referred to as being "connected" to another component, this includes not only a case where it is "directly connected" but also a case where it is "indirectly connected" with another element interposed therebetween. The terms used in this specification are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0046] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0047] As used herein, the term "one", "one (kind / person)", "described (should)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both singular and plural. Therefore, after the reference to "one" element in the claim, the reference to "described" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" and "at least one element" have the same meaning. "At least one (kind / person)" should not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, term "and / or" includes any combination and all combinations of one or more related listed items. "At least one (kind / person) among X, Y and Z" and "at least one (kind / person) selected from X, Y and Z" can be interpreted as any combination (for example, XYZ, XY, YZ and XZ) of two or more among X, Y, Z. It will also be understood that when the terms “comprises and / or comprising” or “includes and / or including” are used in this specification, it indicates the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0048] Here, terms such as first, second, etc. can be used to describe various components, but these components are not limited to these terms. These terms are only used to distinguish one constituent element from another constituent element. Therefore, within the scope disclosed herein, a first component can be referred to as a second component.

[0049] Spatially relative terms such as "below," "above," etc. may be used for descriptive purposes to describe the relationship of one element or feature to another element(s) or another feature(s) as shown in the accompanying drawings. Spatially relative terms are intended to include different directions of use, operation, and / or manufacture in addition to the directions depicted in the accompanying drawings. For example, if the device shown in the accompanying drawings is flipped, an element described as being disposed "below" other elements or features may be disposed "above" the other elements or features. Thus, in one embodiment, the term "below" may include both "above" and "below" directions. Furthermore, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and therefore the spatially relative terms used herein should be interpreted accordingly.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0051] Various embodiments have been described with reference to the accompanying drawings, which illustrate idealized embodiments. Therefore, it is expected that shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but rather should be construed to include variations in shape that may occur, for example, due to manufacturing. Thus, the shapes shown in the drawings may not depict the actual shape of regions of the device, and the embodiments are not limited thereto.

[0052] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0053] Reference Figure 1 , an embodiment of the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0054] The display panel 110 may include subpixels SP. The subpixels SP may be connected to the gate driver 120 via first to m-th gate lines GL1 to GLm, where m is an integer greater than or equal to 1. The subpixels SP may be connected to the data driver 130 via first to n-th data lines DL1 to DLn, where n is an integer greater than or equal to 1. The first to m-th gate lines GL1 to GLm may extend in a first direction DR1 and be sequentially arranged in a second direction DR2 intersecting the first direction DR1. The first to n-th data lines DL1 to DLn may extend in a second direction DR2 and be sequentially arranged in the first direction DR1.

[0055] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Therefore, each of the sub-pixels SP may generate light of a specific color (such as red, green, blue, cyan, magenta, yellow, etc.). Two or more sub-pixels among the sub-pixels SP may constitute or collectively define a pixel (or unit pixel) PXL. In an embodiment, for example, Figure 1 As shown in FIG, three sub-pixels can constitute one pixel PXL.

[0056] The gate driver 120 may be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing at which a data signal is applied, and the like.

[0057] In an embodiment, first emission control lines EL11 to EL1m and second emission control lines EL21 to EL2m connected to the sub-pixels SP arranged in the row direction may be further provided. The first emission control lines EL11 to EL1m and the second emission control lines EL21 to EL2m may extend in the first direction DR1 and be sequentially arranged in the second direction DR2. In an embodiment, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL11 to EL1m and the second emission control lines EL21 to EL2m, and the emission control driver may operate under the control of the controller 150.

[0058] In an embodiment, the gate driver 120 may be provided on one side of the display panel 110. However, the embodiment is not limited thereto. In another embodiment, for example, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, and such drivers may be provided on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. In an embodiment, the gate driver 120 may be provided around the display panel 110 in various forms according to the embodiment.

[0059] The data driver 130 can be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0060] The data driver 130 can apply data signals having grayscale voltages corresponding to the image data DATA to the first to nth data lines DL1 to DLn using voltages from the voltage generator 140. When a gate signal is applied to each of the first to mth gate lines GL1 to GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Consequently, the corresponding subpixels SP can generate light having a brightness corresponding to the data signal. Consequently, an image can be displayed on the display panel 110.

[0061] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0062] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. In an embodiment, for example, the voltage generator 140 may be configured to generate the plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and controlling the adjusted voltage.

[0063] The voltage generator 140 may generate a first driving voltage VDD and a second driving voltage VSS, and the generated first driving voltage VDD and second driving voltage VSS may be provided to the subpixel SP. The first driving voltage VDD may have a relatively high voltage level, and the second driving voltage VSS may have a lower voltage level than the first driving voltage VDD. In other embodiments, the first driving voltage VDD or the second driving voltage VSS may be provided by an external device of the display device 100.

[0064] In an embodiment, the voltage generator 140 may generate various voltages. In an embodiment, for example, the voltage generator 140 may generate an initialization voltage Vint applied to the sub-pixel SP. In an embodiment, for example, the voltage generator 140 may generate a reference voltage Vref applied to the sub-pixel SP.

[0065] The controller 150 may control various operations of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of an image corresponding to the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS based on the control signal CTRL.

[0066] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110 and output the image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG to be suitable for sub-pixels SP in a row unit.

[0067] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1As shown in FIG, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In such an embodiment, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within one driver integrated circuit DIC. In other embodiments, at least one selected from the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0068] In an embodiment, the display device 100 may further include a temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature of its surroundings and generate temperature data TEP representing the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0069] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. In an embodiment, for example, the controller 150 may adjust the data signal and the first and second driving voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0070] Figure 2 It shows Figure 1 A block diagram of an embodiment of one of the sub-pixels of FIG. Figure 2 In the Figure 1 The sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0071] Reference Figure 2 , an embodiment of a sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0072] In an embodiment, the sub-pixel SPij may be connected to the first to fourth power lines PL1 to PL4. In such an embodiment, the first power line PL1 may be a power line that transmits power to the sub-pixel SPij. Figure 1 The second power line PL2 can be a power line for transmitting the first driving voltage VDD to the sub-pixel SPij. Figure 1 The third power line PL3 can be a power line for transmitting the reference voltage Vref to the sub-pixel SPij. Figure 1 The power supply line of the initialization voltage Vint, and the fourth power supply line PL4 can be a power supply line that transmits the initialization voltage Vint to the sub-pixel SPij. Figure 1A power supply line for a second driving voltage VSS.

[0073] The light-emitting element LD may be connected between the first power line PL1 and the fourth power line PL4. The anode electrode AE ​​of the light-emitting element LD may be connected to the first power line PL1 via the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD may be connected to the fourth power line PL4. In an embodiment, for example, the anode electrode AE ​​of the light-emitting element LD may be connected to the first power line PL1 via one or more transistors included in the sub-pixel circuit SPC.

[0074] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm, Figure 1 The i-th first emission control line EL1i (hereinafter, also referred to as the first emission control line EL1i) among the first to m-th first emission control lines EL11 to EL1m and Figure 1 an i-th second emission control line EL2i (hereinafter, also referred to as the second emission control line EL2i) among the first to m-th second emission control lines EL21 to EL2m, and Figure 1 The sub-pixel circuit SPC may be configured to control the light emitting element LD according to signals received through the signal lines.

[0075] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0076] The sub-pixel circuit SPC may operate in response to emission control signals received through the first emission control line EL1i and the second emission control line EL2i.

[0077] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one gate signal selected from the gate signals received via the sub-gate lines of the i-th gate line GLi. The sub-pixel circuit SPC can respond to emission control signals received via the first emission control line EL1i and the second emission control line EL2i to adjust the current flowing from the first power line PL1 through the light-emitting element LD to the fourth power line PL4 according to the stored voltage. Consequently, the light-emitting element LD can generate light having a brightness corresponding to the data signal.

[0078] Figure 3 It shows Figure 2 A circuit diagram of an embodiment of a sub-pixel is shown in FIG. Figure 3 In the Figure 1 The sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0079] Reference Figure 2 and Figure 3 The sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD. The sub-pixel circuit SPC may control the amount of current supplied to the light emitting element LD.

[0080] The sub-pixel circuit SPC may include one or more transistors and one or more capacitors.

[0081] Reference Figure 3 The sub-pixel circuit SPC according to an embodiment of the present invention may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, and a first capacitor C1. In an embodiment, each of the first to sixth transistors TR1 to TR6 may be a P-type metal oxide semiconductor field effect transistor (MOSFET).

[0082] A first electrode of the first transistor TR1 may be connected (e.g., electrically connected) to a first node N1, a second electrode of the first transistor TR1 may be connected to a first power line PL1 to which a first driving voltage VDD is applied, and a gate electrode of the first transistor TR1 may be connected (e.g., electrically connected) to a second node N2.

[0083] A first electrode of the second transistor TR2 may be connected (e.g., electrically connected) to the first node N1, a second electrode of the second transistor TR2 may be connected (e.g., electrically connected) to the second node N2, and a gate electrode of the second transistor TR2 may be electrically connected to the first sub-gate line SGL1i. The second transistor TR2 may be turned on in response to a first gate signal GC[i] at a turn-on level supplied to the first sub-gate line SGL1i.

[0084] A first electrode of the third transistor TR3 may be electrically connected to the j-th data line DLj, a second electrode of the third transistor TR3 may be connected (e.g., electrically connected) to a third node N3, and a gate electrode of the third transistor TR3 may be electrically connected to the second sub-gate line SGL2i. The third transistor TR3 may be turned on in response to a second gate signal GW[i] at a turn-on level supplied to the second sub-gate line SGL2i. The data signal Vdata may be supplied via the j-th data line DLj.

[0085] A first electrode of the fourth transistor TR4 may be connected (e.g., electrically connected) to the third node N3, a second electrode of the fourth transistor TR4 may be connected (e.g., electrically connected) to the second power line PL2 to which the reference voltage Vref is applied, and a gate electrode of the fourth transistor TR4 may be electrically connected to the first emission control line EL1i. The fourth transistor TR4 may be turned on in response to the first emission control signal EM1[i] at an on-level supplied to the first emission control line EL1i.

[0086] A first electrode of the fifth transistor TR5 may be connected (e.g., electrically connected) to the first node N1, a second electrode of the fifth transistor TR5 may be connected (e.g., electrically connected) to the fourth node N4, and a gate electrode of the fifth transistor TR5 may be electrically connected to the second emission control line EL2i. The fifth transistor TR5 may be turned on in response to the second emission control signal EM2[i] at a turn-on level supplied to the second emission control line EL2i.

[0087] A first electrode of the sixth transistor TR6 may be connected (e.g., electrically connected) to the fourth node N4, a second electrode of the sixth transistor TR6 may be connected (e.g., electrically connected) to the third power line PL3 to which the initialization voltage Vint is applied, and a gate electrode of the sixth transistor TR6 may be electrically connected to the third sub-gate line SGL3i. The sixth transistor TR6 may be turned on in response to a third gate signal GB[i] at a turn-on level supplied to the third sub-gate line SGL3i.

[0088] A first electrode of the first capacitor C1 may be connected (eg, electrically connected) to the second node N2 , and a second electrode of the first capacitor C1 may be connected (eg, electrically connected) to the third node N3 .

[0089] A first electrode of the light emitting element LD may be connected (eg, electrically connected) to the fourth node N4 , and a second electrode of the light emitting element LD may be connected (eg, electrically connected) to the fourth power line PL4 to which the second driving voltage VSS is applied.

[0090] The light emitting element LD may generate light (eg, light of a certain brightness) in response to the amount of current (eg, the magnitude of the driving current) supplied from the first power line PL1 to the fourth power line PL4 via the sub-pixel circuit SPC.

[0091] In an embodiment, the light emitting element LD may include an organic light emitting diode. In an embodiment, the light emitting element LD may include an inorganic light emitting diode, such as a micro LED (light emitting diode) or a quantum dot light emitting diode. In an embodiment, the light emitting element LD may be an element composed of a composite of organic and inorganic materials. Figure 3, an embodiment of a sub-pixel SPij including a single light emitting element LD is shown, but in another embodiment, the sub-pixel SPij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0092] Figure 4 It shows Figure 3 The signal timing diagram of the embodiment of the driving method of the sub-pixel shown in FIG. Figure 4 In the figure, the supply to Figure 1 The signal of the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0093] Reference Figure 1 、 Figure 3 and Figure 4 In an embodiment, the gate driver 120 may supply a first emission control signal EM1[i] at a turn-on level (eg, a low level) to the first emission control line EL1i during the first period PR1, the sixth period PR6, and the seventh period PR7.

[0094] The gate driver 120 may supply a second emission control signal EM2[i] at an on-level (e.g., a low level) to the second emission control line EL2i during the first period PR1, the second period PR2, and the seventh period PR7. The second emission control signal EM2[i] may be a signal that is phase-delayed by one horizontal period (1H) from the first emission control signal EM1[i]. One horizontal period (1H) may correspond to the length of a period in which the data signal Vdata is written to the sub-pixel SPij.

[0095] The gate driver 120 may supply the first gate signal GC[i] at a turn-on level (eg, a low level) to the first sub-gate line SGL1i during the first to third periods PR1 to PR3.

[0096] The gate driver 120 may supply the second gate signal GW[i] at a turn-on level (eg, a low level) to the second sub-gate line SGL2i during the third period PR3.

[0097] The gate driver 120 may supply the third gate signal GB[i] at a turn-on level (eg, a low level) to the third sub-gate line SGL3i during the first to fourth periods PR1 to PR4.

[0098] The data driver 130 may supply the data signal Vdata to the j-th data line DLj during the first to seventh periods PR1 to PR7 .

[0099] The first period PR1 may be a period in which the initialization voltage Vint is supplied to the second node N2 and the reference voltage Vref is supplied to the third node N3 .

[0100] The second period PR2 may be a period in which the initialization voltage Vint is supplied to the second node N2 and the third node N3 may float (or no constant voltage is applied). The gate driver 120 may supply the second gate signal GW[i] at the off level to the third transistor TR3 and the first emission control signal EM1[i] at the off level to the fourth transistor TR4, thereby floating the third node N3.

[0101] The third period PR3 may be a period in which the first driving voltage VDD is supplied to the second node N2 and the data signal Vdata is supplied to the third node N3. The gate driver 120 may supply the second gate signal GW[i] at a turn-on level to the third transistor TR3, thereby supplying the data signal Vdata to the third node N3.

[0102] The fourth and fifth periods PR4 and PR5 may be periods in which the second and third nodes N2 and N3 float. The gate driver 120 may supply a gate signal at an off level to the second to fifth transistors TR2 to TR5, thereby floating the second and third nodes N2 and N3.

[0103] The sixth period PR6 may be a period in which the second node N2 floats and the reference voltage Vref is supplied to the third node N3. The gate driver 120 may supply a control signal at an off level to the second, fifth, and sixth transistors TR2, TR5, and TR6, thereby floating the second node N2.

[0104] The seventh period PR7 may be a period in which the reference voltage Vref is supplied to the third node N3 and the light emitting element LD emits light with brightness corresponding to the amount of current supplied from the first transistor TR1 .

[0105] Figures 5 to 11 It shows Figure 3 The sub-pixel is based on Figure 4 The circuit diagram of the signal operation process. Figures 5 to 11 In the Figure 1 An operation process of the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0106] Reference Figure 5, the second transistor TR2 may be turned on by the first gate signal GC[i] at a turn-on level supplied to the first sub gate line SGL1i during the first period PR1.

[0107] The third transistor TR3 may be turned off by the second gate signal GW[i] at the off level (or high level) supplied to the second sub-gate line SGL2i during the first period PR1. When the third transistor TR3 is turned off, the electrical connection between the jth data line DLj and the third node N3 may be blocked.

[0108] The fourth transistor TR4 may be turned on by the first emission control signal EM1[i] at a turn-on level supplied to the first emission control line EL1i during the first period PR1.

[0109] The fifth transistor TR5 may be turned on by the second emission control signal EM2[i] at a turn-on level supplied to the second emission control line EL2i during the first period PR1.

[0110] The sixth transistor TR6 may be turned on by the third gate signal GB[i] at a turn-on level supplied to the third sub-gate line SGL3i during the first period PR1.

[0111] Therefore, during the first period PR1 , the initialization voltage Vint may be applied to the second node N2 , and the reference voltage Vref may be applied to the third node N3 .

[0112] Reference Figure 6 , the second transistor TR2 may maintain a turned-on state by the first gate signal GC[i] at a turned-on level supplied to the first sub-gate line SGL1i during the second period PR2.

[0113] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the second period PR2.

[0114] The fourth transistor TR4 can be turned off by the first emission control signal EM1[i] at the off level (or high level) supplied to the first emission control line EL1i during the second period PR2. When the fourth transistor TR4 is turned off, the electrical connection between the second power line PL2 and the third node N3 can be blocked.

[0115] The fifth transistor TR5 may maintain a turned-on state by the second emission control signal EM2[i] at a turned-on level supplied to the second emission control line EL2i during the second period PR2.

[0116] The sixth transistor TR6 may maintain a turned-on state by the third gate signal GB[i] at a turned-on level supplied to the third sub-gate line SGL3i during the second period PR2.

[0117] Therefore, the voltage of the second node N2 during the second period PR2 may be the initialization voltage Vint, and the third node N3 may float during the second period PR2.

[0118] Reference Figure 7 , the second transistor TR2 may maintain a turned-on state by the first gate signal GC[i] at a turned-on level supplied to the first sub-gate line SGL1i during the third period PR3.

[0119] The third transistor TR3 may be turned on by the second gate signal GW[i] at a turn-on level supplied to the second sub-gate line SGL2i during the third period PR3.

[0120] The fourth transistor TR4 may maintain a turn-off state by the first emission control signal EM1[i] at a turn-off level supplied to the first emission control line EL1i during the third period PR3.

[0121] The fifth transistor TR5 can be turned off by the second emission control signal EM2[i] at the off level (or high level) supplied to the second emission control line EL2i during the third period PR3. When the fifth transistor TR5 is turned off, the electrical connection between the first node N1 and the fourth node N4 can be blocked.

[0122] The sixth transistor TR6 may maintain a turned-on state by the third gate signal GB[i] at a turned-on level supplied to the third sub-gate line SGL3i during the third period PR3.

[0123] Therefore, during the third period PR3 , the voltage of the second node N2 may be (VDD−|Vth|_TR1 ), and the voltage of the third node N3 may be a voltage corresponding to the data signal Vdata.

[0124] Here, |Vth|_TR1 represents the absolute value of the threshold voltage of the first transistor TR1.

[0125] Reference Figure 8 The second transistor TR2 may be turned off by the first gate signal GC[i] at the off level (or high level) supplied to the first sub-gate line SGL1i during the fourth period PR4. When the second transistor TR2 is turned off, the electrical connection between the first node N1 and the second node N2 may be blocked.

[0126] The third transistor TR3 may be turned off by the second gate signal GW[i] at the turn-off level supplied to the second sub-gate line SGL2i during the fourth period PR4. When the third transistor TR3 is turned off, electrical connection between the j-th data line DLj and the third node N3 may be blocked.

[0127] The fourth transistor TR4 may maintain a turn-off state by the first emission control signal EM1[i] at a turn-off level supplied to the first emission control line EL1i during the fourth period PR4.

[0128] The fifth transistor TR5 may maintain a turn-off state by the second emission control signal EM2[i] at a turn-off level supplied to the second emission control line EL2i during the fourth period PR4.

[0129] The sixth transistor TR6 may maintain a turned-on state by the third gate signal GB[i] at a turned-on level supplied to the third sub-gate line SGL3i during the fourth period PR4.

[0130] Therefore, during the fourth period PR4 , the voltage of the second node N2 may be (VDD−|Vth|_TR1), and the voltage of the third node N3 may be a voltage corresponding to the data signal Vdata.

[0131] During the fourth period PR4, the initialization voltage Vint may be supplied to the fourth node N4. A voltage difference between the initialization voltage Vint and the second driving voltage VSS may be less than a threshold voltage of the light emitting element LD.

[0132] Reference Figure 9 , the second transistor TR2 may maintain a turned-off state by the first gate signal GC[i] at a turned-off level supplied to the first sub-gate line SGL1i during the fifth period PR5.

[0133] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the fifth period PR5.

[0134] The fourth transistor TR4 may maintain a turn-off state by the first emission control signal EM1[i] at a turn-off level supplied to the first emission control line EL1i during the fifth period PR5.

[0135] During the fifth period PR5 , the fifth transistor TR5 may maintain a turn-off state by the second emission control signal EM2 [i] at a turn-off level supplied to the second emission control line EL2 i.

[0136] The sixth transistor TR6 can be turned off by the third gate signal GB[i] at the off level (or high level) supplied to the third sub-gate line SGL3i during the fifth period PR5. When the sixth transistor TR6 is turned off, the electrical connection between the fourth node N4 and the third power line PL3 can be blocked.

[0137] Therefore, during the fifth period PR5 , the voltage of the second node N2 may be (VDD−|Vth|_TR1 ), and the voltage of the third node N3 may be a voltage corresponding to the data signal Vdata.

[0138] Reference Figure 10 The second transistor TR2 may maintain a turned-off state by the first gate signal GC[i] at a turned-off level supplied to the first sub-gate line SGL1i during the sixth period PR6. The second node N2 may be in a floating state.

[0139] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the sixth period PR6.

[0140] The fourth transistor TR4 may be turned on by the first emission control signal EM1[i] at a turn-on level supplied to the first emission control line EL1i during the sixth period PR6. A reference voltage Vref may be applied to the third node N3.

[0141] The fifth transistor TR5 may maintain a turn-off state by the second emission control signal EM2[i] at a turn-off level supplied to the second emission control line EL2i during the sixth period PR6.

[0142] The sixth transistor TR6 may maintain a turn-off state by the third gate signal GB[i] at a turn-off level supplied to the third sub-gate line SGL3i during the sixth period PR6.

[0143] Therefore, the reference voltage Vref may be applied to the third node N3. When the voltage of the third node N3 becomes the reference voltage Vref, the voltage of the second node N2 may change due to the coupling phenomenon of the first capacitor C1. The voltage of the second node N2 may become (VDD-|Vth|_TR1-Vdata+Vref).

[0144] Reference Figure 11 , the second transistor TR2 may maintain a turn-off state by the first gate signal GC[i] at a turn-off level supplied to the first sub-gate line SGL1i during the seventh period PR7.

[0145] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the seventh period PR7.

[0146] The fourth transistor TR4 may maintain a turned-on state by the first emission control signal EM1[i] at a turned-on level supplied to the first emission control line EL1i during the seventh period PR7.

[0147] The fifth transistor TR5 may be turned on by the second emission control signal EM2[i] supplied to the second emission control line EL2i during the seventh period PR7.

[0148] The sixth transistor TR6 may maintain a turn-off state by the third gate signal GB[i] at a turn-off level supplied to the third sub-gate line SGL3i during the seventh period PR7.

[0149] Therefore, during the seventh period PR7 , the voltage of the second node N2 may be (VDD−|Vth|_TR1−Vdata+Vref), and the voltage of the third node N3 may be the reference voltage Vref.

[0150] The gate electrode of the first transistor TR1 can be electrically connected to the second node N2, so the voltage (Vg) of the gate electrode of the first transistor TR1 can be the same as (or substantially the same as) the voltage of the second node N2. The source electrode of the first transistor TR1 can be electrically connected to the first power line PL1, so the voltage (Vs) of the source electrode of the first transistor TR1 can be the first driving voltage VDD.

[0151] In the seventh period PR7, a driving current corresponding to the data signal Vdata may flow through the light emitting element LD. The magnitude of the driving current flowing through the light emitting element LD may be determined by the voltage difference between the gate-source voltage (Vsg) and the threshold voltage (|Vth|_TR1) of the first transistor TR1.

[0152] The gate-source voltage (Vsg) of the first transistor TR1 may be a value obtained by subtracting the voltage (Vg) of the gate electrode of the first transistor TR1 from the voltage (Vs) of the source electrode of the first transistor TR1. The gate-source voltage (Vsg) of the first transistor TR1 may be (|Vth|_TR1+Vdata-Vref), and the voltage difference between the gate-source voltage (Vsg) of the first transistor TR1 and the threshold voltage (|Vth|_TR1) may be (Vdata-Vref).

[0153] As a result, the variation in the threshold voltage of the first transistor TR1 can be compensated, and a driving current not affected by the variation in the threshold voltage can flow through the first transistor TR1. Therefore, the display quality can be improved.

[0154] Figure 12 It shows Figure 2 A circuit diagram of another embodiment of a sub-pixel is shown in FIG. Figure 12 In the Figure 1 The sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0155] Reference Figure 2 and Figure 12 ,and Figure 3 Compared with the sub-pixel SPij, Figure 12 The sub-pixel SPij may further include a second capacitor C2.

[0156] Figure 12 The configurations of the first to sixth transistors TR1 to TR6 and the first capacitor C1 in the sub-pixel SPij can be the same as their Figure 3 The configuration of the sub-pixel SPij is the same as that of the sub-pixel SPij. In the following, the description of the first transistor TR1 to the sixth transistor TR6 and the first capacitor C1 will be omitted. Figure 3 Any repetitions of the same are described in detail.

[0157] In such an embodiment, a first electrode of the second capacitor C2 may be connected (eg, electrically connected) to the second node N2, and a second electrode of the second capacitor C2 may be connected (eg, electrically connected) to the first power line PL1 to which the first driving voltage VDD is applied.

[0158] Figures 13 to 19 It shows Figure 12 The sub-pixel is based on Figure 4 The circuit diagram of the signal operation process. Figures 13 to 19 In the Figure 1 The operation process of the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP is taken as an example.

[0159] Reference Figure 13 , the second transistor TR2 may be turned on by the first gate signal GC[i] at a turn-on level supplied to the first sub gate line SGL1i during the first period PR1.

[0160] The third transistor TR3 may be turned off by the second gate signal GW[i] at the off level (or high level) supplied to the second sub-gate line SGL2i during the first period PR1. When the third transistor TR3 is turned off, the electrical connection between the jth data line DLj and the third node N3 may be blocked.

[0161] The fourth transistor TR4 may be turned on by the first emission control signal EM1[i] at a turn-on level supplied to the first emission control line EL1i during the first period PR1.

[0162] The fifth transistor TR5 may be turned on by the second emission control signal EM2[i] at a turn-on level supplied to the second emission control line EL2i during the first period PR1.

[0163] The sixth transistor TR6 may be turned on by the third gate signal GB[i] at a turn-on level supplied to the third sub-gate line SGL3i during the first period PR1.

[0164] Therefore, during the first period PR1 , the initialization voltage Vint may be applied to the second node N2 , and the reference voltage Vref may be applied to the third node N3 .

[0165] Reference Figure 14 , the second transistor TR2 may maintain a turned-on state by the first gate signal GC[i] at a turned-on level supplied to the first sub-gate line SGL1i during the second period PR2.

[0166] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the second period PR2.

[0167] The fourth transistor TR4 can be turned off by the first emission control signal EM1[i] at the off level (or high level) supplied to the first emission control line EL1i during the second period PR2. When the fourth transistor TR4 is turned off, the electrical connection between the second power line PL2 and the third node N3 can be blocked.

[0168] The fifth transistor TR5 may maintain a turned-on state by the second emission control signal EM2[i] at a turned-on level supplied to the second emission control line EL2i during the second period PR2.

[0169] The sixth transistor TR6 may maintain a turned-on state by the third gate signal GB[i] at a turned-on level supplied to the third sub-gate line SGL3i during the second period PR2.

[0170] Therefore, the voltage of the second node N2 during the second period PR2 may be the initialization voltage Vint, and the third node N3 may float during the second period PR2.

[0171] Reference Figure 15 , the second transistor TR2 may maintain a turned-on state by the first gate signal GC[i] at a turned-on level supplied to the first sub-gate line SGL1i during the third period PR3.

[0172] The third transistor TR3 may be turned on by the second gate signal GW[i] at a turn-on level supplied to the second sub-gate line SGL2i during the third period PR3.

[0173] The fourth transistor TR4 may maintain a turn-off state by the first emission control signal EM1[i] at a turn-off level supplied to the first emission control line EL1i during the third period PR3.

[0174] The fifth transistor TR5 can be turned off by the second emission control signal EM2[i] at the off level (or high level) supplied to the second emission control line EL2i during the third period PR3. When the fifth transistor TR5 is turned off, the electrical connection between the first node N1 and the fourth node N4 can be blocked.

[0175] The sixth transistor TR6 may maintain a turned-on state by the third gate signal GB[i] at a turned-on level supplied to the third sub-gate line SGL3i during the third period PR3.

[0176] Therefore, during the third period PR3 , the voltage of the second node N2 may be (VDD−|Vth|_TR1 ), and the voltage of the third node N3 may be a voltage corresponding to the data signal Vdata.

[0177] Here, |Vth|_TR1 is the absolute value of the threshold voltage of the first transistor TR1.

[0178] Reference Figure 16 The second transistor TR2 may be turned off by the first gate signal GC[i] at the off level (or high level) supplied to the first sub-gate line SGL1i during the fourth period PR4. When the second transistor TR2 is turned off, the electrical connection between the first node N1 and the second node N2 may be blocked.

[0179] The third transistor TR3 may be turned off by the second gate signal GW[i] at the turn-off level supplied to the second sub-gate line SGL2i during the fourth period PR4. When the third transistor TR3 is turned off, electrical connection between the j-th data line DLj and the third node N3 may be blocked.

[0180] The fourth transistor TR4 may maintain a turn-off state by the first emission control signal EM1[i] at a turn-off level supplied to the first emission control line EL1i during the fourth period PR4.

[0181] The fifth transistor TR5 may maintain a turn-off state by the second emission control signal EM2[i] at a turn-off level supplied to the second emission control line EL2i during the fourth period PR4.

[0182] The sixth transistor TR6 may maintain a turned-on state by the third gate signal GB[i] at a turned-on level supplied to the third sub-gate line SGL3i during the fourth period PR4.

[0183] Therefore, during the fourth period PR4 , the voltage of the second node N2 may be (VDD−|Vth|_TR1), and the voltage of the third node N3 may be a voltage corresponding to the data signal Vdata.

[0184] During the fourth period PR4, the initialization voltage Vint may be supplied to the fourth node N4. A voltage difference between the initialization voltage Vint and the second driving voltage VSS may be less than a threshold voltage of the light emitting element LD.

[0185] Reference Figure 17 , the second transistor TR2 may maintain a turned-off state by the first gate signal GC[i] at a turned-off level supplied to the first sub-gate line SGL1i during the fifth period PR5.

[0186] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the fifth period PR5.

[0187] The fourth transistor TR4 may maintain a turn-off state by the first emission control signal EM1[i] at a turn-off level supplied to the first emission control line EL1i during the fifth period PR5.

[0188] During the fifth period PR5 , the fifth transistor TR5 may maintain a turn-off state by the second emission control signal EM2 [i] at a turn-off level supplied to the second emission control line EL2 i.

[0189] The sixth transistor TR6 can be turned off by the third gate signal GB[i] at the off level (or high level) supplied to the third sub-gate line SGL3i during the fifth period PR5. When the sixth transistor TR6 is turned off, the electrical connection between the fourth node N4 and the third power line PL3 can be blocked.

[0190] Therefore, during the fifth period PR5 , the voltage of the second node N2 may be (VDD−|Vth|_TR1 ), and the voltage of the third node N3 may be a voltage corresponding to the data signal Vdata.

[0191] Reference Figure 18 The second transistor TR2 may maintain a turned-off state by the first gate signal GC[i] at a turned-off level supplied to the first sub-gate line SGL1i during the sixth period PR6. The second node N2 may be in a floating state.

[0192] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the sixth period PR6.

[0193] The fourth transistor TR4 may be turned on by the first emission control signal EM1[i] at a turn-on level supplied to the first emission control line EL1i during the sixth period PR6. A reference voltage Vref may be applied to the third node N3.

[0194] The fifth transistor TR5 may maintain a turn-off state by the second emission control signal EM2[i] at a turn-off level supplied to the second emission control line EL2i during the sixth period PR6.

[0195] The sixth transistor TR6 may maintain a turn-off state by the third gate signal GB[i] at a turn-off level supplied to the third sub-gate line SGL3i during the sixth period PR6.

[0196] Therefore, the reference voltage Vref may be applied to the third node N3. When the voltage of the third node N3 becomes the reference voltage Vref, the voltage of the second node N2 may change due to the coupling phenomenon of the first capacitor C1. The voltage of the second node N2 may change to

[0197]

[0198] Reference Figure 19 , the second transistor TR2 may maintain a turn-off state by the first gate signal GC[i] at a turn-off level supplied to the first sub-gate line SGL1i during the seventh period PR7.

[0199] The third transistor TR3 may maintain a turn-off state by the second gate signal GW[i] at a turn-off level supplied to the second sub-gate line SGL2i during the seventh period PR7.

[0200] The fourth transistor TR4 may maintain a turned-on state by the first emission control signal EM1[i] at a turned-on level supplied to the first emission control line EL1i during the seventh period PR7.

[0201] The fifth transistor TR5 may be turned on by the second emission control signal EM2[i] supplied to the second emission control line EL2i during the seventh period PR7.

[0202] The sixth transistor TR6 may maintain a turn-off state by the third gate signal GB[i] at a turn-off level supplied to the third sub-gate line SGL3i during the seventh period PR7.

[0203] As a result, during the seventh period PR7, the voltage of the second node N2 may be And the voltage of the third node N3 may be the reference voltage Vref.

[0204] The gate electrode of the first transistor TR1 can be electrically connected to the second node N2, so the voltage (Vg) of the gate electrode of the first transistor TR1 can be the same as (or substantially the same as) the voltage of the second node N2. The source electrode of the first transistor TR1 can be electrically connected to the first power line PL1, so the voltage (Vs) of the source electrode of the first transistor TR1 can be the first driving voltage VDD.

[0205] In the seventh period PR7, a driving current corresponding to the data signal Vdata may flow through the light emitting element LD. The magnitude of the driving current flowing through the light emitting element LD may be determined by the voltage difference between the gate-source voltage (Vsg) and the threshold voltage (|Vth|_TR1) of the first transistor TR1.

[0206] The gate-source voltage (Vsg) of the first transistor TR1 may be a value obtained by subtracting the voltage (Vg) of the gate electrode of the first transistor TR1 from the voltage (Vs) of the source electrode of the first transistor TR1. The gate-source voltage (Vsg) of the first transistor TR1 may be And the voltage difference between the gate-source voltage (Vsg) and the threshold voltage (|Vth|_TR1) of the first transistor TR1 may be

[0207] As a result, the variation in the threshold voltage of the first transistor TR1 can be compensated, and a driving current not affected by the variation in the threshold voltage can flow through the first transistor TR1. Therefore, the display quality can be improved.

[0208] In such an embodiment, a relatively uniform driving current may flow through the light emitting element LD.

[0209] In such an embodiment, the data signal Vdata can be used in a wider range, thereby improving display quality.

[0210] Figure 20 It shows Figure 1 A plan view of an embodiment of a display panel.

[0211] Reference Figure 20 , Figure 1 An embodiment of the display panel 110 (eg, display panel DP) may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0212] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0213] In an embodiment where the display panel DP is used as a display screen for a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device, the display panel DP may be disposed very close to the user's eyes. In such an embodiment, it is desirable to have sub-pixels SP with a relatively high degree of integration. In order to increase the degree of integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB that is a silicon substrate. A display device 100 (see FIG. 1 ) including a display panel DP formed on a substrate SUB that is a silicon substrate Figure 1 ) can be called an organic light emitting diode (OLED) on silicon (OLEDoS) display device.

[0214] The sub-pixels SP are arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix in a first direction DR1 and a second direction DR2 crossing the first direction DR1. However, the embodiment is not limited thereto. In the embodiment, for example, the sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. In the embodiment, for example, the sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0215] Two or more sub-pixels among the plurality of sub-pixels SP may constitute one pixel PXL.

[0216] Components for controlling the sub-pixels SP may be provided in the non-display area NDA on the substrate SUB. In an embodiment, for example, lines connected to the sub-pixels SP (such as Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn) may be disposed in the non-display area NDA.

[0217] from Figure 1 At least one selected from the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA. In an embodiment, Figure 1 The gate driver 120 may be mounted on the display panel DP and disposed in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In an embodiment, Figure 1 The temperature sensor 160 may be disposed in the non-display area NDA to detect the temperature of the display panel DP.

[0218] The pad PD may be provided in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. In an embodiment, for example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0219] The pads PD may connect the display panel DP to the display device 100 (see Figure 1 In an embodiment, voltages and signals for the operation of components included in the display panel DP may be supplied from the display panel DP via the pads PD. Figure 1 In an embodiment, for example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC through the pad PD. In an embodiment, for example, the first driving voltage VDD and the second driving voltage VSS can be received from the driver integrated circuit DIC through the pad PD. In an embodiment, for example, the gate driver 120 is mounted on the display panel DP, the gate control signal GCS (see Figure 1 ) can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0220] In an embodiment, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. In such an embodiment, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film including or made of a flexible material. The driver integrated circuit DIC may be mounted on the circuit board and electrically connected to the pad PD.

[0221] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. In an embodiment, for example, the display area DA may have a shape such as a polygon, a circle, a semicircle, or an ellipse.

[0222] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In such an embodiment, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0223] Figure 21 It shows Figure 20 An exploded perspective view of a portion of the display panel. Figure 21 In the figure, for the sake of clarity and simplicity, the display panel DP is schematically shown. Figure 20 Portions of the display panel DP corresponding to the two pixels PXL1 and PXL2 among the pixels PXL may be similarly configured.

[0224] Reference Figure 20 and Figure 21 In an embodiment of the display panel, each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited thereto. In an embodiment, for example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0225] In an embodiment, Figure 21 As shown in FIG, when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have a quadrilateral shape and the same size as each other. However, the embodiment is not limited thereto. In the embodiment, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be modified to have various shapes.

[0226] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0227] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. In an embodiment, for example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0228] The pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a portion of a circuit element, line, or the like. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0229] The circuit element may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see Figure 2 ). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment where the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment where the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. In an embodiment, for example, each capacitor may include electrodes spaced apart from each other on a plane defined by the first direction DR1 and the second direction DR2. In an embodiment, for example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer may be interposed between the electrodes.

[0230] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , for example, gate lines, emission control lines, and data lines.

[0231] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0232] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0233] A pixel-defining layer (PDL) may be disposed on the anode electrodes AE. The pixel-defining layer (PDL) may include an opening (OP) defined therethrough to expose a portion of each of the anode electrodes (AE). The opening (OP) of the pixel-defining layer (PDL) may be understood as an emission region corresponding to each of the first to third subpixels (SP1, SP3).

[0234] In an embodiment, the pixel defining layer PDL may include an inorganic material. In such an embodiment, the pixel defining layer PDL may include a plurality of stacked inorganic layers. In an embodiment, for example, the pixel defining layer PDL may include silicon oxide (SiO x ) or silicon nitride (SiN x In other embodiments, the pixel defining layer (PDL) may include an organic material. However, the material of the pixel defining layer (PDL) is not limited thereto.

[0235] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0236] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be completely disposed on the pixel defining layer PDL. In such an embodiment, the light emitting structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. In such an embodiment, at least some of the layers in the light emitting structure EMS may be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiment is not limited thereto. In an embodiment, for example, the portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 are separated from each other, and each of the separated portions may be disposed within the opening OP of the pixel defining layer PDL.

[0237] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend throughout the first to third subpixels SP1 to SP3, and the cathode electrode CE may serve as a common electrode for the first to third subpixels SP1 to SP3.

[0238] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may include or be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one selected from various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one selected from silver (Ag) and magnesium (Mg). However, the material of the cathode electrode CE is not limited thereto.

[0239] Any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping with the anode electrode AE, and the portion of the cathode electrode CE overlapping with the anode electrode AE ​​will be understood to constitute one light emitting element LD (see Figure 2 ). In other words, each of the light-emitting elements of the first to third subpixels SP1 to SP3 may include an anode electrode, a portion of the light-emitting structure EMS that overlaps with the anode electrode, and a portion of the cathode electrode CE that overlaps with the anode electrode. In each of the first to third subpixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light-emitting layer of the light-emitting structure EMS to generate excitons, and when the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined by the amount of current flowing through the light-emitting layer. The wavelength range of the generated light may be determined by the configuration of the light-emitting layer.

[0240] The encapsulation layer TFE may be provided on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. In an embodiment, for example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y In an embodiment, for example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0241] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (Al x O y The thin layer including aluminum oxide may be provided on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0242] The thin layer containing aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may also include a thin layer formed of at least one selected from various materials suitable for improving encapsulation efficiency.

[0243] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0244] The color filter layer CFL may be provided between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EMS and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, and each of the color filters CF may pass light of a wavelength range corresponding to the corresponding sub-pixel. In an embodiment, for example, the color filter corresponding to the first sub-pixel SP1 may pass red light, the color filter corresponding to the second sub-pixel SP2 may pass green light, and the color filter corresponding to the third sub-pixel SP3 may pass blue light. Depending on the light emitted from the light emitting structure EMS of each sub-pixel, at least some of the color filters CF may be omitted.

[0245] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light-emitting structure EMS along a desired path. The lens array LA may have a relatively high refractive index. In an embodiment, for example, the lens array LA may have a higher refractive index than the overcoat layer OC. In an embodiment, the lenses LS may include an organic material. In an embodiment, the lenses LS may include an acrylate material. However, the material of the lenses LS is not limited thereto.

[0246] In an embodiment, at least a portion of the color filter CF of the color filter layer CFL and at least a portion of the lens LS of the lens array LA may be shifted in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. Specifically, in a central area of ​​the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned with or overlapped with the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In an area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be shifted in a plane direction from the center of the opening OP of the corresponding pixel defining layer PDL. For example, in an area of ​​the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filters CF of the color filter layer CFL and the corresponding lenses LS of the lens array LA. Therefore, in the center of the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction normal to the display surface. In the outer areas of the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction inclined at a predetermined angle relative to the normal to the display surface.

[0247] An overcoat layer OC may be provided on the lens array LA. The overcoat layer OC may cover the optical functional layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the underlying layers from foreign substances such as dust, moisture, and the like. In an embodiment, for example, the overcoat layer OC may include an inorganic insulating layer or an organic insulating layer. In an embodiment, for example, the overcoat layer OC may include an epoxy resin, but the embodiment is not limited thereto. The overcoat layer OC may have a lower refractive index than the lens array LA.

[0248] A cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect the underlying layers. The cover window CW may have a higher refractive index than the overcoat layer OC. The cover window CW may comprise glass, but embodiments are not limited thereto. In an embodiment, for example, the cover window CW may be encapsulating glass configured to protect components disposed thereunder. In other embodiments, the cover window CW may be omitted.

[0249] Figure 22 It shows Figure 21 A plan view of an embodiment of one of the pixels of FIG. Figure 22 For the sake of clarity and simplicity, the schematic diagram Figure 21The remaining pixels may be configured similarly to the first pixel PXL1.

[0250] Reference Figure 21 and Figure 22 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0251] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA located around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA located around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA located around the third emission area EMA3.

[0252] The first emission area EMA1 may be formed from the light emitting structure EMS (see Figure 21 ) may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 21 As described above, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0253] Figure 23 It is along Figure 22 A cross-sectional view taken along line II'.

[0254] Reference Figure 23 , also refer to Figure 20 In an embodiment of the display panel, a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided. The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. In an embodiment, for example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0255] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. In an embodiment, for example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (see FIG. 1 ) included in the first sub-pixel SP1. Figure 2 ), the transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 23 , for clarity and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0256] The transistor T_SP1 of the first sub-pixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0257] The source region SRA and the drain region DRA may be provided in the substrate SUB. A well WL formed by an ion implantation process may be defined in the substrate SUB, and the source region SRA and the drain region DRA may be provided spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0258] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0259] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and such conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connection portion DRC disposed through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connection portion SRC disposed through one or more insulating layers.

[0260] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the transistors of the first subpixel SP1 .

[0261] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured in the same manner as the transistor T_SP1 of the first subpixel SP1 .

[0262] As such, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0263] The via layer VIAL may be provided on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have an overall flat surface. The via layer VIAL may be configured to flatten the steps (or uneven upper surface) on the pixel circuit layer PCL. The via layer VIAL may include a silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon carbonitride (SiCN), but the embodiment is not limited thereto.

[0264] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0265] On the via layer VIAL, the first to third reflective electrodes RE1 to RE3 may be respectively disposed in the first to third sub-pixels SP1 to SP3. In one or more embodiments, each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via hole disposed through the via layer VIAL.

[0266] The first to third reflective electrodes RE1 to RE3 may function as total reflection mirrors that reflect light emitted from the light emitting structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one selected from aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), as well as alloys of two or more selected from the foregoing materials, but the embodiment is not limited thereto.

[0267] In an embodiment, a connection electrode may be provided below each of the first to third reflective electrodes RE1 to RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be provided between the multiple layers of the connection electrode.

[0268] A buffer pattern BFP may be provided below at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. In an embodiment, for example, the buffer pattern BFP may be provided between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0269] The first to third reflective electrodes RE1 to RE3 can function as fully reflective mirrors, and the cathode electrode CE can function as a semi-reflective mirror. By reciprocating between the respective reflective electrodes and the cathode electrode CE, light emitted from the light-emitting layer of the light-emitting structure EMS can be at least partially amplified, and the amplified light can be output through the cathode electrode CE. In this manner, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonant distance of light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0270] Due to the buffering pattern, the first subpixel SP1 can have a shorter resonance distance than other subpixels. This adjusted resonance distance allows light within a specific wavelength range (e.g., red) to be effectively and efficiently amplified. As a result, the first subpixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0271] exist Figure 23 In the figure, the buffer pattern BFP is shown as being provided to the first subpixel SP1, but not to the second and third subpixels SP2 and SP3, but the embodiment is not limited thereto. The buffer pattern BFP may also be provided to at least one selected from the second and third subpixels SP2 and SP3 to adjust the resonance distance of at least one selected from the second and third subpixels SP2 and SP3. In an embodiment, for example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively, and the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0272] To flatten the steps between the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may substantially cover the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and may have a flat surface. In embodiments, the planarization layer PLNL may be omitted.

[0273] On the planarization layer PLNL, the first to third anode electrodes AE1 to AE3 may be disposed to overlap with the first to third reflective electrodes RE1 to RE3, respectively. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may overlap with the first to third reflective electrodes RE1 to RE3. Figure 22 The first to third emission areas EMA1 to EMA3 have similar shapes. The first to third anode electrodes AE1 to AE3 can be connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode electrode AE1 can be connected to the first reflective electrode RE1 via a first via VIA1 provided through the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 via a second via VIA2 provided through the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 via a third via VIA3 provided through the planarization layer PLNL.

[0274] In an embodiment, the first to third anode electrodes AE1 to AE3 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or the like. x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. In an embodiment, for example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0275] In embodiments, an insulating layer may be further provided to adjust the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be disposed between one or more of the first to third anode electrodes AE1 to AE3 and the corresponding reflective electrode. In such embodiments, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. In embodiments, for example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively, and the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. A pixel-defining layer PDL may be disposed over the first to third anode electrodes AE1 to AE3 and portions of the planarization layer PLNL. The pixel-defining layer PDL may have an opening OP defined therethrough to expose a portion of each of the first to third anode electrodes AE1 to AE3. The opening OP of the pixel-defining layer PDL may define an emission region for each of the first to third subpixels SP1 to SP3. In this way, the pixel definition layer PDL can be provided on Figure 22 The non-emitting area NEA is defined as Figure 22 The first emission area EMA1 to the third emission area EMA3.

[0276] In an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ) In an embodiment, for example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked sequentially, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the embodiment is not limited thereto. The first to third inorganic insulating layers may have a stepped cross-section in a region adjacent to the opening OP.

[0277] The separator SPR may be provided at the boundary area BDA between adjacent sub-pixels. In other words, the separator SPR may be provided at the boundary area BDA between adjacent sub-pixels. Figure 20 At each of the boundary regions between the sub-pixels SP in .

[0278] The separation member SPR may cause a discontinuity to be formed in the light emitting structure EMS at the boundary area BDA. In an embodiment, for example, the light emitting structure EMS may be disconnected or bent at the boundary area BDA due to the separation member SPR.

[0279] The separator SPR may be provided in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more trenches TRCH1 and TRCH2 as the separator SPR at the boundary area BDA. In an embodiment, as shown in FIG. Figure 23 As shown in , one or more trenches TRCH1 and TRCH2 may be defined through the pixel defining layer PDL and may be partially defined in the planarization layer PLNL. In other embodiments, one or more trenches TRCH1 and TRCH2 may be defined through the pixel defining layer PDL and the planarization layer PLNL and may be partially defined in the via layer VIAL. In other embodiments, one or more trenches TRCH1 and TRCH2 may be defined at least partially through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed in the one or more trenches TRCH1 and TRCH2.

[0280] exist Figure 23 , an embodiment in which two trenches TRCH1 and TRCH2 are provided at (e.g., in) the boundary area BDA is shown. However, embodiments are not limited thereto. In an embodiment, for example, the pixel defining layer PDL may include one trench in the boundary area BDA. Alternatively, the pixel defining layer PDL may include three or more trenches in the boundary area BDA.

[0281] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first void VD1 and the second void VD2 may be formed in the light emitting structure EMS at the boundary area BDA (e.g., in the boundary area BDA). Some of the multiple layers stacked in the light emitting structure EMS may be disconnected or bent due to the first void VD1 and the second void VD2. In an embodiment, for example, at least one charge generation layer included in the light emitting structure EMS may be broken in the first void VD1 and the second void VD2. In this way, due to the first trench TRCH1 and the second trench TRCH2, portions of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3 may be at least partially separated.

[0282] exist Figure 23 , an embodiment is shown in which the first voids VD1 and the second voids VD2 are formed in the light emitting structure EMS in the boundary area BDA. However, this is an example, and embodiments are not limited thereto. In an embodiment, for example, a valley may be formed in the light emitting structure EMS in the boundary area BDA. Depending on the shapes of the first trench TRCH1 and the second trench TRCH2, the discontinuous portion formed in the light emitting structure EMS may vary.

[0283] In embodiments, the light emitting structure EMS may be formed by processes such as vacuum deposition, inkjet printing, etc. In this case, the same material as the light emitting structure EMS may be provided on the bottom surface adjacent to the via layer VIAL of the first and second trenches TRCH1 and TRCH2 .

[0284] The separator SPR may be provided in various forms so that the light emitting structure EMS may have a discontinuous portion at the boundary area BDA. In an embodiment, an inorganic insulating pattern additionally stacked on the pixel defining layer PDL may be provided at the boundary area BDA without the first trench TRCH1 and the second trench TRCH2. In an embodiment, the width of the topmost inorganic insulating pattern among the additionally stacked inorganic insulating patterns may be greater than the width of the inorganic insulating pattern directly below it. In an embodiment, for example, at the boundary area BDA, the first to third inorganic insulating patterns may be stacked sequentially from the pixel defining layer PDL, and the topmost third inorganic insulating pattern may have a larger width than the second inorganic insulating pattern. In an embodiment, for example, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross-section at the boundary area BDA. Depending on the shape of the pixel defining layer PDL, the multiple layers included in the light emitting structure EMS may be at least partially broken or bent at the boundary area BDA.

[0285] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be disposed entirely throughout the first to third sub-pixels SP1 to SP3. As described above, due to the separator SPR, the light emitting structure EMS may be at least partially disconnected or bent at the boundary area BDA. Therefore, when the display panel DP operates, the current flowing out from each of the first to third sub-pixels SP1 to SP3 through the layers included in the light emitting structure EMS to the adjacent sub-pixels may be reduced. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0286] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be commonly provided to the first to third subpixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0287] The first anode electrode AE1, the portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, the portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, the portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LD3.

[0288] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0289] The optical functional layer OFL may be disposed on the encapsulation layer TFE. In an embodiment, the optical functional layer OFL may be attached to the encapsulation layer TFE via an adhesive layer APL. In an embodiment, for example, the optical functional layer OFL may be manufactured separately and attached to the encapsulation layer TFE via the adhesive layer APL. The adhesive layer APL may also function to protect underlying layers including the encapsulation layer TFE.

[0290] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, respectively. The first to third color filters CF1 to CF3 may allow light of different wavelength ranges to pass through. In an embodiment, for example, the first to third color filters CF1 to CF3 may allow red, green, and blue light to pass through, respectively.

[0291] In an embodiment, the first to third color filters CF1 to CF3 may partially overlap at the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0292] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include a first lens LS1, a second lens LS2, and a third lens LS3 corresponding to the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, respectively. The first to third lenses LS1 to LS3 may improve light output efficiency by outputting light emitted from the first to third light-emitting elements LD1 to LD3 along their intended paths.

[0293] Figure 24 It shows Figure 21A plan view of another embodiment of one of the pixels.

[0294] Reference Figure 24 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0295] The first subpixel SP1′ may include a first emission area EMA1′ and a non-emission area NEA′ located around the first emission area EMA1′. The second subpixel SP2′ may include a second emission area EMA2′ and a non-emission area NEA′ located around the second emission area EMA2′. The third subpixel SP3′ may include a third emission area EMA3′ and a non-emission area NEA′ located around the third emission area EMA3′.

[0296] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2. The third subpixel SP3' may be arranged in the first direction DR1 with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0297] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Therefore, the second emission area EMA2' may have a larger area than the first emission area EMA1', and the third emission area EMA3' may have a larger area than the second emission area EMA2'. However, the embodiment is not limited thereto. In an embodiment, for example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area as each other, and the third sub-pixel SP3' may have a larger area than each of the first sub-pixel SP1' and the second sub-pixel SP2'. In this way, the areas of the first to third sub-pixels SP1' to SP3' may vary according to the embodiment.

[0298] Figure 25 It shows Figure 21 A plan view of another embodiment of one of the pixels.

[0299] Reference Figure 25 The first pixel PXL1" may include first to third sub-pixels SP1" to SP3". The first sub-pixel SP1" may include a first emission area EMA1" and a non-emission area NEA located around the first emission area EMA1". The second sub-pixel SP2" may include a second emission area EMA2" and a non-emission area NEA located around the second emission area EMA2". The third sub-pixel SP3" may include a third emission area EMA3" and a non-emission area NEA located around the third emission area EMA3".

[0300] When viewed in the third direction DR3, each of the first to third sub-pixels SP1 ″ to SP3 ″ may have a polygonal shape. In an embodiment, for example, each of the first to third sub-pixels SP1 ″ to SP3 ″ may have a polygonal shape. Figure 25 The hexagonal shape shown in .

[0301] When viewed in the third direction DR3, each of the first to third emission areas EMA1″ to EMA3″ may have a circular shape. However, the embodiment is not limited thereto. In an embodiment, for example, each of the first to third emission areas EMA1″ to EMA3″ may have a polygonal shape.

[0302] The first and third subpixels SP1″ and SP3″ may be arranged in the first direction DR1. The second subpixel SP2″ may be arranged relative to the first subpixel SP1″ in a direction inclined at an acute angle to the second direction DR2 (or inclined to the second direction DR2).

[0303] Figure 22 、 Figure 24 and Figure 25 The arrangement of the sub-pixels shown in FIG is an example, and the embodiment is not limited thereto. Each pixel may include two or more sub-pixels, the sub-pixels may be arranged in various ways, each of the sub-pixels may have various shapes, and each of the emission regions of the sub-pixels may also have various shapes.

[0304] Figure 26 is a block diagram illustrating an embodiment of a display system.

[0305] Reference Figure 26 , an embodiment of the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0306] The processor 1100 may perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to and control other components of the display system 1000 via a bus system.

[0307] In an embodiment, Figure 26 As shown in FIG, the display system 1000 may include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and connected to the second display device 1220 through a second channel CH2.

[0308] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The display device 100 described above is similarly configured. In this case, the first image data IMG1 and the first control signal CTRL1 may be respectively used as Figure 1 The input image data IMG and the control signal CTRL are provided.

[0309] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is similarly configured. In this case, the second image data IMG2 and the second control signal CTRL2 may be respectively used as Figure 1 The input image data IMG and the control signal CTRL are provided.

[0310] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, and an ultra-mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0311] Figure 27 It shows Figure 26 A perspective view of an embodiment of a display system.

[0312] Reference Figure 27 , Figure 26 The display system 1000 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on a user's head.

[0313] The head-mounted display device 2000 may include a headband 2100 and a display device storage box 2200. The headband 2100 may be connected to the display device storage box 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to wrap around the sides of the user's head, and the vertical strap may be configured to wrap around the top of the user's head. However, embodiments are not limited thereto. In embodiments, for example, the headband 2100 may be implemented in the form of eyeglass frames, a helmet, or the like.

[0314] The display device storage box 2200 can accommodate Figure 26 The first display device 1210 and the second display device 1220. The display device storage box 2200 can further accommodate Figure 26 Processor 1100.

[0315] Figure 28 It shows Figure 27 A view of an embodiment of a head-mounted display device worn by a user.

[0316] Reference Figure 28 , also refer to Figure 26 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 may be provided in the head-mounted display device 2000. The head-mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0317] In the display device storage box 2200 , a right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user. In the display device storage box 2200 , a left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user.

[0318] The image output from the first display panel DP1 can be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 to guide it toward the user's right eye. The right-eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0319] The image output from the second display panel DP2 can be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 to guide it toward the user's left eye. The left-eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0320] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a flat cross-section. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel may output an image corresponding to a sub-region of the multi-channel lens, and the output image may pass through the corresponding sub-region for viewing by the user.

[0321] The present invention should not be interpreted as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present invention to those skilled in the art.

[0322] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A sub-pixel, characterized in that: The sub-pixel includes: a first transistor including a first electrode connected to the first node, a second electrode connected to a first power supply line to which a first driving voltage is applied, and a gate electrode connected to the second node; a second transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to the first sub-gate line; a third transistor including a first electrode connected to one of the plurality of data lines, a second electrode connected to a third node, and a gate electrode connected to the second sub-gate line; a fourth transistor including a first electrode connected to the third node, a second electrode connected to a second power supply line to which a reference voltage is applied, and a gate electrode connected to the first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to a fourth node, and a gate electrode connected to a second emission control line; a sixth transistor including a first electrode connected to the fourth node, a second electrode connected to a third power line to which an initialization voltage is applied, and a gate electrode connected to a third sub-gate line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode connected to a fourth power supply line to which the second driving voltage is applied.

2. The sub-pixel according to claim 1, wherein: The emission control signal input to the second emission control line is a signal that is phase-delayed by one horizontal period from the emission control signal input to the first emission control line.

3. The sub-pixel according to claim 1, wherein: The capacitor is a first capacitor, and The sub-pixel further includes: The second capacitor includes a first electrode connected to the second node and a second electrode connected to the first power line.

4. The sub-pixel according to claim 1, wherein: Each of the first to sixth transistors is a P-type transistor.

5. The sub-pixel according to claim 1, wherein: A voltage level of the first driving voltage is higher than a voltage level of the second driving voltage.

6. A display device, characterized in that: The display device includes: A display panel comprising a plurality of sub-pixels and a plurality of data lines, a plurality of sub-gate lines and a plurality of emission control lines connected to the plurality of sub-pixels; a data driver providing data signals to the plurality of data lines; a gate driver that provides gate signals to the plurality of sub-gate lines, and the gate driver provides emission control signals to the plurality of emission control lines; and A voltage generator applies an initialization voltage, a reference voltage, a first driving voltage, and a second driving voltage to the plurality of sub-pixels, wherein: The plurality of sub-gate lines include a first sub-gate line, a second sub-gate line and a third sub-gate line, The plurality of emission control lines include a first emission control line and a second emission control line, and The sub-pixels in the plurality of sub-pixels include: a first transistor including a first electrode connected to a first node, a second electrode connected to a first power supply line to which the first driving voltage is applied, and a gate electrode connected to a second node; a second transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to the first sub-gate line; a third transistor including a first electrode connected to a corresponding one of the plurality of data lines, a second electrode connected to a third node, and a gate electrode connected to the second sub-gate line; a fourth transistor including a first electrode connected to the third node, a second electrode connected to a second power supply line to which the reference voltage is applied, and a gate electrode connected to the first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to a fourth node, and a gate electrode connected to the second emission control line; a sixth transistor including a first electrode connected to the fourth node, a second electrode connected to a third power line to which the initialization voltage is applied, and a gate electrode connected to the third sub-gate line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode connected to a fourth power supply line to which the second driving voltage is applied.

7. The display device according to claim 6, wherein: The emission control signal input to the second emission control line is a signal that is phase-delayed by one horizontal period from the emission control signal input to the first emission control line.

8. The display device according to claim 6, wherein: The capacitor is a first capacitor, and The sub-pixel further includes: The second capacitor includes a first electrode connected to the second node and a second electrode connected to the first power line.

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