Display device

Abstract

The display device includes: a display panel having a display area and a non-display area; a plurality of pixels disposed in the display area; a light emitting element disposed in each of the plurality of pixels; a driving transistor disposed in each of the plurality of pixels and connected to the light emitting element; and a common circuit disposed in the non-display area and connected to at least one of the driving transistor and the light emitting element of each of the plurality of pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0137857 filed on October 16, 2023, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device capable of realizing fine pixels. Background Art

[0004] A head-mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet and focuses in front of the user's eyes at a distance close to the user's eyes. A head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0005] Head-mounted displays use multiple lenses to magnify and display images displayed by a small display device. Therefore, the display device used in head-mounted displays needs to provide high-resolution images, for example, images with a resolution of 3,000 pixels per inch (PPI) or higher. To this end, organic light-emitting diodes on silicon (OLEDoS), which are small organic light-emitting display devices with high resolution, have been used as display devices for head-mounted displays. OLEDoS is a device that displays images by providing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Utility Model Content

[0006] Aspects of the present disclosure provide a display device capable of realizing fine pixels.

[0007] According to an embodiment of the present disclosure, a display device may include: a display panel having a display area and a non-display area; a plurality of pixels arranged in the display area; a light-emitting element arranged in each of the plurality of pixels; a driving transistor arranged in each of the plurality of pixels and electrically connected to the light-emitting element; and a common circuit arranged in the non-display area and electrically connected to at least one of the driving transistor and the light-emitting element in each of the plurality of pixels.

[0008] In an embodiment, the common circuit may be electrically connected to at least one of the drain electrode of the driving transistor and the cathode electrode of the light emitting element.

[0009] In an embodiment, the common circuit may include a first power switching circuit electrically connected to a drain electrode of the driving transistor and receiving the driving voltage, the initialization voltage, the first emission signal, and the first initialization gate signal.

[0010] In an embodiment, the first power switching circuit may include: a first emission transistor electrically connected between the drain electrode of the driving transistor and a driving voltage line transmitting a driving voltage; and a first initialization transistor electrically connected between the drain electrode of the driving transistor and an initialization voltage line transmitting an initialization voltage.

[0011] In an embodiment, the first emission signal may be input to a gate electrode of the first emission transistor, and the first initialization gate signal may be input to the gate electrode of the first initialization transistor.

[0012] In an embodiment, the common circuit may further include a second power switching circuit electrically connected to the cathode electrode of the light emitting element and receiving at least one of the second emission signal and the second initialization gate signal, the first common voltage, and the second common voltage.

[0013] In an embodiment, the second power switching circuit may include: a second emission transistor electrically connected between the cathode electrode of the light-emitting element and the first common voltage line transmitting the first common voltage; and a second initialization transistor electrically connected between the cathode electrode of the light-emitting element and the second common voltage line transmitting the second common voltage.

[0014] In an embodiment, the second emission signal may be input to a gate electrode of the second emission transistor, and the second initialization gate signal may be input to the gate electrode of the second initialization transistor.

[0015] In an embodiment, each of the plurality of pixels may include a switching transistor electrically connected between the data line and a gate electrode of the driving transistor.

[0016] In an embodiment, the write gate signal may be input to the gate electrode of the switching transistor.

[0017] In an embodiment, the display device may further include a gate driver that transmits the first emission signal, the second emission signal, the first initialization gate signal, and the second initialization gate signal to a common circuit and transmits a write gate signal to each of the plurality of pixels.

[0018] In an embodiment, in the initialization period, the first initialization gate signal, the second initialization gate signal, and the write gate signal may each have an active level, the first emission signal and the second emission signal may each have an inactive level, and a reference voltage may be applied to the data line.

[0019] In an embodiment, in a threshold voltage detection period after an initialization period, the first emission signal, the second initialization gate signal, and the write gate signal may each have a valid level, the first initialization gate signal and the second emission signal may each have an invalid level, and a reference voltage may be applied to the data line.

[0020] In an embodiment, in a data write period after a threshold voltage detection period, the first emission signal and the second initialization gate signal may each have an active level, the first initialization gate signal and the second emission signal may each have an inactive level, and a data voltage may be applied to the data line.

[0021] In an embodiment, the write gate signal may have an active level during a partial period of the data write period.

[0022] In an embodiment, in an emission period following a data write period, the first emission signal and the second emission signal may each have a valid level, the first initialization gate signal, the second initialization gate signal, and the write gate signal may each have an invalid level, and a reference voltage may be applied to the data line.

[0023] In an embodiment, each of the reference voltage, the initialization voltage, the first common voltage, and the second common voltage may be a direct current (DC) voltage.

[0024] In an embodiment, the initialization voltage may be lower than or equal to the second common voltage, the initialization voltage may be lower than the reference voltage, the reference voltage may be higher than the first common voltage, the reference voltage may be higher than the sum of the initialization voltage and the threshold voltage of the driving transistor, the reference voltage may be higher than the first common voltage and lower than the driving voltage, and the driving voltage may be higher than the sum of the reference voltage and the threshold voltage of the driving transistor.

[0025] In an embodiment, each of the plurality of pixels may further include: a first capacitor electrically connected between the gate electrode of the driving transistor and the anode electrode of the light emitting element; and a second capacitor electrically connected between the anode electrode of the light emitting element and the cathode electrode of the light emitting element.

[0026] In an embodiment, a ratio between the capacitance of the second capacitor and the capacitance of the first capacitor may be approximately 2:1.

[0027] In an embodiment, the second emission transistor and the second initialization transistor may be opposite type transistors.

[0028] In an embodiment, the second emission signal may be input to a gate electrode of the second emission transistor and a gate electrode of the second initialization transistor.

[0029] In an embodiment, the common circuit may include a first power switching circuit electrically connected to the drain electrode of the driving transistor and receiving a driving voltage, an initialization voltage, a first emission signal and a first initialization gate signal, and the cathode electrode of the light-emitting element may be directly connected to a first common voltage line transmitting the first common voltage.

[0030] With the display device according to the present disclosure, multiple pixels can share a common circuit with each other, and thus the number of transistors required for each pixel can be reduced. Therefore, the size of the pixel can be reduced, making it possible to realize fine pixels.

[0031] The effects of the present disclosure are not limited to the above-described effects, and other effects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is an exploded perspective view showing a display device according to an embodiment;

[0034] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A schematic diagram of the layout of the display panel shown in ;

[0035] Figure 3 yes Figure 2 A schematic diagram of an equivalent circuit of a pixel and a sub-common circuit connected to the pixel;

[0036] Figure 4 yes Figure 3 A timing diagram of a first initialization gate signal, a first emission signal, a second initialization gate signal, a second emission signal, a write gate signal, a reference voltage, and a data voltage;

[0037] Figure 5 is used to describe Figure 4 A schematic diagram of the input timing of the data voltage in the data writing cycle;

[0038] Figure 6 is used to describe Figure 3 The display device is Figure 4 Schematic diagram of the operations in the initialization cycle;

[0039] Figure 7 is used to describe Figure 3 The display device is Figure 4 Schematic diagram of the operation in the threshold voltage detection cycle;

[0040] Figure 8is used to describe Figure 3 The display device is Figure 4 A schematic diagram of operations in a data write cycle;

[0041] Figure 9 is used to describe Figure 3 The display device is Figure 4 A schematic diagram of the operation in the launch cycle;

[0042] Figure 10 yes Figure 2 A schematic diagram of an equivalent circuit of a pixel and a sub-common circuit connected to the pixel; and

[0043] Figure 11 yes Figure 2 Schematic diagram of an equivalent circuit of a pixel and a sub-common circuit connected to the pixel. DETAILED DESCRIPTION

[0044] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings which illustrate embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be more thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0045] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. The same reference numerals refer to the same components throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0046] Although the terms "first", "second" etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be named as the second element. The description of an element such as a "first" element may not require or imply the existence of a second element or other elements. In this article, the terms "first", "second" etc. can be used to distinguish elements of different categories or different groups. For the sake of simplicity, the terms "first", "second" etc. can respectively represent "first class (or first group)", "second class (or second group)" etc.

[0047] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. The various embodiments can be practiced individually or in combination.

[0048] In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B." In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or."

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that, unless expressly defined in this specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0050] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is an exploded perspective view showing the display device 10 according to the embodiment. Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of the layout of the display panel 100 shown in FIG.

[0052] Reference Figure 1 and Figure 2 The display device 10 according to the embodiment may be a device for displaying moving images or still images. The display device 10 according to the embodiment may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. In another embodiment, the display device 10 may be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0053] The display device 10 according to the embodiment may include a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing controller 400 , and a power supply circuit 500 .

[0054] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is a thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on a surface (e.g., a rear surface) of the display panel 100. The heat dissipation layer 200 may be used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite having high thermal conductivity or a metal layer made of silver (Ag), copper (Cu), or aluminum (Al).

[0055] The circuit board 300 may be electrically connected to a plurality of pads of the display panel 100 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 1 The circuit board 300 is shown as not being bent, but the present disclosure is not limited thereto. In another embodiment, the circuit board 300 may be bent, and an end portion of the circuit board 300 may be disposed on the rear surface of the display panel 100. The end portion of the circuit board 300 may be an end portion opposite to the other end portion of the circuit board 300 connected to the pad of the display panel 100 using a conductive adhesive member.

[0056] The timing controller 400 may receive digital video data and timing signals from the outside. The timing controller 400 may generate gate control signals, emission control signals, and data control signals for controlling the display panel 100 based on the timing signals. The timing controller 400 may output the gate control signals and emission control signals to the gate driver GD, and output the digital video data and data control signals to the data driver DD.

[0057] The power supply unit 500 may generate a plurality of panel driving voltages according to an external source voltage. For example, the power supply unit 500 may generate a driving voltage, a first common voltage, a second common voltage, and an initialization voltage, and supply the driving voltage, the first common voltage, the second common voltage, and the initialization voltage to the display panel 100.

[0058] Each of the timing controller 400 and the power supply unit 500 may be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. The gate control signal, emission control signal, digital video data, and data control signal of the timing controller 400 may be supplied to the display panel 100 through the circuit board 300. The driving voltage, first common voltage, second common voltage, and initialization voltage of the power supply unit 500 may be supplied to the display panel 100 through the circuit board 300.

[0059] The display panel 100 may have a shape similar to a rectangle in a plan view. For example, the display panel 100 may have a shape similar to a rectangle in a plan view, the shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded or at a right angle with a curvature. The shape of the display panel 100 in a plan view is not limited to a rectangle, and may be a shape similar to other polygons, a circle, or an ellipse. The shape of the display device 10 in a plan view may be consistent with the shape of the display panel 100 in a plan view, but the present disclosure is not limited thereto.

[0060] like Figure 2 As shown in , the display panel 100 may include a display area DA where an image is displayed and a non-display area NDA where no image is displayed.

[0061] In the display area DA of the display panel 100, a plurality of pixels PX, a plurality of write gate lines GWL, a plurality of first common lines CL1, a plurality of second common lines CL2, and a plurality of data lines DL may be provided. Each of the pixels PX may include a light-emitting element ED that emits light. In a plan view, the pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2.

[0062] Each pixel PX may be connected to one write gate line GWL, one first common line CL1, one second common line CL2, and one data line DL. The write gate line GWL may extend in a first direction DR1, and pixels PX arranged in a horizontal line in the extending direction of the write gate line GWL (e.g., the first direction DR1) may be connected to the same write gate line GWL, the same first common line CL1, and the same second common line CL2. The pixels PX in a horizontal line may be connected to different data lines DL, respectively.

[0063] In the non-display area NDA of the display panel 100 , a gate driver GD, a data driver DD, a common circuit CMC, a plurality of first initialization gate lines GIL1 , a plurality of second initialization gate lines GIL2 , a plurality of first emission lines EML1 , and a plurality of second emission lines EML2 may be disposed.

[0064] like Figure 2As shown in , the gate driver GD can be connected to the common circuit CMC. For example, the gate driver GD can be connected to the common circuit CMC via the first initialization gate line GIL1, the second initialization gate line GIL2, the first emission line EML1, and the second emission line EML2. The gate driver GD can generate multiple write gate signals and multiple first initialization gate signals based on the gate control signal from the timing controller 400, and generate multiple first emission signals and multiple second emission signals based on the emission control signal from the timing controller 400. The gate driver GD can supply the first initialization gate signal, the second initialization gate signal, the first emission signal, and the second emission signal to the common circuit CMC. For example, the gate driver GD can supply the first initialization gate signal to the common circuit CMC via the first initialization gate line GIL1, supply the second initialization gate signal to the common circuit CMC via the second initialization gate line GIL2, supply the first emission signal to the common circuit CMC via the first emission line EML1, and supply the second emission signal to the common circuit CMC via the second emission line EML2.

[0065] According to the embodiment, the pixels PX can share a common circuit CMC with each other, and thus the number of transistors required for each pixel PX can be reduced. Therefore, the size of the pixel PX can be reduced, making it possible to realize fine pixels.

[0066] The data driver DD can be connected to the data lines DL. The data driver DD can supply a plurality of data signals to the data lines DL. The data driver DD can receive digital video data and data control signals from the timing controller 400. The data driver DD can convert the digital video data into analog data voltages based on the data control signals from the timing controller 400, and supply the analog data voltages to the data lines DL. The pixels PX of a horizontal line can be selected by a write gate signal from the gate driver GD, and the data voltages can be supplied to the selected pixels PX. For example, the data driver DD can generate a plurality of data voltages based on the timing data control signals from the timing controller 400 and supply the data voltages to the data lines DL. The data driver DD can generate a reference voltage and supply the generated reference voltage to the data lines DL.

[0067] The common circuit CMC may include a plurality of sub-common circuits SCC. The sub-common circuits SCC may be arranged in a row in the second direction DR2 in the non-display area NDA. Each sub-common circuit SCC may be commonly connected to the pixels PX of the aforementioned horizontal line. For example, Figure 2An embodiment in which the common circuit CMC includes five sub-common circuits SCC has been shown, and in the case where the five sub-common circuits SCC are defined as a first sub-common circuit SCC1, a second sub-common circuit SCC2, a third sub-common circuit SCC3, a fourth sub-common circuit SCC4, and a fifth sub-common circuit SCC5 in the order of the opposite direction of the second direction DR2 (hereinafter referred to as the second opposite direction), the first sub-common circuit SCC can be commonly connected to six pixels PX adjacent to the first sub-common circuit SCC1 in the first direction DR1, the second sub-common circuit SCC2 can be commonly connected to six pixels PX adjacent to the second sub-common circuit SCC2 in the first direction DR1, the third sub-common circuit SCC3 can be commonly connected to six pixels PX adjacent to the third sub-common circuit SCC3 in the first direction DR1, the fourth sub-common circuit SCC4 can be commonly connected to six pixels PX adjacent to the fourth sub-common circuit SCC4 in the first direction DR1, and the fifth sub-common circuit SCC5 can be commonly connected to six pixels PX adjacent to the fifth sub-common circuit SCC5 in the first direction DR1.

[0068] Figure 3 yes Figure 2 Schematic diagram of an equivalent circuit of a pixel PX and a sub-common circuit SCC connected to the pixel PX.

[0069] like Figure 3 As shown in , the pixel PX may include a driving transistor Td, a switching transistor Ts, a first capacitor C1, a second capacitor C2, and a light emitting element ED.

[0070] The driving transistor Td may include a gate electrode, a source electrode, a drain electrode, and a body electrode. The driving transistor Td may be electrically connected to the gate electrode according to a data voltage Vdt (see FIG. Figure 4 ) to control the source-drain current (hereinafter referred to as the drive current). The drive current flowing through the channel region of the drive transistor Td may be proportional to the square of the difference between the voltage between the source electrode and the gate electrode and the threshold voltage of the drive transistor Td. The gate electrode of the drive transistor Td may be electrically connected to the first node N1, the drain electrode of the drive transistor Td may be electrically connected to the second node N2, the source electrode of the drive transistor Td may be electrically connected to the third node N3, and the body electrode of the drive transistor Td may be electrically connected to the first common voltage line VSL1 that transmits the first common voltage VSS1.

[0071] The light-emitting element ED can receive a driving current to emit light. The amount of light emitted or the brightness of the light-emitting element ED can be proportional to the magnitude of the driving current. The light-emitting element ED can be an organic light-emitting diode, which includes a first electrode (e.g., an anode electrode), a second electrode (e.g., a cathode electrode), and an organic light-emitting layer disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED can be an inorganic light-emitting element, which includes a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED can be a quantum dot light-emitting element, which includes a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first electrode and the second electrode. In another embodiment, the light-emitting element ED can be a micro light-emitting diode. The first electrode of the light-emitting element ED can be connected to the third node N3. The second electrode of the light-emitting element ED can be connected to the fourth node N4.

[0072] The switching transistor Ts can be turned on by a write gate signal GW from a write gate line GWL to electrically connect the data line DL and the first node N1. A gate electrode of the switching transistor Ts can be electrically connected to the write gate line GWL, a drain electrode of the switching transistor Ts can be electrically connected to the data line DL, a source electrode of the switching transistor Ts can be electrically connected to the first node N1, and a bulk electrode of the switching transistor Ts can be electrically connected to a first common voltage line VSL1. The data line DL can transmit a data voltage or a reference voltage.

[0073] The first capacitor C1 may be electrically connected between the first node N1 and the third node N3. For example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the third node N3.

[0074] The second capacitor C2 may be electrically connected between the third node N3 and the fourth node N4. For example, a first electrode of the second capacitor C2 may be electrically connected to the third node N3, and a second electrode of the second capacitor C2 may be electrically connected to the fourth node N4.

[0075] The sub-common circuit SCC may include a first power switching circuit PSC1 and a second power switching circuit PSC2 .

[0076] The first power switching circuit PSC1 may include a first emission control transistor Te1 and a first initialization transistor Ti1 .

[0077] The first emission control transistor Te1 may be turned on by a first emission signal EM1 from the first emission line EML1 to electrically connect the driving voltage line VDL and the second node N2 to each other. A gate electrode of the first emission control transistor Te1 may be electrically connected to the first emission line EML1, a drain electrode of the first emission control transistor Te1 may be electrically connected to the driving voltage line VDL, a source electrode of the first emission control transistor Te1 may be electrically connected to the second node N2, and a body electrode of the first emission control transistor Te1 may be electrically connected to the first common voltage line VSL1.

[0078] The first initialization transistor Ti1 may be turned on by a first initialization gate signal GI1 from the first initialization gate line GIL1 to electrically connect the second node N2 and the initialization voltage line VIL to each other. A gate electrode of the first initialization transistor Ti1 may be electrically connected to the first initialization gate line GIL1, a drain electrode of the first initialization transistor Ti1 may be electrically connected to the second node N2, a source electrode of the first initialization transistor Ti1 may be electrically connected to the initialization voltage line VIL, and a body electrode of the first initialization transistor Ti1 may be electrically connected to the first common voltage line VSL1.

[0079] The second node N2 may be connected to the first common line CL1. In other words, the second node N2 of each of the pixels PX of one horizontal line may be commonly connected to the first common line CL1.

[0080] The second power switching circuit PSC2 may include a second emission control transistor Te2 and a second initialization transistor Ti2.

[0081] The second emission control transistor Te2 may be turned on by a second emission signal EM2 from the second emission line EML2 to electrically connect the fourth node N4 and the first common voltage line VSL1 to each other. A gate electrode of the second emission control transistor Te2 may be electrically connected to the second emission line EML2, a drain electrode of the second emission control transistor Te2 may be electrically connected to the fourth node N4, a source electrode of the second emission control transistor Te2 may be electrically connected to the first common voltage line VSL1, and a body electrode of the second emission control transistor Te2 may be electrically connected to the first common voltage line VSL1.

[0082] The second initialization transistor Ti2 may be turned on by a second initialization gate signal GI2 from the second initialization gate line GIL2 to electrically connect the fourth node N4 and the second common voltage line VSL2 to each other. A gate electrode of the second initialization transistor Ti2 may be electrically connected to the second initialization gate line GIL2, a drain electrode of the second initialization transistor Ti2 may be electrically connected to the fourth node N4, a source electrode of the second initialization transistor Ti2 may be electrically connected to the second common voltage line VSL2, and a body electrode of the second initialization transistor Ti2 may be electrically connected to the first common voltage line VSL1.

[0083] According to an embodiment, a plurality of pixels PX of a horizontal line can share a sub-common circuit SCC with each other, and thus, four transistors (e.g., transistors Te1, Te2, Ti1, and Ti2) can be removed from each pixel PX. Therefore, the size of the pixel PX can be reduced, making it possible to realize fine pixels.

[0084] Figure 4 yes Figure 3 1 and 2. A timing diagram of the first initialization gate signal GI1, the first emission signal EM1, the second initialization gate signal GI2, the second emission signal EM2, the write gate signal GW, the reference voltage Vref, and the data voltage Vdt.

[0085] Reference Figure 4 Combined with Figure 3 ,like Figure 4 In the embodiment shown in FIG, the display device 10 (see Figure 1 ) can operate based on an initialization period P1, a threshold voltage detection period P2, a data writing period P3 and an emission period P4.

[0086] For each cycle, the first initialization gate signal GI1, the first emission signal EM1, the second initialization gate signal GI2, the second emission signal EM2, and the write gate signal GW may each have an active level or an inactive level. The active level of each of the above signals may be a voltage level that can turn on the transistor to which the corresponding signal is applied. In other words, the signal at the active level may have a value higher than the threshold voltage of the corresponding transistor. For example, Figure 3 As shown in , in the case where each of the transistors Td, Ts, Te1, Te2, Ti1, and Ti2 is an N-type transistor, the effective level of each signal may be a high level (eg, a positive polarity level or a high voltage level).

[0087] The inactive level of each signal may be a voltage level that can turn off the corresponding transistor. In other words, the signal of the inactive level may have a value lower than the threshold voltage of the corresponding transistor. For example, Figure 3As shown in , in the case where each of the transistors Td, Ts, Te1, Te2, Ti1, and Ti2 is an N-type transistor, the inactive level of each signal may be a low level (eg, a negative polarity level or a low voltage level).

[0088] On the contrary, in the case where each of transistors Td, Ts, Te1, Te2, Ti1 and Ti2 is a P-type transistor, the valid level of each signal can be a low level (e.g., a negative polarity level or a low voltage level), and the invalid level of each signal can be a high level (e.g., a positive polarity level or a high voltage level).

[0089] In the initialization period P1, the first and second initialization gate signals GI1, GI2, and GW may each have an active level, and the first and second emission signals EM1 and EM2 may each have an inactive level. In the initialization period P1, the reference voltage Vref may be applied to the data line DL.

[0090] In the threshold voltage detection period P2, the first emission signal EM1, the second initialization gate signal GI2, and the write gate signal GW may each have an active level, and the first initialization gate signal GI1 and the second emission signal EM2 may each have an inactive level. In the threshold voltage detection period P2, the reference voltage Vref may be applied to the data line DL.

[0091] During the data write period P3, the first emission signal EM1 and the second initialization gate signal GI2 may each have an active level, and the first initialization gate signal GI1 and the second emission signal EM2 may each have an inactive level. The write gate signal GW may have an active level during a portion of the data write period P3 (e.g., one horizontal period). During the remaining periods of the data write period P3 except for the one horizontal period of the data write period P3, the write gate signal GW may have an inactive level. During the data write period P3, a data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage corresponding to a specific grayscale (or grayscale / brightness) for displaying an image.

[0092] In the emission period P4, the first emission signal EM1 and the second emission signal EM2 may each have an active level, and the first initialization gate signal GI1, the second initialization gate signal GI2 and the write gate signal GW may each have an inactive level. In the emission period P4, the reference voltage Vref may be applied to the data line DL.

[0093] Each of the above-mentioned reference voltage Vref, the initialization voltage VINT, the first common voltage VSS1 , and the second common voltage VSS2 may be a direct current (DC) voltage.

[0094] The initialization voltage VINT may be lower than or equal to the second common voltage VSS2 . The initialization voltage VINT may be lower than the reference voltage Vref.

[0095] The reference voltage Vref may be higher than the first common voltage VSS1. The reference voltage Vref may be higher than the sum of the initialization voltage VINT and the threshold voltage of the driving transistor Td. The reference voltage Vref may be higher than the first common voltage VSS1 and lower than the driving voltage VDD.

[0096] The driving voltage VDD may be higher than the sum of the reference voltage Vref and the threshold voltage of the driving transistor Td.

[0097] Figure 5 Is used to describe Figure 4 FIG. 1 is a schematic diagram of an input timing of a data voltage Vdt in a data writing period P3.

[0098] like Figure 5 As shown in , the data writing period P3 may include a plurality of horizontal periods H1, H2, H3, ..., Hn-1, and Hn. For example, the data writing period P3 may include a first horizontal period H1 to an nth horizontal period Hn.

[0099] like Figure 2 As shown in FIG, the display device 10 (see Figure 1 ) may include a plurality of write gate lines GWL. For example, the write gate line GWL may include a first write gate line to an nth write gate line. n may be a natural number greater than 4. Each write gate line GWL may be connected to a pixel PX of a corresponding horizontal line. For example, the first write gate line may be commonly connected to the pixel PX of the first horizontal line adjacent to the first sub-common circuit SCC1 in the first direction DR1, the second write gate line may be commonly connected to the pixel PX of the second horizontal line adjacent to the second sub-common circuit SCC2 in the first direction DR1, the third write gate line may be commonly connected to the pixel PX of the third horizontal line adjacent to the third sub-common circuit SCC3 in the first direction DR1, ..., the n-1th write gate line may be commonly connected to the pixel PX of the n-1th horizontal line adjacent to the n-1th sub-common circuit SCCn-1 (not shown in the figure) in the first direction DR1, and the nth write gate line may be commonly connected to the pixel PX of the nth horizontal line adjacent to the nth sub-common circuit SCCn (not shown in the figure) in the first direction DR1.

[0100] During the data write period P3, the first write gate signal GW1, the second write gate signal GW2, the third write gate signal GW3, ..., the (n-1)th write gate signal GWn-1, and the nth write gate signal GWn may be sequentially applied to the first to nth write gate lines, respectively. For example, the first write gate signal GW1, the second write gate signal GW2, the third write gate signal GW3, ..., the (n-1)th write gate signal GWn-1, and the nth write gate signal GWn may sequentially have active levels according to the first horizontal period H1 to the nth horizontal period Hn of the data write period P3. For example, the first write gate signal GW1 may have an active level during the first horizontal period H1, the second write gate signal GW2 may have an active level during the second horizontal period H2, the third write gate signal GW3 may have an active level during the third horizontal period H3, ..., the (n-1)th write gate signal GWn-1 may have an active level during the (n-1)th horizontal period Hn-1, and the nth write gate signal GWn may have an active level during the nth horizontal period Hn. In the data writing period P3 , each of the write gate signals GW1 to GWn may have an active level only during a corresponding horizontal period and have an inactive level during the remaining horizontal periods of the data writing period P3 excluding the corresponding horizontal period.

[0101] The data voltage Vdt of the data write period P3 may include a plurality of data voltages. The data voltages Vdt1, Vdt2, ..., Vdtn-1, and Vdtn may include a first data voltage Vdt1 applied to the data line DL in the first horizontal period H1, a second data voltage Vdt2 applied to the data line DL in the second horizontal period H2, a third data voltage Vdt3 applied to the data line DL in the third horizontal period H3, ..., an n-1th data voltage Vdtn-1 applied to the data line DL in the n-1th horizontal period Hn-1, and an nth data voltage Vdtn applied to the data line DL in the nth horizontal period Hn.

[0102] In the first horizontal period H1, the first write gate signal GW1 may have an active level, and the first data voltage Vdt1 may be applied to the data line DL. In the second horizontal period H2, the second write gate signal GW2 may have an active level, and the second data voltage Vdt2 may be applied to the data line DL. In the third horizontal period H3, the third write gate signal GW3 may have an active level, and the third data voltage Vdt3 may be applied to the data line DL. In the (n-1)th horizontal period Hn-1, the (n-1)th write gate signal GWn-1 may have an active level, and the (n-1)th data voltage Vdtn-1 may be applied to the data line DL. In the (n)th horizontal period Hn, the (n)th write gate signal GWn may have an active level, and the (n)th data voltage Vdtn may be applied to the data line DL.

[0103] Will refer to Figures 6 to 9 The display device 10 according to the embodiment is described (see Figure 1 ) operation. Figures 6 to 9 , a transistor surrounded by a dotted circle may be a transistor in an on-state, and other transistors except the transistor surrounded by the dotted circle may be a transistor in an off-state.

[0104] First, refer to Figure 4 and Figure 6 Description of the display device 10 (see Figure 1 ) Operations in the initialization period P1.

[0105] Figure 6 is used to describe Figure 3 The display device 10 is Figure 4 Schematic diagram of the operations in the initialization period P1.

[0106] like Figure 4 As shown in , during the initialization period P1, the first initialization gate signal GI1, the second initialization gate signal GI2, and the write gate signal GW may each have an active level, and the first emission signal EM1 and the second emission signal EM2 may each have an inactive level. During the initialization period P1, the reference voltage Vref may be applied to the data line DL.

[0107] A first initialization gate signal GI1 having an active level may be applied to a gate electrode of the first initialization transistor Ti1 through the first initialization gate line GIL1 , and thus the first initialization transistor Ti1 may be turned on.

[0108] A second initialization gate signal GI2 having an active level may be applied to the gate electrode of the second initialization transistor Ti2 through the second initialization gate line GIL2 , and thus the second initialization transistor Ti2 may be turned on.

[0109] The write gate signal GW having an active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. Thus, the switching transistor Ts may be turned on.

[0110] The first emission signal EM1 having an inactive level may be applied to the gate electrode of the first emission control transistor Te1 through the first emission line EML1. Therefore, the first emission control transistor Te1 may be turned off.

[0111] The second emission signal EM2 having an inactive level may be applied to the gate electrode of the second emission control transistor Te2 through the second emission line EML2. Therefore, the second emission control transistor Te2 may be turned off.

[0112] The switching transistor Ts described above can be turned on during the initialization period P1, and therefore, the driving transistor Td can also be turned on. For example, the reference voltage Vref from the data line DL can be applied to the gate electrode of the driving transistor Td through the turned-on switching transistor Ts. Such a reference voltage Vref can be higher than the initialization voltage VINT applied to the drain electrode of the driving transistor Td, and therefore, the driving transistor Td can be turned on. Through the turned-on driving transistor Td, the source electrode of the driving transistor Td can have a voltage having a value corresponding to the initialization voltage VINT.

[0113] The switching transistor Ts, the first initialization transistor Ti1, the second initialization transistor Ti2, and the driving transistor Td can each be turned on during the initialization period P1, and thus, the gate electrode (e.g., the first node N1) of the driving transistor Td, the drain electrode (e.g., the second node N2) of the driving transistor Td, and the source electrode (e.g., the third node N3) of the driving transistor Td can each be initialized. For example, the reference voltage Vref from the data line DL can be applied to the first node N1 electrically connected to the gate electrode of the driving transistor Td through the turned-on switching transistor Ts. The initialization voltage VINT from the initialization voltage line VIL can be applied to the second node N2 electrically connected to the drain electrode of the driving transistor Td through the turned-on first initialization transistor Ti1. The initialization voltage VINT from the initialization voltage line VIL can be applied to the third node N3 electrically connected to the source electrode of the driving transistor Td through the turned-on first initialization transistor Ti1 and the turned-on driving transistor Td. Therefore, the voltages of the gate electrode of the driving transistor Td, the drain electrode of the driving transistor Td, and the source electrode of the driving transistor Td can be initialized. For example, the gate electrode of the driving transistor Td can be initialized by the reference voltage Vref, and the drain electrode and source electrode of the driving transistor Td can each be initialized by the initialization voltage VINT. The second common voltage VSS2 can be applied to the fourth node N4 electrically connected to the second electrode (e.g., cathode electrode) of the light-emitting element ED through the turned-on second initialization transistor Ti2. Therefore, the second electrode of the light-emitting element ED can be initialized by the second common voltage VSS2. The second common voltage VSS2 can be higher than the initialization voltage VINT, and therefore, the light-emitting element ED can be biased in the opposite direction during the initialization period P1. In other words, the initialization voltage VINT applied to the third node N3 electrically connected to the first electrode of the light-emitting element ED can be lower than or equal to the second common voltage VSS2 applied to the fourth node N4 electrically connected to the second electrode of the light-emitting element ED, and therefore, the light-emitting element ED can be biased in the opposite direction during the initialization period P1. Therefore, the light-emitting element ED can remain in the off state during the initialization period P1.

[0114] Will refer to Figure 4 and Figure 7 Description of the display device 10 (see Figure 1 ) Operation in the threshold voltage detection period P2.

[0115] Figure 7 is used to describe Figure 3 The display device 10 is Figure 4 Schematic diagram of the operation in the threshold voltage detection period P2.

[0116] like Figure 4As shown in , in the threshold voltage detection period P2, the first emission signal EM1, the second initialization gate signal GI2, and the write gate signal GW may each have an active level, and the first initialization gate signal GI1 and the second emission signal EM2 may each have an inactive level. In the threshold voltage detection period P2, the reference voltage Vref may be applied to the data line DL.

[0117] The first emission signal EM1 having an active level may be applied to the gate electrode of the first emission control transistor Te1 through the first emission line EML1. Therefore, the first emission control transistor Te1 may be turned on.

[0118] A second initialization gate signal GI2 having an active level may be applied to the gate electrode of the second initialization transistor Ti2 through the second initialization gate line GIL2 , and thus the second initialization transistor Ti2 may be turned on.

[0119] A write gate signal GW having an effective level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. Thus, the switching transistor Ts may be turned on. The reference voltage Vref may be applied to the first node N1 through the turned-on switching transistor Ts, and the third node N3 may be maintained at the initialization voltage VINT applied in the previous initialization period P1, and thus, the driving transistor Td may be turned on. In other words, the reference voltage Vref applied to the gate electrode (e.g., the first node N1) of the driving transistor Td may be higher than the initialization voltage VINT applied to the source electrode (e.g., the third node N3) of the driving transistor Td, and thus, the driving transistor Td, which is an N-type transistor, may be turned on.

[0120] A first initialization gate signal GI1 having an inactive level may be applied to the gate electrode of the first initialization transistor Ti1 through the first initialization gate line GIL1. Thus, the first initialization transistor Ti1 may be turned off.

[0121] The second emission signal EM2 having an inactive level may be applied to the gate electrode of the second emission control transistor Te2 through the second emission line EML2. Therefore, the second emission control transistor Te2 may be turned off.

[0122] As described above, the reference voltage Vref applied to the gate electrode of the driving transistor Td can be higher than the initialization voltage VINT applied to the source electrode of the driving transistor Td, and can be lower than the driving voltage VDD applied to the drain electrode of the driving transistor Td. Therefore, the driving transistor Td can be turned on, and current can flow from the second node N2 to the third node N3 via the turned-on driving transistor Td, and therefore, the voltage of the third node N3 can begin to increase. In other words, the voltage of the source electrode of the driving transistor Td can begin to increase. At the moment when the voltage of the source electrode of the driving transistor Td increases so that the gate-source voltage of the driving transistor Td becomes equal to the threshold voltage of the driving transistor Td, the driving transistor Td can be turned off. When the driving transistor Td is turned off, the threshold voltage of the driving transistor Td can be maintained by the first capacitor C1. In other words, during the threshold voltage detection period P2, the voltage of the first node N1 electrically connected to the first electrode of the first capacitor C1 may have a value corresponding to the reference voltage Vref, and the voltage of the third node N3 electrically connected to the second electrode of the first capacitor C1 may have a value corresponding to the voltage obtained by subtracting the threshold voltage of the driving transistor Td from the reference voltage Vref. Therefore, the voltage across the first capacitor C1 may have a value corresponding to the threshold voltage of the driving transistor Td. Therefore, when the driving transistor Td is turned off, the threshold voltage (Vth) of the driving transistor Td may be stored in the first capacitor C1.

[0123] As such, during the threshold voltage detection period P2 , the threshold voltage (Vth) of the driving transistor Td may be detected and held by the first capacitor C1 .

[0124] The light emitting element ED may be biased in the reverse direction in the threshold voltage detection period P2 , and thus the light emitting element ED may be maintained in a turned-off state in the threshold voltage detection period P2 .

[0125] Will refer to Figure 4 and Figure 8 Description of the display device 10 (see Figure 1 ) Operation in the data write cycle P3.

[0126] Figure 8 is used to describe Figure 3 The display device 10 is Figure 4 Schematic diagram of the operation in the data writing cycle P3.

[0127] like Figure 4As shown in , in the data write period P3, the first emission signal EM1 and the second initialization gate signal GI2 may each have an active level, and the first initialization gate signal GI1 and the second emission signal EM2 may each have an inactive level. The write gate signal GW may have an active level during a portion of the data write period P3 (e.g., one horizontal period). During the remaining periods of the data write period P3 except for the one horizontal period of the data write period P3, the write gate signal GW may have an inactive level. In the data write period P3, a data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage corresponding to a specific grayscale (or grayscale / brightness) for displaying an image.

[0128] The first emission signal EM1 having an active level may be applied to the gate electrode of the first emission control transistor Te1 through the first emission line EML1. Therefore, the first emission control transistor Te1 may be turned on.

[0129] A second initialization gate signal GI2 having an active level may be applied to the gate electrode of the second initialization transistor Ti2 through the second initialization gate line GIL2 , and thus the second initialization transistor Ti2 may be turned on.

[0130] The write gate signal GW having an active level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. Thus, the switching transistor Ts may be turned on.

[0131] A first initialization gate signal GI1 having an inactive level may be applied to the gate electrode of the first initialization transistor Ti1 through the first initialization gate line GIL1. Thus, the first initialization transistor Ti1 may be turned off.

[0132] The second emission signal EM2 having an inactive level may be applied to the gate electrode of the second emission control transistor Te2 through the second emission line EML2. Therefore, the second emission control transistor Te2 may be turned off.

[0133] like Figure 8 As shown in FIG, the data voltage Vdt can be applied to the first node N1 through the data line DL and the turned-on switching transistor Ts. When the driving transistor Td, which was in the off state in the previous data writing cycle P3, remains in the off state in the current data writing cycle P3, the third node N3 can remain in a floating state. For example, the driving transistor Td can be in a weakly turned-on state in the data writing cycle P3. However, the third node N3 can remain in a state close to floating.

[0134] The third node N3 may be maintained in a floating state, and thus, the voltage of the third node N3 may be further increased by the voltage coupled by the first capacitor C1 (e.g., the data voltage Vdt). For example, the magnitude of the data voltage Vdt added to the voltage of the third node N3 may be determined by the ratio between the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2. For example, the voltage added to the third node N3 may have a value corresponding to "data voltage Vdt×(capacitance of C1 / (capacitance of C1+capacitance of C2))". Therefore, during the data write period P3, the voltage of the first node N1 may have a value corresponding to the data voltage Vdt, the voltage of the second node N2 may have a value corresponding to the drive voltage VDD, and the voltage of the third node N3 may have a value corresponding to "Vref-Vth+Vdt×{capacitance of C1 / (capacitance of C1+capacitance of C2)}". Vth may be the threshold voltage of the drive transistor Td.

[0135] In this way, the data voltage Vdt can be divided by the first capacitor C1 and the second capacitor C2, and therefore, the range of the data voltage Vdt (e.g., the grayscale expression range) can be expanded. Therefore, fine grayscale expression may be possible, so that the image quality of the display device 10 can be improved. In an embodiment, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 may be the same. However, the present disclosure is not limited thereto, and the capacitance of the second capacitor C2 may be greater than the capacitance of the first capacitor C1. For example, the ratio between the capacitance of the second capacitor C2 and the capacitance of the first capacitor C1 may be approximately 2:1.

[0136] During the data writing period P3, the voltage difference (e.g., gate-source voltage) between the first node N1, which is the gate electrode of the driving transistor Td, and the source electrode of the driving transistor Td can be maintained by the first capacitor C1. Such gate-source voltage can include the threshold voltage (Vth) of the driving transistor Td and the data voltage Vdt.

[0137] The light emitting element ED may be biased in the opposite direction in the data writing period P3 , and the light emitting element ED may thus be maintained in a turned-off state in the data writing period P3 .

[0138] Will refer to Figure 4 and Figure 9 Description of the display device 10 (see Figure 1 ) Operations in the transmission cycle P4.

[0139] Figure 9 is used to describe Figure 3 The display device 10 is Figure 4 Schematic diagram of the operation in the transmission cycle P4.

[0140] like Figure 4 As shown in , in the emission period P4, the first emission signal EM1 and the second emission signal EM2 may each have an active level, and the first initialization gate signal GI1, the second initialization gate signal GI2, and the write gate signal GW may each have an inactive level. In the emission period P4, the reference voltage Vref may be applied to the data line DL.

[0141] The first emission signal EM1 having an active level may be applied to the gate electrode of the first emission control transistor Te1 through the first emission line EML1. Therefore, the first emission control transistor Te1 may be turned on.

[0142] The second emission signal EM2 having an active level may be applied to the gate electrode of the second emission control transistor Te2 through the second emission line EML2. Therefore, the second emission control transistor Te2 may be turned on.

[0143] A first initialization gate signal GI1 having an inactive level may be applied to the gate electrode of the first initialization transistor Ti1 through the first initialization gate line GIL1. Thus, the first initialization transistor Ti1 may be turned off.

[0144] A second initialization gate signal GI2 having an inactive level may be applied to the gate electrode of the second initialization transistor Ti2 through the second initialization gate line GIL2 , and thus the second initialization transistor Ti2 may be turned off.

[0145] The write gate signal GW having an inactive level may be applied to the gate electrode of the switching transistor Ts through the write gate line GWL. Thus, the switching transistor Ts may be turned off.

[0146] In the emission period P4 , the driving transistor Td may be maintained in a turned-on state by the gate-source voltage maintained by the first capacitor C1 .

[0147] During the emission period P4, the voltage of the first node N1 may have a value corresponding to, for example, "Vdt+VEL−Vref+Vth−Δ". VEL may be the voltage of the first electrode (e.g., the third node N3) of the light emitting element ED during the emission period P4, and Δ may have a value corresponding to the above-described "Vref−Vth+Vdt×{capacitance of C1 / (capacitance of C1+capacitance of C2)}".

[0148] In this way, during emission period P4, the driving transistor Td, the first emission control transistor Te1, and the second emission control transistor Te2 can be turned on. Therefore, the driving voltage VDD can be applied to the first electrode (e.g., the third node N3) of the light-emitting element ED via the turned-on driving transistor Td, the first emission control transistor Te1, and the second emission control transistor Te2, and the first common voltage VSS1 can be applied to the second electrode (e.g., the fourth node N4) of the light-emitting element ED via the turned-on second emission control transistor Te2. The gate-source voltage maintained by the first capacitor C1 can include the threshold voltage (Vth) of the driving transistor Td. Therefore, the magnitude of the driving current flowing to the light-emitting element ED via the turned-on driving transistor Td can be determined based on the data voltage Vdt and the threshold voltage (Vth) of the driving transistor Td. Therefore, the driving current supplied to the light-emitting element ED can accurately reflect the magnitude of the data voltage Vdt. In other words, the driving current can have a precise value that compensates for the threshold voltage (Vth) of the driving transistor Td. In this way, the driving current of each pixel PX can be determined while compensating for the different values ​​of the threshold voltage (Vth) of the driving transistor Td of each pixel PX. Therefore, the luminance deviation between each pixel PX caused by the deviation of the threshold voltage Vt between the driving transistors Td of each pixel PX can be minimized. Therefore, the image quality of the display device 10 can be improved.

[0149] The threshold voltage detection period P2 and the data writing period P3 can be separated from each other, and therefore, the data voltage Vdt can be written at high speed. Therefore, the display device 10 can be driven at high speed.

[0150] According to an embodiment, all pixels PX may emit light simultaneously in the emission period P4. For example, the initialization operation, threshold voltage detection operation, and data writing operation of the pixels PX may be sequentially performed in units of one horizontal line, but the emission operation of the pixels PX may be performed simultaneously.

[0151] Figure 10 yes Figure 2 Schematic diagram of an equivalent circuit of a pixel PX and a sub-common circuit SCC connected to the pixel PX.

[0152] Figure 10 The embodiment is similar to the above embodiment in terms of the configuration of the second initialization transistor Ti2. Figure 3 The embodiments are different, and the differences will be described below.

[0153] Figure 10The second initialization transistor Ti2 may be turned on by the second emission signal EM2 from the second emission line EML2 to electrically connect the fourth node N4 and the second common voltage line VSL2 to each other. A gate electrode of the second initialization transistor Ti2 may be electrically connected to the second emission line EML2, a drain electrode of the second initialization transistor Ti2 may be electrically connected to the fourth node N4, a source electrode of the second initialization transistor Ti2 may be electrically connected to the second common voltage line VSL2, and a body electrode of the second initialization transistor Ti2 may be electrically connected to the first common voltage line VSL1.

[0154] Figure 10 The second initialization transistor Ti2 can be a transistor of the opposite type to the second emission control transistor Te2. For example, when the second emission control transistor Te2 is an N-type transistor, the second initialization transistor Ti2 can be a P-type transistor. When the second initialization transistor Ti2 is a P-type transistor, the second emission signal EM2 can be applied to the gate electrode of the second initialization transistor Ti2. This is because, as Figure 4 As shown in , the second initialization gate signal GI2 has a shape whose phase is 180° inverted relative to the phase of the second emission signal EM2. Therefore, when the second emission control transistor Te2 and the second initialization transistor Ti2 are transistors of opposite types, the second emission control transistor Te2 and the second initialization transistor Ti2 can be controlled by the same signal (e.g., the second emission signal EM2). In this case, the second initialization gate signal GI2 and the second initialization gate line GIL2 for transmitting the second initialization gate signal GI2 can be omitted, and the circuit configuration can be simplified.

[0155] Although not shown, the first initialization transistor Ti1 may be a transistor of the opposite type to the first emission control transistor Te1. For example, in the case where the first emission control transistor Te1 is an N-type transistor, the first initialization transistor Ti1 may be a P-type transistor. In the case where the first initialization transistor Ti1 is a P-type transistor, the first emission signal EM1 may be applied to the gate electrode of the first initialization transistor Ti1. This is because, as Figure 4 As shown in , the first initialization gate signal GI1 has a shape whose phase is inverted 180° relative to the phase of the first emission signal EM1. Therefore, in the case where the first emission control transistor Te1 and the first initialization transistor Ti1 are transistors of opposite types, the first emission control transistor Te1 and the first initialization transistor Ti1 can be controlled by the same signal (e.g., the first emission signal EM1).

[0156] For example, Figure 10 Display device 10 (see Figure 1 ) can be based on Figure 4 However, as described above, Figure 4 At least one of the first initialization gate signal GI1 and the second initialization gate signal GI2 may be omitted.

[0157] Figure 11 yes Figure 2 Schematic diagram of an equivalent circuit of a pixel PX and a sub-common circuit SCC connected to the pixel PX.

[0158] Figure 11 The embodiment and the above Figure 3 The difference between the embodiments is that Figure 11 The embodiment does not include the second power switching circuit PSC2, and this difference will be described below.

[0159] like Figure 11 As shown in FIG, the second electrode of the light emitting element ED (for example, the fourth node N4) can be connected (for example, directly connected) to the first common voltage line VSL1. For example, if the threshold voltage of the light emitting element ED is sufficiently high, the second electrode of the light emitting element ED can be connected (for example, directly connected) to the first common voltage line VSL1 without the second power switching circuit PSC2. If the threshold voltage of the light emitting element ED is sufficiently high, the light emitting element ED is switched off during the initialization period P1 (see FIG. Figure 5 ), threshold voltage detection period P2 (see Figure 5 ) and data write cycle P3 (see Figure 5 ) can be non-luminous. Figure 11 In the embodiment, the second power switching circuit PSC2, the second common voltage, and the second common voltage line VSL2 may be omitted, and thus, the circuit may be further simplified.

[0160] For example, Figure 11 Display device 10 (see Figure 1 ) can be based on Figure 4 However, Figure 4 The second initialization gate signal GI2 and the second emission signal EM2 may be omitted.

[0161] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0162] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are intended to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure should not be limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and should be interpreted as including all technical spirits within the scope of equivalents within the scope of this disclosure.

Claims

1. A display device, characterized in that: The display device includes: A display panel having a display area and a non-display area; A plurality of pixels are arranged in the display area; a light emitting element provided in each of the plurality of pixels; a driving transistor provided in each of the plurality of pixels and electrically connected to the light emitting element; and A common circuit is provided in the non-display area and is electrically connected to at least one of the driving transistor and the light emitting element of each of the plurality of pixels.

2. The display device according to claim 1, wherein The common circuit is electrically connected to at least one of a drain electrode of the driving transistor and a cathode electrode of the light emitting element.

3. The display device according to claim 1, wherein The common circuit includes a first power switching circuit electrically connected to a drain electrode of the driving transistor and receiving a driving voltage, an initialization voltage, a first emission signal, and a first initialization gate signal.

4. The display device according to claim 3, wherein: The first power switching circuit includes: a first emission transistor electrically connected between the drain electrode of the driving transistor and a driving voltage line transmitting the driving voltage; and The first initialization transistor is electrically connected between the drain electrode of the driving transistor and an initialization voltage line transmitting the initialization voltage.

5. The display device according to claim 4, wherein: The first emission signal is input to the gate electrode of the first emission transistor, and The first initialization gate signal is input to a gate electrode of the first initialization transistor.

6. The display device according to claim 5, wherein: The common circuit further includes a second power switching circuit electrically connected to a cathode electrode of the light emitting element and receiving at least one of a second emission signal and a second initialization gate signal, a first common voltage, and a second common voltage.

7. The display device according to claim 6, wherein: The second power switching circuit includes: a second emission transistor electrically connected between the cathode electrode of the light emitting element and a first common voltage line transmitting the first common voltage; and A second initialization transistor is electrically connected between the cathode electrode of the light emitting element and a second common voltage line transmitting the second common voltage.

8. The display device according to claim 7, wherein: The second emission signal is input to the gate electrode of the second emission transistor, and The second initialization gate signal is input to a gate electrode of the second initialization transistor.

9. The display device according to claim 8, wherein Each of the plurality of pixels includes a switching transistor electrically connected between a data line and a gate electrode of the driving transistor.

10. The display device according to claim 9, wherein A write gate signal is input to the gate electrode of the switching transistor, and the display device further includes: a gate driver that sends the first emission signal, the second emission signal, the first initialization gate signal, and the second initialization gate signal to the common circuit and sends the write gate signal to each of the plurality of pixels, Among them, during the initialization cycle, The first initialization gate signal, the second initialization gate signal, and the write gate signal each have an active level, The first transmission signal and the second transmission signal each have an inactive level, and A reference voltage is applied to the data line, Wherein, in the threshold voltage detection period after the initialization period, The first emission signal, the second initialization gate signal, and the write gate signal each have an active level, The first initialization gate signal and the second emission signal each have an inactive level, and The reference voltage is applied to the data line, In which, in the data writing cycle after the threshold voltage detection cycle, The first emission signal and the second initialization gate signal each have an active level, The first initialization gate signal and the second emission signal each have an inactive level, and A data voltage is applied to the data line, wherein the write gate signal has an effective level during a portion of the data write cycle, Wherein, in the emission cycle after the data writing cycle, The first transmission signal and the second transmission signal each have an effective level, The first initialization gate signal, the second initialization gate signal, and the write gate signal each have an inactive level, and The reference voltage is applied to the data line.

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