Thin film transistor, pixel circuit and display device

Abstract

The utility model provides a thin film transistor, a pixel circuit and a display device. The thin film transistor comprises a substrate, a grid electrode, an active layer, a grid electrode insulating layer, a first electrode and a second electrode. The grid electrode is located on one side of the substrate. The active layer and the grid electrode are located on the same side of the substrate. The gate insulating layer is located between the gate and the active layer. The first electrode and the second electrode are arranged on the side, away from the substrate, of the active layer in a spaced mode and make contact with the active layer. At least one of the first electrode and the second electrode is provided with a first hollow part, and the orthographic projection of the first hollow part on the substrate is overlapped with the orthographic projection of the grid electrode on the substrate. And / or, the grid electrode is provided with a second hollow part, and at least one of the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate is overlapped with the orthographic projection of the second hollow part on the substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor, a pixel circuit and a display device. Background Art

[0002] Thin-film transistors are a key component widely used in display panels and other electronic devices. They control the flow of current in the active layer through gate voltage, enabling functions such as switching and signal amplification.

[0003] The leakage current of the thin film transistors in existing display panels is relatively large, resulting in problems such as reduced display performance and increased power consumption of the display panels. Utility Model Content

[0004] The present application provides a thin film transistor, a pixel circuit and a display device.

[0005] A first aspect of the present application provides a thin film transistor, comprising:

[0006] substrate;

[0007] a gate, located on one side of the substrate;

[0008] an active layer, located on the same side of the substrate as the gate;

[0009] a gate insulating layer, located between the gate and the active layer;

[0010] A first electrode and a second electrode are spaced apart and arranged on a side of the active layer away from the base substrate, and are in contact with the active layer;

[0011] At least one of the first electrode and the second electrode has a first hollow portion, and an orthographic projection of the first hollow portion on the base substrate overlaps with an orthographic projection of the gate on the base substrate;

[0012] And / or, the gate is provided with a second hollow portion, and at least one of the orthographic projection of the first electrode on the base substrate and the orthographic projection of the second electrode on the base substrate overlaps with the orthographic projection of the second hollow portion on the base substrate.

[0013] In one embodiment, when at least one of the first electrode and the second electrode is provided with a first hollow portion, and the gate is provided with a second hollow portion, the orthographic projection of the first hollow portion on the base substrate and the orthographic projection of the second hollow portion on the base substrate do not overlap.

[0014] In one embodiment, when at least one of the first electrode and the second electrode is provided with a first hollow portion, the orthographic projection of the first hollow portion on the base substrate all falls within the orthographic projection of the gate on the base substrate;

[0015] When the gate is provided with a second hollow portion, at least one of the orthographic projection of the first electrode on the base substrate and the orthographic projection of the second electrode on the base substrate completely covers the orthographic projection of the second hollow portion on the base substrate.

[0016] In one embodiment, the thin film transistor includes two gate electrodes, two first electrodes and one second electrode.

[0017] In one embodiment, the two gates are arranged along the length direction thereof; the two first electrodes are arranged along the length direction thereof;

[0018] The arrangement direction of the two gates is parallel to the arrangement direction of the two first electrodes; the length direction of the second electrode is parallel to the arrangement direction of the first electrodes.

[0019] In one embodiment, the thin film transistor further includes a connecting portion, and ends of the two gates are connected via the connecting portion.

[0020] In one embodiment, the second electrode is provided with the first hollow portion, and an orthographic projection of the first hollow portion provided on the second electrode on the base substrate overlaps with an orthographic projection of the connecting portion on the base substrate.

[0021] In one embodiment, the two first electrodes are respectively provided with the first hollow portion; and / or the two gates are respectively provided with the second hollow portion.

[0022] In one embodiment, the two gates are arranged along their width direction; the two first electrodes are arranged along their width direction; the second electrode is located between the two first electrodes and the length direction of the second electrode is parallel to the length direction of the first electrode.

[0023] In one embodiment, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate both overlap with the orthographic projection of the gate on the substrate; and / or,

[0024] The first electrode and the second electrode are respectively provided with the first hollow portion, and the gate is provided with the second hollow portion.

[0025] A second aspect of the embodiments of the present application provides a pixel circuit including the above-mentioned thin film transistor.

[0026] A third aspect of the embodiments of the present application provides a display device including the above-mentioned pixel circuit.

[0027] By providing the first and second hollow portions, the thin-film transistor of the present application can reduce the area of ​​overlap between the orthographic projections of the first and second electrodes on the substrate and the orthographic projection of the gate on the substrate, thereby reducing the electric field distribution area between the vertically overlapping regions of the first and second electrodes and the gate. When the gate voltage applied to the gate is lower than the threshold voltage, the smaller electric field distribution area can reduce the accumulation of holes in the active layer, thereby reducing the participation of holes in conduction and reducing leakage current.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] Figure 1 A cross-sectional view of a thin film transistor provided in one embodiment of the present application;

[0031] Figure 2 A schematic structural diagram of a thin film transistor provided in one embodiment of the present application;

[0032] Figure 3 A schematic structural diagram of a thin film transistor provided in another embodiment of the present application;

[0033] Figure 4 A schematic structural diagram of a thin film transistor provided in yet another embodiment of the present application;

[0034] Figure 5 A schematic structural diagram of a thin film transistor provided in one embodiment of the present application. DETAILED DESCRIPTION

[0035] Here, the technical solutions in the embodiments (or "implementations") of the present application will be clearly and completely described in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0036] If there are terms related to directional indications or positional relationships in the embodiments of this application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement, etc. between the components in a specific posture (as shown in the accompanying drawings); if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first" and "second" in the embodiments of this application are only used for the purpose of convenience of description and should not be understood as indicating or implying relative importance.

[0037] The thin film transistor, pixel circuit and display device of the present application are described in detail below with reference to the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can complement or be combined with each other.

[0038] The present application provides a thin film transistor, such as Figures 1 to 3 As shown, the thin film transistor includes a base substrate 10 , a gate 20 , an active layer 30 , a gate insulating layer 40 , a first electrode 51 and a second electrode 52 .

[0039] The gate 20 is located on one side of the base substrate 10, the active layer 30 and the gate 20 are located on the same side of the base substrate 10, and the gate insulating layer 40 is located between the gate 20 and the active layer 30. The first electrode 51 and the second electrode 52 are spaced apart and disposed on a side of the active layer 30 away from the base substrate 10, and are in contact with the active layer 30.

[0040] At least one of the first electrode 51 and the second electrode 52 is provided with a first hollow portion 53, and the orthographic projection of the first hollow portion 53 on the base substrate 10 overlaps with the orthographic projection of the gate 20 on the base substrate 10. Alternatively, the gate 20 is provided with a second hollow portion 21, and at least one of the orthographic projections of the first electrode 51 and the second electrode 52 on the base substrate 10 overlaps with the orthographic projection of the second hollow portion 21 on the base substrate 10. Alternatively, at least one of the first electrode 51 and the second electrode 52 is provided with a first hollow portion 53, and the orthographic projection of the first hollow portion 53 on the base substrate 10 overlaps with the orthographic projection of the gate 20 on the base substrate 10, and the gate 20 is provided with a second hollow portion 21, and at least one of the orthographic projections of the first electrode 51 and the second electrode 52 on the base substrate 10 overlaps with the orthographic projection of the second hollow portion 21 on the base substrate 10.

[0041] When the gate-source voltage of the thin film transistor is greater than the threshold voltage (on-state voltage), a conductive channel is formed in the active layer 30, causing current to flow between the first electrode 51 and the second electrode 52, putting the thin film transistor in an on state. When the gate voltage applied to the gate 20 is less than the threshold voltage, the conductive channel disappears, putting the thin film transistor in an off state. When the gate voltage applied to the gate 20 continues to decrease, the holes in the active layer 30 of the thin film transistor will move away from the gate 20 under the action of the gate voltage and continue to accumulate in the back channel region 312, forming a conductive path, resulting in the generation of leakage current. When the gate voltage applied to the gate 20 is further reduced, thermal ion emission occurs between the first electrode 51 and the second electrode 52, and holes accumulate in the front channel region 311 at the junction of the gate insulating layer 40 and the active layer 30, forming a new conductive path, resulting in an increase in leakage current.

[0042] The thin film transistor of the present application can reduce the area of ​​the overlapping portion between the orthographic projection of the first electrode 51 and / or the second electrode 52 on the substrate 10 and the orthographic projection of the gate 20 on the substrate 10 by providing a first hollow portion 53 on at least one of the first electrode 51 and the second electrode 52 and providing a second hollow portion 21 on the gate 20. Since an electric field exists between the overlapping region of the first electrode 51, the second electrode 52 and the gate 20 in the vertical direction, when the gate voltage applied to the gate 20 is lower than the threshold voltage, the accumulation of holes in the active layer 30 can be reduced by reducing the area of ​​this overlapping region, thereby reducing the leakage current formed by the participation of holes in conduction.

[0043] In one embodiment, the base substrate 10 may be an alkali-free glass layer.

[0044] In one embodiment, the gate 20 may be a stack of one or more of molybdenum, titanium, aluminum, and copper.

[0045] In one embodiment, the active layer 30 includes an amorphous silicon layer 31 and a doped amorphous silicon layer 32 located above the amorphous silicon layer 31, and the first electrode 51 and the second electrode 52 are located on the doped amorphous silicon layer 32. In some embodiments, the active layer 30 may also include an amorphous silicon layer and a metal oxide semiconductor layer located above the amorphous silicon layer.

[0046] In one embodiment, the gate insulating layer 40 may be made of a silicon oxide layer or a silicon nitride layer.

[0047] In one embodiment, one of the first electrode 51 and the second electrode 52 is a source electrode, and the other is a drain electrode.

[0048] In one embodiment, the setting of the hollow portion on the thin film transistor may include the following situations: the first hollow portion 53 may be set only on the first electrode 51; or the first hollow portion 53 may be set only on the second electrode 52; or the second hollow portion 21 may be set only on the gate 20; or the first hollow portion 53 may be set on the first electrode 51 and the second hollow portion 21 may be set on the gate 20; or the first hollow portion 53 may be set on the second electrode 52 and the second hollow portion 21 may be set on the gate 20; or the first hollow portion 53 may be set on the first electrode 51 and the second electrode 52 respectively, and the second hollow portion 21 may be set on the gate 20.

[0049] When a first hollow portion 53 is provided on both the first electrode 51 and the second electrode 52, and a second hollow portion 21 is provided on the gate 20, the vertical facing area of ​​the first electrode 51 and the second electrode 52 and the gate 20 can be more effectively reduced, thereby reducing the vertical electric field distribution area between the first electrode 51 and the second electrode 52 and the gate 20, which is more conducive to reducing the generation of leakage current.

[0050] In one embodiment, Figure 1 and Figure 2 As shown, the orthographic projection of the first electrode 51 on the base substrate 10 and the orthographic projection of the second electrode 52 on the base substrate 10 overlap with the orthographic projection of the gate 20 on the base substrate 10. The orthographic projection of the first electrode 51 on the base substrate 10 mentioned here refers to the orthographic projection of the portion of the first electrode 51 excluding the first hollow portion 53 on the base substrate, the orthographic projection of the second electrode 52 on the base substrate 10 refers to the orthographic projection of the portion of the second electrode 52 excluding the first hollow portion 53 on the base substrate 10, and the orthographic projection of the gate 20 on the base substrate 10 refers to the orthographic projection of the portion of the gate 20 excluding the second hollow portion 21 on the base substrate 10. Only when the first electrode 51 and the second electrode 52 overlap with the gate 20 in the vertical direction can a conductive channel be formed between the first electrode 51 and the second electrode 52 by controlling the gate voltage, so that the thin film transistor has normal operating performance.

[0051] In one embodiment, Figure 2 and Figure 3As shown, when at least one of the first electrode 51 and the second electrode 52 is provided with a first hollow portion 53, and the gate 20 is provided with a second hollow portion 21, the orthographic projection of the first hollow portion 53 on the base substrate 10 does not overlap with the orthographic projection of the second hollow portion 21 on the base substrate 10. An electric field exists between the region where the first electrode 51 and the gate 20 overlap in the vertical direction, and an electric field exists between the region where the second electrode 52 and the gate 20 overlap in the vertical direction. Therefore, the above arrangement can further reduce the vertical overlapping area between the first electrode 51 or the second electrode 52 and the gate 20, thereby reducing the accumulation of holes in the active layer 30 and lowering leakage current.

[0052] In one embodiment, Figures 1 to 3 As shown, when at least one of the first electrode 51 and the second electrode 52 is provided with a first hollow portion 53, the orthographic projection of the first hollow portion 53 on the base substrate 10 completely falls within the orthographic projection of the gate 20 on the base substrate 10. When the gate 20 is provided with a second hollow portion 21, at least one of the orthographic projection of the first electrode 51 on the base substrate 10 and the orthographic projection of the second electrode 52 on the base substrate 10 completely covers the orthographic projection of the second hollow portion 21 on the base substrate 10.

[0053] When the first hollow portion 53 and / or the second hollow portion 21 are arranged in the above manner, the overlap area between the first electrode 51 or the second electrode 52 and the gate 20 in the vertical direction can be minimized, which is beneficial for reducing leakage current. Furthermore, the above arrangement prevents the first hollow portion 53 or the second hollow portion 21 from occupying the non-overlapping area between the first electrode 51 or the second electrode 52 and the gate 20 in the vertical direction, thereby reducing the edge effect of the electrode and improving the stability and reliability of the thin film transistor.

[0054] In one embodiment, Figure 4 and Figure 5 As shown, the thin film transistor includes two gate electrodes 20, two first electrodes 51, and one second electrode 52. The dual-gate thin film transistor can more effectively control the electric field distribution in the active layer 30 by independently controlling the voltages of the two gate electrodes, thereby reducing the accumulation of holes in the active layer 30 and thus reducing leakage current.

[0055] In one embodiment, Figure 4 and Figure 5As shown, the thin film transistor further includes a connecting portion 22, through which the ends of the two gate electrodes 20 of the thin film transistor are connected. The connecting portion 22 can reduce the parasitic capacitance between the gate electrode 20 and the first electrode 51 or the second electrode 52, thereby improving the switching speed and response time of the thin film transistor. The connecting portion 22 can also simplify the circuit structure and reduce the number of control signals required for the thin film transistor.

[0056] In one embodiment, Figure 4 As shown, the two gate electrodes 20 of the thin film transistor are arranged along its width, the two first electrodes 51 are arranged along its width, and the second electrode 52 is located between the two first electrodes 51, with the length direction of the second electrode 52 being parallel to the length direction of the first electrode 51. The orthographic projection of one second electrode 52 on the base substrate 10 overlaps with the orthographic projections of the two gate electrodes 20 on the base substrate 10. This helps reduce the contact resistance between the electrodes and the active layer 30 and improves carrier mobility. Using only one second electrode can also optimize the electric field distribution within the thin film transistor, reduce the subthreshold swing, and improve device performance.

[0057] In one embodiment, Figure 5 As shown, the two gate electrodes 20 of the thin-film transistor are arranged along its length, and the two first electrodes 51 are arranged along its length. The arrangement direction of the two gate electrodes 20 is parallel to the arrangement direction of the two first electrodes 51, and the length direction of the second electrode 52 is parallel to the arrangement direction of the first electrodes 51. Compared with the arrangement of the two gate electrodes 20 along its width, this arrangement can effectively reduce the total area of ​​the thin-film transistor, thereby reducing the area ratio of the thin-film transistor in the pixel. This helps to increase the pixel aperture ratio of the display panel, thereby improving the display brightness of the display panel.

[0058] In one embodiment, Figure 4 and Figure 5As shown, the second electrode 52 is provided with the first hollow portion 53, and the orthographic projection of the first hollow portion 53 provided on the second electrode 52 on the substrate 10 overlaps with the orthographic projection of the connecting portion 22 on the substrate 10. The connecting portion 22 between the two gates 20 increases the area of ​​overlap between the orthographic projections of the gates 20 on the substrate 10 and the orthographic projections of the second electrode 52 on the substrate 10, thereby increasing the leakage current of the thin film transistor. Therefore, when the first hollow portion 53 is located directly above the connecting portion 22, the vertical overlap area between the second electrode 52 and the gate 20 can be reduced, thereby reducing leakage current. At the same time, the connecting portion 22 does not overlap with the active layer 30 in the vertical direction. The first hollow portion 53 located directly above the connecting portion 22 can reduce the impact of the first hollow portion 53 on the electric field distribution within the thin film transistor, which is beneficial for improving the reliability of the thin film transistor. In other embodiments, the connecting portion is provided with a second hollow portion, and the orthographic projection of the second hollow portion on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

[0059] In one embodiment, Figure 4 and Figure 5 As shown, the two first electrodes 51 are respectively provided with the first hollow portion 53. This arrangement can simultaneously reduce the overlapping area of ​​the orthographic projection of the two first electrodes 51 on the base substrate 10 and the orthographic projection of the gate 20 on the base substrate 10, thereby effectively reducing the generation of leakage current.

[0060] In one embodiment, Figure 5 As shown, the two gates 20 are respectively provided with a second hollow portion 21. This arrangement can simultaneously reduce the overlapping area of ​​the orthographic projection of the first electrode 51 and the second electrode 52 on the base substrate 10 and the orthographic projection of the gate 20 on the base substrate 10, thereby effectively reducing the generation of leakage current.

[0061] In one embodiment, the number of the first hollow portion 53 and the second hollow portion 21 can be multiple, such as Figure 5 As shown, each first electrode 51 is provided with two first hollow portions 53 , the second electrode 52 is provided with three first hollow portions 53 , and each gate 20 is provided with two second hollow portions 21 .

[0062] In one embodiment, the shapes of the first hollow portion 53 and the second hollow portion 21 can be rectangular, circular, triangular or other irregular shapes.

[0063] An embodiment of the present application further provides a pixel circuit, which includes a plurality of the above-mentioned thin film transistors. The pixel circuit can drive sub-pixels to emit light through the thin film transistors.

[0064] In one embodiment, the pixel circuit further includes a capacitor. For example, the pixel circuit may include multiple thin film transistors and at least one capacitor. For example, the pixel circuit may include two thin film transistors and one capacitor, or seven transistors and one capacitor.

[0065] An embodiment of the present application further provides a display device, which includes the above-mentioned pixel circuit.

[0066] In one embodiment, the display device includes a display panel, which includes a plurality of pixel circuits and a plurality of sub-pixels. The pixel circuits and the sub-pixels may correspond one to one, and each sub-pixel is used to drive the corresponding sub-pixel to emit light. In some embodiments, the display device may be a display panel.

[0067] In one embodiment, the display device further includes a driver and a power supply circuit, wherein the driver is configured to provide a driving signal for driving the sub-pixels to emit light, and the power supply circuit is configured to supply power to the display panel.

[0068] In one embodiment, the display device further includes a housing, and the display panel is disposed in the housing.

[0069] This application does not impose any specific restrictions on the applicability of display devices. It can be any product or component with display function, such as televisions, laptops, tablets, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, etc.

[0070] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application shall be included in the scope of protection of this application.

Claims

1. A thin film transistor, characterized in that: The thin film transistor includes: substrate; a gate, located on one side of the substrate; an active layer, located on the same side of the substrate as the gate; a gate insulating layer, located between the gate and the active layer; A first electrode and a second electrode are spaced apart and arranged on a side of the active layer away from the base substrate, and are in contact with the active layer; At least one of the first electrode and the second electrode is provided with a first hollow portion, and the orthographic projection of the first hollow portion on the substrate overlaps with the orthographic projection of the gate on the substrate; and / or, the gate is provided with a second hollow portion, and at least one of the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the second hollow portion on the substrate.

2. The thin film transistor according to claim 1, wherein When at least one of the first electrode and the second electrode is provided with a first hollow portion, and the gate is provided with a second hollow portion, an orthographic projection of the first hollow portion on the base substrate and an orthographic projection of the second hollow portion on the base substrate do not overlap.

3. The thin film transistor according to claim 1, wherein When at least one of the first electrode and the second electrode is provided with a first hollow portion, the orthographic projection of the first hollow portion on the base substrate all falls within the orthographic projection of the gate on the base substrate; When the gate is provided with a second hollow portion, at least one of the orthographic projection of the first electrode on the base substrate and the orthographic projection of the second electrode on the base substrate completely covers the orthographic projection of the second hollow portion on the base substrate.

4. The thin film transistor according to claim 1, wherein The thin film transistor includes two gate electrodes, two first electrodes and one second electrode.

5. The thin film transistor according to claim 4, wherein: The two gates are arranged along the length direction thereof; the two first electrodes are arranged along the length direction thereof; The arrangement direction of the two gates is parallel to the arrangement direction of the two first electrodes; the length direction of the second electrode is parallel to the arrangement direction of the first electrodes.

6. The thin film transistor according to claim 5, wherein: The thin film transistor further includes a connecting portion, and ends of the two gates are connected via the connecting portion.

7. The thin film transistor according to claim 6, wherein: The second electrode is provided with the first hollow portion, and an orthographic projection of the first hollow portion provided on the second electrode on the base substrate overlaps with an orthographic projection of the connecting portion on the base substrate.

8. The thin film transistor according to claim 4, wherein: The two first electrodes are respectively provided with the first hollow portion; and / or the two gates are respectively provided with the second hollow portion.

9. The thin film transistor according to claim 4, wherein: The two gates are arranged along the width direction thereof; the two first electrodes are arranged along the width direction thereof; the second electrode is located between the two first electrodes and the length direction of the second electrode is parallel to the length direction of the first electrode.

10. The thin film transistor according to claim 1, wherein: The orthographic projection of the first electrode on the base substrate and the orthographic projection of the second electrode on the base substrate both overlap with the orthographic projection of the gate on the base substrate; and / or, The first electrode and the second electrode are respectively provided with the first hollow portion, and the gate is provided with the second hollow portion.

11. A pixel circuit, characterized in that: The thin film transistor comprises the thin film transistor according to any one of claims 1 to 10.

12. A display device, characterized in that: Comprising the pixel circuit as claimed in claim 11.

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