Display device

Abstract

A display device is provided. The display device includes a first conductive layer disposed on a substrate and including at least two metal layers, a first insulating film on the first conductive layer, a transistor on the first insulating film, a pixel electrode on the transistor, an emission layer on the pixel electrode, a common electrode on the emission layer, and a first barrier film disposed on a side surface of one of the at least two metal layers of the first conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0157097 filed on November 14, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device capable of preventing adjacent conductive layers from being connected to each other due to damage to an insulating film. Background Art

[0004] Unlike liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays are self-luminous. Therefore, they do not require a separate light source and can be made lighter and thinner. Furthermore, OLED displays offer high-quality features such as low power consumption, high brightness, and fast response speeds, and are therefore attracting attention as next-generation displays. Utility Model Content

[0005] Aspects of the present disclosure provide a display device capable of preventing adjacent conductive layers from being connected to each other due to damage to an insulating film.

[0006] According to an embodiment of the present disclosure, a display device may include: a first conductive layer arranged on a substrate and including at least two metal layers, a first insulating film on the first conductive layer, a transistor on the first insulating film, a pixel electrode on the transistor, an emission layer on the pixel electrode, a common electrode on the emission layer, and a first blocking film arranged on the side surface of one of the at least two metal layers of the first conductive layer.

[0007] In an embodiment, the at least two metal layers may include a first metal layer on the substrate, a second metal layer on the first metal layer, and a third metal layer on the second metal layer.

[0008] In an embodiment, the first barrier film may be disposed on a side surface of the second metal layer.

[0009] In an embodiment, the first barrier film may surround a side surface of the second metal layer in a plan view.

[0010] In an embodiment, the first barrier film may be disposed on a side surface of the second metal layer between an edge of the first metal layer and an edge of the third metal layer.

[0011] In an embodiment, the second metal layer may be surrounded by the first metal layer, the third metal layer, and the first barrier film.

[0012] In an embodiment, each of the first and third metal layers may include titanium, and the second metal layer may include aluminum.

[0013] In an embodiment, the at least two metal layers may include a first metal layer on the substrate and a second metal layer on the first metal layer.

[0014] In an embodiment, the first barrier film may be disposed on a side surface of the second metal layer.

[0015] In an embodiment, a first barrier film may be further disposed on an upper surface of the second metal layer.

[0016] In an embodiment, the first barrier film may surround a side surface of the second metal layer in a plan view.

[0017] In an embodiment, the first barrier film may be disposed on a side surface of the second metal layer at an edge of the first metal layer.

[0018] In an embodiment, the second metal layer may be surrounded by the first metal layer and the first barrier film.

[0019] In an embodiment, the at least two metal layers may include a first metal layer on the substrate and a second metal layer on the first metal layer.

[0020] In an embodiment, a first barrier film may be disposed on a side surface of the first metal layer.

[0021] In an embodiment, the first barrier film may surround side surfaces of the first metal layer in a plan view.

[0022] In an embodiment, the first barrier film may be disposed on a side surface of the first metal layer at an edge of the second metal layer.

[0023] In an embodiment, the display device may further include a second insulating film disposed between the substrate and the first conductive layer. The first metal layer may be surrounded by the second insulating film, the second metal layer, and the first barrier film.

[0024] In an embodiment, the display device may further include a second conductive layer on the first insulating film.

[0025] In an embodiment, the second conductive layer may overlap the first conductive layer in a plan view.

[0026] In an embodiment, the second conductive layer may include at least two metal layers.

[0027] In an embodiment, the display device may further include a second barrier film disposed on a side surface of one of the at least two metal layers of the second conductive layer.

[0028] According to the embodiments of the present disclosure, it is possible to prevent adjacent conductive layers from being connected to each other due to damage to an insulating film in a display device.

[0029] The effects are not limited to those mentioned above, and more effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

[0031] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 2 It shows Figure 1 A plan view of the display panel.

[0033] Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0034] Figure 4 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0035] Figure 5 is based on Figure 4 An enlarged view of portion A of a display device of the embodiment.

[0036] Figure 6 is based on Figure 4 An enlarged view of portion A of a display device of the embodiment.

[0037] Figure 7 is based on Figure 4 An enlarged view of portion A of a display device of the embodiment.

[0038] Figures 8 to 12 is a schematic cross-sectional view for illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0039] Figure 13 is a schematic cross-sectional view for illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0040] Figures 14 to 18 is a schematic cross-sectional view for illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The advantages and features of the present disclosure and methods for achieving them will become apparent from the following description of the embodiments herein with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in a variety of different ways. The embodiments are provided to make the disclosure of the present disclosure thorough and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the scope of the present disclosure is limited only by the claims.

[0042] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, the element may be directly on, directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. Furthermore, when an element is referred to as being "in contact with," "in contact with," or the like, another element, the element may be "in electrical contact with" or "in physical contact with" the other element; or "indirectly in contact with" the other element. Throughout the description, the same reference numerals represent the same elements. The figures, dimensions, ratios, angles, and number of elements shown in the accompanying drawings are exemplary only and are not limiting.

[0043] For descriptive purposes, spatially relative terms such as "below," "beneath," "lower," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another element(s) as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, in operation, and / or in manufacture other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented as being "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0044] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise," "comprising," "including," and / or "comprising" specify the presence of the described features, wholes, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0045] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below could be referred to as the second element without departing from the teachings of the present disclosure.

[0046] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. The various embodiments can be practiced individually or in combination.

[0047] In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B." In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or."

[0048] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0049] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a plan view illustrating a display device 100 according to an embodiment of the present disclosure. Figure 2 It shows Figure 1 1 is a plan view of the display panel 110.

[0051] refer to Figures 1 to 2 The display device 100 can display moving images or still images. The display device 100 can be used as a display screen for portable electronic devices such as mobile phones, smart phones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-portable mobile PCs (UMPCs), as well as display screens for various products such as televisions, notebooks, monitors, billboards, and Internet of Things (IoT) devices. Those listed above are merely examples, and the display device 100 can also be adopted in other electronic devices.

[0052] According to an embodiment of the present disclosure, the display device 100 may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, and an ultra-small light-emitting display device including an ultra-small light-emitting diode (such as a micro or nano light-emitting diode (micro-LED or nano-LED)). However, it should be understood that the present disclosure is not limited thereto. For example, the display device 100 may be a display device of another type other than a light-emitting display device. In the following description, a light-emitting display device (e.g., an organic light-emitting display device) is disclosed as an embodiment of the display device 100.

[0053] The display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 for supplying drive signals to the pixels PX. The display device 100 may further include additional components. For example, the display device 100 may further include a power supply unit for supplying a supply voltage to the pixels PX, a timing controller for controlling the operation of the first driver 120 and the second driver 130, and the like.

[0054] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include pixels PX for displaying an image. For example, the display area DA may include a pixel region in which the pixels PX are arranged. The non-display area NDA may be an area other than the display area DA that does not display an image. According to an embodiment of the present disclosure, in a plan view, the non-display area NDA may be arranged around the display area DA and surround the display area DA.

[0055] exist Figure 1 and Figure 2 In the embodiment of the present disclosure, a first direction D1, a second direction D2, and a third direction D3 are defined. According to an embodiment of the present disclosure, the first direction D1 may be a horizontal direction of the display panel 110, and the second direction D2 may be a vertical direction of the display panel 110. The third direction D3 may be a thickness direction of the display panel 110.

[0056] According to an embodiment of the present disclosure, the display panel 110 may have a rectangular shape in a plan view. Figure 1 and Figure 2 The display panel 110 has a horizontal length greater than a vertical length, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the vertical length is greater than the horizontal length, or may have a square shape, etc. The display panel 110 may have sharp corners or rounded corners.

[0057] The shape of the display panel 110 is not limited to the above-mentioned rectangular shape, and other shapes may be adopted. For example, the display panel 110 may have a polygonal shape other than a rectangular shape, a circular shape, an elliptical shape, or other shapes.

[0058] According to an embodiment of the present disclosure, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2 and may have a uniform thickness in the third direction D3. In another embodiment, the display panel 110 may have a three-dimensional shape having a curved surface or the like.

[0059] The display panel 110 may be a substantially non-deformable rigid display panel or a deformable (ie, at least partially foldable, bendable, or curlable) flexible display panel. The display panel 110 may be provided to the display device 100 without being bent or with being partially bent.

[0060] The display panel 110 may include a substrate SUB and pixels PX arranged on the substrate SUB. The pixels PX may be arranged in a display area DA on the substrate SUB.

[0061] The substrate SUB may be a base member for manufacturing or providing the display panel 110 and may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA in a plan view.

[0062] According to embodiments, the display area DA may have various shapes. For example, the display area DA may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes in a plan view. According to embodiments of the present disclosure, the display area DA may have a shape that conforms to the shape of the display panel 110.

[0063] The pixels PX may be provided and / or disposed in the display area DA. For example, the display area DA may include a plurality of pixel areas in which the pixels PX are arranged.

[0064] According to an embodiment of the present disclosure, the display device 100 may be a light-emitting display device, and each of the pixels PX may include a light-emitting element located in a corresponding emission region and a pixel circuit connected to the light-emitting element. In the following description of the embodiment, the term "connection" may include an electrical connection and / or a physical connection. Each of the pixel circuits may include a transistor (e.g., a transistor including a drive transistor and at least one switching transistor that generates a drive current corresponding to a data signal) and at least one capacitor (e.g., a capacitor including a storage capacitor).

[0065] The non-display area NDA may include a pad area PA in which pads PD are arranged. According to an embodiment of the present disclosure, the non-display area NDA may further include a driver circuit area located on at least one side of the display area DA. At least one driver, pads PD, and / or lines may be arranged in the non-display area NDA.

[0066] At least one driver or a portion of the driver for driving the pixel PX may be arranged in the driver circuit region. For example, the circuit elements forming the first driver 120 (e.g., the drive transistors and drive capacitors forming the stage circuit of the first driver 120) may be arranged in the driver circuit region on the substrate SUB. According to an embodiment of the present disclosure, the circuit elements of the first driver 120 may be formed in the display panel 110 together with the pixel PX. According to an embodiment of the present disclosure, the drive transistor provided to the first driver 120 may be a transistor of substantially the same or similar type and / or structure as the transistor provided to the pixel PX, and may be formed together with the transistor of the pixel PX.

[0067] The pads PD may be arranged in the pad area PA. At least one circuit board 140 may be arranged and / or coupled to the pad area PA. According to an embodiment of the present disclosure, a plurality of circuit boards 140 connected to corresponding pads PD may be arranged in the pad area PA. The pads PD may include signal pads and power pads for transmitting drive signals and supply voltages required to drive the pixels PX and / or the first driver 120 to the interior of the display panel 110.

[0068] The first driver 120 and the second driver 130 can generate drive signals for controlling the operation timing and brightness of the pixel PX, and can supply the drive signals to the pixel PX. For example, the first driver 120 can be a gate driver including a scan driver and can be connected to the pixel PX through a corresponding gate line. The first driver 120 can supply a gate signal (for example, a control signal that controls the operation timing of the pixel PX, including a scan signal and / or an emission control signal) to the pixel PX. The second driver 130 can be a data driver including a source driver circuit and can be connected to the pixel PX through a corresponding data line. The second driver 130 can supply a corresponding data signal to the pixel PX.

[0069] According to an embodiment of the present disclosure, at least one of the first driver 120 and the second driver 130 or a portion of the at least one driver may be incorporated into the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be disposed on the substrate SUB of the display panel 110 and may be disposed and / or formed in the non-display area NDA.

[0070] Despite Figure 1 In the embodiment, the first driver 120 is formed on one side of the display area DA (for example, in the non-display area NDA on the right side of the display area DA), but the present disclosure is not limited thereto. In another embodiment, the first driver 120 may be located only on the other side of the display area DA (for example, in the non-display area NDA on the left side of the display area DA), or on both sides of the display area DA (for example, in the non-display area NDA on the left and right sides of the display area DA). In another embodiment, a portion of the first driver 120 may be located in the non-display area NDA, while another portion of the first driver 120 may be located in a non-emission area in the display area DA (for example, an area between the emission areas of the pixels PX).

[0071] According to an embodiment of the present disclosure, the other of the first driver 120 and the second driver 130, or a portion of the other driver, may be arranged or formed outside the display panel 110 and may be electrically connected to the display panel 110. For example, the second driver 130 may be implemented with a plurality of integrated circuit chips and may be arranged on a circuit board 140 electrically connected to the pixels PX of the display panel 110. The second driver 130 may be implemented as at least one integrated circuit chip and may be mounted on the non-display area NDA of the display panel 110.

[0072] The circuit board 140 may be connected to the display panel 110 via the pads PD. According to an embodiment of the present disclosure, the circuit board 140 may be, but is not limited to, a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF). According to an embodiment of the present disclosure, the circuit board 140 may be connected to the timing controller and / or the power supply unit via another circuit board or a connector.

[0073] Figure 3 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment of the present disclosure. For example, Figure 3 The present disclosure is not limited to the following examples: Figure 3 and the type and / or structure of the pixel PX in the display device 100 may vary according to the embodiment.

[0074] Apart from Figure 1 and Figure 2 In addition, reference Figure 3 Pixel PX may include a light-emitting element ED and a pixel circuit PC connected to the light-emitting element ED. The light-emitting element ED may be the light source of the pixel PX and may be, but is not limited to, an organic light-emitting diode. The pixel circuit PC may control the emission timing and brightness of the light-emitting element ED.

[0075] The pixel circuit PC may include a transistor T and at least one capacitor C. For example, the pixel circuit PC may include first to fifth transistors T1 to T5 and first and second capacitors C1 and C2. Figure 3 Although all the transistors T are n-type transistors, the type of the transistors T is not limited thereto. For example, at least one transistor T may be formed as a p-type transistor.

[0076] The pixel circuit PC may supply a driving current Id to the light emitting element ED in response to driving signals supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC may supply the driving current Id to the light emitting element ED in response to a gate signal GS supplied from the first driver 120 through a corresponding gate line GL and a data signal DATA supplied from the second driver 130 through a data line DL.

[0077] The first transistor T1 can be a driving transistor of the pixel PX, wherein the size of the drain-source current (e.g., the driving current Id) is determined according to the gate-source voltage. The second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be switching transistors that are turned on or off according to the corresponding gate-source voltage. Depending on the type (e.g., p-type or n-type transistor) and / or operating conditions of each of the first transistor T1 to the fifth transistor T5, the first electrode of each of the first transistor T1 to the fifth transistor T5 can be a drain electrode (or drain region) or a source electrode (or source region), and its second electrode can be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode can be a source electrode.

[0078] The pixel PX can be connected to a first gate line GWL that transmits a first gate signal GW (e.g., a scan signal), a second gate line GIL that transmits a second gate signal GIN, a third gate line GRL that transmits a third gate signal GR, an emission control line ECL that transmits an emission control signal EM, and a data line DL that transmits a data signal DATA. The pixel PX can be connected to a first voltage line VDL that transmits a first pixel voltage ELVDD (also referred to as a "first pixel supply voltage") and a second voltage line VSL that transmits a second pixel voltage ELVSS (also referred to as a "second pixel supply voltage"). According to an embodiment of the present disclosure, the pixel PX can be further connected to an initialization voltage line VIL that transmits an initialization voltage VINT (also referred to as a "third pixel supply voltage") and a reference voltage line VRL that transmits a reference voltage VREF (also referred to as a "fourth pixel supply voltage").

[0079] According to an embodiment of the present disclosure, the first to fifth transistors T1 to T5 may be located in corresponding pixel regions and may be oxide transistors (also referred to as "oxide semiconductor transistors") including an oxide semiconductor (e.g., an oxide semiconductor material). For example, the active layer of each of the first to fifth transistors T1 to T5 may include an oxide semiconductor. However, it should be understood that the present disclosure is not limited thereto. For example, at least one transistor T may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0080] Oxide semiconductors have high carrier mobility and low leakage current, and therefore, even when the oxide transistor is driven for a long period of time, no significant voltage drop occurs. For example, a pixel PX including an oxide transistor can be driven at a low frequency because even when driven at a low frequency, changes in the brightness and / or color of the image due to the voltage drop are negligible. When the first to fifth transistors T1 to T5 are formed of oxide transistors, leakage current in the pixel PX can be suppressed or prevented, and power consumption can be saved.

[0081] Oxide semiconductors may be sensitive to light, and thus the amount of current may change due to external light. According to an embodiment of the present disclosure, a light-blocking pattern or a light-blocking electrode (e.g., a bottom electrode or a back gate electrode) may be arranged under the active layer included in at least one transistor T to block external light. Therefore, the operating characteristics of the transistor T can be stabilized.

[0082] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode (e.g., a drain electrode) connected to the second node N2, and a second electrode (e.g., a source electrode) connected to the third node N3. The first electrode of the first transistor T1 may be connected to the first voltage line VDL via the fifth transistor T5, and the second electrode may be connected to the light emitting element ED. The first transistor T1 may control the magnitude (e.g., amount) of the driving current Id flowing to the light emitting element ED in response to the data signal DATA transmitted to the first node N1.

[0083] According to an embodiment of the present disclosure, the first transistor T1 may further include a bottom electrode BE connected to the third node N3 (e.g., a bottom gate electrode or a back gate electrode of the first transistor T1). The bottom electrode BE of the first transistor T1 may be connected to the third node N3, so that the first transistor T1 is implemented as a transistor having a dual-gate structure (e.g., a dual-gate transistor having a source synchronous structure), thereby improving the operating characteristics of the first transistor T1.

[0084] The second transistor T2 may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The second transistor T2 may be turned on by a first gate signal GW (e.g., a first gate signal GW of a gate-on voltage) transmitted from the first gate line GWL to connect the data line DL to the first node N1. Therefore, the data signal DATA transmitted from the data line DL may be transmitted to the first node N1.

[0085] The third transistor T3 may include a gate electrode connected to the third gate line GRL, a first electrode connected to the reference voltage line VRL, and a second electrode connected to the first node N1. The third transistor T3 may be turned on by a third gate signal GR transmitted from the third gate line GRL and may transmit a reference voltage VREF from the reference voltage line VRL to the first node N1.

[0086] The fourth transistor T4 may include a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3, and a second electrode connected to the initialization voltage line VIL. The fourth transistor T4 may be turned on by the second gate signal GIN sent from the second gate line GIL and may send the initialization voltage VINT from the initialization voltage line VIL to the third node N3.

[0087] The fifth transistor T5 may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first voltage line VDL, and a second electrode connected to the second node N2 (or the first electrode of the first transistor T1). The fifth transistor T5 can be turned on by an emission control signal EM (e.g., an emission control signal EM of a gate-on voltage) from the emission control line ECL to control the timing of emission of the pixel PX.

[0088] Each of the second to fifth transistors T2 to T5 may or may not include a bottom electrode. According to an embodiment of the present disclosure, at least one of the second to fifth transistors T2 to T5 may include a bottom electrode, and the bottom electrode of the at least one switching transistor may be connected to the gate electrode of the switching transistor. By connecting the bottom electrode of the switching transistor to the gate electrode, the cutoff characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be obtained, leakage current can be reduced, and voltage stability can be improved. For example, the operating characteristics of a switching transistor formed of an oxide transistor with a short channel length can be improved by forming a dual-gate structure such as a gate synchronous architecture.

[0089] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may be a storage capacitor of the pixel PX and may store a threshold voltage of the first transistor T1 and a voltage corresponding to the data signal DATA (eg, data voltage).

[0090] The second capacitor C2 may be connected between the first voltage line VDL and the third node N3. According to an embodiment of the present disclosure, the capacitance of the second capacitor C2 may be smaller than the capacitance of the first capacitor C1.

[0091] The light-emitting element ED may be connected between the third node N3 and the second voltage line VSL. For example, the light-emitting element ED may include a first electrode (e.g., an anode electrode) connected to the third node N3, a second electrode (e.g., a cathode electrode) facing the first electrode and connected to the second voltage line VSL, and an emission layer between the first electrode and the second electrode. According to an embodiment of the present disclosure, the first electrode of the light-emitting element ED may be a single electrode individually arranged in each of the pixels PX, and the second electrode of the light-emitting element ED may be a common electrode shared by multiple pixels PX. The light-emitting element ED may emit light having a brightness that is proportional to the drive current Id supplied from the pixel circuit PC.

[0092] Figure 4 is a schematic cross-sectional view showing a display panel 110 according to an embodiment of the present disclosure. For example, Figure 4 A portion of the display area DA of the display panel 110 is schematically shown. Figure 4As an example of the display panel 110 , a light-emitting display panel including light-emitting elements ED (eg, organic light-emitting diodes) is schematically illustrated.

[0093] like Figure 4 As shown in FIG, the display device 10 may include a substrate SUB, a thin film transistor layer TFTL, an emission material layer EMTL, and an encapsulation layer ENC. The thin film transistor layer TFTL, the emission material layer EMTL, and the encapsulation layer ENC may be sequentially arranged on the substrate SUB in a third direction D3. The thin film transistor layer TFTL may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0094] The substrate SUB may be a rigid substrate or a flexible substrate capable of bending, folding, curling, etc. The substrate SUB may be made of an insulating material such as glass, quartz, and a polymer resin. For example, the substrate SUB may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. In another embodiment, the first substrate SUB may include a metal material.

[0095] The first barrier layer BR1 may be disposed on the substrate SUB. The first barrier layer BR1 may be disposed over the entire surface of the substrate SUB. The first barrier layer BR1 may be a film for protecting the thin film transistors T1 to T8 of the thin film transistor layer TFTL and the emission layer EL of the emission material layer EMTL from moisture penetrating through the moisture-susceptible substrate SUB. The first barrier layer BR1 may be composed of a plurality of inorganic films alternately stacked. For example, the first barrier layer BR1 may be composed of a plurality of layers in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0096] The first conductive layer CDL1 may be disposed on the first barrier layer BR1. The first conductive layer CDL1 may include a first light-blocking layer BML1 and a first capacitor electrode CPE1. The first light-blocking layer BML1 and the first capacitor electrode CPE1 may be formed as a single body. For example, the first conductive layer CDL1 may be formed of a metal material such as chromium (Cr) and molybdenum (Mo), or black ink or black dye. The first conductive layer CDL1 may receive a constant voltage. Therefore, the first conductive layer CDL1 may not be electrically floating, and the electrical characteristics of the transistor on the first conductive layer CDL1 may be stabilized.

[0097] The second barrier layer BR2 may be disposed on the first conductive layer CDL1. For example, the second barrier layer BR2 may be disposed on the first light blocking layer BML1 and the first capacitor electrode CPE1. The second barrier layer BR2 and the first barrier layer BR1 may have the same material and configuration.

[0098] The second conductive layer CDL2 may be disposed on the second barrier layer BR2. The second conductive layer CDL2 may include a second light-blocking layer BML2 and a second capacitor electrode CPE2. The second light-blocking layer BML2 and the second capacitor electrode CPE2 may be formed as a single body. The second light-blocking layer BML2 may be disposed on the second barrier layer BR2 and overlap with the first light-blocking layer BML1 in a plan view. The second capacitor electrode CPE2 may be disposed on the first capacitor electrode CPE1 and overlap with the first capacitor electrode CPE1 in a plan view. The first capacitor C1 may be formed where the first capacitor electrode CPE1 and the second capacitor electrode CPE2 overlap each other in a plan view. The second capacitor C2 may be formed where the first light-blocking layer BML1 and the second light-blocking layer BML2 overlap each other in a plan view.

[0099] The buffer layer BF may be disposed on the second conductive layer CDL2. For example, the buffer layer BF may be disposed on the second light-blocking layer BML2 and the second capacitor electrode CPE2. The buffer layer BF may be a layer for protecting the thin film transistors T1 to T5 of the thin film transistor layer TFTL and the emission layer EL of the emission material layer EMTL from moisture penetrating through the moisture-susceptible substrate SUB. The buffer layer BF may be formed of a plurality of inorganic layers alternately stacked on one another. For example, the buffer layer BF may be composed of a plurality of layers in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked on one another.

[0100] The active layer ACT may be disposed on the buffer layer BF. For example, the active layer ACT may be disposed on the buffer layer BF and overlap the second light-blocking layer BML2 in a plan view. The active layer ACT may be made of low-temperature polycrystalline silicon (LTPS). In another embodiment, the active layer ACT may be an oxide-based active layer ACT. For example, the active layer ACT may be an oxide semiconductor such as indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0101] The gate insulator GI may be disposed on each of the active layer ACT and the buffer layer BF. For example, the gate insulator GI may be disposed on the channel region CH and overlap with the channel region CH of the active layer ACT in a plan view. The gate insulator GI may be disposed on the buffer layer BF and overlap with the second capacitor electrode CPE2 of the second conductive layer CDL2 in a plan view. The gate insulator GI may include at least one of tetraethoxysilane (tetraethyl orthosilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the gate insulator GI may have a double-layer structure in which a silicon nitride film having a thickness of approximately 40 nm and a tetraethoxysilane layer having a thickness of approximately 80 nm are stacked on top of each other.

[0102] The third conductive layer CDL3 may be arranged on the gate insulator GI. The third conductive layer CDL3 may include a gate electrode GE and a first capacitor connection electrode CCE1. The gate electrode GE and the first capacitor connection electrode CCE1 may be formed as a single body. The gate electrode GE may be arranged on the gate insulator GI and overlap the channel region CH in a plan view, and the first capacitor connection electrode CCE1 may be arranged on the gate insulator GI arranged on the buffer layer BF. The first capacitor connection electrode CCE1 may be connected to the first capacitor electrode CPE1 via a first contact hole CT1 that penetrates the gate insulator GI, the buffer layer BF, and the second barrier layer BR2.

[0103] The interlayer dielectric layer ILD may be disposed on the third conductive layer CDL3. The interlayer dielectric layer ILD may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The interlayer dielectric layer ILD may include a plurality of inorganic films.

[0104] A source connection electrode SCE, a drain connection electrode DCE, a gate connection electrode GCE, and a second capacitor connection electrode CCE2 may be arranged on the interlayer dielectric layer ILD. One side of the source connection electrode SCE may be connected to the second light-blocking layer BML2 via a second contact hole CT2 extending through the interlayer dielectric layer ILD and the buffer layer BF. The other side of the source connection electrode SCE may be connected to the source electrode SE of the active layer ACT via a third contact hole CT3 extending through the interlayer dielectric layer ILD. The drain connection electrode DCE may be connected to the drain electrode DE of the active layer ACT via a fourth contact hole CT4 extending through the interlayer dielectric layer ILD. The drain connection electrode DCE may be connected to the first capacitor connection electrode CCE1 via a fifth contact hole CT5 extending through the interlayer dielectric layer ILD. The second capacitor connection electrode CCE2 may be connected to the second capacitor electrode CPE2 via a sixth contact hole CT6 extending through the interlayer dielectric layer ILD and the buffer layer BF.

[0105] The first planarization layer VA1 may be disposed on the source connection electrode SCE, the drain connection electrode DCE, the gate connection electrode GCE, and the second capacitor connection electrode CCE2. The first planarization layer VIA1 may include an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or a combination thereof.

[0106] The pixel connection electrode PCE may be disposed on the first planarization layer VA1. One side of the pixel connection electrode PCE may be connected to the source connection electrode SCE via a seventh contact hole CT7 extending through the first planarization layer VA1. The other side of the pixel connection electrode PCE may be connected to the second capacitor connection electrode CCE2 via an eighth contact hole CT8 extending through the first planarization layer VA1.

[0107] The second planarization layer VA2 may be disposed on the pixel connection electrode PCE. The second planarization layer VA2 and the first planarization layer VA1 may include the same material and structure.

[0108] The emission material layer EMTL may be disposed on the second planarization layer VA2. The emission material layer EMTL may include a pixel defining layer PDL and a light emitting element ED stacked in a third direction D3. The light emitting element ED may include a pixel electrode PE, an emission layer EL, and a common electrode CM.

[0109] The pixel electrode PE of the light emitting element ED may be disposed on the second planarization layer VA2 , and may be connected to the pixel connection electrode PCE through a ninth contact hole CT9 penetrating the second planarization layer VA2 .

[0110] In the emission area EA, the pixel electrode PE, the emission layer EL, and the common electrode CM may be stacked one on top of the other, and holes from the pixel electrode PE and electrons from the common electrode CM may be combined with each other in the emission layer EL to emit light. The pixel electrode PE may be an anode electrode of the light-emitting element ED, and the common electrode CM may be a cathode electrode of the light-emitting element ED.

[0111] In a top emission structure in which light is emitted from the emission layer EL toward the common electrode CM, the pixel electrode PE may have a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0112] The pixel defining layer PDL may define the emission area EA of the pixel. To this end, the pixel defining layer PDL may be formed on the second passivation film PAS2 and expose a portion of the pixel electrode PE. The pixel defining layer PDL may cover an edge of the pixel electrode PE.

[0113] The pixel defining layer PDL may be formed of an organic layer including acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or a combination thereof.

[0114] The spacer SPC may be arranged on the pixel defining layer PDL. The spacer SPC may support a mask during the process of manufacturing the emission layer EL. The spacer SPC may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or a combination thereof. According to an embodiment of the present disclosure, the spacer SPC and the pixel defining layer PDL may be integrated with each other. In other words, the spacer SPC and the pixel defining layer PDL may be made of the same material.

[0115] The emission layer EL may be arranged on the pixel electrode PE. The emission layer EL may include an organic material to emit light of a single color. For example, the emission layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a light-emitting material and may be formed using a phosphor or fluorescent material.

[0116] For example, the organic material layer of the emission layer EL that emits light of a first color (e.g., blue) may be, but is not limited to, a phosphor including a host material (including CBP or mCP) and a dopant material (including (4,6-F2ppy)2Irpic or L2BD111).

[0117] The organic material layer of the emission layer EL that emits light of the second color (e.g., green) may be a phosphor including a host material (including CBP or mCP) and a dopant material (including ir(ppy)3 (fac tris(2-phenylpyridine)iridium). In another embodiment, the organic material layer of the emission layer EL that emits light of the second color may be, but is not limited to, a fluorescent material including Alq3 (tris(8-hydroxyquinoline)aluminum).

[0118] The organic material layer of the emission layer EL that emits light of a third color (e.g., red) may be a phosphor including a host material (including carbazole biphenyl (CBP) or mCP (1,3-bis(carbazol-9-yl))) and a dopant (including at least one of PIQIr(acac) (bis(1-phenylisoquinolinol) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinolinol) iridium acetylacetonate), PQIr(tris(1-phenylquinolinol)iridium), and PtOEP (platinum octaethylporphyrin). In another embodiment, the organic material layer of the emission layer EL that emits light of a third color may be, but is not limited to, a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene.

[0119] The common electrode CM may be disposed on the emission layer EL. The common electrode CM may be disposed on the emission layer EL and cover the emission layer EL. The common electrode CM may be a common layer disposed across a plurality of emission layers EL. A capping layer may be formed on the common electrode CM.

[0120] In a top-emission structure, the common electrode CM may be formed of a transparent conductive material (TCP) such as ITO and IZO that transmits light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is formed of a semi-transmissive metal material, light extraction efficiency can be increased by using a microcavity.

[0121] The encapsulation layer ENC may be formed on the emission material layer EMTL. The encapsulation layer ENC may include one or more inorganic films TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the emission material layer EMTL. The encapsulation layer ENC may include at least one organic film to protect the emission material layer EMTL from particles such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0122] A first inorganic encapsulating film TFE1 may be disposed on the common electrode CM, an organic encapsulating film TFE2 may be disposed on the first inorganic encapsulating film TFE1, and a second inorganic encapsulating film TFE3 may be disposed on the organic encapsulating film TFE2. The first inorganic encapsulating film TFE1 and the second inorganic encapsulating film TFE3 may be composed of a plurality of layers in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The organic encapsulating film TFE2 may be an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0123] Figure 5 is based on Figure 4 An enlarged view of portion A of a display device of the embodiment.

[0124] like Figure 5 As shown in FIG, the first conductive layer CDL1 may include a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3. For example, the first light blocking layer BML1 of the first conductive layer CDL1 may include the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 sequentially stacked on the first barrier layer BR1 in the third direction D3.

[0125] The first metal layer ML1 may be disposed on the first barrier layer BR1. For example, the first metal layer ML1 may be disposed between the first barrier layer BR1 and the second metal layer ML2. The first metal layer ML1 may be made of a material including titanium (Ti).

[0126] The second metal layer ML2 may be disposed on the first metal layer ML1. For example, the second metal layer ML2 may be disposed between the first metal layer ML1 and the third metal layer ML3. The thickness of the second metal layer ML2 may be greater than the thickness of the first metal layer ML1 (or the third metal layer ML3). The thickness may be in the third direction D3. For example, the second metal layer ML2 may be made of a material including aluminum (Al).

[0127] The third metal layer ML3 may be disposed on the second metal layer ML2. For example, the third metal layer ML3 may be disposed between the second metal layer ML2 and the second barrier layer BR2. The thickness of the third metal layer ML3 may be equal to the thickness of the first metal layer ML1 described above. The third metal layer ML3 and the first metal layer ML1 may be made of the same material. For example, the third metal layer ML3 may be made of a material containing titanium (Ti).

[0128] The barrier film HBL may be disposed on the side surface Ss of the second metal layer ML2. For example, the barrier film HBL may be disposed on the side surface Ss of the second metal layer ML2, wherein surfaces of the second metal layer ML2 facing each other in the third direction D3 (or the thickness direction of the second metal layer ML2) may be respectively defined as the lower surface Sb and the upper surface Su of the second metal layer ML2, and the surface between the lower surface Sb and the upper surface Su may be defined as the side surface Ss. The lower surface Sb of the second metal layer ML2 may be disposed closer to the substrate SUB than the upper surface Su. The area of ​​the lower surface Sb of the second metal layer ML2 may be greater than the area of ​​the upper surface Su. The above-mentioned first metal layer ML1 may be disposed on the lower surface Sb of the second metal layer ML2, and the third metal layer ML3 may be disposed on the upper surface Su of the second metal layer ML2. The first metal layer ML1 may be in contact with the lower surface Sb of the second metal layer ML2, and the third metal layer ML3 may be in contact with the upper surface Su of the second metal layer ML2. In a cross-sectional view, the second metal layer ML2 may have a diagonal shape, and a side surface Ss of the second metal layer ML2 may be inclined at an angle with respect to a lower surface Sb of the second metal layer ML2 .

[0129] According to an embodiment of the present disclosure, the barrier film HBL may be disposed along the side surface of the second metal layer ML2 .

[0130] According to an embodiment of the present disclosure, the barrier film HBL may be in contact with the side surface of the second metal layer ML2 .

[0131] According to an embodiment of the present disclosure, the barrier film HBL may have a closed curve shape surrounding the second metal layer ML2 in a plan view. For example, the barrier film HBL may have a ring shape surrounding the second metal layer ML2.

[0132] According to an embodiment of the present disclosure, the barrier film HBL may be disposed between the first metal layer ML1 and the third metal layer ML3. For example, the barrier film HBL may surround the second metal layer ML2 between the first metal layer ML1 and the third metal layer ML3.

[0133] According to an embodiment of the present disclosure, the first metal layer ML1 may have an area larger than the lower surface Sb of the second metal layer ML2 in a plan view. The edge (e.g., tip) of the first metal layer ML1 may extend above the edge of the second metal layer ML2 and may not overlap with the second metal layer ML2 in a plan view. For example, the edge of the first metal layer ML1 may surround the edge of the lower surface Sb of the second metal layer ML2 in a plan view.

[0134] According to an embodiment of the present disclosure, the third metal layer ML3 may have an area larger than the upper surface Su of the second metal layer ML2 in a plan view. The edge (e.g., tip) of the third metal layer ML3 may extend above the edge of the second metal layer ML2 and may not overlap with the second metal layer ML2 in a plan view. For example, the edge of the third metal layer ML3 may surround the edge of the upper surface Su of the second metal layer ML2 in a plan view.

[0135] According to an embodiment of the present disclosure, the barrier film HBL may be disposed between an edge (e.g., a tip) of the first metal layer ML1 and an edge (e.g., a tip) of the third metal layer ML3. For example, the barrier film HBL may surround the second metal layer ML2 at the edge of the first metal layer ML1 and the edge of the third metal layer ML3.

[0136] According to an embodiment of the present disclosure, the barrier film HBL may include an insulating film. For example, the barrier film HBL may include at least one of AlO and Al 2 O 3 .

[0137] According to an embodiment of the present disclosure, a barrier film HBL may be formed on the side surface Ss of the second metal layer ML2 by natural oxidation. For example, after forming the first conductive layer CDL1, the first conductive layer CDL1 may be exposed to (or left in) air for a long time, so that an oxide film may be formed on the exposed side surface Ss of the second metal layer ML2. The oxide film may serve as the barrier film HBL.

[0138] According to an embodiment of the present disclosure, the barrier film HBL may be formed by anodization. For example, the barrier film HBL may be formed by forming the first conductive layer CDL1 and oxidizing the exposed side surface Ss of the second metal layer ML2 by anodization.

[0139] According to an embodiment of the present disclosure, the barrier film HBL may be formed by O2 ashing. For example, the barrier film HBL may be formed by forming the first conductive layer CDL1 and oxidizing the exposed side surface Ss of the second metal layer ML2 by O2 ashing.

[0140] According to an embodiment of the present disclosure, the barrier film HBL may be formed by steam drying. For example, by forming the first conductive layer CDL1 and supplying moisture (e.g., H2O) to the first conductive layer CDL1 by steam drying, the barrier film HBL may be formed on the exposed side surface Ss of the second metal layer ML2.

[0141] According to the embodiments of the present disclosure, Figure 5As shown in , the second metal layer ML2 of the first conductive layer CDL1 can be surrounded by the first metal layer ML1, the third metal layer ML3, and the barrier film HBL. In other words, the second metal layer ML2 can be arranged in a defined area (hereinafter referred to as a first shielding area) surrounded by the first metal layer ML1, the third metal layer ML3, and the barrier film HBL. Therefore, the second metal layer ML2 in the first shielding area can be isolated from the outside of the first shielding area by the first metal layer ML1, the third metal layer ML3, and the barrier film HBL.

[0142] The second conductive layer CDL2 and the first conductive layer CDL1 may have the same structure. For example, the second light-blocking layer BML2 of the second conductive layer CDL2 may include a first metal layer ML1′, a second metal layer ML2′, and a third metal layer ML3′. The first metal layer ML1′, the second metal layer ML2′, and the third metal layer ML3′ of the second conductive layer CDL2 may be the same as the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 of the first conductive layer CDL1, respectively; therefore, redundant description will be omitted.

[0143] The barrier film HBL′ surrounding the side surface of the second metal layer ML2 ′ of the second conductive layer CDL2 may be the same as the barrier film HBL surrounding the side surface Ss of the second metal layer ML2 of the first conductive layer CDL1 , and thus, redundant description will be omitted.

[0144] The second metal layer ML2′ of the second conductive layer CDL2 may be disposed in a defined region (hereinafter referred to as a second shielding region) surrounded by the first metal layer ML1′, the third metal layer ML3′, and the barrier film HBL′ of the second conductive layer CDL2. Therefore, the second metal layer ML2′ in the second shielding region may be isolated from the outside of the second shielding region by the first metal layer ML1′, the third metal layer ML3′, and the barrier film HBL′.

[0145] As described above, since the second metal layer ML2 in the first shielding region and the second metal layer ML2' in the second shielding region are shielded from the outside, even if the first conductive layer CDL1 and the second conductive layer CDL2 are arranged adjacent to each other and overlap each other in the third direction D3, the hydrogen path between the second metal layer ML2 in the first shielding region and the second metal layer ML2' in the second shielding region can be blocked. Therefore, even if a hydrogen path is formed due to damage in the insulating film (e.g., the second barrier layer BR2) between the first conductive layer CDL1 and the second conductive layer CDL2 (e.g., a seam, a crack, or a pinhole at the region B in the second barrier layer BR2), the movement of hydrogen from the second metal layer ML2 of the first conductive layer CDL1 to the second metal layer ML2' of the second conductive layer CDL2 (or from the second metal layer ML2' of the second conductive layer CDL2 to the second metal layer ML2 of the first conductive layer CDL1) can be blocked.

[0146] According to an embodiment of the present disclosure, a hydrogen path between the adjacent conductive layers CDL1 and CDL2 may be blocked, so that the adjacent conductive layers CDL1 and CDL2 can be prevented from being connected to each other due to, for example, damage to the insulating film BR1 .

[0147] Figure 6 is based on Figure 4 An enlarged view of portion A of a display device of the embodiment.

[0148] Figure 6 The display device can be similar to the above-described one in terms of the position of the barrier film HBL and the structure of the conductive layer. Figure 5 The display devices are different. The description will focus on the differences.

[0149] like Figure 6 As shown in FIG, the first conductive layer CDL1 may include a first metal layer ML1 and a second metal layer ML2. For example, the first light blocking layer BML1 of the first conductive layer CDL1 may include a first metal layer ML1 and a second metal layer ML2 sequentially stacked on the first barrier layer BR1 in the third direction D3.

[0150] Figure 6 The barrier film HBL may be disposed on the side surface Ss and the upper surface Su of the second metal layer ML2. For example, the barrier film HBL may surround the side surface Ss of the second metal layer ML2 and cover the upper surface Su of the second metal layer ML2 in a plan view. The barrier film HBL may be in contact with the side surface Ss and the upper surface Su of the second metal layer ML2.

[0151] According to an embodiment of the present disclosure, the barrier film HBL may be disposed on an edge of the first metal layer ML1. For example, the barrier film HBL may surround the side surface Ss of the second metal layer ML2 on the edge of the first metal layer ML1.

[0152] In this way, Figure 6 The barrier film HBL can be Figure 5 The barrier film HBL surrounds the exposed side surface Ss of the second metal layer ML2 and may further cover the exposed upper surface Su of the second metal layer ML2.

[0153] According to the embodiments of the present disclosure, Figure 6 As shown in FIG, the second metal layer ML2 of the first conductive layer CDL1 may be surrounded by the first metal layer ML1 and the barrier film HBL. In other words, the second metal layer ML2 may be arranged in a defined area (hereinafter referred to as a third shielding area) surrounded by the first metal layer ML1 and the barrier film HBL. Therefore, the second metal layer ML2 in the third shielding area may be isolated from the outside of the third shielding area by the first metal layer ML1 and the barrier film HBL.

[0154] Figure 6 The second conductive layer CDL2 and the first conductive layer CDL1 may have the same structure. For example, the second light-blocking layer BML2 of the second conductive layer CDL2 may include a first metal layer ML1′ and a second metal layer ML2′. The first metal layer ML1′ and the second metal layer ML2′ of the second conductive layer CDL2 may be the same as the first metal layer ML1 and the second metal layer ML2 of the first conductive layer CDL1, respectively; therefore, redundant descriptions will be omitted.

[0155] The barrier film HBL′ surrounding the side surface of the second metal layer ML2 of the second conductive layer CDL2 may be the same as the barrier film HBL surrounding the side surface Ss of the second metal layer ML2 of the first conductive layer CDL1 , and thus, redundant description will be omitted.

[0156] The second metal layer ML2′ of the second conductive layer CDL2 may be disposed in a defined region (hereinafter referred to as a fourth shielding region) surrounded by the first metal layer ML1′ and the barrier film HBL′ of the second conductive layer CDL2′. Therefore, the second metal layer ML2′ in the fourth shielding region may be isolated from the outside of the fourth shielding region by the first metal layer ML1′ and the barrier film HBL′.

[0157] As described above, since the second metal layer ML2 in the third shielding region and the second metal layer ML2' in the fourth shielding region are shielded from the outside, even if the first conductive layer CDL1 and the second conductive layer CDL2 are arranged adjacent to each other and overlap each other in the third direction D3, the hydrogen path between the second metal layer ML2 in the third shielding region and the second metal layer ML2' in the fourth shielding region can be blocked. Therefore, even if a hydrogen path is formed due to damage in the insulating film (e.g., the second barrier layer BR2) between the first conductive layer CDL1 and the second conductive layer CDL2 (e.g., a seam, a crack, or a pinhole at the region B in the second barrier layer BR2), the movement of hydrogen from the second metal layer ML2 of the first conductive layer CDL1 to the second metal layer ML2' of the second conductive layer CDL2 (or from the second metal layer ML2' of the second conductive layer CDL2 to the second metal layer ML2 of the first conductive layer CDL1) can be blocked.

[0158] According to an embodiment of the present disclosure, a hydrogen path between the adjacent conductive layers CDL1 and CDL2 may be blocked, so that the adjacent conductive layers CDL1 and CDL2 can be prevented from being connected to each other due to, for example, damage to the insulating film BR2 .

[0159] Figure 7 is based on Figure 4 An enlarged view of portion A of a display device of the embodiment.

[0160] Figure 7 The display device can be similar to the above-described one in terms of the structure of the conductive layer. Figure 5 The display devices are different. The description will focus on the differences.

[0161] like Figure 7 As shown in FIG, the first conductive layer CDL1 may include a second metal layer ML2 and a third metal layer ML3. For example, the first light blocking layer BML1 of the first conductive layer CDL1 may include a second metal layer ML2 and a third metal layer ML3 sequentially stacked on the first barrier layer BR1 in the third direction D3.

[0162] Figure 7 The barrier film HBL may be disposed on the side surface Ss of the second metal layer ML2. Figure 7 The barrier film HBL can be used with Figure 5 The above-mentioned barrier film HBL is substantially the same, and therefore, redundant description will be omitted. It should be noted that since Figure 7 The first conductive layer CDL1 does not include the first metal layer ML1, for example, Figure 7 The barrier film HBL may surround the second metal layer ML2 at edges of the first barrier layer BR1 and the third metal layer ML3.

[0163] According to the embodiments of the present disclosure, Figure 7 As shown in FIG, the second metal layer ML2 of the first conductive layer CDL1 may be surrounded by the first barrier layer BR1, the third metal layer ML3, and the barrier film HBL. In other words, the second metal layer ML2 may be arranged in a defined area (hereinafter referred to as a fifth shielding area) surrounded by the first barrier layer BR1, the third metal layer ML3, and the barrier film HBL. Therefore, the second metal layer ML2 in the fifth shielding area may be isolated from the outside of the fifth shielding area by the first barrier layer BR1, the third metal layer ML3, and the barrier film HBL.

[0164] Figure 7 The second conductive layer CDL2 and the first conductive layer CDL1 may have the same structure. For example, the second light-blocking layer BML2 of the second conductive layer CDL2 may include a second metal layer ML2' and a third metal layer ML3'. The second metal layer ML2' and the third metal layer ML3' of the second conductive layer CDL2 may be the same as the second metal layer ML2 and the third metal layer ML3 of the first conductive layer CDL1, respectively; therefore, redundant descriptions will be omitted.

[0165] The barrier film HBL′ surrounding the side surface of the second metal layer ML2′ of the second conductive layer CDL2 is substantially the same as the barrier film HBL′ surrounding the side surface of the second metal layer ML2′ of the second conductive layer CDL2. Figure 7 The barrier film HBL of the side surface Ss of the second metal layer ML2 of the first conductive layer CDL1 is the same, and thus, redundant description will be omitted.

[0166] The second metal layer ML2′ of the second conductive layer CDL2 may be disposed in a defined region (hereinafter referred to as a sixth shielding region) surrounded by the second barrier layer BR2, the third metal layer ML3′, and the barrier film HBL′ of the second conductive layer CDL2. Therefore, the second metal layer ML2′ in the sixth shielding region may be isolated from the outside of the sixth shielding region by the second barrier layer BR2, the third metal layer ML3′, and the barrier film HBL′.

[0167] As described above, since the second metal layer ML2 in the fifth shielding region and the second metal layer ML2' in the sixth shielding region are isolated from the outside, even if the first conductive layer CDL1 and the second conductive layer CDL2 are arranged adjacent to each other and overlap each other in the third direction D3, the hydrogen path between the second metal layer ML2 in the fifth shielding region and the second metal layer ML2' in the sixth shielding region can be blocked. Therefore, even if a hydrogen path is formed due to damage in the insulating film (e.g., the second barrier layer BR2) between the first conductive layer CDL1 and the second conductive layer CDL2 (e.g., a seam, a crack, or a pinhole at the region B in the second barrier layer BR2), the movement of hydrogen from the second metal layer ML2 of the first conductive layer CDL1 to the second metal layer ML2' of the second conductive layer CDL2 (or from the second metal layer ML2' of the second conductive layer CDL2 to the second metal layer ML2 of the first conductive layer CDL1) can be blocked.

[0168] According to an embodiment of the present disclosure, a hydrogen path between the adjacent conductive layers CDL1 and CDL2 may be blocked, so that the adjacent conductive layers CDL1 and CDL2 may be prevented from being connected to each other due to, for example, damage to the insulating film BR1 .

[0169] Figures 8 to 12 is a schematic cross-sectional view for illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0170] like Figure 8 As shown in FIG, a first barrier layer BR1 may be disposed on a substrate, and a first base metal layer BSML1, a second base metal layer BSML2, and a third base metal layer BSML3 may be disposed on the first barrier layer BR1 in this order. For example, the first base metal layer BSML1, the second base metal layer BSML2, and the third base metal layer BSML3 may be sequentially disposed over the entire surface of the substrate. Subsequently, a photoresist pattern PR may be disposed on the third base metal layer BSML3.

[0171] Then, if Figure 9 As shown in FIG, the first base metal layer BSML1, the second base metal layer BSML2, and the third base metal layer BSML3 may be etched using the photoresist pattern PR as a mask to form a first conductive layer CDL1. For example, the first base metal layer BSML1, the second base metal layer BSML2, and the third base metal layer BSML3 may be etched to form a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3.

[0172] Then, if Figure 10 As shown in , the photoresist pattern PR may be removed.

[0173] like Figure 11As shown in FIG, the barrier film HBL may be disposed along the side surface of the second metal layer ML2. For example, the barrier film HBL may be formed by anodization as described above.

[0174] Then, if Figure 12 As shown in FIG, the second barrier layer BR2 may be disposed over the first conductive layer CDL1 and the first barrier layer BR1.

[0175] Subsequently, the second conductive layer CDL2 may be disposed on the second barrier layer BR2. The method of forming the second conductive layer CDL2 may be the same as described above. Figures 8 to 11 The method of forming the first conductive layer CDL1 is the same as that shown in .

[0176] Figure 13 is a schematic cross-sectional view for illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0177] like Figure 13 As shown in FIG, the barrier film HBL may be disposed on the side surface of the second metal layer ML2 without removing the photoresist pattern PR. Figure 8 and Figure 9 After the process shown in Figure 13 technology rather than Figure 10 Subsequently, the photoresist pattern PR may be removed with the barrier film HBL disposed therebetween.

[0178] For example, the reference above Figures 8 to 13 The method of manufacturing the display device described above may be Figure 5 A method for manufacturing a display device.

[0179] Figures 14 to 18 is a schematic cross-sectional view for illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0180] like Figure 14 As shown in FIG, a first barrier layer BR1 may be disposed on a substrate, and a first base metal layer BSML1 and a second base metal layer BSML2 may be disposed on the first barrier layer BR1 in this order. For example, the first base metal layer BSML1 and the second base metal layer BSML2 may be sequentially disposed on the entire surface of the substrate. Subsequently, a photoresist pattern PR may be disposed on the second base metal layer BSML2.

[0181] Then, if Figure 15As shown in FIG, the first and second base metal layers BSML1 and BSML2 may be etched using the photoresist pattern PR as a mask to form a first conductive layer CDL1. For example, the first and second base metal layers BSML1 and BSML2 may be etched to form first and second metal layers ML1 and ML2.

[0182] Then, if Figure 16 As shown in , the photoresist pattern PR may be removed.

[0183] like Figure 17 As shown in FIG, the barrier film HBL may be disposed along the upper surface and the side surface of the second metal layer ML2. For example, the barrier film HBL may be formed by the above-described anodization.

[0184] Then, if Figure 18 As shown in FIG, the second barrier layer BR2 may be disposed over the barrier film HBL and the first barrier layer BR1.

[0185] Subsequently, the second conductive layer CDL2 may be disposed on the second barrier layer BR2. The method of forming the second conductive layer CDL2 may be the same as described above. Figures 14 to 17 The method of forming the first conductive layer CDL1 is the same as that shown in .

[0186] For example, the reference above Figures 14 to 17 The method of manufacturing the display device described above may be Figure 6 A method for manufacturing a display device.

[0187] manufacture Figure 7 The display device method and the above reference Figures 8 to 13 Description of the manufacturing Figure 5 The method of manufacturing a display device is substantially the same except that the first base metal layer BSML1 is removed, and thus, redundant description will be omitted.

[0188] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0189] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are intended to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and should be interpreted as all technical spirits within the scope of equivalents are included in the scope of this disclosure.

Claims

1. A display device, characterized in that: include: a first conductive layer disposed on the substrate and comprising at least two metal layers; a first insulating film on the first conductive layer; a transistor on the first insulating film; a pixel electrode on the transistor; an emission layer on the pixel electrode; a common electrode on the emitting layer; as well as A first barrier film is disposed on a side surface of one of the at least two metal layers of the first conductive layer.

2. The display device according to claim 1, wherein The at least two metal layers include: a first metal layer on the substrate; a second metal layer on the first metal layer; and A third metal layer is on the second metal layer.

3. The display device according to claim 2, wherein: The first barrier film is disposed on a side surface of the second metal layer.

4. The display device according to claim 3, wherein: The first barrier film surrounds the side surface of the second metal layer in a plan view.

5. The display device according to claim 3, wherein The first barrier film is disposed on the side surface of the second metal layer between an edge of the first metal layer and an edge of the third metal layer.

6. The display device according to claim 3, wherein: The second metal layer is surrounded by the first metal layer, the third metal layer, and the first barrier film.

7. The display device according to claim 1, wherein The at least two metal layers include: a first metal layer on the substrate; and A second metal layer is on the first metal layer, wherein the first barrier film is disposed on a side surface of the second metal layer.

8. The display device according to claim 1, wherein The at least two metal layers include: a first metal layer on the substrate; and A second metal layer is on the first metal layer.

9. The display device according to claim 8, wherein The first barrier film is disposed on a side surface of the first metal layer.

10. The display device according to claim 1, wherein Further including: a second conductive layer on the first insulating film; as well as The second barrier film, wherein the second conductive layer overlaps with the first conductive layer in a plan view, wherein the second conductive layer comprises at least two metal layers, and The second barrier film is arranged on a side surface of one of the at least two metal layers of the second conductive layer.

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