Display device

Abstract

The utility model relates to a display device. The display device includes: a substrate; an active pattern including a first region, a second region, a first channel region, and a second channel region; a first conductive layer; a second conductive layer; a first electrode pattern including a first barrier pattern protruding toward the second channel region from a portion overlapping the first region; a second electrode pattern including a second barrier pattern protruding toward the first channel region from a portion overlapping the first electrode pattern and overlapping the first channel region; and a first initialization voltage line including a third blocking pattern overlapping the second channel region.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device including an oxide semiconductor. Background Art

[0002] Display devices display images to provide visual information to users. Recently, there has been a growing demand for technologies that reduce the power consumption of display devices. Consequently, research is underway into low-frequency driving methods for driving display devices at relatively low frequencies.

[0003] In the case of the low-frequency driving method, leakage current may be generated due to light from the outside, and therefore, there is a problem that a flicker phenomenon is recognized by a user. Utility Model Content

[0004] Embodiments provide a display device having improved low-frequency characteristics.

[0005] According to an embodiment, a display device may include: a substrate; an active pattern disposed on the substrate and including a first region, a first channel region disposed adjacent to the first region in a first direction, a second region spaced apart from the first region in a second direction intersecting the first direction, and a second channel region disposed between the first region and the second region; a first conductive layer disposed on the active pattern and including a first gate voltage line overlapping the first channel region and a second gate voltage line overlapping the second channel region; a second conductive layer disposed on the first conductive layer and including a bias voltage line overlapping the second region and a first stabilization electrode overlapping a portion of the first region; a first electrode pattern disposed on the second conductive layer and including a first barrier pattern protruding from a portion overlapping the first region toward the second channel region; a second electrode pattern disposed on the first electrode pattern and including a second barrier pattern protruding from a portion overlapping the first electrode pattern toward the first channel region and overlapping the first channel region; and a first initialization voltage line disposed on the first electrode pattern, including a third barrier pattern overlapping the second channel region and extending along the first direction.

[0006] In an implementation, the first barrier pattern may overlap a portion of the first stabilization electrode.

[0007] In an embodiment, the first barrier pattern may be adjacent to the first stabilizing electrode in a plan view.

[0008] In an implementation, the third barrier pattern may overlap a portion of the first stabilization electrode.

[0009] In an embodiment, the active pattern may further include a third region disposed adjacent to the first channel region in a first direction, a third channel region disposed adjacent to the third region in a direction opposite to the second direction, and a fourth channel region disposed adjacent to the second region in a direction opposite to the first direction.

[0010] In an implementation, the third barrier pattern may overlap at least a portion of the fourth channel region.

[0011] In an embodiment, a portion of the first gate voltage line may overlap with the third channel region, and a portion of the second gate voltage line may overlap with the fourth channel region.

[0012] In an embodiment, the first gate voltage line may include a first gate electrode respectively overlapping the first channel region and the third channel region, and the first channel region, the third channel region, and the first gate electrode may form a compensation transistor.

[0013] In an embodiment, the second gate voltage line may include a second gate electrode overlapping the second channel region and the fourth channel region, and the second channel region, the fourth channel region, and the second gate electrode may form an initialization transistor.

[0014] In an implementation, the first stabilization electrode may overlap the third region of the active pattern to form a first stabilization capacitor.

[0015] In an embodiment, the bias voltage line may overlap the second region of the active pattern to form a second stabilizing capacitor.

[0016] In an embodiment, the display device may further include: a second initialization voltage line, which is set on the same layer as the first electrode pattern, overlaps with each of a portion of the first channel region and a portion of the second barrier pattern, and extends along the second direction; and a power voltage line, which is set on the same layer as the first initialization voltage line and is formed integrally with the second electrode pattern.

[0017] In an embodiment, the display device may further include: a light-emitting element, which is arranged on the first initialization voltage line and the power voltage line and includes a pixel electrode, a light-emitting layer arranged on the pixel electrode, and a common electrode arranged on the light-emitting layer; and a pixel defining layer, which is arranged on the pixel electrode and includes a light-blocking material.

[0018] According to an embodiment, a display device may include: a light emitting element; a driving transistor configured to provide a driving current to the light emitting element; a compensation transistor including a first sub-transistor and a second sub-transistor, the first sub-transistor including an output terminal electrically connected to a gate electrode of the driving transistor, the second sub-transistor including an output terminal electrically connected to an input terminal of the first sub-transistor and an input terminal electrically connected to the output terminal of the driving transistor; an initialization transistor including a third sub-transistor and a fourth sub-transistor, the third sub-transistor including an output terminal electrically connected to the gate electrode of the driving transistor, the fourth sub-transistor including an output terminal electrically connected to the input terminal of the third sub-transistor and an input terminal electrically connected to an initialization voltage line; a first barrier pattern disposed on the gate electrode of the driving transistor and disposed between a portion of an active pattern intersecting with the output terminals of the first sub-transistor and the third sub-transistor and the third sub-transistor; a second barrier pattern disposed on the first barrier pattern and overlapping with at least a portion of the first sub-transistor; and a third barrier pattern disposed on the first barrier pattern and overlapping with at least a portion of the third sub-transistor and the fourth sub-transistor.

[0019] In an embodiment, the display device may further include a first electrode pattern electrically connecting the gate electrode of the driving transistor with each of the output terminal of the first sub-transistor and the output terminal of the third sub-transistor.

[0020] In an implementation, the first barrier pattern may be integrally formed with the first electrode pattern.

[0021] In an embodiment, the second barrier pattern may be integrally formed with the second electrode pattern and the power voltage line, the second electrode pattern overlapping a portion of the first barrier pattern, the power voltage line extending from the second electrode pattern, and the third barrier pattern is integrally formed with the initialization voltage line, which is disposed on the same layer as the power voltage line.

[0022] In an embodiment, the display device may further include: a first stabilization capacitor disposed on each of the first sub-transistor and the second sub-transistor and located between the first sub-transistor and the second sub-transistor; and a second stabilization capacitor disposed on each of the third sub-transistor and the fourth sub-transistor and located between the third sub-transistor and the fourth sub-transistor.

[0023] In an embodiment, the first stabilization capacitor includes a first stabilization electrode overlapping a portion of the active pattern disposed between an input terminal of the first sub-transistor and an output terminal of the second sub-transistor, and the second stabilization capacitor includes a second stabilization electrode overlapping a portion of the active pattern disposed between an input terminal of the third sub-transistor and an output terminal of the fourth sub-transistor.

[0024] In an embodiment, each of the first and third barrier patterns overlaps a portion of the first stabilization electrode.

[0025] In a display device according to an embodiment of the present disclosure, the display device may include: an active pattern including first to third regions; first to fourth sub-transistors; a first electrode pattern including a first barrier pattern; a second electrode pattern including a second barrier pattern; and an initialization voltage line including a third barrier pattern. The first barrier pattern may overlap a portion of the first region by protruding from a portion of the first electrode pattern that overlaps with the first region toward the third sub-transistor, and the third barrier pattern may overlap the third sub-transistor. Furthermore, the second barrier pattern may overlap the first sub-transistor.

[0026] Therefore, external light incident on the first sub-transistor, a portion of the first region adjacent to the first sub-transistor, and the third sub-transistor can be blocked. Therefore, leakage current and flickering caused by external light can be reduced, and the low-frequency characteristics of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 yes Figure 1 An enlarged plan view of area A in FIG.

[0030] Figure 3 is included in Figure 2 Circuit diagram of sub-pixels in multiple pixels.

[0031] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 It shows Figure 1 Layout diagram of the display device in .

[0032] Figure 13 yes Figure 12 An enlarged plan view of area B in FIG.

[0033] Figure 14 、 Figure 15 and Figure 16 Some components are not shown. Figure 13Layout diagram of the display device in .

[0034] Figure 17 It is shown along Figure 13 A sectional view of a section taken along line II'. DETAILED DESCRIPTION

[0035] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0036] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0037] refer to Figure 1 A display device DD according to an embodiment of the present disclosure may include a display panel PN. The display panel PN may include a display area DA and a peripheral area PA. The display panel PN may include a substrate SUB. A component for emitting light may be provided on the substrate SUB.

[0038] The display area DA may be an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. A plurality of pixels PX may be arranged in the display area DA. For example, each of the plurality of pixels PX may include a driving element and a light emitting element.

[0039] The pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other.

[0040] The peripheral area PA may be an area where no image is displayed. In addition, the peripheral area PA may surround at least a portion of the display area DA. For example, the peripheral area PA may completely surround the display area DA.

[0041] A driver for driving the display panel PN may be provided in the peripheral area PA. For example, the driver may be configured to drive the pixels PX. The driver may include a data driver, a gate driver, a light emitting driver, a power supply voltage generator, and a timing controller. The plurality of pixels PX may emit light based on signals received from the driver.

[0042] Figure 2 yes Figure 1 An enlarged plan view of region A in FIG. For example, Figure 2 is used to explain the Figure 1 FIG. 1 is a view of a plurality of sub-pixels SPX1 , SPX2 , SPX3 , and SPX4 in each of the pixels PX.

[0043] refer to Figure 1 and Figure 2 , each of the plurality of pixels PX may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , a third sub-pixel SPX3 , and a fourth sub-pixel SPX4 .

[0044] The first subpixel SPX1 and the third subpixel SPX3 may be arranged along the Nth column C(N). The second subpixel SPX2 and the fourth subpixel SPX4 may be arranged along the N+1th column C(N+1). The N+1th column C(N+1) may be disposed adjacent to the Nth column C(N).

[0045] In addition, the first subpixel SPX1 and the second subpixel SPX2 may be arranged along the Nth row R(N). The third subpixel SPX3 and the fourth subpixel SPX4 may be arranged along the N+1th row R(N+1). The N+1th row R(N+1) may be disposed adjacent to the Nth row R(N).

[0046] In this way, the arrangement of subpixels can be repeated until the preset rows and columns. For example, the first subpixel SPX1 and the third subpixel SPX3 can be arranged along odd columns, and the second subpixel SPX2 and the fourth subpixel SPX4 can be arranged along even columns. In addition, the first subpixel SPX1 and the second subpixel SPX2 can be arranged along odd rows, and the third subpixel SPX3 and the fourth subpixel SPX4 can be arranged along even rows.

[0047] Each of the first subpixel SPX1, the second subpixel SPX2, the third subpixel SPX3, and the fourth subpixel SPX4 can be connected to an initialization voltage line. The initialization voltage line may include a first initialization voltage line VINT and a second initialization voltage line VAINT. Since the first initialization voltage line VINT and the second initialization voltage line VAINT are separated from each other, color deviation can be improved at low brightness.

[0048] The initialization voltage line may have a grid structure in a plan view. The first initialization voltage line VINT may include a horizontal portion VINT_H extending along a first direction DR1 and a vertical portion VINT_V extending along a second direction DR2. The second initialization voltage line VAINT may also include a horizontal portion VAINT_H extending along the first direction DR1 and a vertical portion VAINT_V extending along the second direction DR2.

[0049] The horizontal portions VINT_H of the first initialization voltage line VINT and the horizontal portions VAINT_H of the second initialization voltage line VAINT, which extend parallel to the first direction DR1, may be alternately arranged along the second direction DR2. For example, each of the first subpixel SPX1 and the second subpixel SPX2 may be connected to the first initialization voltage line VINT. Each of the third subpixel SPX3 and the fourth subpixel SPX4 may be connected to the second initialization voltage line VAINT.

[0050] The initialization voltage line can be electrically connected to the subpixel through the first hole Ha and the second hole Hb. For example, the first subpixel SPX1 located in the Nth row R(N) may overlap only with the horizontal portion VINT_H of the first initialization voltage line VINT. The horizontal portion VAINT_H of the second initialization voltage line VAINT may be located in the N+1th row R(N+1). Therefore, the first subpixel SPX1 may not overlap with the horizontal portion VAINT_H of the second initialization voltage line VAINT. At the same time, the third subpixel SPX3 located in the N+1th row R(N+1) may overlap only with the horizontal portion VAINT_H of the second initialization voltage line VAINT. Therefore, the third subpixel SPX3 may not overlap with the horizontal portion VINT_H of the first initialization voltage line VINT. However, when the first hole Ha and the second hole Hb are formed, the third subpixel SPX3 can receive the second initialization voltage through the second initialization voltage line VAINT through the connecting line, and the first subpixel SPX1 can receive the first initialization voltage from the first initialization voltage line VINT.

[0051] The first subpixel SPX1, the second subpixel SPX2, the third subpixel SPX3, and the fourth subpixel SPX4 may have an RGBG pentile pixel arrangement. For example, the first subpixel SPX1 may emit blue light, the third subpixel SPX3 may emit red light, and each of the second subpixel SPX2 and the fourth subpixel SPX4 may emit green light. However, the present disclosure is not limited thereto and may have various arrangements such as an RBGB, RBRG pentile pixel arrangement, or an RGB pixel arrangement.

[0052] exist Figure 2 In FIG. 5 , each of the plurality of pixels PX is shown as having an initialization voltage line, but the present disclosure may not be limited thereto. For example, the initialization voltage line may be shared with pixels adjacent to each of the plurality of pixels PX.

[0053] Figure 3 is included in Figure 2 For example, Figure 3 yes Figure 2 Circuit diagram of the first sub-pixel SPX1 in .

[0054] refer to Figure 1 、 Figure 2 and Figure 3 The first sub-pixel SPX1 may include a light emitting element LED and a pixel circuit PXCa. The pixel circuit PXCa may apply a driving current to the light emitting element LED, and the light emitting element LED may generate light based on the driving current.

[0055] The pixel circuit PXCa may include at least one transistor and at least one capacitor. The pixel circuit PXCa may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a storage capacitor CST.

[0056] An input terminal of the first transistor T1 may be connected to the data voltage line DATA. For example, the first transistor T1 may receive a data voltage from the data voltage line DATA through the input terminal and generate a driving current corresponding to the data voltage.

[0057] The output terminal of the first transistor T1 can be connected to the light-emitting element LED. For example, the first transistor T1 can apply a driving current to the light-emitting element LED through the output terminal. The gate terminal of the first transistor T1 can be connected to a first node N1 connected to the storage capacitor CST. In this specification, the first transistor T1 may be referred to as a driving transistor.

[0058] An input terminal of the second transistor T2 may be connected to the data voltage line DATA, an output terminal of the second transistor T2 may be connected to the input terminal of the first transistor T1, and a gate terminal of the second transistor T2 may be connected to the first gate voltage line GW.

[0059] Therefore, the second transistor T2 may be turned on by the first gate voltage supplied from the first gate voltage line GW. During a period in which the second transistor T2 is turned on, the second transistor T2 may apply the data voltage to the input terminal of the first transistor T1.

[0060] The third transistor T3 may include a first sub-transistor T3-1 and a second sub-transistor T3-2 connected to each other. The input terminal of the first sub-transistor T3-1 may be connected to the output terminal of the second sub-transistor T3-2. The output terminal of the first sub-transistor T3-1 may be connected to the first node N1 connected to the gate terminal of the first transistor T1. The input terminal of the second sub-transistor T3-2 may be connected to the output terminal of the first transistor T1. The output terminal of the second sub-transistor T3-2 may be connected to the input terminal of the first sub-transistor T3-1. The gate terminal of the first sub-transistor T3-1 and the gate terminal of the second sub-transistor T3-2 may each be connected to a first gate voltage line GW.

[0061] Therefore, the third transistor T3 can be turned on by the first gate voltage provided from the first gate voltage line GW. During the period in which the third transistor T3 is turned on, the third transistor T3 can compensate for the threshold voltage of the first transistor T1 by diode-connecting the first transistor T1. In this specification, the third transistor T3 may be referred to as a compensation transistor.

[0062] The fourth transistor T4 may include a third sub-transistor T4-1 and a fourth sub-transistor T4-2 connected to each other. The input terminal of the third sub-transistor T4-1 may be connected to the output terminal of the fourth sub-transistor T4-2. The output terminal of the third sub-transistor T4-1 may be connected to the gate terminal of the first transistor T1. The input terminal of the fourth sub-transistor T4-2 may be connected to the first initialization voltage line VINT. The output terminal of the fourth sub-transistor T4-2 may be connected to the input terminal of the third sub-transistor T4-1. The gate terminal of the third sub-transistor T4-1 and the gate terminal of the fourth sub-transistor T4-2 may each be connected to the second gate voltage line GI.

[0063] Therefore, the fourth transistor T4 can be turned on by the second gate voltage provided from the second gate voltage line GI. During the period in which the fourth transistor T4 is turned on, the fourth transistor T4 can apply the first initialization voltage provided from the first initialization voltage line VINT to the gate electrode of the first transistor T1. In this specification, the fourth transistor T4 can be referred to as an initialization transistor.

[0064] An input terminal of the fifth transistor T5 may be connected to the first power voltage line ELVDD, an output terminal of the fifth transistor T5 may be connected to the input terminal of the first transistor T1, and a gate terminal of the fifth transistor T5 may be connected to the emission control line EM.

[0065] Therefore, the fifth transistor T5 may be turned on by the emission control voltage supplied from the emission control line EM. During a period in which the fifth transistor T5 is turned on, the fifth transistor T5 may apply the first power voltage supplied from the first power voltage line ELVDD to the first transistor T1.

[0066] In an embodiment, the first power voltage provided from the first power voltage line ELVDD and the second power voltage provided from the second power voltage line ELVSS connected to the light emitting element LED may each be a constant voltage. In this case, the first power voltage and the second power voltage may have different voltage levels.

[0067] An input terminal of the sixth transistor T6 may be connected to an output terminal of the first transistor T1 , an output terminal of the sixth transistor T6 may be connected to the light emitting element LED, and a gate terminal of the sixth transistor T6 may be connected to an emission control line EM.

[0068] Therefore, the sixth transistor T6 may be turned on by the emission control signal provided from the emission control line EM. During a period in which the sixth transistor T6 is turned on, the sixth transistor T6 may apply a driving current to the light emitting element LED.

[0069] The input terminal of the seventh transistor T7 may be connected to the second initialization voltage line VAINT, the output terminal of the seventh transistor T7 may be connected to the anode of the light emitting element LED, and the gate terminal of the seventh transistor T7 may be connected to the third gate voltage line GB.

[0070] Therefore, the seventh transistor T7 may be turned on by the third gate voltage supplied from the third gate voltage line GB. During a period in which the seventh transistor T7 is turned on, the seventh transistor T7 may apply the second initialization voltage supplied from the second initialization voltage line VAINT to the light emitting element LED.

[0071] An input terminal of the eighth transistor T8 may be connected to the bias voltage line VBIAS, an output terminal of the eighth transistor T8 may be connected to the input terminal of the first transistor T1, and a gate terminal of the eighth transistor T8 may be connected to the third gate voltage line GB.

[0072] Therefore, the eighth transistor T8 may be turned on by the third gate voltage supplied from the third gate voltage line GB. During a period in which the eighth transistor T8 is turned on, the eighth transistor T8 may apply a bias voltage to the first transistor T1.

[0073] The pixel circuit PXCa may include a storage capacitor CST, a first stabilization capacitor CS1, a second stabilization capacitor CS2, and a diode parasitic capacitor CLED.

[0074] A first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor T1 , and a second terminal of the storage capacitor CST may be connected to the first power voltage line ELVDD.

[0075] The storage capacitor CST may maintain a voltage level of the gate electrode of the first transistor T1 during a deactivation period of the first gate voltage supplied from the first gate voltage line GW.

[0076] A first terminal of the first stabilization capacitor CS1 may be connected to each of an input terminal of the first sub-transistor T3-1 and an output terminal of the second sub-transistor T3-2. A second terminal of the first stabilization capacitor CS1 may be connected to the first power voltage line ELVDD.

[0077] The first stabilizing capacitor CS1 can keep the voltage level at each of the input terminal of the first sub-transistor T3-1 and the output terminal of the second sub-transistor T3-2 relatively constant. Therefore, the leakage current in the third transistor T3 can be reduced, and the low-frequency characteristics of the display device can be improved.

[0078] A first terminal of the second stabilizing capacitor CS2 may be connected to each of the input terminal of the third sub-transistor T4-1 and the output terminal of the fourth sub-transistor T4-2. A second terminal of the second stabilizing capacitor CS2 may be connected to the bias voltage line VBIAS.

[0079] The second stabilizing capacitor CS2 can keep the voltage level at each of the input terminal of the third sub-transistor T4-1 and the output terminal of the fourth sub-transistor T4-2 constant. Therefore, the leakage current in the fourth transistor T4 can be reduced, and the low-frequency characteristics of the display device can be improved.

[0080] One end of the diode parasitic capacitor CLED may be connected to the anode electrode of the light emitting element LED, and the other end of the diode parasitic capacitor CLED may be connected to the cathode electrode of the light emitting element LED.

[0081] However, the circuit structure of the pixel circuit PXCa of the present disclosure may not be limited to Figure 3 Furthermore, each of the second subpixel SPX2 , the third subpixel SPX3 , and the fourth subpixel SPX4 may have a pixel circuit structure substantially the same as that of the first subpixel SPX1 .

[0082] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 It shows Figure 1 Layout diagram of the display device in .

[0083] The display device DD may include pixel circuits of a plurality of sub-pixels arranged adjacent to each other. The plurality of pixel circuits may include substantially the same components. For example, Figures 4 to 12 The first pixel circuit PC1 in the embodiment may be a first sub-pixel (eg, Figure 2The second pixel circuit PC2 may be a part of the first sub-pixel SPX1 in the embodiment of the present invention, and the second pixel circuit PC2 may be a part of the second sub-pixel (eg, Figure 2 A portion of the second sub-pixel SPX2).

[0084] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 is used to explain the first to third barrier patterns (eg, Figure 9 、 Figure 10 、 Figure 11 and Figure 12 Hereinafter, for the convenience of explanation, the focus will be on the first pixel circuit PC1 (eg, Figure 3 The pixel circuit PXCa in FIG.

[0085] Figure 4 1 is a plan view for explaining the active pattern ACT.

[0086] refer to Figure 1 and Figure 4 The display device DD may include an active pattern ACT. The active pattern ACT may be disposed on a substrate SUB.

[0087] The active pattern ACT may include a first active region ACT1 and a second active region ACT2. The active pattern ACT may include the first active region ACT1 having relatively high conductivity and the second active region ACT2 having relatively low conductivity. For example, the first active region ACT1 may be a doped region doped with n-type impurities or p-type impurities. In addition, the second active region ACT2 may be a non-doped region or a region doped at a lower concentration than the first active region ACT1.

[0088] The first active area ACT1 may include a first area AE1, a second area AE2, a third area AE3, a fourth area AE4, a fifth area AE5, a sixth area AE6, a seventh area AE7, an eighth area AE8, a ninth area AE9, a tenth area AE10, an eleventh area AE11, and a twelfth area AE12. In this case, the twelfth area AE12 may include an Nth area AE12(N) included in an Nth pixel circuit in an Nth row and an N1th area AE12(N-1) included in an N-1th pixel circuit in an N-1th row adjacent to the Nth row. The first active area ACT1 may function as an electrode, a signal line, an input terminal of a transistor, an output terminal of a transistor, and / or a terminal of a capacitor.

[0089] The second active region ACT2 may include a first channel region T3-1c, a second channel region T4-1c, a third channel region T3-2c, a fourth channel region T4-2c, a fifth channel region T1c, a sixth channel region T2c, a seventh channel region T5c, an eighth channel region T6c, a ninth channel region T7c, and a tenth channel region T8c. The second active region ACT2 may be connected to the first conductive layer (e.g., Figure 5 The region overlaps with the first conductive layer CL1 in the transistor and may be a region defining a channel region (or active region) of the transistor.

[0090] The first region AE1 may be disposed adjacent to the first channel region T3 - 1c in the first direction DR1. The second region AE2 may be spaced apart from the first region AE1 in a second direction DR2 intersecting the first direction DR1.

[0091] Further references Figure 3 , the output terminal of the first sub-transistor T3-1 may be defined in the first area AE1. The output terminal of the first sub-transistor T3-1 may be positioned in the first area AE1 from the first channel area T3-1c in a direction opposite to the first direction DR1. The output terminal of the third sub-transistor T4-1 may be defined in the first area AE1. The output terminal of the third sub-transistor T4-1 may be positioned in the first area AE1 from the second channel area T4-1c in a direction opposite to the second direction DR2. For example, each of the output terminal of the first sub-transistor T3-1 and the output terminal of the third sub-transistor T4-1 may be positioned in the first area AE1.

[0092] Specifically, the output terminal of the first sub-transistor T3-1 and the output terminal of the third sub-transistor T4-1 may be the first region AE1 through the first contact hole (eg, Figure 9 The first contact hole CNT1 in the conductive layer is electrically connected to the third conductive layer (eg, Figure 9components of the third conductive layer CL3) (e.g., Figure 9 portion of the first bottom electrode pattern BEP1).

[0093] The second channel region T4-1c may be located between the first region AE1 and the second region AE2. For example, the second channel region T4-1c may be disposed adjacent to the first region AE1 in the second direction DR2 and adjacent to the second region AE2 in a direction opposite to the second direction DR2.

[0094] The input terminal of the third sub-transistor T4-1 and the output terminal of the fourth sub-transistor T4-2 may be defined in the second area AE2. The input terminal of the third sub-transistor T4-1 may be positioned in the second direction DR2 from the second channel area T4-1c. Furthermore, the output terminal of the fourth sub-transistor T4-2 may be positioned in the first direction DR1 from the fourth channel area T4-2c. For example, each of the input terminal of the third sub-transistor T4-1 and the output terminal of the fourth sub-transistor T4-2 may be positioned in the second area AE2.

[0095] The third region AE3 may be spaced apart from the first region AE1 in the first direction DR1. The third region AE3 may be disposed adjacent to the first channel region T3-1c in the first direction DR1. The third channel region T3-2c may be disposed adjacent to the third region AE3 in a direction opposite to the second direction DR2.

[0096] The input terminal of the first sub-transistor T3-1 and the output terminal of the second sub-transistor T3-2 may be defined in the third area AE3. The input terminal of the first sub-transistor T3-1 may be positioned in the first direction DR1 from the first channel area T3-1c. Furthermore, the output terminal of the second sub-transistor T3-2 may be positioned in the second direction DR2 from the third channel area T3-2c. For example, the positions of the input terminal of the first sub-transistor T3-1 and the output terminal of the second sub-transistor T3-2 may be the same in the third area AE3.

[0097] The fourth channel region T4-2c may be disposed adjacent to the second region AE2 in a direction opposite to the first direction DR1. The first region AE1, the second region AE2, the third region AE3, the first channel region T3-1c, the second channel region T4-1c, the third channel region T3-2c, and the fourth channel region T4-2c may be disposed therein to block incident light. Figure 3 A region of the external light blocking pattern in each of the third transistor T3 and the fourth transistor T4 is provided.

[0098] An input terminal of the second sub-transistor T3-2 may be defined in the fourth region AE4. The input terminal of the second sub-transistor T3-2 may be located in a direction opposite to the second direction DR2 from the third channel region T3-2c.

[0099] An input terminal of the fourth sub-transistor T4-2 may be defined in the eleventh region AE11. The input terminal of the fourth sub-transistor T4-2 may be located in a direction opposite to the first direction DR1 from the fourth channel region T4-2c.

[0100] Figure 5 is a plan view for explaining the first conductive layer CL1.

[0101] refer to Figure 3 and Figure 5 , the pixel circuit PXCa may include a first conductive layer CL1. The first conductive layer CL1 may include a first gate voltage line GW, a second gate voltage line GI, a first storage electrode CSTE1, an emission control line EM, and a third gate voltage line GB. Each of the first gate voltage line GW, the second gate voltage line GI, the first storage electrode CSTE1, the emission control line EM, and the third gate voltage line GB may be provided in the same layer.

[0102] A first gate voltage may be applied to a first gate voltage line GW. A second gate voltage may be applied to a second gate voltage line GI. A third gate voltage may be applied to a third gate voltage line GB. An emission control voltage may be applied to an emission control line EM.

[0103] Figure 6 is a plan view for explaining the active pattern ACT and the first conductive layer CL1.

[0104] refer to Figure 3 、 Figure 4 、 Figure 5 and Figure 6 , the first conductive layer CL1 may be disposed on the active pattern ACT. Specifically, the first insulating layer (eg, Figure 17 A first insulating layer IL1 (in the active pattern ACT) may be disposed on the active pattern ACT, and a first conductive layer CL1 may be disposed on the first insulating layer.

[0105] The first conductive layer CL1 may overlap the active pattern ACT. A portion of the first conductive layer CL1 overlapping the active pattern ACT may be defined as a gate electrode of the transistor.

[0106] Specifically, a portion of the first gate voltage line GW may overlap with each of the first channel region T3-1c, the third channel region T3-2c, and the sixth channel region T2c. The portions of the first gate voltage line GW overlapping with the first channel region T3-1c, the third channel region T3-2c, and the sixth channel region T2c may be the gate electrode of the first sub-transistor T3-1, the gate electrode of the second sub-transistor T3-2, and the gate electrode of the second transistor T2, respectively.

[0107] A portion of the second gate voltage line GI may overlap with each of the second channel region T4-1c and the fourth channel region T4-2c. The portions of the second gate voltage line GI overlapping with the second channel region T4-1c and the fourth channel region T4-2c may be gate electrodes of the third sub-transistor T4-1 and the fourth sub-transistor T4-2, respectively.

[0108] A portion of the first storage electrode CSTE1 may overlap with the fifth channel region T1c. The portion of the first storage electrode CSTE1 overlapping with the fifth channel region T1c may be referred to as the gate electrode of the first transistor T1. That is, the portion of the first storage electrode CSTE1 overlapping with the fifth channel region T1c may be the gate electrode of the driving transistor.

[0109] The emission control line EM may overlap each of the seventh and eighth channel regions T5c and T6c. Portions of the emission control line EM overlapping the seventh and eighth channel regions T5c and T6c may be gate electrodes of the fifth and sixth transistors T5 and T6, respectively.

[0110] The third gate voltage line GB may overlap each of the ninth and tenth channel regions T7c and T8c. Portions of the third gate voltage line GB overlapping the ninth and tenth channel regions T7c and T8c may be gate electrodes of the seventh and eighth transistors T7 and T8.

[0111] Figure 7 is a plan view for explaining the second conductive layer CL2.

[0112] The second conductive layer CL2 may include a first stabilization electrode CSE1 of the first stabilization capacitor CS1, a bias voltage line VBIAS, and a second storage electrode CSTE2. A bias voltage may be applied to the bias voltage line VBIAS. The bias voltage line VBIAS may include an Nth bias voltage line VBIAS(N) included in the pixel circuits of the Nth row and an N+1th bias voltage line VBIAS(N+1) included in the pixel circuits of the N+1th row.

[0113] Figure 8is a plan view for explaining the active pattern ACT, the first conductive layer CL1, and the second conductive layer CL2.

[0114] refer to Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 , the second conductive layer CL2 may be disposed on the first conductive layer CL1. Specifically, the second insulating layer (eg, Figure 17 The second insulating layer IL2 in the embodiment may be disposed on the first conductive layer CL1, and the second conductive layer CL2 may be disposed on the second insulating layer.

[0115] The first stabilization electrode CSE1 may overlap with the third area AE3 of the active pattern ACT. Specifically, the first stabilization electrode CSE1 may overlap with the third area AE3 of the active pattern ACT, which defines the input terminal of the first sub-transistor T3-1 and the output terminal of the second sub-transistor T3-2. Therefore, the first stabilization electrode CSE1 may constitute the first terminal of the first stabilization capacitor CS1.

[0116] The second storage electrode CSTE2 may overlap with the first storage electrode CSTE1 to form a storage capacitor CST. In this case, the first storage electrode CSTE1 may form a first terminal of the storage capacitor CST. In addition, the second storage electrode CSTE2 may constitute a second terminal of the storage capacitor CST. An opening exposing a portion of the first storage electrode CSTE1 may be defined by the second storage electrode CSTE2.

[0117] The Nth bias voltage line VBIAS(N) may overlap with the second area AE2 of the active pattern ACT. Specifically, the Nth bias voltage line VBIAS(N) may overlap with the second area AE2 of the active pattern ACT, which defines the input terminal of the third sub-transistor T4-1 and the output terminal of the fourth sub-transistor T4-2. Therefore, a second terminal of the second stabilization capacitor CS2 connected to the Nth bias voltage line VBIAS(N) may be defined in the second stabilization electrode CSE2.

[0118] The (N+1)th bias voltage line VBIAS(N+1) may be substantially the same as the (N)th bias voltage line VBIAS(N), except for the pixel circuits in the (N+1)th row.

[0119] Figure 9 is a plan view for explaining the first contact hole CNT1 and the third conductive layer CL3.

[0120] refer to Figure 9The third conductive layer CL3 may include a vertical portion VINT_V of a first initialization voltage line (e.g., first initialization voltage line VINT), a first vertical power voltage line ELVDD_V, a vertical portion VAINT_V of a second initialization voltage line (e.g., second initialization voltage line VAINT), a first bottom electrode pattern BEP1, a second bottom electrode pattern BEP2, a third bottom electrode pattern BEP3, a fourth bottom electrode pattern BEP4, and a fifth bottom electrode pattern BEP5. The first bottom electrode pattern BEP1 may include a first barrier pattern BP1.

[0121] A first initialization voltage may be applied to a vertical portion VINT_V of a first initialization voltage line, a first power voltage may be applied to a first vertical power voltage line ELVDD_V, and a second initialization voltage may be applied to a vertical portion VAINT_V of a second initialization voltage line.

[0122] Each of the first bottom electrode pattern BEP1, the second bottom electrode pattern BEP2, the third bottom electrode pattern BEP3, the fourth bottom electrode pattern BEP4, and the fifth bottom electrode pattern BEP5 may be spaced apart from each other. Each of the first bottom electrode pattern BEP1, the second bottom electrode pattern BEP2, the third bottom electrode pattern BEP3, the fourth bottom electrode pattern BEP4, and the fifth bottom electrode pattern BEP5 may be spaced apart from a signal line extending along the second direction DR2 (e.g., a vertical portion VINT_V of the first initialization voltage line, a first vertical power voltage line ELVDD_V, and a vertical portion VAINT_V of the second initialization voltage line).

[0123] Further references Figure 8 and Figure 9 The first contact hole CNT1 may be a through hole so that the third conductive layer CL3 contacts a component disposed below the third conductive layer CL3 (e.g., the active pattern ACT, the first conductive layer CL1, or the second conductive layer CL2). The third conductive layer CL3 may protrude toward the component disposed below the third conductive layer CL3 through the first contact hole CNT1.

[0124] Figure 10 1 is a plan view for explaining the first conductive layer CL1, the second conductive layer CL2, the first contact hole CNT1 and the third conductive layer CL3. Figure 17 The third insulating layer IL3 in the second conductive layer CL2 may be provided on the second conductive layer CL2, and the third conductive layer CL3 may be provided on the third insulating layer. In addition, a first contact hole CNT1 may be defined, which is formed in a thickness direction (eg, Figure 17The conductive layer CL3 passes through at least one of the first to third insulating layers in a thickness direction (in the thickness direction DR3) and exposes an upper surface of a component disposed under the third conductive layer CL3.

[0125] refer to Figure 3 、 Figure 4 and Figure 10 , the vertical portion VINT_V of the first initialization voltage line may contact the active pattern ACT. For example, the vertical portion VINT_V of the first initialization voltage line may be electrically connected to a portion of the second pixel circuit PC2 through the first contact hole CNT1. Thus, the vertical portion VINT_V of the first initialization voltage line may apply the first initialization voltage to the input terminal of the fourth sub-transistor T4-2.

[0126] The first vertical power voltage line ELVDD_V may contact the second storage electrode CSTE2. For example, the first vertical power voltage line ELVDD_V may be electrically connected to the second storage electrode CSTE2 through the first contact hole CNT1. Thus, the first vertical power voltage line ELVDD_V may apply the first power voltage to the second storage electrode CSTE2.

[0127] The first vertical power voltage line ELVDD_V may contact the first stabilization electrode CSE1. For example, the first vertical power voltage line ELVDD_V may be electrically connected to the first stabilization electrode CSE1 through the first contact hole CNT1. Thus, the first vertical power voltage line ELVDD_V may provide the first power voltage to the first stabilization electrode CSE1.

[0128] The first vertical power voltage line ELVDD_V may contact the seventh area AE7 of the active pattern ACT. For example, the first vertical power voltage line ELVDD_V may be electrically connected to the seventh area AE7 of the active pattern ACT through the first contact hole CNT1. Thus, the first vertical power voltage line ELVDD_V may provide the first power voltage to the input terminal of the fifth transistor T5.

[0129] The vertical portion VAINT_V of the second initialization voltage line may contact the Nth area AE12 (N) of the active pattern ACT. Therefore, the vertical portion VAINT_V of the second initialization voltage line may provide the second initialization voltage to the input terminal of the seventh transistor T7.

[0130] The first bottom electrode pattern BEP1 may contact the first storage electrode CSTE1 and the first area AE1 of the active pattern ACT. For example, the first bottom electrode pattern BEP1 may be electrically connected to the first storage electrode CSTE1 and the first area AE1 of the active pattern ACT through a first contact hole CNT1. Specifically, the first bottom electrode pattern BEP1 may connect the first storage electrode CSTE1, which is the gate electrode of the first transistor T1, and the first area AE1, where the output terminal of the first sub-transistor T3-1 and the output terminal of the third sub-transistor T4-1 are located. Therefore, the gate electrode of the first transistor T1, the output terminal of the first sub-transistor T3-1, and the output terminal of the third sub-transistor T4-1 may be electrically connected to each other in the first area AE1.

[0131] The first bottom electrode pattern BEP1 may include a first barrier pattern BP1 that overlaps a portion of the first stabilization electrode CSE1. The first barrier pattern BP1 may be a portion of the first bottom electrode pattern BEP1 that protrudes in the second direction DR2 from the portion of the first bottom electrode pattern BEP1 that overlaps the first area AE1. Therefore, external light incident on a portion of the first area AE1 may be blocked, thereby reducing leakage current and flickering caused by the external light, and improving low-frequency characteristics of the display device.

[0132] Specifically, the first barrier pattern BP1 may block external light incident on the first area AE1 disposed adjacent to the third sub-transistor T4-1 in a direction opposite to the second direction DR2, and the first stabilization electrode CSE1 is disposed between the first bottom electrode pattern BEP1 and the first area AE1 in a thickness direction. In this specification, the first bottom electrode pattern BEP1 may be referred to as a first electrode pattern.

[0133] The second bottom electrode pattern BEP2 may contact the eighth area AE8 of the active pattern ACT. Specifically, the second bottom electrode pattern BEP2 may be electrically connected to the eighth area AE8 where the output terminals of the sixth and seventh transistors T6 and T7 are disposed through the first contact hole CNT1.

[0134] The third bottom electrode pattern BEP3 may contact the sixth area AE6 of the active pattern ACT. Specifically, the third bottom electrode pattern BEP3 may contact the sixth area AE6, which serves as the input terminal of the second transistor T2, through the first contact hole CNT1. The third bottom electrode pattern BEP3 may be connected to the data voltage line DATA. Therefore, a data voltage applied to the data voltage line DATA can be transmitted to the input terminal of the second transistor T2 through the third bottom electrode pattern BEP3.

[0135] The fourth bottom electrode pattern BEP4 may contact each of the fifth area AE5 and the ninth area AE9 of the active pattern ACT. For example, the fourth bottom electrode pattern BEP4 may electrically connect the fifth area AE5 and the ninth area AE9 to each other. Specifically, the fourth bottom electrode pattern BEP4 may electrically connect the input terminal of the first transistor T1 and the output terminal of the eighth transistor T8. Therefore, as described above, the bias voltage applied to the eighth transistor T8 can be transmitted to the first transistor T1.

[0136] The fifth bottom electrode pattern BEP5 may contact each of the N+1th bias voltage line VBIAS(N+1) and the tenth area AE10 of the active pattern ACT. Specifically, the fifth bottom electrode pattern BEP5 may electrically connect the N+1th bias voltage line VBIAS(N+1) and the input terminal of the eighth transistor T8 to each other through the first contact hole CNT1.

[0137] Figure 11 is a plan view for explaining the second contact hole CNT2 and the fourth conductive layer CL4.

[0138] refer to Figure 10 and Figure 11 , a horizontal bridge line BRS_H, a first horizontal power voltage line ELVDD_H, a horizontal portion of a first initialization voltage line VINT_H, a first top electrode pattern TEP1, and a second top electrode pattern TEP2 may be disposed on the third conductive layer CL3 with an insulating layer disposed therebetween.

[0139] The horizontal bridge line BRS_H may include an Nth horizontal bridge line BRS_H(N) included in the pixel circuits of the Nth row and an N+1th horizontal bridge line BRS_H(N+1) included in the pixel circuits of the N+1th row.

[0140] A first power voltage may be applied to a first horizontal power voltage line ELVDD_H. The first horizontal power voltage line ELVDD_H may include a third top electrode pattern TEP3. For example, the first horizontal power voltage line ELVDD_H and the third top electrode pattern TEP3 may be integrally formed. Specifically, the third top electrode pattern TEP3 may be a protruding portion of the first horizontal power voltage line ELVDD_H that protrudes from a portion of the first horizontal power voltage line ELVDD_H.

[0141] The first initialization voltage may be applied to the horizontal portion VINT_H of the first initialization voltage line. The horizontal portion VINT_H of the first initialization voltage line may include a third blocking pattern BP3.

[0142] Each of the first and second top electrode patterns TEP1 and TEP2 may be spaced apart from each other. Each of the first and second top electrode patterns TEP1 and TEP2 may be spaced apart from signal lines extending along the first direction DR1 (e.g., the horizontal bridge line BRS_H, the first horizontal power voltage line ELVDD_H, and the horizontal portion VINT_H of the first initialization voltage line).

[0143] The second contact hole CNT2 may be a through hole to contact the fourth conductive layer CL4 and a component disposed below the fourth conductive layer CL4 (eg, the third conductive layer CL3). The fourth conductive layer CL4 may be connected to the component disposed below the fourth conductive layer CL4 through the second contact hole CNT2.

[0144] Figure 12 1 is a plan view for explaining the first conductive layer CL1, the second conductive layer CL2, the first contact hole CNT1, the third conductive layer CL3, the second contact hole CNT2 and the fourth conductive layer CL4. Figure 17 A first through-hole insulating layer VIA1 may be provided on the third conductive layer CL3, and a fourth conductive layer CL4 may be provided on the first through-hole insulating layer VIA1. In addition, a second contact hole CNT2 may be defined, which is formed to pass through the first through-hole insulating layer in the thickness direction and expose the upper surface of the third conductive layer CL3.

[0145] refer to Figure 3 and Figure 12 The first horizontal power voltage line ELVDD_H may be electrically connected to the first vertical power voltage line ELVDD_V through the second contact hole CNT2. The first horizontal power voltage line ELVDD_H may be electrically connected to the second storage electrode CSTE2, the first stabilization electrode CSE1, and the seventh area AE7 of the active pattern ACT.

[0146] The third top electrode pattern TEP3, which is part of the first horizontal power voltage line ELVDD_H, may include a second barrier pattern BP2 that overlaps with the first sub-transistor T3-1. The second barrier pattern BP2 may protrude from the third top electrode pattern TEP3 toward the first sub-transistor T3-1. Specifically, the second barrier pattern BP2 may protrude in the first direction DR1 from a portion of the third top electrode pattern TEP3 (where the third top electrode pattern TEP3 overlaps with the first bottom electrode pattern BEP1). Thus, external light incident on the first sub-transistor T3-1 may be blocked, reducing leakage current and flicker caused by external light, and improving the low-frequency characteristics of the display device. In this specification, the third top electrode pattern TEP3 may be referred to as a second electrode pattern.

[0147] The second barrier pattern BP2 may overlap with a portion of the vertical portion of the second initialization voltage line VAINT_V disposed adjacent to the first sub-transistor T3-1. Furthermore, the second barrier pattern BP2 may overlap with a portion of the first gate voltage line GW disposed adjacent to the first sub-transistor T3-1. Thus, the second barrier pattern BP2 may cover the first sub-transistor T3-1, so that the upper surface of the active pattern ACT around the first sub-transistor T3-1 is not exposed.

[0148] The horizontal portion VINT_H of the first initialization voltage line can be electrically connected to the vertical portion VINT_V of the first initialization voltage line through the second contact hole CNT2. The second contact hole connecting the horizontal portion VINT_H of the first initialization voltage line and the vertical portion VINT_V of the first initialization voltage line can be the first hole described above (e.g., Figure 2 The first hole in Ha).

[0149] The horizontal portion of the first initialization voltage line VINT_H may include a third barrier pattern BP3 that overlaps with the third sub-transistor T4-1. The third barrier pattern BP3 may overlap with the third sub-transistor T4-1. Specifically, the third barrier pattern BP3 may protrude from a portion of the horizontal portion VINT_H (where the horizontal portion of the first initialization voltage line VINT_H overlaps with the vertical portion of the second initialization voltage line VAINT_V) in a direction opposite to the first direction DR1. Thus, external light incident on the third sub-transistor T4-1 can be blocked, reducing leakage current and flicker caused by external light, and improving the low-frequency characteristics of the display device.

[0150] The third barrier pattern BP3 may overlap a portion of the first vertical power voltage line ELVDD_V and a portion of the fourth sub-transistor T4-2. Furthermore, the third barrier pattern BP3 may overlap a portion of the first stabilization electrode CSE1. Thus, the third barrier pattern BP3, together with the first barrier pattern BP1 and the first stabilization electrode CSE1, may block the third sub-transistor T4-1 and a portion of the first area AE1 adjacent to the third sub-transistor T4-1.

[0151] The first top electrode pattern TEP1 may overlap the third bottom electrode pattern BEP3. The first top electrode pattern TEP1 may contact the third bottom electrode pattern BEP3 through the second contact hole CNT2. The first top electrode pattern TEP1 may be disposed in the fourth conductive layer CL4 and connected to the data voltage line DATA extending along the second direction DR2. Therefore, a data voltage applied from the data voltage line DATA may be provided to the input terminal of the second transistor T2 through the first top electrode pattern TEP1 and the third bottom electrode pattern BEP3.

[0152] The second top electrode pattern TEP2 may overlap the second bottom electrode pattern BEP2. The second top electrode pattern TEP2 may contact the second bottom electrode pattern BEP2. The second top electrode pattern TEP2 may contact the pixel electrode (eg, Figure 17 Therefore, the pixel electrode of the light emitting element LED may be connected to the eighth area AE8 of the active pattern ACT through the second top electrode pattern TEP2 and the second bottom electrode pattern BEP2.

[0153] Figure 13 yes Figure 12 An enlarged plan view of area B in FIG. Figure 14 、 Figure 15 and Figure 16 It shows Figure 13 Layout diagram of the display device in .

[0154] For example, Figure 14 Only the Figure 13 1 is a plan view of the active pattern ACT, the first gate voltage line GW, the second gate voltage line GI, the first stabilization electrode CSE1 and the first bottom electrode pattern BEP1 in FIG. Figure 15 Only the Figure 13 1 is a plan view of the active pattern ACT, the first gate voltage line GW, the second gate voltage line GI, the first stabilization electrode CSE1 and the third top electrode pattern TEP3 in FIG. Figure 16 is a plan view illustrating the active pattern ACT, the first gate voltage line GW, the second gate voltage line GI, the first stabilization electrode CSE1, and the horizontal portion VINT_H of the first initialization voltage line.

[0155] refer to Figure 13 In an embodiment, the first barrier pattern BP1 and the third barrier pattern BP3 may be spaced apart from each other in the second direction DR2. Figure 13 Not shown, the first and third barrier patterns BP1 and BP3 may overlap each other in the thickness direction. The first stabilization electrode CSE1 may be substantially disposed between the first and third barrier patterns BP1 and BP3 in the second direction DR2 and overlap each of the first and third barrier patterns BP1 and BP3 in a plan view.

[0156] The first barrier pattern BP1, the first stabilization electrode CSE1, and the third barrier pattern BP3 may completely cover the active pattern forming the third sub-transistor T4-1 except for a portion of the second area AE2. The second barrier pattern BP2 may completely cover the active pattern forming the first sub-transistor T3-1 except for a portion of the third area AE3.

[0157] refer to Figure 14 The first barrier pattern BP1 may be a protruding portion that protrudes from the first line L1 of the first bottom electrode pattern BEP1 in the second direction DR2 toward the third sub-transistor T4-1. The first line L1 may be an imaginary line that surrounds a portion of the first area AE1 adjacent to the third sub-transistor T4-1. The first barrier pattern BP1 may overlap a portion of the first stabilization electrode CSE1 in a plan view. Alternatively, the first barrier pattern BP1 may not overlap with the first stabilization electrode CSE1 in a plan view, but may instead be adjacent to the first stabilization electrode CSE1 in a plan view.

[0158] refer to Figure 15 The second barrier pattern BP2 may be a protruding portion protruding from the second line L2 of the third top electrode pattern TEP3 in the first direction DR1. The second barrier pattern BP2 may be a portion of the first horizontal power voltage line ELVDD_H. The second line L2 may be an imaginary line surrounding a portion of the first area AE1 disposed adjacent to the first sub-transistor T3-1.

[0159] refer to Figure 16 The third barrier pattern BP3 may be a protruding portion protruding from the third line L3 of the horizontal portion VINT_H of the first initialization voltage line in a direction opposite to the first direction DR1. The third line L3 may be an imaginary line surrounding the second area AE2 disposed adjacent to the third sub-transistor T4-1.

[0160] Hereinafter, the effects of the present disclosure according to comparative examples and embodiments will be described.

[0161] According to Example 1, a 2.9 μm 2 According to Example 2, a third barrier pattern BP3 having an area of ​​9.7 μm is manufactured. 2 The second barrier pattern BP2 has an area of ​​2.9 μm 2 According to Example 3, a structure of a third barrier pattern BP3 having an area of ​​3.4 μm is manufactured. 2 The first barrier pattern BP1 has an area of ​​9.7 μm 2 The second barrier pattern BP2 has an area of ​​2.9 μm 2 The structure of the third barrier pattern BP3 is shown.

[0162] According to the comparative example, a transistor including the first barrier pattern BP1, the second barrier pattern BP2, and the third barrier pattern BP3 and having a 25.7 μm thickness between the first sub-transistor T3-1 and the third sub-transistor T4-1 is manufactured. 2The total exposed areas of the structures according to the comparative example and the embodiment are shown in Table 1 below.

[0163] [Table 1]

[0164]

[0165] Table 2 below shows the visibility index, which indicates the degree of flicker and light-blocking properties when the display devices according to the comparative example and the embodiment are exposed to external light. The higher the visibility index, the more likely the flicker occurs and the lower the light-blocking properties. The unit of the visibility index may be just noticeable difference (JND).

[0166] [Table 2]

[0167]

[0168] As a result, compared with the comparative example, the first, second, and third embodiments, each including a structure including at least one of the first, second, and third barrier patterns BP1, BP2, and BP3, have improved light blocking characteristics. Specifically, the third embodiment, including all of the first, second, and third barrier patterns BP1, BP2, and BP3, has the best light blocking characteristics.

[0169] Figure 17 It is shown along Figure 13 A sectional view of a section taken along line II'.

[0170] refer to Figure 17 The display device DD may include a substrate SUB, a buffer layer BUF, an active pattern ACT, a first insulating layer IL1, a first gate electrode GE1, a second gate electrode GE2, a second insulating layer IL2, a first stabilization electrode CSE1, a second stabilization electrode CSE2, a third insulating layer IL3, a vertical portion of a second initialization voltage line VAINT_V, a first bottom electrode pattern BEP1, a first vertical power voltage line ELVDD_V, a first through-hole insulating layer VIA1, a third top electrode pattern TEP3, a horizontal portion of the first initialization voltage line VINT_H, a second through-hole insulating layer VIA2, a pixel electrode PXE, a pixel defining layer PDL, a light emitting layer EML, a common electrode CE and an encapsulation layer TFE.

[0171] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may include a transparent resin substrate. For example, the transparent resin substrate may include a polyimide substrate. In this case, the polyimide substrate SUB may include a first organic layer, a first barrier layer, a second organic layer, and the like. Alternatively, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a non-alkaline glass substrate, and the like. These may be used alone or in combination.

[0172] The buffer layer BUF may be provided on the substrate SUB. The buffer layer BUF may prevent impurities from diffusing from the substrate SUB to the active pattern ACT. The buffer layer BUF may include an inorganic insulating material. The inorganic insulating material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0173] The active pattern ACT may include a silicon semiconductor material. For example, the silicon semiconductor material may include amorphous silicon, polycrystalline silicon, or the like. Alternatively, the active pattern ACT may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium zinc oxide (IGO), indium zinc oxide (IZO), or the like. These materials may be used alone or in combination.

[0174] The first insulating layer IL1 may be disposed on the buffer layer BUF. The first insulating layer IL1 may cover the active pattern ACT disposed on the buffer layer BUF. For example, the first insulating layer IL1 may have a substantially uniform thickness along the contour of the active pattern ACT. Alternatively, the first insulating layer IL1 may sufficiently cover the active pattern ACT and may have a substantially flat upper surface without generating steps around the active pattern ACT.

[0175] The first insulating layer IL1 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0176] The first gate electrode GE1 and the second gate electrode GE2 may be a first conductive layer (eg, Figure 5 The first conductive layer may include a conductive material. For example, the first conductive layer may include silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), or the like. x N y), tungsten (W), tungsten nitride (W x N y ), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0177] The first gate electrode GE1 may be a portion of the first gate voltage line GW of the first conductive layer that overlaps with the active pattern ACT. For example, the first gate electrode GE1 may overlap with the first channel region T3-1c and the third channel region T3-2c of the active pattern ACT. Therefore, the first gate electrode GE1 and the first channel region T3-1c may together form a first sub-transistor T3-1. Furthermore, the second gate electrode GE2 and the third channel region T3-2c may together form a second sub-transistor T3-2.

[0178] The second gate electrode GE2 may be a portion of the second gate voltage line GI of the first conductive layer that overlaps with the active pattern ACT. For example, the second gate electrode GE2 may overlap with the second channel region T4-1c and the fourth channel region T4-2c of the active pattern ACT. Therefore, the second gate electrode GE2 and the second channel region T4-1c may together form a third sub-transistor T4-1. Furthermore, the second gate electrode GE2 and the fourth channel region T4-2c may together form a fourth sub-transistor T4-2.

[0179] The second insulating layer IL2 may be disposed on the first gate electrode GE1 and the second gate electrode GE2. The second insulating layer IL2 may cover the first conductive layer. The second insulating layer IL2 may have a substantially uniform thickness along the contour of each of the first gate electrode GE1 and the second gate electrode GE2. Alternatively, the second insulating layer IL2 may sufficiently cover each of the first gate electrode GE1 and the second gate electrode GE2 without generating steps around the first gate electrode GE1 and the second gate electrode GE2.

[0180] The second insulating layer IL2 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0181] The first stabilization electrode CSE1 and the second stabilization electrode CSE2 may be a second conductive layer (eg, Figure 7 The second conductive layer may include a conductive material. For example, the second conductive layer may include silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), or the like. x N y), tungsten (W), tungsten nitride (W x N y ), copper (Cu), and indium. It may include tin oxide (indium tin oxide (ITO)), indium zinc oxide (IZO), etc., and they may be used alone or in combination with each other.

[0182] The first stabilization electrode CSE1 and the second stabilization electrode CSE2 may be disposed on the second insulating layer IL2 . The first stabilization electrode CSE1 may form a first stabilization capacitor CS1 together with the third area AE3 of the active pattern ACT . The second stabilization electrode CSE2 may form a second stabilization capacitor CS2 together with the second area AE2 of the active pattern ACT .

[0183] The third insulating layer IL3 may be disposed on the first stabilizing electrode CSE1 and the second stabilizing electrode CSE2. The third insulating layer IL3 may be disposed on the second conductive layer. The third insulating layer IL3 may cover the second conductive layer. The third insulating layer IL3 may have a substantially uniform thickness along the contour of each of the first stabilizing electrode CSE1 and the second stabilizing electrode CSE2. Optionally, the third insulating layer IL3 may sufficiently cover each of the first stabilizing electrode CSE1 and the second stabilizing electrode CSE2 without creating steps around the first stabilizing electrode CSE1 and the second stabilizing electrode CSE2.

[0184] The third insulating layer IL3 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0185] The vertical portion VAINT_V of the second initialization voltage line, the first bottom electrode pattern BEP1, and the first vertical power voltage line ELVDD_V may be formed by a third conductive layer (eg, Figure 9 The third conductive layer may be provided on the third insulating layer IL3.

[0186] The third conductive layer may include a conductive material. For example, the third conductive layer may include silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), or the like. x N y ), tungsten (W), tungsten nitride (W x N y ), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In addition, the third conductive layer can have a single layer or multilayer structure containing at least one of the above-mentioned materials.

[0187] The first barrier pattern BP1, which is a portion of the first bottom electrode pattern BEP1, may overlap a portion of the first stabilization electrode CSE1. However, the first barrier pattern BP1 may not overlap the second gate electrode GE2 included in the third sub-transistor T4-1.

[0188] A first through hole insulating layer VIA1 may be disposed on the third conductive layer. The first through hole insulating layer VIA1 may include an organic insulating material such as polyimide (PI).

[0189] The third top electrode pattern TEP3 and the horizontal portion VINT_H of the first initialization voltage line may be a fourth conductive layer (eg, Figure 11 The fourth conductive layer may be disposed on the first through-hole insulating layer VIA1. The first through-hole insulating layer VIA1 may have a substantially flat top surface.

[0190] The fourth conductive layer may include a conductive material. For example, the fourth conductive layer may include silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), or the like. x N y ), tungsten (W), tungsten nitride (W x N y ), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In addition, the fourth conductive layer can have a single layer or multilayer structure including at least one of the above-mentioned materials.

[0191] The second barrier pattern BP2 that is a portion of the third top electrode pattern TEP3 may overlap the first gate electrode GE1 included in the first sub-transistor T3-1. For example, one end of the second barrier pattern BP2 may extend in the first direction DR1 to completely cover the first channel region T3-1c.

[0192] The third barrier pattern BP3, which is a portion of the horizontal portion VINT_H of the first initialization voltage line, may overlap the second gate electrode GE2 included in the third sub-transistor T4-1. In a cross-sectional view, the third barrier pattern BP3 may overlap all portions of the second gate electrode GE2 in the first direction DR1. Furthermore, one end of the third barrier pattern BP3 may overlap a portion of the second gate electrode GE2 constituting the fourth sub-transistor T4-2. However, the present disclosure is not limited thereto.

[0193] The second through hole insulating layer VIA2 may be disposed on the fourth conductive layer. The second through hole insulating layer VIA2 may include an organic insulating material such as polyimide (PI). The second through hole insulating layer VIA2 may have a substantially flat top surface.

[0194] The pixel electrode PXE may be disposed on the second through-hole insulating layer VIA2. The pixel electrode PXE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0195] A pixel-defining layer (PDL) may be disposed on the pixel electrode (PXE). The pixel-defining layer (PDL) may partially cover the pixel electrode (PXE). Furthermore, an opening may be defined in the pixel-defining layer (PDL) to expose at least a portion of the pixel electrode (PXE). For example, the opening of the pixel-defining layer (PDL) may expose the center portion of the pixel electrode (PXE), while the pixel-defining layer (PDL) may cover the edge of the pixel electrode (PXE). The pixel-defining layer (PDL) may include an organic insulating material, such as polyimide (PI).

[0196] In embodiments, the pixel defining layer (PDL) may further include a light-blocking material. Light-blocking materials may include black dyes, black pigments, carbon black, metals (e.g., chromium), and metal oxides. Therefore, the pixel defining layer (PDL) including the light-blocking material blocks external light from entering the first and third sub-transistors T3-1 and T4-1, thereby reducing leakage current and flicker caused by external light. This can further reduce flicker and improve the low-frequency characteristics of the display device.

[0197] The light emitting layer EML may be disposed on the pixel electrode PXE. The light emitting layer EML may be disposed on the pixel electrode PXE exposed by the opening of the pixel defining layer PDL. The light emitting layer EML may include an organic light emitting material, quantum dots, and the like.

[0198] The common electrode CE may be disposed on the light-emitting layer EML and the pixel-defining layer PDL. The common electrode CE may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. These may be used alone or in combination.

[0199] The light emitting element LED may include a pixel electrode PXE, a light emitting layer EML, and a common electrode CE.

[0200] The encapsulation layer TFE may be provided on the common electrode CE. The encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. The organic encapsulation layer may include an organic insulating material.

[0201] The display device according to the embodiment may be applied to electronic devices included in computers, notebooks, mobile phones, smart phones, smart tablets, PMPs, PDAs, MP3 players, and the like.

[0202] Although the display device according to the embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is an example and may be modified and changed by one of ordinary skill in the relevant art without departing from the technical spirit described in the appended claims.

Claims

1. A display device, characterized in that The display device includes: substrate; an active pattern disposed on the substrate and including a first region, a first channel region disposed adjacent to the first region in a first direction, a second region spaced apart from the first region in a second direction intersecting the first direction, and a second channel region disposed between the first region and the second region; a first conductive layer disposed on the active pattern and comprising a first gate voltage line overlapping the first channel region and a second gate voltage line overlapping the second channel region; a second conductive layer disposed on the first conductive layer and comprising a bias voltage line overlapping the second region and a first stabilizing electrode overlapping a portion of the first region; a first electrode pattern disposed on the second conductive layer and comprising a first barrier pattern protruding from a portion overlapping the first region toward the second channel region; a second electrode pattern disposed on the first electrode pattern and including a second barrier pattern that protrudes from a portion overlapping the first electrode pattern toward the first channel region and overlaps the first channel region; and The first initialization voltage line is disposed on the first electrode pattern, includes a third barrier pattern overlapping the second channel region, and extends along the first direction.

2. The display device according to claim 1, wherein The first barrier pattern overlaps a portion of the first stabilizing electrode.

3. The display device according to claim 1, wherein The first barrier pattern adjoins the first stabilizing electrode in a plan view.

4. The display device according to claim 1, wherein The third barrier pattern overlaps a portion of the first stabilizing electrode.

5. The display device according to claim 1, wherein The active pattern further includes a third region disposed adjacent to the first channel region in the first direction, a third channel region disposed adjacent to the third region in a direction opposite to the second direction, and a fourth channel region disposed adjacent to the second region in a direction opposite to the first direction.

6. The display device according to claim 5, wherein: The third barrier pattern overlaps at least a portion of the fourth channel region.

7. The display device according to claim 1, wherein The display device further includes: a second initialization voltage line disposed on the same layer as the first electrode pattern, overlapping each of a portion of the first channel region and a portion of the second barrier pattern, and extending along the second direction; a power voltage line provided on the same layer as the first initialization voltage line and formed integrally with the second electrode pattern; a light emitting element provided on the first initialization voltage line and the power voltage line, and comprising a pixel electrode, a light emitting layer provided on the pixel electrode, and a common electrode provided on the light emitting layer; and The pixel defining layer is disposed on the pixel electrode and includes a light blocking material.

8. A display device, characterized in that The display device includes: Light-emitting element; a driving transistor configured to provide a driving current to the light emitting element; a compensation transistor including a first sub-transistor and a second sub-transistor, the first sub-transistor including an output terminal electrically connected to the gate electrode of the driving transistor, the second sub-transistor including an output terminal electrically connected to the input terminal of the first sub-transistor and an input terminal electrically connected to the output terminal of the driving transistor; an initialization transistor including a third sub-transistor and a fourth sub-transistor, the third sub-transistor including an output terminal electrically connected to the gate electrode of the drive transistor, the fourth sub-transistor including an output terminal electrically connected to the input terminal of the third sub-transistor and an input terminal electrically connected to an initialization voltage line; a first barrier pattern disposed on the gate electrode of the driving transistor and disposed between a portion of the active pattern intersecting the output terminal of the first sub-transistor and the output terminal of the third sub-transistor and the third sub-transistor; a second barrier pattern disposed on the first barrier pattern and overlapping at least a portion of the first sub-transistor; and A third barrier pattern is disposed on the first barrier pattern and overlaps at least a portion of the third sub-transistor and the fourth sub-transistor.

9. The display device according to claim 8, wherein The display device further includes: a first stabilizing capacitor provided on each of the first sub-transistor and the second sub-transistor and located between the first sub-transistor and the second sub-transistor; and a second stabilizing capacitor provided on each of the third sub-transistor and the fourth sub-transistor and located between the third sub-transistor and the fourth sub-transistor; wherein the first stabilizing capacitor includes a first stabilizing electrode overlapping a portion of the active pattern disposed between the input terminal of the first sub-transistor and the output terminal of the second sub-transistor, and The second stabilizing capacitor includes a second stabilizing electrode overlapping a portion of the active pattern disposed between the input terminal of the third sub-transistor and the output terminal of the fourth sub-transistor.

10. The display device according to claim 9, wherein: Each of the first and third barrier patterns overlaps a portion of the first stabilizing electrode.

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