Display device

Abstract

A display device is disclosed. The display device includes: an active layer disposed on a substrate; a gate electrode disposed on the active layer to overlap with the active layer and defining a channel region of the active layer; a pixel electrode disposed on the gate electrode; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer. In a channel region, the channel region has a channel length in a first direction, and at least one side of the channel region defining the channel length has a diagonal shape or a bent shape such that the channel length varies in a second direction intersecting the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0167532, filed on November 28, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that includes a plurality of emission regions (e.g., pixel circuits) and is capable of expressing fine grayscales of an image displayed by the display device by extending a driving range of a voltage applied to the emission regions via a driving line. Background Art

[0004] Organic light-emitting diode (OLED) displays have self-luminous properties and, unlike liquid crystal displays (LCDs), do not require a separate light source, thus reducing thickness and weight. Furthermore, OLED displays are attracting attention as next-generation displays for TVs, monitors, and portable electronic devices due to their high-quality features such as low power consumption, high brightness, and high response speed. Utility Model Content

[0005] Aspects of the present disclosure provide a display device capable of expressing fine grayscales by extending a driving range of an OLED included in the display device.

[0006] According to an aspect of the present disclosure, a display device is provided having a channel region with a channel length, the channel region having an oblique line shape or a meandering shape such that the channel length changes in one direction.

[0007] According to an embodiment of the present disclosure, a display device includes: an active layer arranged on a substrate; a gate electrode arranged on the active layer to overlap with the active layer and define a channel region of the active layer; a pixel electrode arranged on the gate electrode; a light-emitting layer arranged on the pixel electrode; and a common electrode arranged on the light-emitting layer, wherein, in the channel region, the channel region has a channel length in a first direction, and at least one side of the channel region that defines the channel length has a slant shape or a bent shape, so that the channel length changes in a second direction intersecting with the first direction.

[0008] In an embodiment, the channel region may have a trapezoidal shape.

[0009] In an embodiment, the gate electrode may have a trapezoidal shape.

[0010] In an embodiment, the active layer may have a rectangular shape.

[0011] In an embodiment, the gate electrode may have a quadrilateral shape.

[0012] In an embodiment, the active layer may have a quadrilateral shape with two sides bent inward or outward relative to each other.

[0013] In an embodiment, the channel region may have an arc shape.

[0014] In an embodiment, the gate electrode may have a trapezoidal shape.

[0015] In an embodiment, the active layer may have an arc shape.

[0016] In an embodiment, the gate electrode may have a quadrilateral shape.

[0017] In an embodiment, the active layer may have an arc shape.

[0018] In an embodiment, the channel region may have a hexagonal shape.

[0019] In an embodiment, the gate electrode may have a hexagonal shape.

[0020] In an embodiment, the channel region may include a first region having a quadrilateral shape, a second region having a quadrilateral shape, and a third region disposed between the first region and the second region and having a hexagonal shape.

[0021] In an embodiment, the channel region may include a first region having a quadrilateral shape, a second region having a quadrilateral shape, and a third region disposed between the first region and the second region and having an octagonal shape.

[0022] In an embodiment, the channel region may include a first region having a quadrilateral shape, a second region having a quadrilateral shape, and a third region disposed between the first region and the second region and having an elliptical shape.

[0023] In an embodiment, the entire third region may overlap with the active layer.

[0024] In an embodiment, the channel region may include: a first region having a quadrilateral shape; a second region having a quadrilateral shape; a third region arranged between the first region and the second region and having a trapezoidal shape; and a fourth region arranged between the second region and the third region and having an inverted trapezoidal shape.

[0025] In an embodiment, the channel region may include: a first region having a quadrilateral shape; a second region having a quadrilateral shape; a third region arranged between the first region and the second region and having a trapezoidal shape; a fourth region arranged between the third region and the second region and having an inverted trapezoidal shape; and a fifth region arranged between the fourth region and the third region and having a quadrilateral shape.

[0026] In an embodiment, the channel region may have semicircular grooves respectively formed on two sides facing each other in the first direction.

[0027] In an embodiment, the channel region may have semi-elliptical grooves respectively formed on two sides facing each other in the first direction.

[0028] In an embodiment, the channel region may include a first region having a trapezoidal shape, and a second region spaced apart from the first region in a first direction and having an inverted trapezoidal shape.

[0029] According to an embodiment of the present disclosure, an organic light emitting diode includes: an active layer arranged on a substrate; a gate electrode arranged on the active layer to overlap with the active layer and define a channel region of the active layer, wherein, in a channel region having a channel length, at least one side of the channel region that defines the channel length has a slanted shape or a bent shape, so that the channel length changes in a direction different from the direction in which the channel length extends.

[0030] According to the display device of the present disclosure, the display device can express fine grayscales by extending the driving range.

[0031] The effects of the present disclosure are not limited to the above-described effects, and other effects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In the accompanying drawings, the size, thickness, ratio, and dimensions of the elements may be exaggerated for ease of description and for clarity. Similar reference numerals and / or similar reference symbols refer to similar elements throughout. These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an embodiment constructed according to the principles of the present disclosure;

[0034] Figure 2 is a cross-sectional view of a display device according to an embodiment;

[0035] Figure 3 is a plan view of a display unit of a display device according to an embodiment;

[0036] Figure 4 is a block diagram of a display panel and a display driver according to an embodiment;

[0037] Figure 5 is a circuit diagram of a pixel of a display device according to an embodiment;

[0038] Figure 6 is included Figure 5 a cross-sectional view of a display device including a first transistor;

[0039] Figure 7 is a plan view of a transistor according to an embodiment;

[0040] Figure 8 is a plan view of a transistor according to an embodiment;

[0041] Figure 9 is a plan view of a transistor according to an embodiment;

[0042] Figure 10 is a plan view of a transistor according to an embodiment;

[0043] Figure 11 is a plan view of a transistor according to an embodiment;

[0044] Figure 12 is a plan view of a transistor according to an embodiment;

[0045] Figure 13 is a plan view of a transistor according to an embodiment;

[0046] Figure 14 is a plan view of a transistor according to an embodiment;

[0047] Figure 15 is a plan view of a transistor according to an embodiment;

[0048] Figure 16 is a plan view of a transistor according to an embodiment;

[0049] Figure 17 is a plan view of a transistor according to an embodiment;

[0050] Figure 18 is a plan view of a transistor according to an embodiment;

[0051] Figure 19 is a plan view of a transistor according to an embodiment;

[0052] Figure 20 is a plan view of a transistor according to an embodiment; and

[0053] Figure 21is a diagram for explaining the operation of a transistor of a display device according to an embodiment. DETAILED DESCRIPTION

[0054] The advantages and features of the present disclosure and methods for achieving them will become apparent from the detailed description of the embodiments below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in different forms. The embodiments are provided so that the disclosure of the present disclosure is thorough and will fully convey the scope of the present disclosure to those skilled in the art. It should be noted that the scope of the present disclosure is limited only by the claims.

[0055] As used herein, the phrase "element A on element B" means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Like reference numerals denote like elements throughout the description. The numbers, dimensions, ratios, angles, and numbers of elements given in the drawings are illustrative only and not limiting.

[0056] Although terms such as first, second, etc. are used to arbitrarily distinguish between the elements described by these terms, these terms are not necessarily intended to indicate the tense or other priority of these elements. These terms are only used to distinguish one element from another. Therefore, as used herein, within the technical scope of the present disclosure, a first element may be a second element.

[0057] The multiple features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly appreciated by those skilled in the art, various technical interactions and operations are possible. The various embodiments can be practiced individually or in combination.

[0058] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent settings. Here, the various embodiments are not necessarily exclusive and do not necessarily limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0059] Unless otherwise specified, the illustrated embodiments are understood to provide illustrative features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0060] The use of cross hatching and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading will not convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two continuously described processes may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, similar reference numerals and / or reference symbols represent similar elements.

[0061] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intervening elements. Additionally, the DR1 axis, DR2 axis, and DR3 axis are not limited to the three axes of a rectangular coordinate system, such as the x-axis, y-axis, and z-axis, and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0062] Although the terms "first," "second," etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0063] Spatially relative terms, such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element(s) as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture, in addition to the orientations depicted in the accompanying drawings. For example, if the device in the drawings were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the illustrative term "below" is capable of encompassing both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0064] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "the," as used herein, are intended to include the plural forms as well. In addition, the terms "comprises," "comprising," "includes," and / or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, parts, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation and not as terms of degree, and are therefore used to take into account the inherent deviations in measured, calculated, and / or provided values ​​that one of ordinary skill in the art would recognize.

[0065] Various embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of the illustrated regions, but rather include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of a device and, therefore, are not necessarily intended to be limiting.

[0066] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control the blocks, units, and / or modules to perform the various functions discussed herein, and the blocks, units, and / or modules can be optionally driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. In addition, without departing from the scope of this disclosure, each block, unit, and / or module of some illustrative embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Furthermore, the blocks, units and / or modules of some illustrative embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the disclosure.

[0067] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0068] Figure 1 is a perspective view of a display device 10 according to an embodiment constructed according to the principles of the present disclosure.

[0069] refer to Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). For example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, wristwatches, eyeglass displays, and head-mounted displays (HMDs).

[0070] The display device 10 may have a planar shape similar to a quadrilateral, or otherwise referred to herein as a three-dimensional rectangular shape. For example, the display device 10 may have a planar shape similar to a quadrilateral with short sides in the first direction DR1 and long sides in the second direction DR2. Each corner where the short sides extending in the first direction DR1 and the long sides extending in the second direction DR2 intersect may be rounded with a predetermined curvature or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral and may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0071] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0072] The display panel 100 may include a main area MA and a sub-area SBA.

[0073] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA arranged around the display area DA (i.e., on the periphery of the display area DA or on the outside of the display area DA relative to a plan view). The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a light-emitting element ED (e.g., see FIG. 1 ). Figure 5 and Figure 6 ).

[0074] For example, each of the plurality of light emitting elements ED may include but is not limited to at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode.

[0075] The non-display area NDA may be an area outside the display area DA, such as Figure 1 The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies gate signals to gate lines and fan-out lines connecting the display driver 200 and the display area DA.

[0076] The sub-area SBA may be formed from one side of the main area MA (such as from Figure 1The sub-area SBA may include a flexible material that can be bent, folded, curled, etc. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3). The sub-area SBA may include the display driver 200 and a pad unit connected to the circuit board 300. Alternatively, in some implementations, the sub-area SBA may be omitted, and the display driver 200 and the pad unit may be arranged in the non-display area NDA.

[0077] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines. The display driver 200 may supply power voltages to the power lines and gate control signals to the gate driver. The display driver 200 may be formed as an integrated circuit and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be arranged in the sub-area SBA and may overlap with the main area MA in the thickness direction (third direction DR3) by bending the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0078] The circuit board 300 may be attached to the pad unit of the display panel 100 using an anisotropic conductive film. Leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0079] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the multiple touch electrodes of the touch sensing unit and sense changes in capacitance between the multiple touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may determine whether an input has been made and calculate the coordinates of the input based on the changes in capacitance between the multiple touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0080] The power supply unit 500 may be disposed on the circuit board 300 to supply a power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a first driving voltage and supply the first driving voltage to the driving voltage line VDL (see FIG. 1 ). Figure 3), an initialization voltage (e.g., a first initialization voltage and a second initialization voltage) may be generated and supplied to an initialization voltage line (e.g., a first initialization voltage line and a second initialization voltage line), and a common voltage may be generated and supplied to a common electrode common to a plurality of light-emitting elements ED of a plurality of pixels. For example, the first driving voltage may be a high potential voltage for driving the light-emitting elements ED, and the common voltage may be a low potential voltage for driving the light-emitting elements ED.

[0081] Figure 2 is a cross-sectional view of a display device 10 according to an embodiment.

[0082] refer to Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0083] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, rolled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0084] The thin film transistor layer TFTL may be arranged on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting pixel circuits of the pixels. The thin film transistor layer TFTL may also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 and the data lines, and leads connecting the display driver 200 and the pad unit. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0085] The thin film transistor layer TFTL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. Thin film transistors, gate lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be arranged in the display area DA. Gate control lines and fan-out lines of the thin film transistor layer TFTL may be arranged in the non-display area NDA. Lead lines of the thin film transistor layer TFTL may be arranged in the sub-area SBA.

[0086] The light-emitting element layer (EMTL) may be disposed on the thin film transistor layer (TFTL). The light-emitting element layer (EMTL) may include: a plurality of light-emitting elements (ED), each including a pixel electrode, a light-emitting layer, and a common electrode sequentially stacked to emit light; and a pixel-defining layer that defines pixels. The light-emitting elements (ED) of the light-emitting element layer (EMTL) may be disposed in the display area (DA).

[0087] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage (e.g., a predetermined or selectable voltage) through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively. The holes and electrons may then combine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode, and the common electrode may be a cathode, but the present disclosure is not limited thereto.

[0088] For another example, each of the plurality of light emitting elements ED may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0089] The encapsulation layer ENC may cover the upper surface and side surfaces of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EMTL.

[0090] The touch sensing unit TSU may be disposed on the encapsulation layer ENC. The touch sensing unit TSU may include a plurality of touch electrodes for capacitively sensing a user's touch, and touch lines connecting the touch electrodes and the touch driver 400. For example, as known to those skilled in the art, the touch sensing unit TSU may sense a user's touch using mutual capacitance or self-capacitance.

[0091] For another example, the touch sensing unit TSU may be disposed on a separate substrate SUB disposed on the display unit DU. In this case, the substrate SUB supporting the touch sensing unit TSU may be a base member that encapsulates the display unit DU.

[0092] The touch electrodes of the touch sensing unit TSU may be arranged in a touch sensor area overlapping the display area DA, and the touch lines of the touch sensing unit TSU may be arranged in a touch peripheral area overlapping the non-display area NDA.

[0093] A color filter layer (CFL) may be disposed on the touch sensing unit (TSU). The color filter layer (CFL) may include multiple color filters corresponding to the multiple emission regions. Each of the multiple color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer (CFL) may absorb a portion of light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the color filter layer (CFL) may prevent color distortion caused by reflection of external light.

[0094] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0095] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material capable of bending, folding, curling, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include the display driver 200 and a pad unit electrically connected to the circuit board 300.

[0096] Figure 3 is a plan view of the display unit DU of the display device 10 according to the embodiment. Figure 4 is a block diagram of a display panel 100 and a display driver 200 according to an embodiment.

[0097] refer to Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0098] The display area DA may include a plurality of pixels PX, a plurality of driving voltage lines VDL connected to the plurality of pixels PX, a plurality of common voltage lines (eg, Figure 5 a common voltage line VSL in the circuit), a plurality of gate lines GL, and a plurality of data lines DL.

[0099] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, a driving voltage line VDL, and a common voltage line VSL. Each of the plurality of pixels PX may include at least one transistor, a light emitting element ED, and a capacitor.

[0100] A plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 intersecting the first direction DR1. The gate lines GL may be arranged along the second direction DR2. The gate lines GL may sequentially supply gate signals to the pixels PX.

[0101] A plurality of data lines DL may extend in a second direction DR2 and may be spaced apart from each other in a first direction DR1. The data lines DL may be arranged along the first direction DR1. The data lines DL may supply a data voltage to the pixels PX. The data voltage may determine the brightness of each of the plurality of pixels PX. Depending on the embodiment, one pixel may be connected to two different data lines. For example, one pixel may be connected to a first data line and a second data line.

[0102] A plurality of driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The driving voltage lines VDL may be arranged along the first direction DR1. The driving voltage lines VDL may supply a driving voltage to the pixels PX. The driving voltage may be a high potential voltage for driving the light-emitting elements ED of the pixels PX.

[0103] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, a fan-out line FL, and a gate control line GSL.

[0104] The fan-out line FL may extend from the display driver 200 to the display area DA. The fan-out line FL may supply a data voltage received from the display driver 200 to the data line DL.

[0105] The gate control line GSL may extend from the display driver 200 to the gate driver 610. The gate control line GSL may supply a gate control signal GCS received from the display driver 200 to the gate driver 610.

[0106] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad unit DP. The pad unit DP may be arranged closer to the edge of the sub-area SBA than the display driver 200. The pad unit DP may be electrically connected to the circuit board 300 through an anisotropic conductive film.

[0107] refer to Figure 4 , the display driver 200 may include a timing controller 210 and a data driver 220 .

[0108] The timing controller 210 can receive digital video data DATA and timing signals from the circuit board 300. The timing controller 210 can control the operation timing of the data driver 220 by generating a data control signal DCS based on the timing signals, control the operation timing of the gate driver 610 by generating a gate control signal GCS, and control the operation timing of the emission control driver by generating an emission control signal. The timing controller 210 can supply the gate control signal GCS to the gate driver 610 via the gate control line GSL. The timing controller 210 can supply the digital video data DATA and the data control signal DCS to the data driver 220.

[0109] The data driver 220 may convert the digital video data DATA into a data voltage (e.g., an analog data voltage) and supply the data voltage to the data line DL through the fan-out line FL. The gate signal of the gate driver 610 may select a pixel PX to which the data voltage is to be supplied, and the selected pixel PX may receive the data voltage through the data line DL.

[0110] The power supply unit 500 may be disposed on the circuit board 300 to supply a power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a first driving voltage and supply the first driving voltage to the driving voltage line VDL, may generate an initialization voltage and supply the initialization voltage to the initialization voltage line, and may generate a common voltage and supply the common voltage to a common electrode common to the plurality of light-emitting elements ED of the plurality of pixels PX. The common voltage may be applied to the common electrode via the common voltage line VSL.

[0111] The gate driver 610 may be arranged outside one side of the display area DA or on one side of the non-display area NDA, and the emission control driver may be arranged outside the other side of the display area DA or on the other side of the non-display area NDA. However, the present disclosure is not limited thereto. For another example, the gate driver 610 and the emission control driver may be arranged on one side or the other side of the non-display area NDA.

[0112] The gate driver 610 may include a plurality of transistors that generate gate signals based on the gate control signal GCS. The transistors of the gate driver 610 may be formed on the same layer as the transistors of the pixel PX. The gate driver 610 may supply the gate signals to the gate lines GL.

[0113] Figure 5 is a circuit diagram of a pixel PX of the display device 10 according to an embodiment.

[0114] refer to Figure 5 , the pixel PX may be connected to the gate line GL, the data line DL, the driving voltage line VDL, and the common voltage line VSL.

[0115] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0116] The pixel circuit PC may include a first transistor T1 , a second transistor T2 , and a capacitor Cst.

[0117] The first transistor T1 may include a first gate electrode GE1, a second gate electrode GE2, a source electrode, and a drain electrode. The first transistor T1 may control a drain-source current (hereinafter referred to as a drive current) according to a data voltage applied to the first gate electrode GE1. The first transistor T1 may have a first gate electrode GE1 electrically connected to the source electrode of the second transistor T2, a second gate electrode GE2 electrically connected to the source electrode of the first transistor T1, a drain electrode electrically connected to a drive voltage line VDL, and a source electrode connected to a first electrode (or anode or pixel electrode) of the light-emitting element ED. The drive voltage line VDL may transmit a drive voltage ELVDD.

[0118] The light-emitting element ED may emit light in response to a received driving current. The amount of light or brightness of the light-emitting element ED may be proportional to the magnitude of the driving current. The light-emitting element ED may include a first electrode, a second electrode (or a cathode or a common electrode), and an organic light-emitting layer, and the organic light-emitting layer may be arranged between the first and second electrodes. In another example, the light-emitting element ED may be an inorganic light-emitting element ED that may include a first electrode, a second electrode, and an inorganic semiconductor, and the inorganic semiconductor may be arranged between the first and second electrodes. In another example, the light-emitting element ED may be a quantum dot light-emitting element ED that may include a first electrode, a second electrode, and a quantum dot light-emitting layer, and the quantum dot light-emitting layer may be arranged between the first and second electrodes. In another example, the light-emitting element ED may be a micro light-emitting diode. The first electrode of the light-emitting element ED may be electrically connected to the source electrode of the first transistor T1. The second electrode of the light-emitting element ED may be connected to a common voltage line VSL. The second electrode of the light-emitting element ED may receive a common voltage ELVSS (e.g., a low potential voltage) from the common voltage line VSL.

[0119] The second transistor T2 can be turned on by a gate signal GS of the gate line GL to electrically connect the data line DL and the first gate electrode GE1 of the first transistor T1. The second transistor T2 turned on based on the gate signal GS can supply a data voltage from the data line DL to the first gate electrode GE1 of the first transistor T1. The second transistor T2 may have a gate electrode electrically connected to the gate line GL, a drain electrode electrically connected to the data line DL, and a source electrode electrically connected to the first gate electrode GE1 of the first transistor T1.

[0120] The capacitor Cst may be electrically connected between the first gate electrode GE1 of the first transistor T1 and the driving voltage line VDL. The first electrode of the capacitor Cst may be electrically connected to the first gate electrode GE1 of the first transistor T1, and the second electrode of the capacitor Cst may be electrically connected to the driving voltage line VDL. For example, the capacitor Cst may store a data voltage supplied from the data line DL through the second transistor T2.

[0121] Each of the first transistor T1 and the second transistor T2 may include an oxide-based active layer. For example, the oxide-based active layer may include indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO). The transistor including the oxide-based active layer may have a coplanar structure in which the gate electrode is arranged at the top of the coplanar structure. The transistor including the oxide-based active layer may correspond to an n-type transistor and may output current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0122] Figure 6 is included Figure 5 FIG. 1 is a cross-sectional view of a display device 10 including a first transistor T1 .

[0123] refer to Figure 6 The display device 10 according to the present embodiment may include a substrate SUB, a light blocking layer BML, a buffer layer BF, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The light blocking layer BML, the buffer layer BF, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially arranged from bottom to top on the substrate SUB along the third direction DR3. Here, the thin film transistor layer TFTL may include the above-mentioned Figure 5 The first transistor T1 and the second transistor T2. Figure 6 , the first transistor T1 included in the thin film transistor layer TFTL is illustrated as an example.

[0124] The substrate SUB may be a rigid substrate or a flexible substrate capable of bending, folding, or curling. The substrate SUB may be made of an insulating material such as glass, quartz, or a polymer resin. The polymer material may be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate SUB may include a metal material.

[0125] The light-blocking layer BML may be arranged on the substrate SUB. The light-blocking layer BML may be arranged on the substrate SUB and overlap with the active layer ACT, which will be described in more detail later. For example, the light-blocking layer BML may be made of a metal material such as chromium (Cr) or molybdenum (Mo), or may be made of black ink or black dye. In the case where the light-blocking layer BML is made of a metal material, the light-blocking layer BML may receive static electricity. Therefore, the light-blocking layer BML may not be electrically floating, and the electrical characteristics of the first transistor T1 and the second transistor T2 on the light-blocking layer BML may be stable. For example, performance degradation of the oxide-based first transistor T1 and the second transistor T2 can be minimized. Oxide semiconductors are sensitive to light, and the amount of current may vary due to external light. The light-blocking layer BML may include the second gate electrode GE2 of the first transistor T1. In other words, a portion of the light-blocking layer BML may correspond to the second gate electrode GE2 of the first transistor T1.

[0126] The buffer layer BF may be disposed on the light-blocking layer BML. The buffer layer BF may be disposed over the entire surface of the substrate SUB including the light-blocking layer BML. The buffer layer BF may be a layer for protecting the transistors of the thin-film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture introduced through the substrate SUB, which is susceptible to moisture permeation. The buffer layer BF may be composed of a plurality of alternately stacked inorganic layers. For example, the buffer layer BF may have a multilayer structure in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0127] The active layer ACT may be disposed on the buffer layer BF. For example, the active layer ACT may be disposed on the buffer layer BF so as to overlap with the second gate electrode GE2 of the light-blocking layer BML. For example, the active layer ACT may be an oxide semiconductor. For example, the active layer ACT may be a semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO). Furthermore, for example, the active layer ACT may be crystalline silicon, polycrystalline silicon, or amorphous silicon.

[0128] The gate insulating layer GTI may be disposed on the active layer ACT. For example, the gate insulating layer GTI may overlap with the channel region CH of the active layer ACT. The gate insulating layer GTI may include tetraethyl orthosilicate (TEOS), silicon nitride (SiN x ) and at least one of silicon oxide (SiO 2 ). For example, the gate insulating layer GTI may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethyl orthosilicate layer having a thickness of 80 nm are sequentially stacked.

[0129] The first gate electrode GE1 may be disposed on the gate insulating layer GTI. The first gate electrode GE1 may be disposed on the gate insulating layer GTI to overlap with the channel region CH of the active layer ACT. The first gate electrode GE1 may be made of aluminum (Al) or titanium (Ti). In addition, the first gate electrode GE1 may have a double-layer or triple-layer structure in which aluminum (Al) and titanium (Ti) are stacked.

[0130] An interlayer insulating layer ITL may be disposed on the first gate electrode GE1. The interlayer insulating layer ITL may be disposed over the entire surface of the substrate SUB including the first gate electrode GE1. The interlayer insulating layer ITL may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The interlayer insulating layer ITL may include a plurality of inorganic layers.

[0131] A source connection electrode SCE and a drain connection electrode DCE may be disposed on the interlayer insulating layer ITL. The source connection electrode SCE may be connected to the source electrode SE of the active layer ACT via a first contact hole CT1 penetrating the interlayer insulating layer ITL. The drain connection electrode DCE may be connected to the drain electrode DE of the active layer ACT via a second contact hole CT2 penetrating the interlayer insulating layer ITL. The source connection electrode SCE and the drain connection electrode DCE may be made of the same material as the first gate electrode GE1 described above.

[0132] The passivation layer PAS may be disposed on the source connection electrode SCE and the drain connection electrode DCE. The passivation layer PAS may be disposed on the entire surface of the substrate SUB including the interlayer insulating layer ITL. The passivation layer PAS may be made of the same material as the interlayer insulating layer ITL.

[0133] The planarization layer VA may be disposed on the passivation layer PAS. The planarization layer VA may be disposed on the entire surface of the substrate SUB including the passivation layer PAS. The planarization layer VA may include an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0134] A light-emitting element layer EMTL including a pixel electrode PE, a light-emitting element ED, and a pixel-defining layer PDL may be disposed on the planarization layer VA. The pixel electrode PE may be connected to the source connection electrode SCE via a third contact hole CT3 penetrating the planarization layer VA. The pixel electrode PE may be connected to the source electrode SE of the active layer ACT via the source connection electrode SCE.

[0135] The light-emitting element ED may include a pixel electrode PE, a light-emitting layer EL, and a common electrode CM. The emission area EA is a region in which the pixel electrode PE, the light-emitting layer EL, and the common electrode CM are sequentially stacked, so that holes from the pixel electrode PE and electrons from the common electrode CM combine with each other in the light-emitting layer EL to emit light. In this case, the pixel electrode PE may be the anode of the light-emitting element ED, and the common electrode CM may be the cathode of the light-emitting element ED.

[0136] In a top emission structure in which light is emitted from the light-emitting layer EL toward the common electrode CM, the pixel electrode PE may be formed as a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or in order to increase reflectivity, the pixel electrode PE may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0137] The pixel defining layer (PDL) defines the emission area EA of the pixel PX. To this end, the pixel defining layer (PDL) may be disposed on the planarization layer VA to expose a portion of the pixel electrode PE. The pixel defining layer (PDL) may cover the edge of the pixel electrode PE. The pixel defining layer (PDL) may be made of an organic layer such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0138] The spacer SPC may be disposed on the pixel defining layer PDL. The spacer SPC may support a mask during the process of manufacturing the light emitting layer EL. The spacer SPC may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0139] The light-emitting layer EL may be formed on the pixel electrode PE. The light-emitting layer EL may include an organic material that emits light of a predetermined color. For example, the light-emitting layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits the predetermined light and may be formed using a phosphorescent material or a fluorescent material.

[0140] The pixel PX may include a first pixel emitting light of a first color through a first emission area, a second pixel emitting light of a second color through a second emission area, and a third pixel emitting light of a third color through a third emission area.

[0141] The organic material layer of the first light-emitting layer of the first emission region emitting light of the first color may be a phosphorescent material including a host material and a dopant, the host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl) (mCP), and the dopant including any one or more of bis(1-phenylisoquinoline) iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinoline) iridium acetylacetonate (PQIr(acac), tris(1-phenylquinoline) iridium (PQIr) and platinum octaethylporphyrin (PtOEP). Alternatively, the organic material layer of the first light-emitting layer of the first emission region may be a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene. However, the present disclosure is not limited to this.

[0142] The organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including Ir(ppy)3 (fac-tris(2-phenylpyridine)iridium). Alternatively, the organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a fluorescent material including tris(8-hydroxyquinoline)aluminum (Alq3). However, the present disclosure is not limited thereto.

[0143] The organic material layer of the third light emitting layer of the third emission region emitting light of the third color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111. However, the present disclosure is not limited thereto.

[0144] The common electrode CM may be disposed on the light-emitting layer EL. For example, the common electrode CM may be disposed on the first, second, and third light-emitting layers. The common electrode CM may cover the first, second, and third light-emitting layers. The common electrode CM may be a common layer commonly disposed on the first to third light-emitting layers. A capping layer may be formed on the common electrode CM.

[0145] In a top-emission structure, the common electrode CM can be made of a light-transmitting transparent conductive material (TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the common electrode CM is made of a semi-transmissive conductive material, light output efficiency can be improved through a microcavity.

[0146] The encapsulation layer ENC may be formed on the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer to prevent oxygen or moisture from penetrating the light-emitting element layer EMTL. Furthermore, the encapsulation layer ENC may include at least one organic layer to protect the light-emitting element layer EMTL from foreign matter, such as dust or other types of debris. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0147] A first encapsulating inorganic layer TFE1 may be disposed on the common electrode CM, an encapsulating organic layer TFE2 may be disposed on the first encapsulating inorganic layer TFE1, and a second encapsulating inorganic layer TFE3 may be disposed on the encapsulating organic layer TFE2. Each of the first encapsulating inorganic layer TFE1 and the second encapsulating inorganic layer TFE3 may have a multilayer structure in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulating organic layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0148] A barrier layer may be disposed between the substrate SUB and the light-blocking layer BML. The barrier layer may be a layer for protecting the first and second transistors T1 and T2 of the thin-film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture introduced through the substrate SUB, which is susceptible to moisture permeation. The barrier layer may be composed of a plurality of alternately stacked inorganic layers. For example, the barrier layer may have a multilayer structure in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0149] Figure 7 is a plan view of a transistor TR according to an embodiment.

[0150] The transistor TR of the display device 10 according to the present embodiment may include a gate electrode GE disposed on the active layer ACT to overlap the active layer ACT. Here, the gate electrode GE may be disposed on the gate insulating layer GTI to partially overlap the active layer ACT, thereby defining a channel region CH of the active layer ACT.

[0151] According to embodiments, for example, in a channel region CH having a channel length L in a first direction DR1, at least one side of the channel region CH defining the channel length L may have an oblique or meandering shape such that the channel length L changes along a second direction DR2 intersecting the first direction DR1. Specific examples are described below.

[0152] like Figure 7 As shown in FIG, the transistor TR may include a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0153] The active layer ACT may include the drain electrode DE, the source electrode SE, and the channel region CH of the transistor TR. The active layer ACT may have a rectangular shape.

[0154] The gate electrode GE may have a Figure 7 The gate insulating layer GTI may be disposed between the gate electrode GE and the active layer ACT.

[0155] The gate electrode GE may overlap the active layer ACT. The channel region CH of the transistor TR may be formed in a region where the gate electrode GE and the active layer ACT overlap. For example, Figure 7 As shown in FIG, the channel region CH may be defined as a region surrounded by a first side S1 , a second side S2 , a third side S3 , and a fourth side S4 .

[0156] A portion of the active layer ACT adjacent to one side of the channel region CH and not overlapping the gate electrode GE may be defined as the drain electrode DE of the transistor TR, and a portion of the active layer ACT adjacent to the other side of the channel region CH and not overlapping the gate electrode GE may be defined as the source electrode SE of the transistor TR.

[0157] The channel length L of the channel region CH may be defined as the distance between the drain electrode DE and the source electrode SE, and the channel width W of the channel region CH may be defined as the length of the facing surfaces of the drain electrode DE and the source electrode SE. Figure 7 In the embodiment, the channel length L may be defined as the distance of the channel region CH in the first direction DR1, and the channel width W may be defined as the distance of the channel region CH in the second direction DR2. For example, the channel width W may be defined as the size of the first side S1 or the second side S2.

[0158] The channel region CH may have a Figure 7 . For example, the first side S1 and the second side S2 of the channel region CH facing each other may have an oblique line shape, so that the distance between the first side S1 and the second side S2 (for example, the distance in the first direction DR1) gradually increases along the second direction DR2. The third side S3 and the fourth side S4 facing each other may be shaped like straight lines parallel to each other. Here, the first side S1 and the second side S2 may have an oblique line shape, so that the first side S1 and the second side S2 are symmetrical with each other with respect to the second direction DR2. The length of the fourth side S4 may be greater than the length of the third side S3.

[0159] As described above, since the first side S1 and the second side S2 have an oblique line shape, the length of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase along the second direction DR2. In an embodiment, the channel region CH may have a minimum channel length Lmin at the third side S3 and a maximum channel length Lmax at the fourth side S4.

[0160] As described above, since the channel length L of the channel region CH changes along the second direction DR2, the transistor TR may have a structure in which a plurality of sub-transistors having different channel lengths L are connected in parallel. Since the plurality of sub-transistors have different channel lengths L, the plurality of threshold voltages (e.g., sub-threshold voltages) of the plurality of sub-transistors may have different values. Therefore, the variation in the current (e.g., drain current) according to the threshold voltage of the transistor TR may be reduced. Therefore, the driving range of the transistor TR can be expanded, thereby enabling detailed grayscale expression, such as fine grayscale.

[0161] Figure 8 is a plan view of a transistor TR according to an embodiment.

[0162] Figure 8 The transistor TR and Figure 7 The transistor TR of FIG. 1 is different in the shape of the active layer ACT and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0163] like Figure 8 As shown in the figure, the active layer ACT may have a meandering shape (or a rounded shape). Therefore, the channel region CH of the active layer ACT overlapping with the gate electrode GE may also have a meandering shape. For example, among the first to fourth sides S1 to S4 of the channel region CH, the third side S3 and the fourth side S4 facing each other in the second direction DR2 may have a meandering shape (or a rounded shape). In an embodiment, each of the active layer ACT and the channel region CH may have an arc shape.

[0164] Figure 9 is a plan view of a transistor TR according to an embodiment.

[0165] The active layer ACT may include the drain electrode DE, the source electrode SE, and the channel region CH of the transistor TR. The active layer ACT may have a rectangular shape with two sides bent.

[0166] The gate electrode GE may have a Figure 9 The gate insulating layer GTI may be disposed between the gate electrode GE and the active layer ACT.

[0167] The gate electrode GE may overlap the active layer ACT. The channel region CH of the transistor TR may be formed in a region where the gate electrode GE and the active layer ACT overlap. For example, Figure 9 As shown in FIG, the channel region CH may be defined as a region surrounded by a first side S1, a second side S2, a third side S3, and a fourth side S4.

[0168] The channel region CH may have a Figure 9 . For example, the first side S1 and the second side S2 facing each other of the channel region CH may have an oblique line shape, so that the distance between the first side S1 and the second side S2 gradually increases along the oblique line direction (hereinafter referred to as the first oblique line direction) between the first direction DR1 and the reverse direction of the second direction DR2 (hereinafter referred to as the second reverse direction). The third side S3 and the fourth side S4 facing each other may be shaped like straight lines parallel to each other. Here, the first side S1 and the second side S2 may have an oblique line shape, so that the first side S1 and the second side S2 are symmetrical with each other with respect to the first oblique line direction.

[0169] As described above, since the first side S1 and the second side S2 have an oblique shape, the channel length L of the channel region CH may change along the first oblique direction. For example, the channel length L of the channel region CH may gradually increase along the first oblique direction. In an embodiment, the channel region CH may have a minimum channel length Lmin at the third side S3 and a maximum channel length Lmax at the fourth side S4.

[0170] As described above, since the channel length L of the channel region CH changes along the first oblique direction, the transistor TR may have a structure in which a plurality of sub-transistors having different channel lengths L are connected in parallel. Since the plurality of sub-transistors have different channel lengths L, the plurality of threshold voltages (e.g., sub-threshold voltages) of the plurality of sub-transistors may have different values. Therefore, the variation in the current (e.g., drain current) according to the threshold voltage of the transistor TR may be reduced. Therefore, the driving range of the transistor TR may be expanded, thereby enabling detailed grayscale expression, e.g., fine grayscale.

[0171] Figure 10 is a plan view of a transistor TR according to an embodiment.

[0172] Figure 10 The transistor TR and Figure 9 The transistor TR of FIG. 1 is different in the shape of the active layer ACT and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0173] like Figure 10As shown in the figure, the active layer ACT may have a meandering shape (or a rounded shape). Therefore, the channel region CH of the active layer ACT overlapping with the gate electrode GE may also have a meandering shape. For example, among the first to fourth sides S1 to S4 of the channel region CH, the third side S3 and the fourth side S4 facing each other in the first oblique direction may have a meandering shape (or a rounded shape). In an embodiment, each of the active layer ACT and the channel region CH may have an arc shape.

[0174] Figure 11 is a plan view of a transistor TR according to an embodiment.

[0175] Figure 11 The transistor TR and Figure 7 The transistor TR of FIG. 1 is different in the shape of the gate electrode GE and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0176] like Figure 11 As shown in , the gate electrode GE may have a polygonal (eg, hexagonal) shape including six sides.

[0177] The active layer ACT Figure 11 The channel region CH overlapped with the gate electrode GE may have a polygonal (eg, hexagonal) shape including six sides. In other words, the channel region CH may be defined by first to sixth sides S1 to S6 in the overlapped region between the active layer ACT and the gate electrode GE.

[0178] The first and second sides S1, S2 of the channel region CH facing each other may have an oblique line shape, such that the distance between the first and second sides S1 and S2 gradually increases along the second direction DR2. The third and fourth sides S3, S4 of the channel region CH facing each other may have an oblique line shape, such that the distance between the third and fourth sides S3 and S4 gradually decreases along the second direction DR2. In addition, the fifth and sixth sides S5, S6 facing each other may be shaped like parallel straight lines. Here, the first and second sides S1, S2 may have an oblique line shape, such that the first and second sides S1 and S2 are symmetrical with respect to the second direction DR2. The third and fourth sides S3, S4 may have an oblique line shape, such that the third and fourth sides S3 and S4 are symmetrical with respect to the second direction DR2. The first and third sides S1, S3 adjacent to each other may have an oblique line shape, such that the first and third sides S1 and S3 are symmetrical with respect to the first direction DR1. The second side S2 and the fourth side S4 adjacent to each other may have an oblique line shape such that the second side S2 and the fourth side S4 are symmetrical to each other with respect to the first direction DR1 .

[0179] As described above, since each of the first side S1, the second side S2, the third side S3, and the fourth side S4 has a slanted line shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase along the second direction DR2 between the first side S1 and the second side S2, and may gradually decrease along the second direction DR2 between the third side S3 and the fourth side S4. In an embodiment, the channel region CH may have a minimum channel length Lmin at the fifth side S5 or the sixth side S6, and may have a maximum channel length Lmax between the vertex between the adjacent first side S1 and the third side S3 and the vertex between the adjacent second side S2 and the fourth side S4.

[0180] Figure 12 is a plan view of a transistor TR according to an embodiment.

[0181] Figure 12 The transistor TR and Figure 7 The transistor TR of FIG. 1 is different in the shape of the gate electrode GE and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0182] like Figure 12 As shown in FIG, the gate electrode GE may have a polygonal shape including ten sides.

[0183] The active layer ACT Figure 12 The channel region CH overlapped by the gate electrode GE may have a polygonal shape including ten sides. In other words, the channel region CH may be defined by the first side S1 to the tenth side S10 in the overlapping region between the active layer ACT and the gate electrode GE. For example, Figure 12 The channel region CH may have a polygonal shape including a first region having a quadrilateral shape (for example, a quadrilateral region including the fifth side S5, the sixth side S6 and the ninth side S9), a second region having a quadrilateral shape (for example, a quadrilateral region including the seventh side S7, the eighth side S8 and the tenth side S10), and a third region arranged between the first region and the second region and having a hexagonal shape (for example, a hexagonal region including the first side S1, the second side S2, the third side S3 and the fourth side S4).

[0184] The first and second sides S1, S2 of the channel region CH facing each other may have an oblique line shape, such that the distance between the first and second sides S1 and S2 gradually increases along the second direction DR2. The third and fourth sides S3, S4 of the channel region CH facing each other may have an oblique line shape, such that the distance between the third and fourth sides S3 and S4 gradually decreases along the second direction DR2. Furthermore, the fifth and sixth sides S5, S6 facing each other may be shaped like parallel straight lines, the seventh and eighth sides S7, S8 facing each other may be shaped like parallel straight lines, and the ninth and tenth sides S9, S10 facing each other may be shaped like parallel straight lines. Here, the first and second sides S1, S2 may have an oblique line shape, such that the first and second sides S1, S2 are symmetrical with respect to the second direction DR2. The third and fourth sides S3, S4 may have an oblique line shape, such that the third and fourth sides S3, S4 are symmetrical with respect to the second direction DR2. The first side S1 and the third side S3 adjacent to each other may have an oblique line shape so that the first side S1 and the third side S3 are symmetrical with each other relative to the first direction DR1. The second side S2 and the fourth side S4 adjacent to each other may have an oblique line shape so that the second side S2 and the fourth side S4 are symmetrical with each other relative to the first direction DR1.

[0185] As described above, since each of the first side S1, the second side S2, the third side S3, and the fourth side S4 has a slanted line shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase along the second direction DR2 between the first side S1 and the second side S2, and may gradually decrease along the second direction DR2 between the third side S3 and the fourth side S4. In an embodiment, the channel region CH may have a minimum channel length Lmin at the ninth side S9 or the tenth side S10, and may have a maximum channel length Lmax between the vertex between the adjacent first side S1 and the third side S3 and the vertex between the adjacent second side S2 and the fourth side S4.

[0186] Figure 13 is a plan view of a transistor TR according to an embodiment.

[0187] Figure 13 The transistor TR and Figure 7 The transistor TR of FIG. 1 is different in the shape of the gate electrode GE and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0188] like Figure 13 As shown in FIG, the gate electrode GE may have a polygonal shape including twelve sides.

[0189] The active layer ACT Figure 13The channel region CH overlapped by the gate electrode GE may have a polygonal shape including twelve sides. In other words, the channel region CH may be defined by the first side S1 to the twelfth side S12 in the overlapping region between the active layer ACT and the gate electrode GE. For example, Figure 13 The channel region CH may have a polygonal shape including a first region having a quadrilateral shape (for example, a quadrilateral region including the seventh side S7, the eighth side S8 and the eleventh side S11), a second region having a quadrilateral shape (for example, a quadrilateral region including the ninth side S9, the tenth side S10 and the twelfth side S12), and a third region arranged between the first region and the second region and having an octagonal shape (for example, an octagonal region including the first side S1, the second side S2, the third side S3, the fourth side S4, the fifth side S5 and the sixth side S6).

[0190] The first and second sides S1, S2 of the channel region CH facing each other may have an oblique line shape, such that the distance between the first and second sides S1 and S2 gradually increases along the second direction DR2. The fifth and sixth sides S5, S6 of the channel region CH facing each other may have an oblique line shape, such that the distance between the fifth and sixth sides S5 and S6 gradually decreases along the second direction DR2. Furthermore, the third and fourth sides S3, S4 facing each other may be shaped like parallel straight lines, the seventh and eighth sides S7, S8 facing each other may be shaped like parallel straight lines, the ninth and tenth sides S9, S10 facing each other may be shaped like parallel straight lines, and the eleventh and twelfth sides S11, S12 facing each other may be shaped like parallel straight lines. Here, the first and second sides S1, S2 may have an oblique line shape, such that the first and second sides S1, S2 are symmetrical with respect to the second direction DR2. The fifth and sixth sides S5, S6 may have an oblique line shape, such that the fifth and sixth sides S5, S6 are symmetrical with respect to the second direction DR2. The first side S1 and the fifth side S5, which are respectively adjacent to one side and the other side of the third side S3, may have an oblique line shape so that the first side S1 and the fifth side S5 are symmetrical with each other relative to the first direction DR1. The second side S2 and the sixth side S6, which are respectively adjacent to one side and the other side of the fourth side S4, may have an oblique line shape so that the second side S2 and the sixth side S6 are symmetrical with each other relative to the first direction DR1.

[0191] As described above, since each of the first side S1, the second side S2, the fifth side S5, and the sixth side S6 has a slanted line shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase along the second direction DR2 between the first side S1 and the second side S2, and may gradually decrease along the second direction DR2 between the fifth side S5 and the sixth side S6. In an embodiment, the channel region CH may have a minimum channel length Lmin at the eleventh side S11 or the twelfth side S12, and may have a maximum channel length Lmax between the third side S3 and the fourth side S4 facing each other in the first direction DR1.

[0192] Figure 14 is a plan view of a transistor TR according to an embodiment.

[0193] Figure 14 The transistor TR and Figure 7 The transistor TR of FIG. 1 is different in the shape of the gate electrode GE and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0194] like Figure 14 As shown in FIG, the gate electrode GE may have a polygonal shape including eight sides.

[0195] The active layer ACT Figure 14 The channel region CH overlapped by the gate electrode GE may have a polygonal shape including eight sides. In other words, the channel region CH may be defined by the first side S1 to the eighth side S8 in the overlapping region between the active layer ACT and the gate electrode GE. Here, each of the first side S1 and the second side S2 facing each other in the first direction DR1 may have a parabolic (or bent) shape. For example, the first side S1 may have a parabolic shape that is convex in the reverse direction of the first direction DR1 (hereinafter referred to as the first reverse direction), and the second side S2 may have a parabolic shape that is convex in the first direction DR1. The first side S1 and the second side S2 may be symmetrical to each other with respect to the second direction DR2. For example, Figure 14 The channel region CH may have a polygonal shape including a first region having a quadrilateral shape (e.g., a quadrilateral region including the third side S3, the fourth side S4, and the seventh side S7), a second region having a quadrilateral shape (e.g., a quadrilateral region including the fifth side S5, the sixth side S6, and the eighth side S8), and a third region arranged between the first and second regions and having an elliptical shape (e.g., a region including the first side S1 and the second side S2). The entire third region may overlap with the active layer ACT.

[0196] As described above, since each of the first side S1 and the second side S2 has a parabolic shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase or decrease along the second direction DR2 between the first side S1 and the second side S2. In an embodiment, the channel region CH may have a minimum channel length Lmin at the seventh side S7 or the eighth side S8, and may have a maximum channel length Lmax between the center of the first side S1 and the center of the second side S2.

[0197] Figure 15 is a plan view of a transistor TR according to an embodiment.

[0198] Figure 15 The transistor TR and Figure 14 The transistor TR of FIG. 1 is different in the shape of the active layer ACT and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0199] like Figure 15 , the channel region CH may have a polygonal shape including four sides. In other words, the channel region CH may be defined by the first side S1 to the fourth side S4 in the overlapping region between the active layer ACT and the gate electrode GE. Here, each of the first side S1 and the second side S2 facing each other in the first direction DR1 may have a parabolic (or meandering) shape. For example, the first side S1 may have a parabolic shape that is convex in the reverse direction of the first direction DR1 (hereinafter referred to as the first reverse direction), and the second side S2 may have a parabolic shape that is convex in the first direction DR1. The first side S1 and the second side S2 may be symmetrical with each other with respect to the second direction DR2.

[0200] As described above, since each of the first side S1 and the second side S2 has a parabolic shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase or decrease along the second direction DR2 between the first side S1 and the second side S2. In an embodiment, the channel region CH may have a minimum channel length Lmin at the third side S3 or the fourth side S4, and may have a maximum channel length Lmax between the center of the first side S1 and the center of the second side S2.

[0201] Figure 16 is a plan view of a transistor TR according to an embodiment.

[0202] Figure 16 The transistor TR and Figure 12 The transistor TR of FIG. 1 is different in the shape of the active layer ACT and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0203] like Figure 16 As shown in FIG, the gate electrode GE may have a polygonal shape including ten sides.

[0204] like Figure 16 , the channel region CH may have a polygonal shape including ten sides. In other words, the channel region CH may be defined by first to tenth sides S1 to S10 in the overlapping region between the active layer ACT and the gate electrode GE.

[0205] The first and second sides S1, S2 of the channel region CH facing each other may have an oblique line shape, such that the distance between the first and second sides S1 and S2 gradually decreases along the second direction DR2. The third and fourth sides S3, S4 of the channel region CH facing each other may have an oblique line shape, such that the distance between the third and fourth sides S3 and S4 gradually increases along the second direction DR2. In addition, the fifth and sixth sides S5, S6 facing each other may be shaped like parallel straight lines, the seventh and eighth sides S7, S8 facing each other may be shaped like parallel straight lines, and the ninth and tenth sides S9, S10 facing each other may be shaped like parallel straight lines. Here, the first and second sides S1, S2 may have an oblique line shape, such that the first and second sides S1, S2 are symmetrical with respect to the second direction DR2. The third and fourth sides S3, S4 may have an oblique line shape, such that they are symmetrical with respect to the second direction DR2. The first side S1 and the third side S3 adjacent to each other may have an oblique line shape so that the first side S1 and the third side S3 are symmetrical to each other with respect to the first direction DR1. The second side S2 and the fourth side S4 adjacent to each other may have an oblique line shape so that the second side S2 and the fourth side S4 are symmetrical to each other with respect to the first direction DR1. For example, Figure 16 The channel region CH may have a polygonal shape, which includes a first region having a quadrilateral shape (for example, a quadrilateral region including the fifth side S5, the sixth side S6 and the ninth side S9), a second region having a quadrilateral shape (for example, a quadrilateral region including the seventh side S7, the eighth side S8 and the tenth side S10), a third region arranged between the first region and the second region and having a trapezoidal shape (for example, a trapezoidal region including the first side S1 and the second side S2), and a fourth region arranged between the second region and the third region and having an inverted trapezoidal shape (for example, an inverted trapezoidal region including the third side S3 and the fourth side S4).

[0206] As described above, since each of the first side S1, the second side S2, the third side S3, and the fourth side S4 has a slanted line shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually decrease along the second direction DR2 between the first side S1 and the second side S2, and may gradually increase along the second direction DR2 between the third side S3 and the fourth side S4. In an embodiment, the channel region CH may have a maximum channel length Lmax at the ninth side S9 or the tenth side S10, and may have a minimum channel length Lmin between the vertex between the adjacent first side S1 and the third side S3 and the vertex between the adjacent second side S2 and the fourth side S4.

[0207] Figure 17 is a plan view of a transistor TR according to an embodiment.

[0208] Figure 17 The transistor TR and Figure 13 The transistor TR of FIG. 1 is different in the shape of the active layer ACT and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0209] like Figure 17 As shown in FIG, the gate electrode GE may have a polygonal shape including twelve sides.

[0210] like Figure 17 , the channel region CH may have a polygonal shape including twelve sides. In other words, the channel region CH may be defined by the first side S1 to the twelfth side S12 in the overlapping region between the active layer ACT and the gate electrode GE. For example, Figure 17 The channel region CH may have a polygonal shape, which includes a first region having a quadrilateral shape (for example, a quadrilateral region including the seventh side S7, the eighth side S8 and the eleventh side S11), a second region having a quadrilateral shape (for example, a quadrilateral region including the ninth side S9, the tenth side S10 and the twelfth side S12), a third region arranged between the first region and the second region and having a trapezoidal shape (for example, a trapezoidal region including the first side S1 and the second side S2), a fourth region arranged between the third region and the second region and having an inverted trapezoidal shape (for example, an inverted trapezoidal region including the fifth side S5 and the sixth side S6), and a fifth region arranged between the fourth region and the third region and having a quadrilateral shape (for example, a quadrilateral region including the third side S3 and the fourth side S4).

[0211] The first and second sides S1, S2 of the channel region CH facing each other may have an oblique line shape, such that the distance between the first and second sides S1 and S2 gradually decreases along the second direction DR2. The fifth and sixth sides S5, S6 of the channel region CH facing each other may have an oblique line shape, such that the distance between the fifth and sixth sides S5 and S6 gradually increases along the second direction DR2. Furthermore, the third and fourth sides S3, S4 facing each other may be shaped like parallel straight lines, the seventh and eighth sides S7, S8 facing each other may be shaped like parallel straight lines, the ninth and tenth sides S9, S10 facing each other may be shaped like parallel straight lines, and the eleventh and twelfth sides S11, S12 facing each other may be shaped like parallel straight lines. Here, the first and second sides S1, S2 may have an oblique line shape, such that the first and second sides S1, S2 are symmetrical with respect to the second direction DR2. The fifth and sixth sides S5, S6 may have an oblique line shape, such that the fifth and sixth sides S5, S6 are symmetrical with respect to the second direction DR2. The first side S1 and the fifth side S5, which are respectively adjacent to one side and the other side of the third side S3, may have an oblique line shape so that the first side S1 and the fifth side S5 are symmetrical with each other relative to the first direction DR1. The second side S2 and the sixth side S6, which are respectively adjacent to one side and the other side of the fourth side S4, may have an oblique line shape so that the second side S2 and the sixth side S6 are symmetrical with each other relative to the first direction DR1.

[0212] As described above, since each of the first side S1, the second side S2, the fifth side S5, and the sixth side S6 has a slanted line shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually decrease along the second direction DR2 between the first side S1 and the second side S2, and may gradually increase along the second direction DR2 between the fifth side S5 and the sixth side S6. In an embodiment, the channel region CH may have a maximum channel length Lmax at the eleventh side S11 or the twelfth side S12, and may have a minimum channel length Lmin between the third side S3 and the fourth side S4 facing each other in the first direction DR1.

[0213] Figure 18 is a plan view of a transistor TR according to an embodiment.

[0214] Figure 18 The transistor TR and Figure 14 The transistor TR of FIG. 1 is different in the shape of the active layer ACT and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0215] like Figure 18 As shown in FIG, the gate electrode GE may have a polygonal shape including eight sides.

[0216] like Figure 18 As shown in the figure, the channel region CH may have a polygonal shape including eight sides. In other words, the channel region CH may be defined by the first side S1 to the eighth side S8 in the overlapping area between the active layer ACT and the gate electrode GE. Here, each of the first side S1 and the second side S2 facing each other in the first direction DR1 may have a parabolic (or bent) shape. For example, the first side S1 may have a parabolic shape that is convex in the first direction DR1 (or concave in the first direction DR1), and the second side S2 may have a parabolic shape that is convex in the first direction DR1 (or concave in the first direction DR1), and the second side S2 may have a parabolic shape that is convex in the first reverse direction (or concave in the first reverse direction). The first side S1 and the second side S2 may be symmetrical to each other with respect to the second direction DR2. For example, Figure 18 The channel region CH may have semicircular grooves respectively formed on two sides facing each other in the first direction DR1.

[0217] As described above, since each of the first side S1 and the second side S2 has a parabolic shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually increase or decrease along the second direction DR2 between the first side S1 and the second side S2. In an embodiment, the channel region CH may have a maximum channel length Lmax at the seventh side S7 or the eighth side S8, and may have a minimum channel length Lmin between the center of the first side S1 and the center of the second side S2.

[0218] Figure 19 is a plan view of a transistor TR according to an embodiment.

[0219] Figure 19 The transistor TR and Figure 17 The transistor TR of FIG. 1 is different in the shape of the gate electrode GE and the shape of the channel region CH. Therefore, for the sake of brevity, the following description will focus on such differences.

[0220] like Figure 19 As shown in FIG, the gate electrode GE may have a polygonal shape including twelve sides.

[0221] like Figure 19 , the channel region CH may have a polygonal shape including twelve sides. In other words, the channel region CH may be defined by first to twelfth sides S1 to S12 in the overlapping region between the active layer ACT and the gate electrode GE.

[0222] The first side S1 and the second side S2 of the channel region CH facing each other may have a curved (or rounded) shape, such that the distance between the first side S1 and the second side S2 gradually decreases along the second direction DR2. The fifth side S5 and the sixth side S6 of the channel region CH facing each other may have a curved (or rounded) shape, such that the distance between the fifth side S5 and the sixth side S6 gradually increases along the second direction DR2. In addition, the third side S3 and the fourth side S4 facing each other may be shaped like parallel straight lines, the seventh side S7 and the eighth side S8 facing each other may be shaped like parallel straight lines, the ninth side S9 and the tenth side S10 facing each other may be shaped like parallel straight lines, and the eleventh side S11 and the twelfth side S12 facing each other may be shaped like parallel straight lines. Here, the first side S1 and the second side S2 may have a curved shape, such that the first side S1 and the second side S2 are symmetrical with respect to the second direction DR2. The fifth side S5 and the sixth side S6 may have a bent shape so that the fifth side S5 and the sixth side S6 are symmetrical with respect to the second direction DR2. The first side S1 and the fifth side S5 adjacent to one side and the other side of the third side S3, respectively, may have a bent shape so that the first side S1 and the fifth side S5 are symmetrical with respect to the first direction DR1. The second side S2 and the sixth side S6 adjacent to one side and the other side of the fourth side S4, respectively, may have a bent shape so that the second side S2 and the sixth side S6 are symmetrical with respect to the first direction DR1. For example, Figure 19 The channel region CH may have semi-elliptical grooves respectively formed on two sides facing each other in the first direction DR1.

[0223] As described above, since each of the first side S1, the second side S2, the fifth side S5, and the sixth side S6 has a meander shape, the channel length L of the channel region CH may vary along the second direction DR2. For example, the channel length L of the channel region CH may gradually decrease along the second direction DR2 between the first side S1 and the second side S2, and may gradually increase along the second direction DR2 between the fifth side S5 and the sixth side S6. In an embodiment, the channel region CH may have a maximum channel length Lmax at the eleventh side S11 or the twelfth side S12, and may have a minimum channel length Lmin between the third side S3 and the fourth side S4, which face each other in the first direction DR1.

[0224] Figure 20 is a plan view of a transistor TR according to an embodiment.

[0225] like Figure 20 As shown in , the gate electrode GE may include a first gate electrode GE1 and a second gate electrode GE2 .

[0226] Figure 20 The transistor TR may include a first sub-transistor STR1 and a second sub-transistor STR2 connected in series.

[0227] The first sub-transistor STR1 may include a first gate electrode GE1 , a first drain electrode DE1 , and a first source electrode SE1 .

[0228] The second sub-transistor STR2 may include a second gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2. The second drain electrode DE2 of the second sub-transistor STR2 may be connected to the first source electrode SE1 of the first sub-transistor STR1. For example, the second drain electrode DE2 and the first source electrode SE1 may be formed integrally with each other.

[0229] The active layer ACT may include a first drain electrode DE1, a first source electrode SE1, a first channel region CH1, a second drain electrode DE2, a second source electrode SE2, and a second channel region CH2. The active layer ACT may have a rectangular shape.

[0230] The first gate electrode GE1 may have Figure 20 The gate insulating layer GTI may be disposed between the first gate electrode GE1 and the active layer ACT.

[0231] The first gate electrode GE1 may overlap the active layer ACT. The first channel region CH1 of the first sub-transistor STR1 may be formed in a region where the first gate electrode GE1 overlaps the active layer ACT. Figure 20 As shown in FIG, the first channel region CH1 may be defined as a region surrounded by a first side S1, a second side S2, a third side S3, and a fourth side S4.

[0232] A portion of the active layer ACT that is adjacent to one side of the first channel region CH1 and does not overlap with the first gate electrode GE1 and the second gate electrode GE2 may be defined as a first drain electrode DE1 of the first sub-transistor STR1, and a portion of the active layer ACT that is adjacent to the other side of the first channel region CH1 and does not overlap with the first gate electrode GE1 and the second gate electrode GE2 may be defined as a first source electrode SE1 of the first sub-transistor STR1.

[0233] The channel length L of the first channel region CH1 may be defined as the distance between the first drain electrode DE1 and the first source electrode SE1, and the channel width of the first channel region CH1 may be defined as the length of the facing surfaces of the first drain electrode DE1 and the first source electrode SE1. Figure 20 In the embodiment, the channel length L may be defined as the distance of the first channel region CH1 in the first direction DR1, and the channel width may be defined as the distance of the first channel region CH1 in the second direction DR2. For example, the channel width of the first channel region CH1 may be defined as the size of the first side S1 or the second side S2.

[0234] The first channel region CH1 may have a Figure 20 For example, any one of the first side S1 and the second side S2 facing each other of the first channel region CH1 (e.g., the second side S2) may have an oblique line shape such that the distance between the first side S1 and the second side S2 (e.g., the distance in the first direction DR1) gradually decreases along the second direction DR2.

[0235] As described above, since the second side S2 has a slanted shape, the channel length L of the first channel region CH1 may vary along the second direction DR2. For example, the channel length L of the first channel region CH1 may gradually decrease along the second direction DR2. In an embodiment, the first channel region CH1 may have a maximum channel length Lmax at the third side S3 and a minimum channel length Lmin at the fourth side S4.

[0236] The gate electrode GE may have a slit 555 positioned between the first and second gate electrodes GE1 and GE2, and the active layer ACT may be exposed through the slit 555. For example, the first source electrode SE1 and the second drain electrode DE2 of the active layer ACT may overlap the slit 555 of the gate electrode GE.

[0237] Since the channel length L of the first channel region CH1 changes along the second direction DR2, the first sub-transistor STR1 can have a structure in which multiple 1-1 sub-transistors having different channel lengths L are connected in parallel. Since the multiple 1-1 sub-transistors have multiple different channel lengths L, the threshold voltages (e.g., sub-threshold voltages) of the multiple 1-1 sub-transistors can have different values. Therefore, the variation in current (e.g., drain current) depending on the threshold voltage of the first sub-transistor STR1 can be reduced. Therefore, the driving range of the first sub-transistor STR1 can be expanded, thereby enabling detailed grayscale expression, such as fine grayscale.

[0238] The second gate electrode GE2 may have Figure 20 Here, the second gate electrode GE2 and the first gate electrode GE1 may be symmetrical (e.g., point-symmetrical) to each other. In other words, when the first gate electrode GE1 has a trapezoidal shape, the second gate electrode GE2 may have an inverted trapezoidal shape. The gate insulating layer GTI may be arranged between the second gate electrode GE2 and the active layer ACT.

[0239] The second gate electrode GE2 may overlap the active layer ACT. The second channel region CH2 of the second sub-transistor STR2 may be formed in a region where the second gate electrode GE2 overlaps the active layer ACT. Figure 20 As shown in FIG, the second channel region CH2 may be defined as a region surrounded by a first side S1 ′, a second side S2 ′, a third side S3 ′, and a fourth side S4 ′.

[0240] A portion of the active layer ACT that is adjacent to one side of the second channel region CH2 and does not overlap with the first gate electrode GE1 and the second gate electrode GE2 may be defined as a second drain electrode DE2 of the second sub-transistor STR2, and a portion of the active layer ACT that is adjacent to the other side of the second channel region CH2 and does not overlap with the first gate electrode GE1 and the second gate electrode GE2 may be defined as a second source electrode SE2 of the second sub-transistor STR2.

[0241] The channel length L' of the second channel region CH2 may be defined as the distance between the second drain electrode DE2 and the second source electrode SE2, and the channel width of the second channel region CH2 may be defined as the length of the facing surfaces of the second drain electrode DE2 and the second source electrode SE2. Figure 20 In the embodiment of the present invention, the channel length L' can be defined as the distance of the second channel region CH2 in the first direction DR1, and the channel width can be defined as the distance of the second channel region CH2 in the second direction DR2. For example, the channel width of the second channel region CH2 can be defined as the size of the first side S1' or the second side S2'. The second channel region CH2 and the first channel region CH1 can be adjacent to each other in the first direction DR1.

[0242] The second channel region CH2 may have a Figure 20 For example, any one of the first side S1′ and the second side S2′ facing each other of the second channel region CH2 (e.g., the first side S1′) may have an oblique line shape such that the distance between the first side S1′ and the second side S2′ (e.g., the distance in the first direction DR1) gradually increases along the second direction DR2.

[0243] As described above, since the first side S1' has a slanted shape, the channel length L' of the second channel region CH2 may vary along the second direction DR2. For example, the channel length L' of the second channel region CH2 may gradually decrease along the second direction DR2. In an embodiment, the second channel region CH2 may have a minimum channel length Lmin' at the third side S3' and a maximum channel length Lmax' at the fourth side S4'.

[0244] Because the channel length L' of the second channel region CH2 changes along the second direction DR2, the second sub-transistor STR2 can have a structure in which multiple first-second sub-transistors having different channel lengths L' are connected in parallel. Since the multiple first-second sub-transistors have multiple different channel lengths L', the threshold voltages (e.g., sub-threshold voltages) of the multiple first-second sub-transistors can have different values. Therefore, the variation in current (e.g., drain current) depending on the threshold voltage of the second sub-transistor STR2 can be reduced. Therefore, the driving range of the second sub-transistor STR2 can be expanded, thereby enabling detailed grayscale expression, such as fine grayscale.

[0245] above Figures 7 to 20 At least one of the plurality of transistors TR may be applied to Figure 6 For example, the channel region CH of the first transistor T1 may have a variable channel length L, such as Figures 7 to 20 The channel region CH of any one of the plurality of transistors TR is the same.

[0246] In an embodiment, the first gate electrode GE1 and the active layer ACT of the first transistor T1 may be connected to Figures 7 to 20 The gate electrode GE and the active layer ACT of any one of the plurality of transistors TR have the same configuration.

[0247] In addition, in an embodiment, the second gate electrode GE2 of the first transistor T1 and the active layer ACT may be connected to Figures 7 to 20 The gate electrode GE and the active layer ACT of any one of the plurality of transistors TR have the same configuration.

[0248] In addition, in an embodiment, the first gate electrode GE1 and the second gate electrode GE2 of the first transistor T1 may be connected to Figures 7 to 20 The gate electrode GE of any one of the plurality of transistors TR has the same configuration. In addition, the active layer ACT of the first transistor T1 may be connected to the gate electrode GE of the plurality of transistors TR. Figures 7 to 20 The active layer ACT of any one of the plurality of transistors TR has the same configuration.

[0249] In addition, in an embodiment, the first gate electrode GE1 and the active layer ACT of the first transistor T1 may be connected to Figures 7 to 20 The gate electrode GE and the active layer ACT of any one of the plurality of transistors TR have the same configuration. In addition, the second gate electrode GE2 of the first transistor T1 may have, for example, a quadrilateral shape so that the channel region CH formed in the overlapping region between the second gate electrode GE2 and the active layer ACT has a fixed channel length.

[0250] In addition, in an embodiment, the second gate electrode GE2 of the first transistor T1 and the active layer ACT may be connected to Figures 7 to 20 The gate electrode GE and the active layer ACT of any one of the plurality of transistors TR have the same configuration. In addition, the first gate electrode GE1 of the first transistor T1 may have, for example, a quadrilateral shape so that the channel region CH formed in the overlapping region between the first gate electrode GE1 and the active layer ACT has a fixed channel length.

[0251] Figure 21 is a diagram for explaining the operation of the transistor TR of the display device 10 according to the embodiment.

[0252] Figure 211 , a characteristic curve CC1 of a comparative transistor TR (hereinafter referred to as a first characteristic curve CC1) and a characteristic curve CC2 of a transistor TR included in the display device 10 according to an embodiment (hereinafter referred to as a second characteristic curve CC2) are illustrated. The X-axis represents the magnitude of the gate-source voltage of the transistor TR, and the Y-axis represents the magnitude of the current (e.g., drain current) of the transistor TR.

[0253] The first characteristic curve CC1 is a curve of gate-source voltage and drain current for each channel length L when the channel length L of the transistor TR is fixed. Figure 21 , six first characteristic curves CC1 are sequentially illustrated from the left in the order of characteristic curve 1-1, characteristic curve 1-2, characteristic curve 1-3, characteristic curve 1-4, characteristic curve 1-5, and characteristic curve 1-6. Here, characteristic curve 1-1 may be a characteristic curve when the channel length L of transistor TR is approximately 4 μm. Characteristic curve 1-2 may be a characteristic curve when the channel length L of transistor TR is approximately 5 μm. Characteristic curve 1-3 may be a characteristic curve when the channel length L of transistor TR is approximately 6 μm. Characteristic curve 1-4 may be a characteristic curve when the channel length L of transistor TR is approximately 7 μm. Characteristic curve 1-5 may be a characteristic curve when the channel length L of transistor TR is approximately 8 μm. Characteristic curve 1-6 may be a characteristic curve when the channel length L of transistor TR is approximately 9 μm.

[0254] The second characteristic curve CC2 is a curve of gate-source voltage and drain current for each range of channel length L when the channel length L of the transistor TR is variable. Figure 21 , four second characteristic curves CC2 are sequentially illustrated in the order of the 2-1st characteristic curve, the 2-2nd characteristic curve, the 2-3rd characteristic curve, and the 2-4th characteristic curve from the left. Here, the 2-1st characteristic curve may be a characteristic curve when the channel length L of the transistor TR is in the range of about 4 μm to about 9 μm. The 2-2nd characteristic curve may be a characteristic curve when the channel length L of the transistor TR is in the range of about 5 μm to about 9 μm. The 2-3rd characteristic curve may be a characteristic curve when the channel length L of the transistor TR is in the range of about 6 μm to about 9 μm. The 2-4th characteristic curve may be a characteristic curve when the channel length L of the transistor TR is in the range of about 7 μm to about 9 μm.

[0255] like Figure 21As shown in FIG, the slope of the second characteristic curve CC2 is smaller than the slope of the first characteristic curve CC1. Therefore, the transistor TR included in the display device 10 according to the embodiment can ensure a wider driving range than the comparative transistor TR.

[0256] The display device according to the present disclosure is capable of expressing fine grayscales due to an expanded driving range.

[0257] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, characterized in that: include: an active layer disposed on a substrate; a gate electrode disposed on the active layer to overlap with the active layer and define a channel region of the active layer; a pixel electrode, the pixel electrode being arranged on the gate electrode; a light-emitting layer, the light-emitting layer being arranged on the pixel electrode; as well as a common electrode, the common electrode being arranged on the light-emitting layer, In which, in the channel region, the channel region has a channel length in a first direction, and at least one side of the channel region that defines the channel length has an oblique line shape or a bent shape, so that the channel length changes in a second direction intersecting the first direction.

2. The display device according to claim 1, wherein The channel region has a trapezoidal shape, wherein the gate electrode has a trapezoidal shape, and Wherein, the active layer has a rectangular shape.

3. The display device according to claim 1, wherein The gate electrode has a quadrilateral shape, and Herein, the active layer has a quadrilateral shape with two sides bent inward or outward relative to each other.

4. The display device according to claim 1, wherein The channel region has an arc shape, wherein the gate electrode has a trapezoidal shape, and Wherein, the active layer has an arc shape.

5. The display device according to claim 1, wherein The gate electrode has a quadrilateral shape, and Wherein, the active layer has an arc shape.

6. The display device according to claim 1, wherein The channel region has a hexagonal shape, and Wherein, the gate electrode has a hexagonal shape.

7. The display device according to claim 1, wherein The channel region includes: a first region having a quadrilateral shape; a second region having a quadrilateral shape; and A third region is disposed between the first region and the second region and has a hexagonal shape.

8. The display device according to claim 1, wherein The channel region includes: a first region having a quadrilateral shape; a second region having a quadrilateral shape; and A third region is disposed between the first region and the second region and has an octagonal shape.

9. The display device according to claim 1, wherein The channel region includes: a first region having a quadrilateral shape; a second region having a quadrilateral shape; and A third region is disposed between the first region and the second region and has an elliptical shape.

10. The display device according to claim 1, wherein The channel region includes: a first region having a quadrilateral shape; a second region having a quadrilateral shape; a third region disposed between the first region and the second region and having a trapezoidal shape; and A fourth region is disposed between the second region and the third region and has an inverted trapezoidal shape.

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