Display device

Abstract

The present application relates to a display device including: a first electrode on a substrate; a pixel defining layer on the first electrode; a separation layer on the pixel defining layer and having a void and an opening partially exposing the void; a light emitting unit on the first electrode and the separation layer, the light emitting unit being separated at an opening in the separation layer; and a second electrode on the light emitting unit and covering the opening in the separation layer.

Description

TECHNICAL FIELD

[0001] Aspects of embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. BACKGROUND

[0002] Recently, as interest in information display increases, research and development of display devices are continuously conducted. SUMMARY

[0003] Embodiments of the present disclosure provide a display device exhibiting improved reliability and a method of manufacturing the display device.

[0004] Aspects and features of the present disclosure are not limited to those described above, and other aspects and features not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] According to embodiments of the present disclosure, a display device includes a first electrode on a substrate, a pixel-defining layer on the first electrode, a separation layer on the pixel-defining layer and having a void and an opening partially exposing the void, a light-emitting unit on the first electrode and the separation layer and separated at the opening in the separation layer, and a second electrode on the light-emitting unit and covering the opening in the separation layer.

[0006] The display device can further include a conductive layer on the pixel-defining layer.

[0007] The separation layer can at least partially surround the conductive layer.

[0008] The conductive layer can be in the void.

[0009] The separation layer can include an inorganic material.

[0010] The pixel-defining layer can have a first area overlapping the void and a second area outside the first area, and a thickness of the first area can be the same as a thickness of the second area.

[0011] The pixel-defining layer can have a first area overlapping the void and a second area outside the first area, and a thickness of the first area can be less than a thickness of the second area.

[0012] The substrate can include a first sub-pixel and a second sub-pixel adjacent to each other, and the separation layer can be at a boundary between the first sub-pixel and the second sub-pixel.

[0013] The light-emitting unit of the first sub-pixel and the light-emitting unit of the second sub-pixel can be separated at the opening in the separation layer.

[0014] The second electrode of the first sub-pixel and the second electrode of the second sub-pixel can be connected over the opening in the separation layer.

[0015] According to an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a first electrode on a substrate; forming a pixel defining layer on the first electrode; forming a metal layer on the pixel defining layer; forming a separation layer on the metal layer; forming an opening in the separation layer to at least partially expose the metal layer; etching the metal layer; and forming a light-emitting unit on the first electrode and the separation layer.

[0016] During the etching of the metal layer, the metal layer may be removed to form a gap between the pixel defining layer and the separation layer.

[0017] During the etching of the metal layer, the pixel defining layer may be partially etched.

[0018] The light emitting units may be separated at gaps.

[0019] The method of manufacturing a display device may further include forming a second electrode on the light emitting unit.

[0020] The second electrode may cover the opening in the separation layer.

[0021] The method of manufacturing a display device may further include forming a conductive layer on the pixel defining layer.

[0022] The metal layer may be formed directly on the conductive layer.

[0023] During the etching of the metal layer, the pixel defining layer may be covered by the conductive layer.

[0024] The separation layer may at least partially surround the conductive layer.

[0025] Additional aspects and features, as well as details and descriptions of other embodiments, are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the disclosure and together with the description describe aspects and features of the disclosure.

[0027] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0028] Figure 2 It shows Figure 1 is a block diagram of an embodiment of one sub-pixel of a display device shown in .

[0029] Figure 3 It shows Figure 2 Circuit diagram of an embodiment of a sub-pixel shown in .

[0030] Figure 4 It shows Figure 1 A plan view of an embodiment of a display panel is shown in FIG.

[0031] Figure 5 It shows Figure 4 An exploded perspective view of a portion of a display panel is shown in FIG.

[0032] Figure 6 It shows Figure 5 1 is a plan view of an embodiment of one pixel of a display panel shown in .

[0033] Figure 7 It is along Figure 6 A cross-sectional view taken along line II' in FIG.

[0034] Figure 8 yes Figure 7 A cross-sectional view of the separation layer shown in FIG.

[0035] Figure 9 According to another embodiment, Figure 6 A cross-sectional view taken along line II' in FIG.

[0036] Figure 10 yes Figure 9 A cross-sectional view of the separation layer shown in FIG.

[0037] Figure 11 According to another embodiment Figure 9 A cross-sectional view of the separation layer shown in FIG.

[0038] Figure 12 Including from Figure 7 A cross-sectional view of a light emitting structure in one of the first to third light emitting elements shown in .

[0039] Figure 13 According to another embodiment, Figure 7 A cross-sectional view of a light emitting structure in one of the first to third light emitting elements shown in .

[0040] Figure 14 According to another embodiment Figure 5 A plan view of one of the pixels shown in FIG.

[0041] Figure 15 According to another embodiment Figure 5 A plan view of one of the pixels shown in FIG.

[0042] Figure 16 is a block diagram illustrating an embodiment of a display system.

[0043] Figure 17 It shows Figure 16 A perspective view of an application example of the display system shown in FIG.

[0044] Figure 18 is shown as worn by the user Figure 17 FIG. 1 is a diagram of a head-mounted display device shown in FIG.

[0045] Figures 19 to 29 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment.

[0046] Figures 30 to 38 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the following description, parts necessary for understanding the aspects and features of the present disclosure are described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the present disclosure. In addition, the present disclosure may be implemented in other forms and is therefore not limited to the embodiments described herein. However, the embodiments described herein are provided to describe in sufficient detail to those skilled in the art to which the present disclosure belongs so as to easily implement the technical spirit of the present disclosure.

[0048] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may also be present. When an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For example, when a first element is described as being “coupled to” or “connected to” a second element, the first element can be directly coupled or directly connected to the second element, or the first element can be indirectly coupled or indirectly connected to the second element via one or more intervening elements.

[0049] In the accompanying drawings, for clarity of illustration, the sizes of various elements, layers, etc. may be exaggerated. The same reference numerals represent the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. In addition, when describing the embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure." Expressions, such as "at least one of" and "any one of", when located after a column of elements, modify the entire column of elements and do not modify the individual elements in the column. For example, the expression "at least one of a, b, and c" represents only a, only b, only c, a and b, a and c, b and c, a, b, and c, all or variations thereof. As used herein, the terms "use," "using," and "used" can be considered to be synonymous with the terms "utilize," "utilizing," and "utilizing," respectively. As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and are not used as degree terms, and are intended to explain the inherent variations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0050] It will be understood that although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be restricted by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of exemplary embodiments, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0051] For ease of description, spatially relative terms such as "below," "beneath," "down," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "below" or "below" other elements or features will then be oriented "above" or "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0052] The terms used herein are for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "includes," "including," "comprises," and / or "comprising," when used in this specification, specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0053] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate idealized embodiments. Therefore, it is expected that shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown and should be construed to include variations in shape that may occur, for example, due to manufacturing. As described above, the shapes shown in the accompanying drawings may not represent the actual shapes of regions of the device, and the embodiments are not limited thereto.

[0054] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0055] refer to Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0056] The display panel 110 may include subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0057] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Therefore, each of the sub-pixels SP may generate light of a specific color (such as red, green, blue, cyan, magenta, yellow, etc.). Two or more sub-pixels from the sub-pixels SP may constitute a pixel PXL. For example, in Figure 1 In the embodiment shown in FIG, three sub-pixels SP may constitute one pixel PXL.

[0058] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In some embodiments, the gate control signal GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with a timing at which data signals are applied, and the like.

[0059] In some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP and arranged in the row direction can be further provided. In such embodiments, the gate driver 120 can include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver can operate (e.g., can be controlled by) under the control of the controller 150.

[0060] The gate driver 120 can be provided on one side of the display panel 110. However, embodiments are not limited thereto. For example, the gate driver 120 can be divided into two or more drivers that are physically and / or logically separated. Such drivers can be provided on one side of the display panel 110 and on another side of the display panel 110 opposite the one side. Accordingly, the gate driver 120 can be arranged around the display panel 110 in various shapes according to embodiments.

[0061] The data driver 130 can be connected to the sub-pixels SP arranged in a column direction through first to n-th data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In some embodiments, the data control signal DCS can include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0062] The data driver 130 can apply data signals having a gray scale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn by using a voltage from the voltage generator 140. The data signals corresponding to the image data DATA can be applied to the data lines DL1 to DLn when the gate signals are applied to each of the first to m-th gate lines GL1 to GLm. Accordingly, the corresponding sub-pixels SP can generate light corresponding to the data signals. Thus, an image can be displayed on the display panel 110.

[0063] In some embodiments, the gate driver 120 and the data driver 130 can include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0064] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and may provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to receive an input voltage from outside the display device 100, adjust the received voltage, and regulate the adjusted voltage to generate a plurality of voltages.

[0065] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and second power supply voltage VSS may be provided to the subpixel SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a lower voltage level than the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided from a device external to the display device 100.

[0066] In addition, the voltage generator 140 can generate various voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a predetermined reference voltage) can be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 can generate the reference voltage.

[0067] The controller 150 may control various operations of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0068] The controller 150 may convert the input image data IMG into data suitable for the display device 100 or the display panel 110 to output the image data DATA. In some embodiments, the controller 150 may align the input image data IMG to fit the sub-pixels SP in a row unit to output the image data DATA.

[0069] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on a single integrated circuit. Figure 1As shown in FIG, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In such an embodiment, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within a single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as another component separate from the driver integrated circuit DIC.

[0070] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature of its surrounding environment and generate temperature data TEP representing the sensed temperature. In some embodiments, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0071] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0072] Figure 2 It shows Figure 1 FIG. 1 is a block diagram of an embodiment of one of the sub-pixels in the display panel 110 shown in FIG. Figure 2 In the figure, the arrangement is shown in Figure 1 The subpixel SPij in the i-th row and j-th column among the subpixels SP shown in is taken as an example, where i may be an integer greater than or equal to 1 and less than or equal to m, and j may be an integer greater than or equal to 1 and less than or equal to n.

[0073] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0074] The light emitting element LD may be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be a node transmitting a first power supply voltage VDD, and the second power supply voltage node VSSN may be a node transmitting a second power supply voltage VSS.

[0075] The anode electrode AE ​​of the light-emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0076] The sub-pixel circuit SPC can be connected to the Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm shown in FIG. Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm and the Figure 1 The j-th data line DLj among the first to n-th data lines DL1 to DLn is shown in FIG. The sub-pixel circuit SPC may be configured to control the light emitting element LD according to signals received through these signal lines.

[0077] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In some embodiments, such as Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0078] The sub-pixel circuit SPC may operate in response to an emission control signal received via the i-th emission control line ELi. In some embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received via the corresponding sub-emission control line.

[0079] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can regulate the current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN through the light-emitting element LD according to the stored voltage in response to the emission control signal received via the i-th emission control line ELi. Consequently, the light-emitting element LD can generate light having a brightness corresponding to the data signal.

[0080] Figure 3 It shows Figure 2 Circuit diagram of an embodiment of a sub-pixel shown in .

[0081] refer to Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0082] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi shown in FIG, the i-th gate line GLi′ may further include a third sub-gate line SGL3. Figure 2 Compared to the i-th emission control line ELi shown in FIG, the i-th emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0083] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0084] The first transistor T1 may be connected between the first power supply voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2. Therefore, the first transistor T1 may be turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0085] The second transistor T2 may be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1. Therefore, the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0086] The third transistor T3 may be connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2. Therefore, the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub-emission control line SEL2. Therefore, the fourth transistor T4 may be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0088] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN may be configured to transmit an initialization voltage. In some embodiments, the initialization voltage may be from, for example, Figure 1 . In other embodiments, the initialization voltage may be provided by a device external to the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3. Therefore, the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0089] The sixth transistor T6 may be connected between the first power supply voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub-emission control line SEL1. Therefore, the sixth transistor T6 may be turned on in response to the emission control signal of the first sub-emission control line SEL1.

[0090] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The second capacitor C2 may be connected between the first power supply voltage node VDDN and the second node N2.

[0091] Therefore, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. However, embodiments are not limited thereto. The sub-pixel circuit SPC may be implemented as one of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may be variable.

[0092] The first to sixth transistors T1 to T6 may be P-type transistors. Each of the first to sixth transistors T1 to T6 may be a MOSFET (metal oxide silicon field effect transistor). However, the embodiment is not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 may be an N-type transistor.

[0093] In some embodiments, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0094] The light emitting element LD can include an anode electrode AE, a cathode electrode CE, and a light emitting layer. The light emitting layer can be disposed between the anode electrode AE and the cathode electrode CE. After a data signal transmitted through the jth data line DLj is reflected on a voltage at the second node N2, the emission control signals of the first sub emission control line SEL1 and the second sub emission control line SEL2 are enabled at a low level, and the fourth transistor T4 and the sixth transistor T6 can be turned on. The first transistor T1 can be turned on according to the voltage at the second node N2. Accordingly, a current can flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD can emit light according to the amount of current flowing therethrough.

[0095] Figure 4 is a plan view illustrating an embodiment of the display panel shown in Figure 1

[0096] Referring to Figure 4 , Figure 1 The display panel DP of the display panel 110 shown in FIG. 1 can have a display area DA and a non-display area NDA. The display panel DP can display an image at the display area DA. The non-display area NDA can be disposed around the display area DA.

[0097] The display panel DP can include a substrate SUB, a sub-pixel SP, and a pad PD.

[0098] When the display panel DP is used as a display screen for a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP can be positioned very close to a user's eyes. In such an embodiment, it can be necessary to have a sub-pixel SP having a relatively high integration. To increase the integration of the sub-pixel SP, the substrate SUB can be provided as a silicon substrate. The sub-pixel SP and / or the display panel DP can be formed on the silicon substrate. A display device 100 (see, e.g., FIG. 1) including the display panel DP formed on the substrate SUB can be referred to as an OLED on silicon (OLEDoS) display device. Figure 1

[0099] The sub-pixel SP can be disposed in the display area DA on the substrate SUB. The sub-pixel SP can be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, embodiments are not limited thereto. For example, the sub-pixel SP can be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixel SP can be arranged in a honeycomb shape along the first direction DR1 and the second direction DR2. The shape ( is a registered trademark of Samsung Display Co., Ltd.), also referred to as a diamond pattern. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction. ​​

[0100] Two or more sub-pixels from among the plurality of sub-pixels SP may constitute one pixel PXL.

[0101] Components for controlling the sub-pixels SP may be provided in the non-display area NDA on the substrate SUB. Figure 1 Wiring lines connected to the sub-pixels SP of the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn shown in FIG. 5 may be disposed in the non-display area NDA.

[0102] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 shown in FIG may be integrated in the non-display area NDA of the display panel DP. In some embodiments, Figure 1 The gate driver 120 shown in FIG can be mounted on the display panel DP and disposed in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In some embodiments, a temperature sensor 160 can be disposed in the non-display area NDA to detect the temperature of the display panel DP.

[0103] The pad PD may be provided in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a wiring. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0104] The pads PD can connect the display panel DP to other components of the display device 100 (see, for example, Figure 1 In some embodiments, voltages and signals required for the operation of components included in the display panel DP can be received from the display panel DP through the pads PD. Figure 1 . For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC via the pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS can be received from the driver integrated circuit DIC via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pad PD.

[0105] In some embodiments, the circuit board can be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. In such embodiments, the circuit board can be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC can be mounted on the circuit board and electrically connected to the pad PD.

[0106] In some embodiments, the display area DA may have various shapes. The display area DA may have a closed loop shape with straight and / or curved sides. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, or an ellipse.

[0107] In some embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have an at least partially rounded display surface. In some embodiments, the display panel DP may be curved, folded, or rolled. In these embodiments, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0108] Figure 5 It shows Figure 4 An exploded perspective view of a portion of the display panel is shown in FIG. Figure 5 In the embodiment, for the sake of clarity and simplicity, the display panel DP is schematically shown. Figure 4 Portions corresponding to two pixels PXL1 and PXL2 among the pixels PXL shown in FIG. Portions corresponding to the remaining pixels of the display panel DP may be similarly configured.

[0109] refer to Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0110] Figure 5 The embodiment in which the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 have a square shape and the same size when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 is shown. However, the embodiment is not limited thereto. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may have various shapes.

[0111] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0112] In some embodiments, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon germanium. The substrate SUB may also be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0113] The pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a portion of a circuit element, wiring, or the like. The conductive pattern may include copper, but embodiments are not limited thereto.

[0114] The circuit element may include a sub-pixel circuit SPC of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see, for example, Figure 2 ). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion having a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by the first direction DR1 and the second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, with an insulating layer interposed therebetween.

[0115] The wiring of the pixel circuit layer PCL may include a signal line connected to each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3, for example, a gate line, an emission control line, a data line, etc. The wiring may also include a signal line connected to each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. Figure 2 The wiring may also include a wiring connected to the first power supply voltage node VDDN shown in FIG. Figure 2 The wiring of the second power supply voltage node VSSN is shown in .

[0116] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0117] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0118] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may have an opening OP exposing a portion of the anode electrode AE. The opening OP in the pixel defining layer PDL may be understood as an emission region corresponding to the first to third subpixels SP1 to SP3.

[0119] In some embodiments, the pixel defining layer PDL may include an inorganic material. In such an embodiment, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0120] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP in the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, etc.

[0121] In some embodiments, the light emitting structure EMS may fill the opening OP in the pixel defining layer PDL and may be completely disposed on the upper surface of the pixel defining layer PDL. The light emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In such an embodiment, at least some of the layers in the light emitting structure EMS may be separated (e.g., disconnected) or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, embodiments are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and the separated light emitting structures EMS may be disposed within the opening OP in the pixel defining layer PDL.

[0122] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third subpixels SP1 to SP3. Therefore, the cathode electrode CE may serve as a common electrode of the first to third subpixels SP1 to SP3.

[0123] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0124] One of the anode electrodes AE, a portion of the light emitting structure EMS overlapping with the anode electrode AE, and a portion of the cathode electrode CE overlapping with the anode electrode AE ​​may be understood to constitute one light emitting element LD (see, for example Figure 2 Each of the light-emitting elements of the first to third subpixels SP1 to SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS that overlaps with the anode electrode AE, and a portion of the cathode electrode CE that overlaps with the anode electrode AE. In each of the first to third subpixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light-emitting layer of the light-emitting structure EMS to generate excitons. When the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined by the amount of current flowing through the light-emitting layer. The wavelength range of the generated light may be determined by the configuration of the light-emitting layer.

[0125] The encapsulation layer TFE may be provided on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In some embodiments, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked with each other. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), etc. However, the materials of the organic layer and the inorganic layer constituting the encapsulation layer TFE are not limited thereto.

[0126] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO xThe thin film containing aluminum oxide may be located on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0127] The thin film containing aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0128] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0129] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EMS to selectively output light in a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3. Each of the color filters CF may transmit light in a wavelength range corresponding to each sub-pixel. For example, the color filter corresponding to the first sub-pixel SP1 may transmit red light, the color filter corresponding to the second sub-pixel SP2 may transmit green light, and the color filter corresponding to the third sub-pixel SP3 may transmit blue light. Depending on the light emitted from the light emitting structure EMS of each sub-pixel, at least some of the color filters CF may be omitted.

[0130] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3. Each lens LS may improve light output efficiency by outputting light emitted from the light-emitting structure EMS along a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the overcoat layer OC. In some embodiments, the lenses LS may include an organic material. In some embodiments, the lenses LS may include an acrylic material. However, the material of the lenses LS is not limited thereto.

[0131] In some embodiments, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be displaced in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the openings OP in the pixel defining layer PDL. For example, in a central region of the display area DA, when viewed in a third direction DR3, the centers of the color filters and the lenses may be aligned with or overlap with the centers of the openings OP in the pixel defining layer PDL. For example, in the central region of the display area DA, the openings OP in the pixel defining layer PDL may completely overlap with the corresponding color filters of the color filter layer CFL and the corresponding lenses of the lens array LA. In a region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the centers of the color filters and the lenses may be displaced in a planar direction from the centers of the openings OP in the pixel defining layer PDL. For example, in a region of the display area DA adjacent to the non-display area NDA, the openings OP in the pixel defining layer PDL may partially overlap with the corresponding color filters of the color filter layer CFL and the corresponding lenses of the lens array LA. Therefore, in the central area of ​​the display area DA, light emitted from the light emitting structure EMS can be efficiently output in the normal direction of the display surface. In the peripheral area of ​​the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction inclined at an angle (e.g., a predetermined angle) relative to the normal direction of the display surface.

[0132] An overcoat layer (OC) may be disposed on the lens array LA. The overcoat layer (OC) may cover the optical function layer (OFL), the encapsulation layer (TFE), the light emitting structure (EMS), and / or the pixel circuit layer (PCL). The overcoat layer (OC) may include various materials suitable for protecting underlying layers from foreign matter such as dust and moisture. For example, the overcoat layer (OC) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OC) may include epoxy resin, but embodiments are not limited thereto. The overcoat layer (OC) may have a lower refractive index than the lens array (LA).

[0133] A cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect underlying layers. The cover window CW may have a higher refractive index than the overcoat layer OC. The cover window CW may comprise glass, but embodiments are not limited thereto. For example, the cover window CW may be encapsulating glass configured to protect underlying components. In other embodiments, the cover window CW may be omitted.

[0134] Figure 6 It shows Figure 5 For clarity and simplicity of description, Figure 6 Schematically shows the Figure 5The first pixel PXL1 among the first and second pixels PXL1 and PXL2 shown in FIG. The remaining pixels may be configured similarly to the first pixel PXL1.

[0135] refer to Figure 5 and Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0136] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA surrounding the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA surrounding the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA surrounding the third emission area EMA3.

[0137] The first emission area EMA1 may be a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1 (see, for example, Figure 5 ) emits light. The second emission area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 5 As described, each emission region may be understood as an opening OP in the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0138] Figure 7 It is along Figure 6 A cross-sectional view taken along line II' in FIG. Figure 8 yes Figure 7 A cross-sectional view of the separation layer shown in FIG. Figure 9 According to another embodiment, Figure 6 A cross-sectional view taken along line II' in FIG. Figure 10 yes Figure 9 A cross-sectional view of the separation layer shown in FIG. Figure 11 According to another embodiment Figure 9 A cross-sectional view of the separation layer shown in FIG.

[0139] refer to Figure 7 , a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB may be provided.

[0140] The substrate SUB may include a silicon wafer substrate formed by a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0141] The pixel circuit layer PCL may be provided on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC included in the first sub-pixel SP1 (see, for example, FIG. 2 ). Figure 2 ). The transistor T_SP2 of the second sub-pixel SP2 may be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 , for clarity and concise illustration, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0142] The transistor T_SP1 of the first sub-pixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0143] The source region SRA and the drain region DRA may be disposed within the substrate SUB. A well WL formed by an ion implantation process may be disposed within the substrate SUB, and the source region SRA and the drain region DRA may be disposed to be spaced apart from each other within the well WL. The region between the source region SRA and the drain region DRA within the well WL may be defined as a channel region.

[0144] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0145] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain area DRA via a drain connection portion DRC penetrating (or extending through) one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source area SRA via a source connection portion SRC penetrating (or extending through) one or more insulating layers.

[0146] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or wirings, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the transistors of the first subpixel SP1.

[0147] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured similarly to the transistor T_SP1 of the first subpixel SP1 .

[0148] Therefore, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0149] The through hole layer VIAL may be provided on the pixel circuit layer PCL. The through hole layer VIAL may cover the pixel circuit layer PCL and may have an entire flat surface. The through hole layer VIAL may be configured to flatten the step difference of the pixel circuit layer PCL. The through hole layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbon nitride (SiCN), but the embodiment is not limited thereto.

[0150] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0151] On the via layer VIAL, first to third reflective electrodes RE1 to RE3 may be disposed in the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 may contact circuit elements disposed in the pixel circuit layer PCL via a via hole penetrating (or extending through) the via layer VIAL.

[0152] The first to third reflective electrodes RE1 to RE3 may function as reflectors (e.g., total reflectors) that reflect light emitted from the light emitting structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but embodiments are not limited thereto.

[0153] In some embodiments, a connecting electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but embodiments are not limited thereto. In some embodiments, the corresponding reflective electrode may be positioned between multiple layers of the connecting electrode.

[0154] A buffer pattern BFP may be provided below at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but embodiments are not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP may be provided between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0155] The first to third reflective electrodes RE1 to RE3 can function as reflectors (e.g., full reflectors), and the cathode electrode CE can function as a semi-reflective mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by at least partially reciprocating between the corresponding reflective electrodes and the cathode electrode CE. The amplified light can be output through the cathode electrode CE. As described above, the distance between each reflective electrode and the cathode electrode CE can be understood as a resonant distance for light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0156] Due to the buffer pattern BFP, the first subpixel SP1 can have a shorter resonance distance than other subpixels. The resonance distance adjusted in this way can effectively and efficiently amplify light within a specific wavelength range (e.g., red). Therefore, the first subpixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0157] Figure 7An embodiment is shown in which the buffer pattern BFP is provided only in the first subpixel SP1, and not in the second subpixel SP2 and the third subpixel SP3. However, the embodiment is not limited thereto. The buffer pattern is provided in at least one of the second subpixel SP2 and the third subpixel SP3, so that the resonance distance of at least one of the second subpixel SP2 and the third subpixel SP3 can be adjusted. For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively. Furthermore, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0158] To flatten the step differences between the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL may be disposed on the through-hole layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may generally cover the first to third reflective electrodes RE1 to RE3 and the through-hole layer VIAL and may have a flat surface. In some embodiments, the planarization layer PLNL may be omitted.

[0159] The first to third anode electrodes AE1 to AE3 may be disposed on the planarization layer PLNL to overlap with the first to third reflective electrodes RE1 to RE3. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may have the same Figure 6 The first to third emission areas EMA1 to EMA3 may have similar shapes as shown in FIG. The first to third anode electrodes AE1 to AE3 may be connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode electrode AE1 may be connected to the first reflective electrode RE1 via a first through-hole VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 via a second through-hole VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 via a third through-hole VIA3 penetrating the planarization layer PLNL.

[0160] In some embodiments, the first to third anode electrodes AE1 to AE3 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0161] In some embodiments, an insulating layer may be further provided to adjust the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be provided between one or more of the first to third anode electrodes AE1 to AE3 and the reflective electrode. In such embodiments, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively. Furthermore, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE.

[0162] The pixel defining layer PDL may be disposed on the first to third anode electrodes AE1 to AE3 and portions of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing portions of the first to third anode electrodes AE1 to AE3. The opening OP in the pixel defining layer PDL may define emission regions of the first to third sub-pixels SP1 to SP3. As described above, the pixel defining layer PDL may be disposed on Figure 6 The non-emitting area NEA shown in FIG. Figure 6 The first emission area EMA1 to the third emission area EMA3.

[0163] According to an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of. For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked one on top of another, and each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride. However, the embodiment is not limited thereto. The first to third inorganic insulating layers may have a step-shaped cross-section in a region adjacent to the opening OP, but the present disclosure is not limited thereto.

[0164] The separation layer SPR may be provided in the boundary area BDA between adjacent sub-pixels. As an example, the separation layer SPR may be provided Figure 4 A separation layer SPR may be disposed on the pixel defining layer PDL in each boundary region between the sub-pixels SP shown in FIG.

[0165] The separation layer SPR may cause a discontinuity to be formed in the light emitting structure EMS at the boundary area BDA. For example, the light emitting structure EMS may be separated (eg, broken) or bent in the boundary area BDA by the separation layer SPR.

[0166] like Figure 8 As shown in , the separation layer SPR may have a void VD. The separation layer SPR may have an opening partially exposing (or opening) the void VD.

[0167] Some or all of the multiple layers included in the light emitting structure EMS may be separated or bent in the boundary area BDA through the opening in the separation layer SPR or through the void VD exposed by the opening in the separation layer SPR. Some or all of the multiple layers included in the light emitting structure EMS may be separated or bent on the opening in the separation layer SPR or on the void VD exposed by the opening in the separation layer SPR. For example, at least one charge generation layer included in the light emitting structure EMS may be separated in the boundary area BDA through the opening in the separation layer SPR or through the void VD exposed by the opening in the separation layer SPR.

[0168] The separation layer SPR may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials, but the present disclosure is not limited thereto.

[0169] The conductive layer CL may be further disposed on the pixel defining layer PDL. The conductive layer CL may be disposed in the gap VD in the separation layer SPR. As an example, the separation layer SPR may at least partially surround the conductive layer CL. The conductive layer CL may include titanium (Ti), but the present disclosure is not limited thereto.

[0170] like Figures 9 to 11 As shown in , the conductive layer CL may be omitted according to the embodiment. In such an embodiment, the pixel defining layer PDL may be at least partially exposed by the void VD in the separation layer SPR. The pixel defining layer PDL may have a first area A1 overlapping with the void VD in the separation layer SPR and a second area A2 excluding the first area A1 (or in addition to the first area A1). Figure 10As shown in FIG, the thickness H1 of the first area A1 of the pixel defining layer PDL may be the same as the thickness H2 of the second area A2. Figure 11 As shown in FIG, a thickness H1 of the first area A1 of the pixel defining layer PDL may be smaller than a thickness H2 of the second area A2, but the present disclosure is not limited thereto.

[0171] The light emitting structure EMS may be disposed on the anode electrode AE ​​and the separation layer SPR. The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP in the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP in the pixel defining layer PDL and may be disposed to completely span the first to third subpixels SP1 to SP3.

[0172] As described above, the light emitting structure EMS may be at least partially separated or bent in the boundary area BDA by the separation layer SPR. As an example, the light emitting structure EMS may be separated in the boundary area BDA by an opening of the separation layer SPR or by a gap VD exposed by an opening in the separation layer SPR. The light emitting structure EMS may be at least partially separated or bent on the opening in the separation layer SPR or on the gap VD exposed by the opening in the separation layer SPR. Therefore, when the display panel DP is operating, the current flowing from each of the first to third sub-pixels SP1 to SP3 to the adjacent sub-pixels through the layer included in the light emitting structure EMS may be reduced. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0173] The cathode electrode CE may be provided on the light emitting structure EMS. The cathode electrode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0174] The cathode electrode CE may cover the opening in the separation layer SPR or the void VD exposed by the opening in the separation layer SPR. The cathode electrode CE may be connected in the boundary area BDA and provided in common to the first to third subpixels SP1 to SP3. In the boundary area BDA, the cathode electrode CE may be connected to (or above) the opening in the separation layer SPR or to (or above) the void VD exposed by the opening in the separation layer SPR.

[0175] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and a portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and a portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and a portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LD3.

[0176] The encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0177] The optically functional layer OFL can be disposed on the encapsulation layer TFE. In some embodiments, the optically functional layer OFL can be attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optically functional layer OFL can be manufactured separately and attached to the encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL can also protect underlying layers including the encapsulation layer TFE.

[0178] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1 to SP3. The first to third color filters CF1 to CF3 may transmit light of different wavelength ranges. For example, the first to third color filters CF1 to CF3 may transmit red light, green light, and blue light, respectively.

[0179] In some embodiments, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be disposed between the first to third color filters CF1 to CF3.

[0180] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3. The first, second, and third lenses LS1, LS2, and LS3 may improve light output efficiency by outputting light emitted from the first to third light-emitting elements LD1 to LD3 along a desired path.

[0181] Figure 12 is included in Figure 7 A cross-sectional view of a light emitting structure in one of the first to third light emitting elements shown in .

[0182] refer to Figure 12 , the light emitting structure EMS may have a series structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 shown in FIG is configured substantially the same.

[0183] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0184] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first and second hole transport units HTU1 and HTU2 may have the same configuration or different configurations.

[0185] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0186] A connection layer, which may be provided in the form of a charge generation layer CGL, may be provided between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect them to each other. In some embodiments, the charge generation layer CGL may have a stacked structure including a p-type dopant layer and an n-type dopant layer. For example, the p-type dopant layer may include a p-type dopant such as HAT-CN, TCNQ, NDP-9, etc., and the n-type dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, embodiments are not limited thereto.

[0187] In some embodiments, the first and second light emitting layers EML1 and EML2 can generate different colors of light. The light emitted from each of the first and second light emitting layers EML1 and EML2 can mix and be visually recognized as white light. For example, the first light emitting layer EML1 can generate blue light, and the second light emitting layer EML2 can generate yellow light. In some embodiments, the second light emitting layer EML2 can include a stacked structure of a first sub light emitting layer configured to generate red light and a second sub light emitting layer configured to generate green light. The red and green light can mix to provide yellow light. In such embodiments, a middle layer configured to transport holes and / or block transport of electrons can be further disposed between the first and second sub light emitting layers.

[0188] In other embodiments, the first and second light emitting layers EML1 and EML2 can generate the same color of light.

[0189] The light emitting structure EMS can be formed by a method such as vacuum deposition, inkjet printing, etc., but embodiments are not limited thereto.

[0190] Figure 13 is a cross-sectional view of a light emitting structure included in one of the first to third light emitting elements shown in Figure 7 FIG. 1.

[0191] Referring to Figure 13 , the light emitting structure EMS' can have a series structure in which the first to third light emitting units EU1' to EU3' are stacked. The light emitting structure EMS' can be configured substantially identically in each of the first to third light emitting elements LD1 to LD3 shown in Figure 7 FIG. 1.

[0192] Each of the first to third light emitting units EU1' to EU3' can include a light emitting layer that generates light according to an applied current. The first light emitting unit EU1' can include a first light emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light emitting layer EML1' can be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light emitting unit EU2' can include a second light emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light emitting layer EML2' can be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light emitting unit EU3' can include a third light emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light emitting layer EML3' can be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0193] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration or different configurations.

[0194] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0195] The first charge generation layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0196] In some embodiments, the first to third light-emitting layers EML1' to EML3' may generate light of different colors. The light emitted from each of the first to third light-emitting layers EML1' to EML3' may be mixed and visually recognized as white light. For example, the first light-emitting layer EML1' may generate blue light, the second light-emitting layer EML2' may generate green light, and the third light-emitting layer EML3' may generate red light.

[0197] In other embodiments, two or more of the first to third light emitting layers EML1 ′ to EML3 ′ may generate light of the same color.

[0198] and Figure 12 and Figure 13 The implementation shown in Figure 7 The light emitting structure EMS shown in FIG may include one light emitting unit in each of the first to third light emitting elements LD1 to LD3. In such an embodiment, the light emitting unit included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light emitting unit of the first light emitting element LD1 may emit red light, the light emitting unit of the second light emitting element LD2 may emit green light, and the light emitting unit of the third light emitting element LD3 may emit blue light. In such an embodiment, Figure 7 Unlike the embodiment shown in , the light emitting units of the first to third subpixels SP1 to SP3 may be separated from each other, and each of them may be disposed within an opening OP in the pixel defining layer PDL. In such an embodiment, at least some of the color filters CF1 to CF3 may be omitted.

[0199] Figure 14 According to another embodiment Figure 5 A plan view of one of the pixels shown in FIG.

[0200] refer to Figure 14 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0201] The first subpixel SP1′ may have a first emission area EMA1′ and a non-emission area NEA′ surrounding the first emission area EMA1′. The second subpixel SP2′ may have a second emission area EMA2′ and a non-emission area NEA′ surrounding the second emission area EMA2′. The third subpixel SP3′ may have a third emission area EMA3′ and a non-emission area NEA′ surrounding the third emission area EMA3′.

[0202] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2. The third subpixel SP3' may be arranged in the first direction DR1 with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0203] The second subpixel SP2' may have an area larger than the first subpixel SP1', and the third subpixel SP3' may have an area larger than the second subpixel SP2'. Therefore, the second emission area EMA2' may have an area larger than the first emission area EMA1', and the third emission area EMA3' may have an area larger than the second emission area EMA2'. However, embodiments are not limited thereto. For example, the first subpixel SP1' and the second subpixel SP2' may have substantially the same area, and the third subpixel SP3' may have an area larger than each of the first subpixel SP1' and the second subpixel SP2'. Therefore, the areas of the first to third subpixels SP1' to SP3' may vary depending on the embodiment.

[0204] Figure 15 According to another embodiment Figure 5 A plan view of one of the pixels shown in FIG.

[0205] refer to Figure 15, the first pixel PXL1” may include first to third sub-pixels SP1”. The first sub-pixel SP1” may have a first emission area EMA1” and a non-emission area NEA” around the first emission area EMA1”. The second sub-pixel SP2” may have a second emission area EMA2” and a non-emission area NEA” around the second emission area EMA2”. The third sub-pixel SP3” may have a third emission area EMA3” and a non-emission area NEA” around the third emission area EMA3”.

[0206] When viewed in the third direction DR3, the first to third sub-pixels SP1 ″ to SP3 ″ may have polygonal shapes. For example, the first to third sub-pixels SP1 ″ to SP3 ″ may have polygonal shapes. Figure 11 The hexagonal shape shown in .

[0207] When viewed in the third direction DR3 , the first to third emission areas EMA1 ″ to EMA3 ″ may have a circular shape. However, embodiments are not limited thereto. For example, each of the first to third emission areas EMA1 ″ to EMA3 ″ may have a polygonal shape.

[0208] The first subpixel SP1 ″ and the third subpixel SP3 ″ may be arranged in the first direction DR1 . With respect to the first subpixel SP1 ″, the second subpixel SP2 ″ may be arranged in a direction inclined (or diagonally inclined) at an acute angle with respect to the second direction DR2 .

[0209] Figure 6 、 Figure 14 and Figure 15 The arrangement of the sub-pixels shown in the figure is only an example, and the embodiment is not limited thereto. Each pixel may include two or more sub-pixels, and the sub-pixels may be arranged in various ways. Each of the sub-pixels may have various shapes, and each of the emission areas may also have various shapes.

[0210] Figure 16 is a block diagram illustrating an embodiment of a display system.

[0211] refer to Figure 16 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0212] The processor 1100 can perform various tasks and calculations. In some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system and control other components of the display system 1000.

[0213] Figure 16 An embodiment is shown in which the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and may be connected to the second display device 1220 through a second channel CH2.

[0214] The processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can communicate with the reference Figure 1 In such an embodiment, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 The input image data IMG and control signal CTRL are shown in FIG.

[0215] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is similarly configured. In such an embodiment, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 The input image data IMG and control signal CTRL are shown in FIG.

[0216] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smartphone, a tablet personal computer, a smartwatch, a watch phone, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0217] Figure 17 It shows Figure 16 A perspective view of an application example of the display system shown in FIG.

[0218] refer to Figure 17 , Figure 16 The display system 1000 shown in FIG. 1 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on a user's head.

[0219] The head-mounted display device 2000 may include a head-mounted strap 2100 and a display device storage box 2200. The head-mounted strap 2100 may be connected to the display device storage box 2200. The head-mounted strap 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to surround the sides of the user's head (e.g., extend around the sides of the user's head), and the vertical strap may be configured to surround the top of the user's head (e.g., extend around the top of the user's head). However, embodiments are not limited thereto. For example, the head-mounted strap 2100 may be implemented in the form of a glasses frame, a helmet, etc.

[0220] The display device storage box 2200 can accommodate Figure 12 The first display device 1210 and the second display device 1220 are shown in FIG. The display device storage box 2200 can also accommodate Figure 12 The processor 1100 shown in FIG.

[0221] Figure 18 is shown as worn by the user Figure 17 FIG. 1 is a diagram of a head-mounted display device shown in FIG.

[0222] refer to Figure 18 In the head mounted display device 2000, a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220 may be provided. The head mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0223] The right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user in the display device storage box 2200. The left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user in the display device storage box 2200.

[0224] The image output from the first display panel DP1 can be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 to guide it toward the user's right eye. The right-eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0225] The image output from the second display panel DP2 can be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 to guide it toward the user's left eye. The left-eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0226] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a flat cross-section. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In such embodiments, each display panel may output an image corresponding to a sub-region of the multi-channel lens, and the output image may pass through the corresponding sub-region and be displayed to the user.

[0227] Next, a method of manufacturing the display device according to the above-described embodiment will be described.

[0228] Figures 19 to 29 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment. Figures 19 to 29 Describes manufacturing Figure 7 and Figure 8 For ease of description, components are briefly shown and some reference numerals are omitted.

[0229] refer to Figure 19 First, the anode electrode AE ​​may be formed on the substrate SUB, and first to third anode electrodes AE1 to AE3 may be formed on the planarization layer PLNL to overlap with the first to third reflective electrodes RE1 to RE3, respectively.

[0230] refer to Figure 20 Next, a pixel defining layer (PDL) may be formed on the anode electrode AE ​​and the planarization layer PLNL. The pixel defining layer (PDL) may have (eg, may be formed, processed, or etched to have) an opening OP exposing portions of the first to third anode electrodes AE1 to AE3.

[0231] refer to Figure 21 , a conductive layer CL and a separation layer SPR may be formed on the pixel definition layer PDL. Figure 7 ) is formed in a conductive layer CL and a separation layer SPR.

[0232] refer to Figure 22 First, a conductive layer CL may be formed on the pixel definition layer PDL. Figure 4 ) process, the conductive layer CL is formed simultaneously, but the present disclosure is not limited thereto.

[0233] refer to Figure 23 , the metal layer ML may be formed on the conductive layer CL. The metal layer ML may be directly formed on the conductive layer CL.

[0234] refer to Figure 24, a separation layer SPR may be formed on the metal layer ML. The separation layer SPR may be made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ), but the present disclosure is not limited thereto.

[0235] refer to Figure 25 , the separation layer SPR may be partially removed to form an opening. The opening in the separation layer SPR may at least partially expose the metal layer ML.

[0236] refer to Figure 26 , the metal layer ML may be etched. The metal layer ML below the separation layer SPR may be removed through the opening in the separation layer SPR.

[0237] In the process of etching the metal layer ML, due to the difference in etching ratio between the metal layer ML and the conductive layer CL, the metal layer ML can be selectively etched. For example, in the step of etching the metal layer ML, the pixel defining layer PDL can be covered by the conductive layer CL. For this purpose, the conductive layer CL can be formed of titanium (Ti), and the metal layer ML can be formed of aluminum (Al). However, the materials constituting the metal layer ML and the conductive layer CL are not limited thereto, and can be changed in various ways within the range that the metal layer ML can be selectively etched. As described above, when the metal layer ML provided below the separation layer SPR is removed, a gap VD can be formed between the pixel defining layer PDL and the separation layer SPR. The conductive layer CL can be formed in the gap VD and at least partially surrounded by the separation layer SPR.

[0238] refer to Figure 27 , a light emitting structure EMS may be formed on the anode electrode AE ​​and the separation layer SPR. The light emitting structure EMS may be formed in the boundary area BDA (see, for example, FIG. 1 ) through the opening in the separation layer SPR or the void VD exposed by the opening in the separation layer SPR. Figure 7 Some or all of the plurality of layers included in the light emitting structure EMS may be separated or bent on the opening in the separation layer SPR or on the void VD exposed by the opening in the separation layer SPR.

[0239] refer to Figure 28, a cathode electrode CE may be formed on the light emitting structure EMS. The cathode electrode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0240] The cathode electrode CE may cover the opening in the separation layer SPR or the void VD exposed by the opening in the separation layer SPR. The cathode electrode CE may be connected to the boundary area BDA (see, for example, Figure 7 ), and may be commonly provided to the first to third sub-pixels SP1 to SP3. In the boundary area BDA, the cathode electrode CE may be connected to (e.g., above, or may continuously extend above) the opening in the separation layer SPR, or connected to the void VD exposed by the opening in the separation layer SPR.

[0241] refer to Figure 29 By sequentially forming an encapsulation layer TFE, an optical functional layer OFL, an outer coating OC and a cover window CW on the light emitting element layer LDL, the Figure 7 and Figure 8 The display device shown in .

[0242] Hereinafter, another embodiment will be described. In the following embodiment, the same components as those already described will be denoted by the same reference numerals, and overlapping descriptions will be omitted or simplified.

[0243] Figures 30 to 38 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment. Figures 30 to 38 Describes manufacturing Figures 9 to 11 For ease of description, components are briefly shown and some reference numerals are omitted.

[0244] refer to Figure 30 , a separation layer SPR may be formed on the pixel definition layer PDL. Figure 19 and Figure 20 The beginning step of the steps of forming the pixel defining layer PDL is described, so an overlapping description will be omitted.

[0245] refer to Figure 31 First, a metal layer ML may be formed on the pixel defining layer PDL. The metal layer ML may be directly formed on the pixel defining layer PDL.

[0246] refer to Figure 32 Next, a separation layer SPR may be formed on the metal layer ML. The separation layer SPR may be made of, for example, silicon oxide (SiO x ), silicon nitride (SiNx ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ), but the present disclosure is not limited thereto.

[0247] refer to Figure 33 , the separation layer SPR may be partially removed to form an opening. The opening in the separation layer SPR may at least partially expose the metal layer ML.

[0248] refer to Figure 34 and Figure 35 , the metal layer ML may be etched. The metal layer ML below the separation layer SPR may be removed through the opening in the separation layer SPR. When the metal layer ML is removed, a gap VD may be formed between the pixel defining layer PDL and the separation layer SPR. The pixel defining layer PDL may have a first region A1 overlapping with the gap VD in the separation layer SPR and a second region A2 excluding the first region A1 (e.g., in addition to the first region A1).

[0249] In an embodiment, Figure 34 As shown in FIG, the thickness H1 of the first area A1 of the pixel defining layer PDL may be the same as the thickness H2 of the second area A2. Figure 35 As shown in FIG, in the process of etching the metal layer ML, the first area A1 of the pixel defining layer PDL may be at least partially etched. Therefore, the thickness H1 of the first area A1 of the pixel defining layer PDL may be less than the thickness H2 of the second area A2, but the present disclosure is not limited thereto.

[0250] refer to Figure 36 , a light emitting structure EMS may be formed on the anode electrode AE ​​and the separation layer SPR. The light emitting structure EMS may be formed in the boundary area BDA (see, for example, FIG. 1 ) through the opening in the separation layer SPR or the void VD exposed by the opening in the separation layer SPR. Figure 7 Some or all of the plurality of layers included in the light emitting structure EMS may be separated or bent on the opening in the separation layer SPR or on the void VD exposed by the opening in the separation layer SPR.

[0251] refer to Figure 37, a cathode electrode CE may be formed on the light emitting structure EMS. The cathode electrode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0252] The cathode electrode CE may cover the opening in the separation layer SPR or the void VD exposed by the opening in the separation layer SPR. The cathode electrode CE may be connected to the boundary area BDA (see, for example, Figure 7 ) in the boundary area BDA (for example, it may continuously extend across the boundary area BDA) and may be commonly provided to the first to third sub-pixels SP1 to SP3. In the boundary area BDA, the cathode electrode CE may be connected to the opening in the separation layer SPR (for example, it may extend above the opening in the separation layer SPR) or connected to the gap VD exposed by the opening in the separation layer SPR.

[0253] refer to Figure 38 By sequentially forming an encapsulation layer TFE, an optical functional layer OFL, an outer coating OC and a cover window CW on the light emitting element layer LDL, the Figures 9 to 11 The display device shown in .

[0254] According to the above embodiment, a part or all of the light emitting structure can be separated by the separation layer formed in the boundary region between adjacent sub-pixels, thereby reducing or minimizing the current flowing to the adjacent sub-pixels.

[0255] The aspects and features of the present disclosure are not limited to the above-mentioned aspects, features and descriptions, and many more various other aspects and features are included in this specification.

[0256] Although embodiments and implementations thereof have been described herein, other embodiments and modifications may be derived from the foregoing description. Therefore, the spirit of the present disclosure is not limited to the foregoing embodiments, but may also be applied to the claims set forth below and their equivalents.

Claims

1. A display device, characterized in that: include: a first electrode on the substrate; a pixel defining layer, on the first electrode; a separation layer on the pixel defining layer and having a gap and an opening partially exposing the gap; a light emitting unit on the first electrode and the separation layer, the light emitting unit being separated at the opening in the separation layer; as well as The second electrode is on the light emitting unit and covers the opening in the separation layer.

2. The display device according to claim 1, wherein A conductive layer is also included on the pixel defining layer.

3. The display device according to claim 2, wherein: The separation layer at least partially surrounds the conductive layer.

4. The display device according to claim 2, wherein: The conductive layer is in the gap.

5. The display device according to claim 4, wherein: The separation layer includes an inorganic material.

6. The display device according to claim 4, wherein: The pixel defining layer has a first region overlapping the gap and a second region outside the first region, and The thickness of the first region is the same as the thickness of the second region.

7. The display device according to claim 4, wherein: The pixel defining layer has a first region overlapping the gap and a second region outside the first region, and The thickness of the first region is smaller than the thickness of the second region.

8. The display device according to claim 4, wherein: The substrate includes a first sub-pixel and a second sub-pixel adjacent to each other, and The separation layer is located at a boundary between the first sub-pixel and the second sub-pixel.

9. The display device according to claim 8, wherein The light emitting unit of the first sub-pixel and the light emitting unit of the second sub-pixel are separated at the opening in the separation layer.

10. The display device according to claim 8, wherein The second electrode of the first sub-pixel and the second electrode of the second sub-pixel are connected over the opening in the separation layer.

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