Display device

Abstract

The present disclosure relates to a display device capable of reducing or minimizing a defect rate thereof. According to one or more embodiments of the present disclosure, a display device includes: a first pixel including a first pixel circuit and a first light emitting element, the first pixel circuit being separated from a portion of the first light emitting element; and a second pixel including a second pixel circuit and a second light emitting element, the second pixel circuit being separated from a portion of the second light emitting element and connected to a portion of the first light emitting element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0167531, filed on November 28, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a display device that can reduce its defect rate and a method of manufacturing the display device. BACKGROUND

[0004] An organic light emitting display device includes a display element whose luminance is changed by a current, for example, including an organic light emitting diode.

[0005] Such an organic light emitting display device includes a plurality of pixels that provide light of different colors. SUMMARY

[0006] Aspects of the present disclosure provide a display device that can reduce or minimize its defect rate and a method of manufacturing the display device.

[0007] According to one or more embodiments of the present disclosure, a display device includes a first pixel including a first pixel circuit and a first light emitting element, the first pixel circuit being separated from a portion of the first light emitting element, and a second pixel including a second pixel circuit and a second light emitting element, the second pixel circuit being separated from a portion of the second light emitting element and connected to a portion of the first light emitting element.

[0008] A first anode of the first light emitting element can include a first portion and a second portion separated from each other by a first cut hole penetrating the first anode, wherein a second anode of the second light emitting element includes a first portion and a second portion separated from each other by a second cut hole penetrating the second anode.

[0009] The first portion of the first anode can be connected to a first driving transistor of the first pixel circuit, wherein the first portion of the second anode is connected to a second driving transistor of the second pixel circuit.

[0010] The second portion of the first anode can be connected to a first light emitting layer of the first light emitting element and the first portion of the second anode.

[0011] The display device can further include a connection pattern connecting the second portion of the first anode to the first portion of the second anode.

[0012] The connection pattern can be in the same layer as the first anode and the second anode.

[0013] The connection pattern can include a conductive ink.

[0014] The conductive ink may include Ag ink.

[0015] The display device may further include a pixel defining layer over the connection pattern to overlap the connection pattern and defining a pixel region of the first pixel and a pixel region of the second pixel.

[0016] The gate electrode and the drain electrode of the first driving transistor of the first pixel circuit may be separated from the first pixel circuit, wherein the source electrode of the first driving transistor is separated from the first anode of the first light emitting element.

[0017] The first driving transistor of the first pixel circuit may include an active layer including a drain electrode and a source electrode and including a first portion and a second portion separated from each other by a third cutting hole penetrating the active layer.

[0018] The first portion of the active layer may include a source electrode of the first driving transistor and a channel region of the first driving transistor, wherein the second portion of the active layer includes a drain electrode of the first driving transistor.

[0019] The display device may further include an insulating layer above the first driving transistor, wherein the third cutting hole penetrates the insulating layer.

[0020] The display device may further include a first data line connected to the first pixel and a second data line connected to the second pixel.

[0021] The display device may further include a data driver for transmitting a data voltage corresponding to the first pixel to the second data line in a data input period of the first pixel.

[0022] The display device may further include a data converter for converting first digital video data corresponding to the second pixel into second digital video data corresponding to the first pixel, and for providing the second digital video data to a data driver, wherein the data driver is configured to generate a data voltage corresponding to the first pixel based on the second digital video data.

[0023] The data converter may include a lookup table having coordinate information of the coordinates of the first pixel and the coordinates of the second pixel.

[0024] The data converter is configured to convert the first digital video data into second digital video data based on the coordinates of the first pixel and the coordinates of the second pixel.

[0025] The first light-emitting element may include a green light-emitting layer, and wherein the second light-emitting element includes a red light-emitting layer or a blue light-emitting layer.

[0026] The second pixel may be adjacent to the first pixel.

[0027] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: preparing a substrate having a first driving transistor for a first pixel, a second driving transistor for a second pixel, and a first insulating layer above the first driving transistor and the second driving transistor; separating the first gate electrode of the first driving transistor from the pixel circuit of the first pixel; dividing the active layer of the first driving transistor into a first portion including a first channel region and a first source electrode and a second portion including a first drain electrode by forming a first cutting hole penetrating the first insulating layer and the active layer of the first driving transistor; forming a second insulating layer above the first insulating layer; forming a first anode connected to the first source electrode and a second anode connected to the second source electrode above the second insulating layer; dividing the first anode into a first portion connected to the first driving transistor and a second portion to be connected to the first light-emitting layer of the first pixel by forming a second cutting hole and a third cutting hole penetrating the first anode and the second anode, respectively, and dividing the second anode into a first portion connected to the second driving transistor of the second pixel and a second portion; connecting the second portion of the first anode to the first portion of the second anode; forming a pixel defining layer above the first anode and the second anode; forming a first light-emitting layer above the first anode; forming a second light-emitting layer above the second anode; and forming a cathode above the first light-emitting layer and the second light-emitting layer.

[0028] The first light-emitting layer may include a green light-emitting layer, wherein the second light-emitting layer includes a red light-emitting layer or a blue light-emitting layer.

[0029] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a circuit diagram of a display device according to one or more embodiments;

[0032] Figure 2 Is used to illustrate the repair Figure 1 A diagram of a circuit method of a display device;

[0033] Figure 3 yes Figure 2 a partial cross-sectional view of a first pixel, a second pixel, and a third pixel;

[0034] Figures 4 to 9is a cross-sectional view for explaining a method of manufacturing a display device according to one or more embodiments;

[0035] Figure 10 is a block diagram of a driving circuit of a display device according to one or more embodiments;

[0036] Figure 11 shows a lookup table included in a data converter of Figure 10 ; and

[0037] Figure 12 is a graph for explaining luminance contributions of red, green, and blue pixels of a display device. DETAILED DESCRIPTION

[0038] Aspects of some embodiments of the present disclosure and methods of realizing the same can be more readily understood by reference to the following detailed description and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, irrelevant to the description of the embodiments, or not necessary for understanding aspects of the present disclosure by one of ordinary skill in the art can be omitted. Unless otherwise specified, the same reference numbers, symbols, or combinations thereof, represent the same elements throughout the drawings and written description, and thus, repetitive description thereof can be omitted.

[0039] The described embodiments can have various modifications and can be implemented in different forms, and should not be interpreted as being limited to only the embodiments shown herein. The use of "can," "may," or "might" in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and alternatives falling within the scope of the idea and technical scope of the present disclosure. Furthermore, each of the features of the various embodiments of the present disclosure can be partially or wholly combined with each other, and various interlocks and drives are possible in the technical field. Each of the embodiments can be realized independently of each other, or can be realized together in an associated relationship.

[0040] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. Also, the use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of adjacent regions. As such, unless specifically stated otherwise, the presence of cross-hatching or shading in a drawing generally does not indicate or imply any preference or requirement for particular materials, material properties, dimensions, ratios, commonality of elements between illustrations, and / or any other characteristic, attribute, property, or the like of the elements being portrayed in the drawings.

[0041] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures for purposes of expediency and illustration. Therefore, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, embodiments disclosed herein are not limited to the precise structures described herein and illustrated in the accompanying drawings, as such embodiments can vary from the illustrated embodiments as a result, for example, of manufacturing techniques and / or tolerances.

[0042] For example, an implant region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurred.

[0043] For ease of description, spatially relative terms, such as "below", "beneath", "lower", "bottom", "under", "above", "upper", "top", and the like, can be used herein for the purpose of describing the orientation of one element or feature relative to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below", "beneath", or "under" other elements or features would then be oriented "above", "upper", or "top" relative to the other elements or features. As such, the exemplary terms "below", "beneath", and "under" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it can mean that the first part is disposed on the upper side or lower side of the second part, without being limited to a particular side based on the gravitational orientation of the device.

[0044] Furthermore, the phrase “in a schematic cross-sectional view” means when viewed from the side through a vertical cut of a portion of the object taken in a schematic cross-section. The term “overlap” or “overlapped” means that a first object can be above or below a second object, or on a side of the second object, and vice versa. Additionally, the term “overlap” can include stacking, facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by one of ordinary skill in the art. The expression “not overlap” can include the meaning of “spaced apart from” or “separated from” or “offset from” as well as any other suitable equivalent as will be appreciated and understood by one of ordinary skill in the art. The terms “face” and “facing” can mean that a first object can be directly opposite or indirectly opposite a second object. In case a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, but still facing each other.

[0045] It will be understood that when an element, layer, region or component is referred to as being “formed on” another element, layer, region or component, “on” another element, layer, region or component, “connected to” or “(operatively or communicatively) coupled to” another element, layer, region or component, it can be directly formed on, directly on, directly connected to or directly coupled to another element, layer, region or component, or indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to another element, layer, region or component, such that one or more intervening elements, layers, regions or components can exist. Moreover, this can collectively mean directly coupled or directly connected or indirectly coupled or indirectly connected as well as integrally coupled or integrally connected or non-integrally coupled or non-integrally connected. For example, when a layer, region or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region or component, it can be directly electrically connected or directly electrically coupled to another layer, region and / or component, or one or more intervening layers, regions or components can exist. The one or more intervening components can include switches, resistors, capacitors, etc. In describing implementations, expressions of connection indicate electrical connections, and “directly connected / directly coupled” or “directly on” refer to one component directly connected or directly coupled another component or directly on another component without intervening components, unless explicitly described as directly connected.

[0046] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components such as "between...", "directly between...", or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0047] For the purposes of this disclosure, expressions such as "at least one of" or "any one of" or "one or more of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases, when preceding / following a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0048] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are used only to distinguish one element, component, component, area, region, layer, section or part from another element, component, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below may be referred to as the second element, second component, second area, second layer or second section. The description of an element as a "first" element may not require or imply the presence of a second element or other element. The terms "first", "second", etc. may also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0049] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "have," "having," "includes," and "including," when used in this specification, specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0050] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously, or in a reverse order to the described order.

[0051] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within an acceptable deviation range for the particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0052] In some embodiments, known structures and devices can be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary ambiguity in various embodiments. Those skilled in the art will understand that such blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connectors and other electrical circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from those of the dedicated hardware. In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0054] Figure 1 is a circuit diagram of a display device according to one or more embodiments.

[0055] The display device may include a plurality of pixels. Figure 1 Three adjacent ones of the pixels PX1 , PX2 and PX3 are shown.

[0056] like Figure 1 As shown in FIG, the pixel may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a plurality of transistors T1, T2, and T3, at least one capacitor Cst, and at least one light emitting diode as a light emitting element.

[0057] For example, the first pixel PX1 may include a first light-emitting element ED1, the second pixel PX2 may include a second light-emitting element ED2, and the third pixel PX3 may include a third light-emitting element ED3. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may provide light of different corresponding colors. For example, the first light-emitting element ED1 may include a light-emitting layer that provides red light, the second light-emitting element ED2 may include a light-emitting layer that provides green light, and the third light-emitting element ED3 may include a light-emitting layer that provides blue light.

[0058] The first pixel PX1, the second pixel PX2, and the third pixel PX3 may have the same configuration. Therefore, the configuration of the first pixel PX1 will be described below as a representative example.

[0059] The first pixel PX1 may include a pixel circuit and a light emitting element connected to the pixel circuit. Here, the pixel circuit of the first pixel PX1 may include, for example, a driving transistor T1, a switching transistor T2, an initialization transistor T3, and a capacitor Cst.

[0060] The drain electrode and source electrode of each transistor T1, T2 or T3 described below are named so as to distinguish the two electrodes located on the corresponding sides of the channel of each transistor T1, T2 or T3. Depending on the potential difference, the source electrode can be changed to the drain electrode, or the drain electrode can be changed to the source electrode.

[0061] The gate electrode of the driving transistor T1 may be connected to the first electrode of the capacitor Cst, the drain electrode of the driving transistor T1 may be connected to the driving voltage line VDL transmitting the driving voltage ELVDD, and the source electrode of the driving transistor T1 may be connected to the anode of the first light-emitting element ED1 and to the second electrode of the capacitor Cst. The driving transistor T1 may receive the data voltage D1, D2, or D3 according to the switching operation of the switching transistor T2 and may provide a driving current to the first light-emitting element ED1 according to the voltage stored in the capacitor Cst.

[0062] The gate electrode of the switching transistor T2 can be connected to a first scan line transmitting a first scan signal SC, the drain electrode of the switching transistor T2 can be connected to a data line transmitting a data voltage D1, D2, or D3 or a reference voltage, and the source electrode of the switching transistor T2 can be connected to the first electrode of the capacitor Cst and to the gate electrode of the driving transistor T1. Multiple data lines DL1, DL2, and DL3 can transmit different data voltages D1, D2, and D3, respectively. The switching transistors T2 of pixels PX1, PX2, and PX3 can be connected to different data lines DL1, DL2, and DL3, respectively. For example, the switching transistor T2 of the first pixel PX1 can be connected to the first data line DL1, the switching transistor T2 of the second pixel PX2 can be connected to the second data line DL2, and the switching transistor T2 of the third pixel PX3 can be connected to the third data line DL3.

[0063] The switching transistor T2 may be turned on according to the first scan signal SC to transmit the reference voltage or the data voltage D1 , D2 , or D3 to the gate electrode of the driving transistor T1 and to the first electrode of the capacitor Cst.

[0064] The gate electrode of the initialization transistor T3 may be connected to the second scan line transmitting the second scan signal SS, the drain electrode of the initialization transistor T3 may be connected to the second electrode of the capacitor Cst, to the source electrode of the driving transistor T1, and to the anode of the first light-emitting element ED1, and the source electrode of the initialization transistor T3 may be connected to the initialization voltage line VIL transmitting the initialization voltage INIT. The initialization transistor T3 may be turned on in response to the second scan signal SS to transmit the initialization voltage INIT to the anode of the first light-emitting element ED1 and to the second electrode of the capacitor Cst, thereby initializing the voltage of the anode of the first light-emitting element ED1.

[0065] A first electrode of the capacitor Cst is connected to the gate electrode of the driving transistor T1, and a second electrode of the capacitor Cst is connected to the drain electrode of the initialization transistor T3 and to the anode of the first light emitting element ED1. A cathode of the first light emitting element ED1 is connected to a common voltage line VSL transmitting a common voltage ELVSS.

[0066] The first light emitting element ED1 may emit light at a brightness level corresponding to the driving current generated by the driving transistor T1 .

[0067] Figure 1 An example of the operation of the circuit shown in (eg, an example of the operation during one frame) will be described below. Here, a case where the transistors T1, T2, and T3 are N-channel transistors will be described as an example, but the present disclosure is not limited to this case.

[0068] When a frame begins, a high-level first scan signal SC and a high-level second scan signal SS may be provided during an initialization period to turn on the switching transistor T2 and the initialization transistor T3. A reference voltage from the data line may be provided to the gate electrode of the driving transistor T1 and to one end of the capacitor Cst via the turned-on switching transistor T2, and an initialization voltage INIT may be provided to the source electrode of the driving transistor T1 and to the anode of the first light-emitting element ED1 via the turned-on initialization transistor T3. Therefore, during the initialization period, the source electrode of the driving transistor T1 and the anode of the first light-emitting element ED1 may be initialized to the initialization voltage INIT. At this time, the difference between the reference voltage and the initialization voltage INIT may be stored in the capacitor Cst.

[0069] Next, if the second scan signal SS goes low while the first scan signal SC remains high during the sensing period, the switching transistor T2 can remain on and the initialization transistor T3 can be turned off. The gate electrode of the driving transistor T1 and the end of the capacitor Cst can be maintained at the reference voltage by the turned-on switching transistor T2, and the source electrode of the driving transistor T1 and the anode of the first light-emitting element ED1 can be electrically isolated from the initialization voltage line VIL by the turned-off initialization transistor T3. Therefore, the driving transistor T1 can be turned off if the voltage of the source electrode becomes "reference voltage - Vth" in response to the current flowing from the drain electrode to the source electrode. Vth represents the threshold voltage of the driving transistor T1. At this time, the voltage difference between the gate and source electrodes of the driving transistor T1 can be stored in the capacitor Cst, and the threshold voltage Vth of the driving transistor T1 can be sensed. Because a data signal compensated based on the characteristic information sensed during the sensing period is generated, the characteristic differences of the driving transistor T1 between pixels can be compensated externally.

[0070] Next, if a first scan signal SC at a high level and a second scan signal SS at a low level are provided during the data input period, the switching transistor T2 may be turned on and the initialization transistor T3 may be turned off. The data voltage D1, D2, or D3 from each data line DL1, DL2, or DL3 is provided to the gate electrode of the driving transistor T1 and the end of the capacitor Cst through the turned-on switching transistor T2 of each pixel PX1, PX2, or PX3. At this time, due to the turned-off driving transistor T1, the source electrode of the driving transistor T1 and the anode of the first light-emitting element ED1 can substantially maintain the potential during the sensing period.

[0071] Next, in the emission period, the driving transistor T1 turned on by the data voltage D1, D2 or D3 applied to the gate electrode may generate a driving current according to the data voltage D1, D2 or D3, and the first light emitting element ED1 may emit light in response to the driving current.

[0072] Figure 2 Is used to illustrate the repair Figure 1 A diagram of a circuit method of a display device.

[0073] like Figure 2 As shown in FIG, if an error occurs in at least one of the transistors of the second pixel PX2 (e.g., the driving transistor T1), the second pixel PX2 may be determined to be a defective pixel that cannot normally provide light. In this case, a repair process may be performed on the second pixel PX2. The repair process will be described in detail below.

[0074] First, for ease of description, the driving transistor T1, the switching transistor T2, the initialization transistor T3, and the capacitor Cst included in the first pixel PX1 will be referred to as the first driving transistor T1, the first switching transistor T2, the first initialization transistor T3, and the first capacitor Cst, respectively. The driving transistor T1, the switching transistor T2, the initialization transistor T3, and the capacitor Cst included in the second pixel PX2 will be referred to as the second driving transistor T1, the second switching transistor T2, the second initialization transistor T3, and the second capacitor Cst, respectively. The driving transistor T1, the switching transistor T2, the initialization transistor T3, and the capacitor Cst included in the third pixel PX3 will be referred to as the third driving transistor T1, the third switching transistor T2, the third initialization transistor T3, and the third capacitor Cst, respectively.

[0075] like Figure 2 As shown in , the gate electrode of the second driving transistor T1 can be separated from the pixel circuit of the second pixel PX2. For example, the gate electrode of the second driving transistor T1 can be cut in the first cutting area CA1. Therefore, the gate electrode of the second driving transistor T1 can be separated from the source electrode of the second switching transistor T2 and the first electrode of the second capacitor Cst.

[0076] like Figure 2 As shown in , the drain electrode of the second driving transistor T1 can be separated from the pixel circuit of the second pixel PX2. For example, the drain electrode of the second driving transistor T1 can be cut in the second cutting area CA2. Therefore, the drain electrode of the second driving transistor T1 can be separated from the driving voltage line VDL.

[0077] like Figure 2As shown in FIG, the anode of the second light-emitting element ED2 can be separated from the pixel circuit of the second pixel PX2. For example, the anode of the second light-emitting element ED2 can be cut in the third cutting area CA3. Therefore, the anode of the second light-emitting element ED2 can be separated from the source electrode of the second driving transistor T1, the drain electrode of the second initialization transistor T3, and the second electrode of the second capacitor Cst.

[0078] like Figure 2 As shown in FIG, the anode of the third light-emitting element ED3 can be separated from the pixel circuit of the third pixel PX3. For example, the anode of the third light-emitting element ED3 can be cut in the fourth cutting area CA4. Thus, the anode of the third light-emitting element ED3 can be separated from the source electrode of the third driving transistor T1, the drain electrode of the third initialization transistor T3, and the second electrode of the third capacitor Cst. As a result, the third pixel PX3 can be dimmed.

[0079] like Figure 2 As shown in FIG, the source electrode of the third driving transistor T1, the drain electrode of the third initialization transistor T3, the second electrode of the third capacitor Cst, and the anode of the second light-emitting element ED2 can be connected to each other by a connection pattern CPT. In other words, the pixel circuit of the third pixel PX3, which is a normal pixel, can be connected to the second light-emitting element ED2 of the second pixel PX2, which is a defective pixel.

[0080] Through the above repair and darkening processes, the second light-emitting element ED2 of the second pixel PX2, which is a defective pixel, can be normally driven by another pixel adjacent to the second pixel PX2 (e.g., the third pixel PX3). For example, the second light-emitting element ED2 of the second pixel PX2 can emit light in response to the drive current generated by the pixel circuit of the third pixel PX3 (e.g., the third drive transistor T1, the third switching transistor T2, the third initialization transistor T3, and the third capacitor Cst). At this time, the second data voltage D2 can be applied to the third data line DL3 connected to the third pixel PX3 instead of the third data voltage D3 corresponding to the third pixel PX3. For example, the second data voltage D2 can be applied to the third data line DL3 during the data input period of the second pixel PX2. Therefore, the second light-emitting element ED2 of the second pixel PX2 can provide light corresponding to the amplitude (or grayscale value) of the second data voltage D2, which is the original (e.g., intended) data voltage.

[0081] Instead of the pixel circuit of the third pixel PX3, the pixel circuit of another pixel (for example, the first pixel PX1 adjacent to the second pixel PX2) may also or alternatively be connected to the second light emitting element ED2 of the second pixel PX2 as a defective pixel. Figure 2Similarly to the third light-emitting element ED3 of the third pixel PX3 in FIG, the first light-emitting element ED1 of another pixel (for example, the first pixel PX1) can be separated from the pixel circuit of the first pixel PX1. In addition, the pixel circuit of the first pixel PX1 can be connected to the anode of the second light-emitting element ED2. In this case, the second data voltage D2 can be applied to the first data line DL1 connected to the first pixel PX1. For example, the second data voltage D2 can be applied to the first data line DL1 during the data input period of the second pixel PX2.

[0082] Figure 3 yes Figure 2 FIG. 1 is a partial cross-sectional view of a first pixel PX1, a second pixel PX2, and a third pixel PX3.

[0083] like Figure 3 As shown in , the display device may include a substrate SUB, a barrier layer BR, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially disposed on the substrate SUB. Here, the thin film transistor layer TFTL may include the aforementioned pixel circuit for each pixel.

[0084] The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded, or curled. The substrate SUB may be made of an insulating material such as glass, quartz, or a polymer resin. The polymer material may be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate SUB may include a metal material.

[0085] A plurality of light blocking layers BML may be located on the substrate SUB. The light blocking layers BML may be made of, for example, a metal material such as chromium (Cr) or molybdenum (Mo), or may be made of black ink or black dye. If the light blocking layers BML are made of a metal material, they may receive static power. Therefore, the light blocking layers BML may not be electrically floating, and the electrical characteristics of the transistors on the light blocking layers BML may be stabilized. Therefore, for example, performance degradation of the oxide-based transistor T1 may be reduced or minimized. At the same time, oxide semiconductors are sensitive to light, and changes in the amount of current may occur due to external light.

[0086] The buffer layer BF may be located on the light blocking layer BML. The buffer layer BF may be located on (e.g., on) the entire surface of the substrate SUB over which the barrier layer BR is disposed. The buffer layer BF may be a layer for protecting the transistors T1, T2, and T3 of the thin film transistor layer TFTL and the light-emitting layer of the light-emitting element layer EMTL from moisture introduced through the substrate SUB, which is susceptible to moisture permeation. The buffer layer BF may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer BF may be a multilayer in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0087] The first active layer ACT1 and the second active layer ACT2 may be located on the buffer layer BF. Each of the first active layers ACT1 may include a first drain electrode DE1, a first source electrode SE1, and a first channel region CH1. The first channel region CH1 may be located between the first drain electrode DE1 and the first source electrode SE1. Here, each of the first active layers ACT1 may be located on the buffer layer BF such that the first channel region CH1 of the first active layer ACT1 overlaps the light blocking layer BML. Each of the second active layers ACT2 may include a second drain electrode DE2, a second source electrode SE2, and a second channel region CH2. The second channel region CH2 may be located between the second drain electrode DE2 and the second source electrode SE2.

[0088] The first active layer ACT1 may include polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material. If the first active layer ACT1 includes an oxide semiconductor material, it may include indium gallium zinc oxide (IGZO). If the first active layer ACT1 includes polycrystalline silicon or an oxide semiconductor material, the source electrode and the drain electrode in each of the first active layers ACT1 may be a conductive region doped with ions to provide conductivity. The second active layer ACT2 may be made of the same material as the first active layer ACT1 described above.

[0089] The first gate insulating layer GTI1 and the second gate insulating layer GTI2 may be located on the first active layer ACT1 and the second active layer ACT2, respectively. For example, the first gate insulating layer GTI1 may be located on the first active layer ACT1 to overlap with the first channel region CH1 of the first active layer ACT1, and the second gate insulating layer GTI2 may be located on the second active layer ACT2 to overlap with the second channel region CH2 of the second active layer ACT2.

[0090] The first gate electrode GE1 may be located on the first gate insulating layer GTI1 . The first gate electrode GE1 may be located on the first gate insulating layer GTI1 to overlap with the first channel region CH1 of the first active layer ACT1 .

[0091] The second gate electrode GE2 can be located on the second gate insulating layer GTI2. The second gate electrode GE2 can be positioned on the second gate insulating layer GTI2 to overlap the second channel region CH2 of the second active layer ACT2.

[0092] The first interlayer insulating layer ITL1 can be located on the first gate electrode GE1 and on the second gate electrode GE2. For example, the first interlayer insulating layer ITL1 can be located on (e.g., above) the entire surface of the substrate SUB on which the first gate electrode GE1 and the second gate electrode GE2 are disposed. The first interlayer insulating layer ITL1 can include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating layer ITL1 can include a plurality of inorganic layers.

[0093] The plurality of anode connection electrodes ACE, the drive voltage line VDL, the plurality of source connection electrodes SCE, the first data line DL1, the second data line DL2, and the third data line DL3 can be located on the first interlayer insulating layer ITL1.

[0094] The anode connection electrode ACE can be connected to the light-blocking layer BML through the first contact hole CT1 that penetrates the first interlayer insulating layer ITL1 and the buffer layer BF, respectively. In addition, the anode connection electrode ACE can be connected to the first source electrode SE1 of the first active layer ACT1 through the second contact hole CT2 that penetrates the first interlayer insulating layer ITL1. For example, the anode connection electrode ACE of the first pixel PX1 can be connected to the light-blocking layer BML of the first pixel PX1 and connected to the first source electrode SE1 of the first active layer ACT1 of the first pixel PX1. The anode connection electrode ACE of the second pixel PX2 can be connected to the light-blocking layer BML of the second pixel PX2 and connected to the first source electrode SE1 of the first active layer ACT1 of the second pixel PX2. The anode connection electrode ACE of the third pixel PX3 can be connected to the light-blocking layer BML of the third pixel PX3 and connected to the first source electrode SE1 of the first active layer ACT1 of the third pixel PX3.

[0095] The drive voltage line VDL can be connected to the first drain electrode DE1 of the first active layer ACT1 through the third contact hole CT3 that penetrates the first interlayer insulating layer ITL1.

[0096] The source connection electrode SCE may be connected to the second source electrode SE2 of the second active layer ACT2 through a fourth contact hole CT4 penetrating the first interlayer insulating layer ITL1. For example, the source connection electrode SCE of the first pixel PX1 may be connected to the second source electrode SE2 of the second active layer ACT2 of the first pixel PX1, the source connection electrode SCE of the second pixel PX2 may be connected to the second source electrode SE2 of the second active layer ACT2 of the second pixel PX2, and the source connection electrode SCE of the third pixel PX3 may be connected to the second source electrode SE2 of the second active layer ACT2 of the third pixel PX3.

[0097] The first data line DL1 may be connected to the second drain electrode DE2 of the first switching transistor T2 via a fifth contact hole CT5 penetrating the first interlayer insulating layer ITL1. The second data line DL2 may be connected to the second drain electrode DE2 of the second switching transistor T2 via a fifth contact hole CT5 penetrating the first interlayer insulating layer ITL1. The third data line DL3 may be connected to the second drain electrode DE2 of the third switching transistor T2 via a fifth contact hole CT5 penetrating the first interlayer insulating layer ITL1.

[0098] The second interlayer insulating layer ITL2 may be located on the anode connection electrode ACE, the driving voltage line VDL, the source connection electrode SCE, the first data line DL1, the second data line DL2, and the third data line DL3. For example, the second interlayer insulating layer ITL2 may be located on (e.g., on) the entire surface of the substrate SUB over which the anode connection electrode ACE, the driving voltage line VDL, the source connection electrode SCE, the first data line DL1, the second data line DL2, and the third data line DL3 are disposed. The second interlayer insulating layer ITL2 may include the same material as the first interlayer insulating layer ITL1 described above.

[0099] The planarization layer VA may be located on the second interlayer insulating layer ITL2. The planarization layer VA may be located on (e.g., over) the entire surface of the substrate SUB over which the second interlayer insulating layer ITL2 is located. The planarization layer VA may include an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0100] The light-emitting element layer EMTL may be located on the planarization layer VA. For example, a first anode AE1, a second anode AE2, and a third anode AE3 may be located on the planarization layer VA. The first anode AE1 may be connected to the anode connection electrode ACE of the first pixel PX1 via a sixth contact hole CT6 that penetrates the planarization layer VA and the second interlayer insulating layer ITL2. The second anode AE2 may be connected to the anode connection electrode ACE of the second pixel PX2 via a sixth contact hole CT6 that penetrates the planarization layer VA and the second interlayer insulating layer ITL2. The third anode AE3 may be connected to the anode connection electrode ACE of the third pixel PX3 via a sixth contact hole CT6 that penetrates the planarization layer VA and the second interlayer insulating layer ITL2.

[0101] In addition to the first anode AE1 , the second anode AE2 , and the third anode AE3 , the light emitting element layer EMTL may further include a plurality of light emitting elements and a pixel defining layer PDL.

[0102] The light-emitting elements may include, for example, a first light-emitting element ED1 of the first pixel PX1, a second light-emitting element ED2 of the second pixel PX2, and a third light-emitting element ED3 of the third pixel PX3. The first light-emitting element ED1 may include a first anode AE1, a first light-emitting layer EL1, and a common electrode / cathode CE. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting layer EL2, and a cathode CE. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting layer EL3, and a cathode CE. The first light-emitting element ED1 may provide light through the first emission area EA1, the second light-emitting element ED2 may provide light through the second emission area EA2, and the third light-emitting element ED3 may provide light through the third emission area EA3.

[0103] The first light-emitting element ED1 may include a first anode AE1, a first light-emitting layer EL1, and a cathode CE. The first emission region EA1 may be a region where the first anode AE1, the first light-emitting layer EL1, and the cathode CE are sequentially stacked so that holes from the first anode AE1 and electrons from the cathode CE recombine with each other in the first light-emitting layer EL1 to emit light.

[0104] The second light-emitting element ED2 may include a second anode AE2, a second light-emitting layer EL2, and a cathode CE. The second emission region EA2 may be a region where the second anode AE2, the second light-emitting layer EL2, and the cathode CE are sequentially stacked so that holes from the second anode AE2 and electrons from the cathode CE are recombined in the second light-emitting layer EL2 to emit light.

[0105] The third light-emitting element ED3 may include a third anode AE3, a third light-emitting layer EL3, and a cathode CE. The third emission region EA3 may be a region where the third anode AE3, the third light-emitting layer EL3, and the cathode CE are sequentially stacked so that holes from the third anode AE3 and electrons from the cathode CE recombine with each other in the third light-emitting layer EL3 to emit light.

[0106] In a top emission structure in which light is emitted from the light-emitting layer (e.g., EL1) toward the cathode CE, the anode (e.g., AE1) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or, in order to increase reflectivity, may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0107] The pixel-defining layer (PDL) defines the first emission area EA1, the second emission area EA2, and the third emission area EA3 of the first pixel PX1, the second pixel PX2, and the third pixel PX3. To this end, the pixel-defining layer (PDL) may be positioned on the planarization layer VA to expose a portion of the first anode AE1, a portion of the second anode AE2, and a portion of the third anode AE3. The pixel-defining layer (PDL) may cover the edges of the first anode AE1, the second anode AE2, and the third anode AE3. The pixel-defining layer (PDL) may be made of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0108] In one or more embodiments, a spacer may be located on the pixel defining layer PDL. The spacer may support a mask during the process of manufacturing the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. The spacer may be made of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0109] Light-emitting layers EL1, EL2, and EL3 may be formed on anodes AE1, AE2, and AE3, respectively. The first light-emitting layer EL1 may include an organic material to emit light of a corresponding color (e.g., a predetermined color). For example, the first light-emitting layer EL1 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a light-emitting material and may be formed using a phosphorescent material or a fluorescent material.

[0110] For example, the organic material layer of the first light-emitting layer EL1 of the first emission region EA1 for emitting light of a first color (e.g., red) may be a phosphorescent material including a host material and a dopant material, the host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl) (mCP), and the dopant material including any one or more of bis(1-phenylisoquinolinolato) iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinolinolato) iridium acetylacetonate (PQIr(acac)), tris(1-phenylquinolinolato) iridium (PQIr), and platinum octaethylporphyrin (PtOEP). Alternatively, the organic material layer of the first light-emitting layer EL1 of the first emission region EA1 may be a fluorescent material including PBD:Eu(DBM)3(Phen) or dinaphthylene. However, the present disclosure is not limited thereto.

[0111] The organic material layer of the second light-emitting layer EL2 of the second emission area EA2 for emitting light of the second color (for example, green) can be a phosphorescent material including a host material and a dopant material, the host material including CBP or mCP, and the dopant material including Ir(ppy)3 (fac tris(2-phenylpyridine)iridium). Alternatively, the organic material layer of the second light-emitting layer EL2 of the second emission area EA2 for emitting light of the second color can be a fluorescent material including tris(8-hydroxyquinoline)aluminum (Alq3). However, the present disclosure is not limited thereto.

[0112] The organic material layer of the third light emitting layer EL3 of the third emission area EA3 for emitting light of a third color (e.g., blue) may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111. However, the present disclosure is not limited thereto.

[0113] The cathode CE may be located on the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. The cathode CE may cover the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. The cathode CE may be a common layer located on the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. In one or more embodiments, a capping layer may be formed on the cathode CE.

[0114] In a top-emission structure, the cathode (CE) can be made of a light-transmitting transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. If the cathode (CE) is made of a semi-transmissive conductive material, the microcavity can improve light output efficiency.

[0115] The encapsulation layer ENC may be formed on the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer to reduce or prevent oxygen or moisture from penetrating into the light-emitting element layer EMTL. Furthermore, the encapsulation layer ENC may include at least one organic layer to protect the light-emitting element layer EMTL from foreign matter, such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer sequentially stacked on the cathode CE.

[0116] The first encapsulating inorganic layer of the encapsulating layer ENC may be located on the cathode CE, the encapsulating organic layer may be located on the first encapsulating inorganic layer, and the second encapsulating inorganic layer may be located on the encapsulating organic layer. Each of the first encapsulating inorganic layer and the second encapsulating inorganic layer may be a multilayer in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulating organic layer may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0117] A portion of the first active layer ACT1 included in the second pixel PX2 may be cut. For example, the first drain electrode DE1 of the second drive transistor T1 may be cut in the second cutting area CA2. To this end, a first cutting hole H1 may be formed in the second cutting area CA2, penetrating the second interlayer insulating layer ITL2, the first interlayer insulating layer ITL1, and the first active layer ACT1 of the second pixel PX2. For example, the first active layer ACT1 of the second pixel PX2 may be cut into two parts in the second cutting area CA2 (for example, the area between the first channel region CH1 and the first drain electrode DE1). In this example, the first active layer ACT1 of the second pixel PX2 may be divided into a first part (for example, a first part including the first source electrode SE1 and the first channel region CH1) and a second part (for example, a second part including the first drain electrode DE1). Therefore, the connection between the first drain electrode DE1 of the second drive transistor T1 and the driving voltage line VDL may be disconnected by the first cutting hole H1 in the second cutting area CA2.

[0118] A portion of the second anode AE2 included in the second pixel PX2 may be cut. For example, the second anode AE2 may be cut in the third cutting area CA3. To this end, a second cutting hole H2 may be formed in the third cutting area CA3 that penetrates the second anode AE2. For example, the second anode AE2 may be cut into two parts in the third cutting area CA3. In the example, the second anode AE2 may be divided into a first portion AE2-1 (e.g., a first portion connected to the anode connection electrode ACE of the second pixel PX2 and not connected to the second light-emitting layer EL2) and a second portion AE2-2 (e.g., a second portion not connected to the anode connection electrode ACE of the second pixel PX2 and connected to the second light-emitting layer EL2). Therefore, the connection between the second portion AE2-2 of the second anode AE2 and the anode connection electrode ACE of the second pixel PX2 may be disconnected by the second cutting hole H2 in the third cutting area CA3. Here, the first portion AE2-1 of the second anode AE2 and the third cutting area CA3 may overlap with the pixel defining layer PDL. In addition, an edge of the second portion AE2 - 2 of the second anode AE2 may overlap the pixel defining layer PDL, and the rest of the second portion AE2 - 2 may be located in the second emission area EA2 and connected to the second light emitting layer EL2 .

[0119] In one or more embodiments, the first gate electrode GE1 of the second driving transistor T1 may be separated from the first electrode of the second capacitor Cst and from the second source electrode SE2 of the second switching transistor T2 by another cutting hole (eg, a cutting hole of the first cutting area CA1 ).

[0120] Therefore, the second driving transistor T1 and the second light emitting element ED2 of the second pixel PX2 may be electrically and / or physically separated from the pixel circuit of the second pixel PX2 .

[0121] A portion of the third anode AE3 included in the third pixel PX3 may be cut. For example, the third anode AE3 may be cut in the fourth cut area CA4. To this end, a third cut hole H3 may be formed in the fourth cut area CA4, penetrating the third anode AE3. For example, the third anode AE3 may be cut into two portions in the fourth cut area CA4. In this example, the third anode AE3 may be divided into a first portion AE3-1 (e.g., a first portion connected to the anode connection electrode ACE of the third pixel PX3 and not connected to the third light-emitting layer EL3) and a second portion AE3-2 (e.g., a second portion not connected to the anode connection electrode ACE of the third pixel PX3 and connected to the third light-emitting layer EL3). Therefore, the connection between the second portion AE3-2 of the third anode AE3 and the anode connection electrode ACE of the third pixel PX3 may be disconnected by the third cut hole H3 of the fourth cut area CA4. Here, the first portion AE3-1 of the third anode AE3 and the fourth cut area CA4 may overlap with the pixel defining layer PDL. In addition, an edge of the second portion AE3 - 2 of the third anode electrode AE3 may overlap with the pixel defining layer PDL, and the rest of the second portion AE3 - 2 may be located in the third emission area EA3 .

[0122] Therefore, the third light emitting element ED3 of the third pixel PX3 may be electrically and / or physically separated from the pixel circuit of the third pixel PX3.

[0123] The second portion AE2-2 of the second anode AE2 and the first portion AE3-1 of the third anode AE3 may be connected to each other. For example, the second portion AE2-2 of the second anode AE2 and the first portion AE3-1 of the third anode AE3 may be connected to each other by a connection pattern CPT. The connection pattern CPT may be located on the same layer as the first anode AE1, the second anode AE2, and the third anode AE3. For example, the connection pattern CPT may be located on the planarization layer VA. At least a portion of the connection pattern CPT may contact the first portion AE2-1 of the second anode AE2, the second portion AE3-2 of the third anode AE3, and the planarization layer VA. At least a portion of the connection pattern CPT may be located on the first portion AE2-1 of the second anode AE2 and on the second portion AE3-2 of the third anode AE3. At least a portion of the connection pattern CPT may be located between the planarization layer VA and the pixel defining layer PDL. At least a portion of the connection pattern CPT may be located between the second portion AE2-2 of the second anode AE2 and the pixel defining layer PDL. At least a portion of the connection pattern CPT may be located between the first portion AE3-1 of the third anode AE3 and the pixel defining layer PDL. The connection pattern CPT may include, for example, conductive ink. The conductive ink may include, for example, Ag ink. The Ag ink may include Ag nanoparticles dispersed in the ink.

[0124] The pixel circuit of the third pixel PX3 can be connected to the second anode AE2 of the second pixel PX2 via the third cutout hole H3 and the connection pattern CPT, and is not connected to the third anode AE3 of the third pixel PX3. In other words, the pixel circuit of the third pixel PX3, including the third driving transistor T1, the third switching transistor T2, the third initialization transistor T3, and the third capacitor Cst, can be connected to the second light-emitting element ED2 of the second pixel PX2 instead of the third light-emitting element ED3 of the third pixel PX3. Therefore, the second light-emitting element ED2 of the second pixel PX2, which is a defective pixel, can be driven by the pixel circuit of the third pixel PX3, which is a normal pixel.

[0125] Figures 4 to 9 is a cross-sectional view for explaining a method of manufacturing a display device according to one or more embodiments.

[0126] First, if Figure 4 As shown in , a substrate SUB can be prepared, on which a buffer layer BF, a first interlayer insulating layer ITL1, a second interlayer insulating layer ITL2, a light blocking layer BML, a first gate insulating layer GTI1, a second gate insulating layer GTI2, transistors T1, T2, and T3, an anode connection electrode ACE, data lines DL1, DL2, and DL3, a source connection electrode SCE, and a driving voltage line VDL are located. Then, a first cutting hole H1 can be formed in the second cutting area CA2 to penetrate the second interlayer insulating layer ITL2, the first interlayer insulating layer ITL1, and the first active layer ACT1 of the second pixel PX2. For example, the first cutting hole H1 can be formed by a laser beam LB. In other words, as the laser beam LB is irradiated to the first cutting area CA1, the first active layer ACT1 of the second pixel PX2 can be divided into a first portion (e.g., a first source electrode SE1 and a first channel region CH1) and a second portion (e.g., a first drain electrode DE1) in the first cutting area CA1.

[0127] Next, if Figure 5 As shown in FIG, the planarization layer VA may be positioned on the second interlayer insulating layer ITL2. Here, the planarization layer VA may be further positioned in the first cutting hole H1. In other words, the first cutting hole H1 may be filled with the planarization layer VA.

[0128] Next, if Figure 6As shown in FIG. 6A, the sixth contact hole CT6 can be formed to penetrate the planarization layer VA and the second interlayer insulating layer ITL2. Then, the first anode AE1, the second anode AE2, and the third anode AE3 can be positioned on the planarization layer VA. At this time, the first anode AE1 can be connected to the anode connection electrode ACE of the first pixel PX1 through the sixth contact hole CT6 of the first pixel PX1, the second anode AE2 can be connected to the anode connection electrode ACE of the second pixel PX2 through the sixth contact hole CT6 of the second pixel PX2, and the third anode AE3 can be connected to the anode connection electrode ACE of the third pixel PX3 through the sixth contact hole CT6 of the third pixel PX3.

[0129] Next, as shown in FIG. 6B, the second cut hole H2 can be formed in the third cut region CA3 to cut the second anode AE2. For example, the second cut hole H2 can be formed by the laser beam LB. In other words, as the laser beam LB is irradiated to the third cut region CA3, the second anode AE2 of the second pixel PX2 can be divided into a first portion AE2-1 (e.g., a first portion connected to the anode connection electrode ACE of the second pixel PX2 and not connected to the second light emitting layer EL2) and a second portion AE2-2 (e.g., a second portion not connected to the anode connection electrode ACE of the second pixel PX2 and connected to the second light emitting layer EL2) in the third cut region CA3. Figure 7 Next, as shown in FIG. 6B, the second cut hole H2 can be formed in the third cut region CA3 to cut the second anode AE2. For example, the second cut hole H2 can be formed by the laser beam LB. In other words, as the laser beam LB is irradiated to the third cut region CA3, the second anode AE2 of the second pixel PX2 can be divided into a first portion AE2-1 (e.g., a first portion connected to the anode connection electrode ACE of the second pixel PX2 and not connected to the second light emitting layer EL2) and a second portion AE2-2 (e.g., a second portion not connected to the anode connection electrode ACE of the second pixel PX2 and connected to the second light emitting layer EL2) in the third cut region CA3.

[0130] Figure 7 Next, as shown in FIG. 6B, the second cut hole H2 can be formed in the third cut region CA3 to cut the second anode AE2. For example, the second cut hole H2 can be formed by the laser beam LB. In other words, as the laser beam LB is irradiated to the third cut region CA3, the second anode AE2 of the second pixel PX2 can be divided into a first portion AE2-1 (e.g., a first portion connected to the anode connection electrode ACE of the second pixel PX2 and not connected to the second light emitting layer EL2) and a second portion AE2-2 (e.g., a second portion not connected to the anode connection electrode ACE of the second pixel PX2 and connected to the second light emitting layer EL2) in the third cut region CA3.

[0131] Next, as shown in FIG. 6B, the second cut hole H2 can be formed in the third cut region CA3 to cut the second anode AE2. For example, the second cut hole H2 can be formed by the laser beam LB. In other words, as the laser beam LB is irradiated to the third cut region CA3, the second anode AE2 of the second pixel PX2 can be divided into a first portion AE2-1 (e.g., a first portion connected to the anode connection electrode ACE of the second pixel PX2 and not connected to the second light emitting layer EL2) and a second portion AE2-2 (e.g., a second portion not connected to the anode connection electrode ACE of the second pixel PX2 and connected to the second light emitting layer EL2) in the third cut region CA3. Figure 8 ​As shown in FIG, a connection pattern CPT may be positioned on the planarization layer VA to connect the second portion AE2-2 of the second anode AE2 to the first portion AE3-1 of the third anode AE3. For example, the connection pattern CPT may be made of conductive ink. The conductive ink may be applied to the second portion AE2-2 of the second anode AE2 and the first portion AE3-1 of the third anode AE3. Furthermore, the conductive ink may be applied between the second portion AE2-2 of the second anode AE2 and the first portion AE3-1 of the third anode AE3. The conductive ink may then be cured to form the connection pattern CPT.

[0132] Next, if Figure 9 As shown in FIG, a pixel defining layer PDL may be positioned on the first anode AE1 or the second anode AE2, on the third anode AE3, and on the connection pattern CPT. At this time, a portion of the pixel defining layer PDL may be positioned in the second cutting hole H2 and the third cutting hole H3. In other words, each of the second cutting hole H2 and the third cutting hole H3 may be filled with the pixel defining layer PDL.

[0133] Next, if Figure 3 As shown in FIG, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be positioned on the first anode AE1, the second anode AE2, and the third anode AE3, respectively. At this time, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be sequentially formed by different corresponding processes.

[0134] Next, a cathode CE may be positioned on the first light emitting layer EL1 , on the second light emitting layer EL2 , and on the third light emitting layer EL3 .

[0135] Then, the encapsulation layer ENC may be positioned on the cathode CE.

[0136] Figure 10 is a block diagram of a driving circuit of a display device according to one or more embodiments.

[0137] like Figure 10 As shown in , the driving circuit of the display device may include a timing controller 222 and a data driver 444 .

[0138] The timing controller 222 may receive digital video data and timing signals from the system 111. The timing controller 222 may control the operation timing of the data driver 444 by generating a data control signal based on the timing signal, may control the operation timing of the gate driver by generating a gate control signal, and may control the operation timing of the emission control driver by generating an emission control signal. The timing controller 222 may provide the digital video data and the data control signal to the data driver 444.

[0139] In addition, the timing controller 222 can convert digital video data from the system 111 based on the repaired pixels and the dimmed pixels. To this end, the timing controller 222 can include a data converter 333. The data converter 333 can convert the digital video data from the system 111. For example, if the second pixel PX2 (e.g., a green pixel) is repaired as described above, the data converter 333 can convert digital video data corresponding to the dimmed third pixel PX3 (e.g., a blue pixel) adjacent to the second pixel PX2 (hereinafter, referred to as third digital video data) into digital video data corresponding to the second pixel PX2 (hereinafter, referred to as second digital video data), and can provide the second digital video data to the data driver 444. The data driver 444 then converts the second digital video data into an analog data voltage D2 (hereinafter, referred to as a second data voltage) and transmits the second data voltage D2 to the third data line DL3 connected to the third pixel PX3. Then, the pixel circuit of the third pixel PX3 can generate a driving current corresponding to the second data voltage D2 and can provide the driving current to the second light emitting element ED2 of the second pixel PX2. Therefore, the repaired second pixel PX2 can provide light at a brightness level corresponding to the magnitude of the original second data voltage D2.

[0140] The data driver 444 can convert the digital video data from the timing controller 222 into analog data voltages D1, D2, and D3, and can provide the data voltages D1, D2, and D3 to the data lines through the fan-out lines. The scan signal of the gate driver can select the pixel to which the data voltage is to be provided, and the selected pixel can receive the data voltage through the data line. For example, the gate driver can provide a first scan signal SC to the gate electrode of the switching transistor T2 and a second scan signal SS to the gate electrode of the initialization transistor T3.

[0141] Figure 11 Shown included in Figure 10 The lookup table 555 in the data converter 333 is configured as follows.

[0142] The data converter 333 may include Figure 11 For example, the data converter 333 may include a lookup table 555 having coordinate information about the coordinates of the repair pixel (eg, the second pixel PX2) and the coordinates of the dimmed pixel (eg, the third pixel PX3) connected to the repair pixel.

[0143] The data converter 333 can convert the first digital video data (e.g., digital video data corresponding to the darkened pixels) into the second digital video data (e.g., digital video data corresponding to the repaired pixels) based on the coordinates of the repaired pixels and the coordinates of the darkened pixels stored in the lookup table 555.

[0144] The X and Y in the lookup table 555 can represent the coordinates of the repaired pixel (e.g., a green pixel). In addition, the "color" in the lookup table 555 can represent the pixel (or coordinates of the pixel) of the light-emitting element connected to the repaired pixel. For example, row 1 of the lookup table 555 shows 1920 as the X coordinate, 1080 as the Y coordinate, and R as the color. This can mean that the light-emitting element of the pixel at the X coordinate of 1920 and the Y coordinate of 1080 (e.g., the repaired green pixel) is connected to the pixel circuit of the red pixel adjacent to the pixel. Here, the red pixel in row 1 is a darkened pixel. For another example, row 2 of the lookup table 555 shows 1000 as the X coordinate, 400 as the Y coordinate, and B as the color. This can mean that the light-emitting element of the pixel at the X coordinate of 1000 and the Y coordinate of 400 (e.g., the repaired green pixel) is connected to the pixel circuit of the blue pixel adjacent to the pixel. Here, the blue pixel in row 2 is a darkened pixel.

[0145] The data converter 333 can detect digital video data corresponding to the dimmed pixels and convert the detected digital video data into digital video data corresponding to the repaired pixels based on the above-mentioned lookup table 555. For example, the data converter 333 can convert the red digital video data corresponding to the dimmed red pixels in row 1 into green digital video data (e.g., green digital video data corresponding to the repaired pixels in row 1 of the lookup table 555). For another example, the data converter 333 can convert the blue digital video data corresponding to the dimmed blue pixels in row 2 into green digital video data (e.g., green digital video data corresponding to the repaired pixels in row 2 of the lookup table 555). The digital video data converted by the data converter 333 can be provided to the data driver 444.

[0146] According to one or more embodiments, if a green pixel, which contributes most to brightness among a group of red, green, and blue pixels, is defective, the light-emitting element of the green pixel is driven using a driving current from a pixel circuit of another normal pixel adjacent to the green pixel. Thus, the defect rate of a display device can be reduced or minimized.

[0147] Figure 12 A diagram for explaining luminance contributions of red pixels, green pixels, and blue pixels of a display device.

[0148] exist Figure 12 , the X-axis represents the position (eg, coordinate) of a pixel, and the Y-axis represents brightness.

[0149] The first unit pixel UPX1 , the second unit pixel UPX2 , and the third unit pixel UPX3 may each be a unit pixel including a red pixel, a green pixel, and a blue pixel.

[0150] The first unit pixel UPX1 includes red, green, and blue pixels. Here, if only the red pixel among the red, green, and blue pixels of the first unit pixel UPX1 is dimmed, the brightness of the first region A is the brightness of the first unit pixel UPX1.

[0151] The second unit pixel UPX2 includes red, green, and blue pixels. Here, if only the green pixel among the red, green, and blue pixels of the second unit pixel UPX2 is dimmed, the brightness of the second region B is the brightness of the second unit pixel UPX2.

[0152] The third unit pixel UPX3 includes red, green and blue pixels. Here, if only the blue pixel among the red, green and blue pixels of the third unit pixel UPX3 is dimmed, the brightness of the third region C is the brightness of the third unit pixel UPX3.

[0153] like Figure 12 As shown in , it can be seen that if the green pixel is dimmed, the brightness of the unit pixel is the lowest. Therefore, if the green pixel is defective, the driving current from the pixel circuit of another adjacent pixel (for example, a red pixel or a blue pixel) is used to drive the light-emitting element of the green pixel. Therefore, the defect rate of the display device can be reduced or minimized.

[0154] In the display device according to the present disclosure, the defect rate may be reduced or minimized.

[0155] However, the effects of the present disclosure are not limited to those described herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

[0156] It will be understood by those skilled in the art that the present disclosure may be implemented in other forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above exemplary embodiments are illustrative and not restrictive in all aspects. It should be understood that the scope of the present disclosure is defined by the claims rather than the above detailed description, and all modifications and variations derived from the claims and their functional equivalents fall within the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: a first pixel comprising a first pixel circuit and a first light-emitting element, wherein the first pixel circuit is separated from a portion of the first light-emitting element; as well as The second pixel includes a second pixel circuit and a second light-emitting element, wherein the second pixel circuit is separated from a portion of the second light-emitting element and is connected to a portion of the first light-emitting element.

2. The display device according to claim 1, wherein The first anode of the first light emitting element includes a first portion and a second portion separated from each other by a first cutting hole penetrating the first anode, and The second anode of the second light-emitting element includes a first portion and a second portion separated from each other by a second cutting hole penetrating the second anode.

3. The display device according to claim 2, wherein: The first portion of the first anode is connected to a first driving transistor of the first pixel circuit, and The first portion of the second anode is connected to a second driving transistor of the second pixel circuit.

4. The display device according to claim 3, wherein The second portion of the first anode is connected to the first light-emitting layer of the first light-emitting element and the first portion of the second anode.

5. The display device according to claim 4, wherein: Also included is a connection pattern connecting the second portion of the first anode to the first portion of the second anode.

6. The display device according to claim 3, wherein: A gate electrode and a drain electrode of the first driving transistor of the first pixel circuit are separated from the first pixel circuit, and The source electrode of the first driving transistor is separated from the first anode of the first light-emitting element.

7. The display device according to claim 6, wherein: The first driving transistor of the first pixel circuit includes an active layer including the drain electrode and the source electrode and including a first portion and a second portion separated from each other by a third cutting hole penetrating the active layer.

8. The display device according to claim 7, wherein: The first portion of the active layer includes the source electrode of the first driving transistor and a channel region of the first driving transistor, and The second portion of the active layer includes the drain electrode of the first driving transistor.

9. The display device according to claim 1, wherein Also includes: a first data line connected to the first pixel; as well as A second data line is connected to the second pixel.

10. The display device according to claim 9, wherein Also includes: a data driver, configured to transmit a data voltage corresponding to the first pixel to the second data line during a data input period of the first pixel; a data converter for converting first digital video data corresponding to the second pixel into second digital video data corresponding to the first pixel, and for providing the second digital video data to the data driver, wherein the data driver is configured to generate the data voltage corresponding to the first pixel based on the second digital video data, wherein the data converter includes a lookup table having coordinate information of the coordinates of the first pixel and the coordinates of the second pixel, and The data converter is configured to convert the first digital video data into the second digital video data based on the coordinates of the first pixel and the coordinates of the second pixel.

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