Array substrate and display device

Abstract

Provided is an array substrate, comprising: a plurality of first electrodes located on a substrate to form first electrode rows extending in a first direction and first electrode columns extending in a second direction; the data lines extend in the second direction, and orthographic projections of the data lines on the substrate and orthographic projections of the first electrode columns on the substrate are alternately arranged; the at least one first electrode includes: a first electrode body; the first electrode protruding part is located on the side, close to the first data line, of the first electrode body, the second electrode protruding part is located on the side, close to the second data line, of the first electrode body, and the distance between the first electrode body and the first data line is smaller than or equal to the distance between the first electrode body and the second data line. The overlapping area of the orthographic projection of the first electrode protruding part on the substrate and the orthographic projection of the first data line on the substrate is smaller than or equal to the overlapping area of the orthographic projection of the second electrode protruding part on the substrate and the orthographic projection of the second data line on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid crystal display devices have been widely used in people's lives and work due to their advantages such as low radiation, small size and low power consumption. Specifically, they are used in electronic devices such as laptop computers, personal digital assistants, flat-screen TVs, and mobile phones. During the production process of liquid crystal display devices, if the production process fluctuates, the pixel electrodes or common electrodes therein will be offset. As a result, there will be a pixel crosstalk problem caused by the unequal coupling capacitance on both sides of the data line (for example, the lateral field capacitance between the data line and the pixel electrode), which affects the picture display effect and thus affects the user's viewing experience. Targeted improvement of these display defects is a topic that R&D personnel continue to focus on.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art. Utility Model Content

[0004] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide an array substrate and a display device.

[0005] According to one aspect of an embodiment of the present disclosure, an array substrate is provided, including:

[0006] substrate;

[0007] a plurality of first electrodes, located on the base substrate and arranged in an array along a first direction and a second direction to form first electrode rows extending in the first direction and first electrode columns extending in the second direction; and

[0008] Data lines are located on the base substrate and extend along the second direction, wherein the orthographic projections of the data lines on the base substrate and the orthographic projections of the first electrode columns on the base substrate are alternately arranged;

[0009] Wherein, at least one of the first electrodes comprises:

[0010] a first electrode body;

[0011] The first electrode protrusion is located on a side of the first electrode body close to the first data line.

[0012] The second electrode protrusion is located on a side of the first electrode body close to the second data line.

[0013] The distance between the first electrode body and the first data line is less than or equal to the distance between the first electrode body and the second data line, and the overlapping area between the orthographic projection of the first electrode protrusion on the base substrate and the orthographic projection of the first data line on the base substrate is less than or equal to the overlapping area between the orthographic projection of the second electrode protrusion on the base substrate and the orthographic projection of the second data line on the base substrate; or

[0014] The distance between the first electrode body and the first data line is greater than or equal to the distance between the first electrode body and the second data line, and the overlapping area between the orthographic projection of the first electrode protrusion on the base substrate and the orthographic projection of the first data line on the base substrate is greater than or equal to the overlapping area between the orthographic projection of the second electrode protrusion on the base substrate and the orthographic projection of the second data line on the base substrate.

[0015] In some embodiments, the first electrode protrusion is provided in the same layer as the first electrode body and is electrically connected thereto, and the first electrode protrusion protrudes from the first electrode body toward the first data line; and / or,

[0016] The second electrode protrusion is provided in the same layer as the first electrode body and is electrically connected thereto. The second electrode protrusion protrudes from the first electrode body toward the second data line.

[0017] In some embodiments, the first data line includes:

[0018] a first data line body; and

[0019] The first data line protrusion is located on a side of the first data line body close to the first electrode.

[0020] The second data line includes:

[0021] a second data line body; and

[0022] The second data line protrusion is located on a side of the second data line body close to the first electrode.

[0023] The distance between the first data line protrusion and the first electrode body is less than or equal to the distance between the second data line protrusion and the first electrode body, and the overlapping area between the orthographic projection of the first data line protrusion on the base substrate and the orthographic projection of the first electrode protrusion on the base substrate is less than or equal to the overlapping area between the orthographic projection of the second data line protrusion on the base substrate and the orthographic projection of the second electrode protrusion on the base substrate; or

[0024] The distance between the first data line protrusion and the first electrode body is greater than or equal to the distance between the second data line protrusion and the first electrode body, and the overlapping area between the orthographic projection of the first data line protrusion on the base substrate and the orthographic projection of the first electrode protrusion on the base substrate is greater than or equal to the overlapping area between the orthographic projection of the second data line protrusion on the base substrate and the orthographic projection of the second electrode protrusion on the base substrate.

[0025] In some embodiments, the first data line protrusion and the first data line body are provided in the same layer and are electrically connected; and / or,

[0026] The second data line protrusion and the second data line body are arranged in the same layer and are electrically connected.

[0027] In some embodiments, the first data line protrusion and the second data line protrusion are located between adjacent first electrode columns, and the first data line protrusion and the second data line protrusion are spaced apart along the first direction; and / or,

[0028] The array substrate further includes a scan signal line extending along a first direction, and the orthographic projections of the first data line protrusion and the second data line protrusion on the base substrate do not overlap with the orthographic projection of the scan signal line on the base substrate.

[0029] In some embodiments, the array substrate further includes:

[0030] an active layer located between the base substrate and the first electrode, wherein an orthographic projection of at least a portion of the active layer on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate, and the at least a portion of the active layer is electrically connected to the data line;

[0031] The at least a portion of the active layer, the first data line protrusion, and at least a portion of the second data line protrusion are disposed in the same layer.

[0032] In some embodiments, the array substrate further includes: a plurality of second electrodes located between the base substrate and the first electrodes, the plurality of second electrodes and the plurality of first electrodes being located on different layers of the array substrate, wherein orthographic projections of the plurality of second electrodes on the base substrate at least partially overlap with orthographic projections of the plurality of first electrodes on the base substrate;

[0033] The first electrode protrusion includes a first sub-electrode protrusion and a second sub-electrode protrusion, and the second electrode protrusion includes a third sub-electrode protrusion and a fourth sub-electrode protrusion;

[0034] The first sub-electrode protrusion and the third sub-electrode protrusion are provided in the same layer as the first electrode and are electrically connected;

[0035] The second sub-electrode protrusion and the fourth sub-electrode protrusion are provided in the same layer as the second electrode and are electrically connected;

[0036] The orthographic projections of the first sub-electrode protrusion, the second sub-electrode protrusion, the third sub-electrode protrusion, and the fourth sub-electrode protrusion on the base substrate do not overlap with each other.

[0037] In some embodiments, the first electrode is one of a pixel electrode and a common electrode.

[0038] In some embodiments, a plurality of first electrode protrusions and a plurality of second electrode protrusions on the same first electrode column are alternately arranged along the second direction.

[0039] In some embodiments, the first electrode protrusion and the second electrode protrusion are symmetrical with respect to the center of the first electrode.

[0040] In some embodiments, the orthographic projections of the first electrode protrusion and the second electrode protrusion on the base substrate are one of a triangle, a sector, a rectangle, and an ellipse.

[0041] Another aspect of the embodiments of the present disclosure provides a display device comprising a display substrate as described above.

[0042] In some embodiments, the display device further includes a color filter substrate, and the color filter substrate is arranged opposite to the array substrate;

[0043] Wherein, the color film substrate comprises:

[0044] a light shielding layer, wherein an orthographic projection of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate;

[0045] The first electrode protrusion and the second electrode protrusion are located on a side of the light shielding layer close to the base substrate, and the orthographic projections of the first electrode protrusion and the second electrode protrusion on the base substrate are respectively located within the orthographic projections of the light shielding layer on the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0047] Figure 1 A schematic diagram of a pixel array in related art is schematically shown;

[0048] Figure 2 Schematically shows a display screen and a data line signal waveform diagram of a pixel structure with crosstalk in the related art;

[0049] Figure 3A is a schematic plan view of an array substrate according to some exemplary embodiments of the present disclosure;

[0050] Figure 3B According to some exemplary embodiments of the present disclosure, the array substrate is Figure 3A A cross-sectional view taken along line AA';

[0051] Figure 3C is a planar schematic diagram of a first electrode in an array substrate that is offset according to some exemplary embodiments of the present disclosure;

[0052] Figure 4A is a schematic plan view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0053] Figure 4B According to some other exemplary embodiments of the present disclosure, the array substrate is Figure 4A A cross-sectional view taken along line BB';

[0054] Figure 4C is a planar schematic diagram of a first electrode in an array substrate that is offset according to some other exemplary embodiments of the present disclosure;

[0055] Figure 5A is a schematic plan view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0056] Figure 5B According to some other exemplary embodiments of the present disclosure, the array substrate is Figure 5A A cross-sectional view taken along line CC';

[0057] Figure 5C is a planar schematic diagram of a first electrode in an array substrate that is offset according to some other exemplary embodiments of the present disclosure;

[0058] Figure 6A is a schematic plan view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0059] Figure 6B According to some other exemplary embodiments of the present disclosure, the array substrate is Figure 6A A cross-sectional view taken along line DD';

[0060] Figure 6C is a planar schematic diagram of a second electrode in an array substrate that is offset according to some other exemplary embodiments of the present disclosure;

[0061] Figure 7Ais a schematic plan view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0062] Figure 7B According to some other exemplary embodiments of the present disclosure, the array substrate is Figure 7A A cross-sectional view taken along line EE';

[0063] Figure 7C is a planar schematic diagram of a first electrode and / or a second electrode in an array substrate that is offset according to some other exemplary embodiments of the present disclosure;

[0064] Figure 8 It is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.

[0065] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0066] The technical solution of the present disclosure is further described in detail below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of the present disclosure and should not be construed as limiting the present disclosure.

[0067] Furthermore, in the following detailed description, for ease of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent that one or more embodiments can be practiced without these specific details.

[0068] It should be understood that, although the terms first, second, etc. can be used here to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiments, the first element can be named as the second element, and similarly, the second element can be named as the first element. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0069] It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on another element or layer or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers, such as "between," "directly between," "adjacent," "directly adjacent," and the like, should be interpreted in a like fashion. Also, the terms "first," "second," "third," etc. can be understood as having either a chronological and / or a logical meaning. For example, a first element can be understood as having a meaning of a chronologically first element, a logically first element, or the like. Further, the X-axis, Y-axis and Z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions not perpendicular to each other. For the purpose of the present disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as any one of X, Y and Z, either alone or in any combination(s) of two or more of X, Y and Z, such as XYZ, XY, YZ and XZ.

[0070] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0071] First, a crosstalk problem occurring in a display in the related art is simply explained.

[0072] Figure 1 A pixel array of the related art is schematically shown. Figure 2 A display screen and a data line signal waveform when a pixel structure of the related art occurs crosstalk are schematically shown.

[0073] Reference Figure 1D1-D7 are data lines in the pixel structure, and G1-G4 are scanning signal lines in the pixel structure. The pixel electrodes (the pixel electrode shape can be an irregular pattern) are arranged on the left and right sides of each data line, and the pixel electrodes are arranged in column inversion, that is, each pixel electrode has the same polarity as the pixel electrode adjacent to it in the column and has the opposite polarity as the pixel electrode adjacent to it in the row; the polarity of the pixel electrode is changed when the next picture data is changed, that is, the polarity of the pixel electrode is changed. The structure also includes a thin film transistor (TFT), the gate of the TFT is electrically connected to the scanning signal line, the drain of the TFT is electrically connected to the data line, and the source of the TFT is electrically connected to the pixel electrode. Exemplarily, a plurality of liquid crystal pixels on a liquid crystal display can be driven by the TFT integrated behind, so that high-speed, high-brightness, and high-contrast screen information can be displayed. The TFT is an N-type TFT, when the gate voltage is high, the TFT of the pixel is turned on, and the data line loads the voltage signal into the pixel electrode; when the gate voltage is low, the TFT is turned off, and the storage capacitor between the pixel electrode and the common electrode allows the voltage value in the pixel electrode to be maintained until the next frame.

[0074] In the column inversion architecture product, the incidence of vertical crosstalk (V-CT) is high, and the inventors have found that this problem can be caused by the coupling capacitance between the pixel electrode and the two adjacent data lines.

[0075] Reference Figure 1 In the column inversion architecture, the polarities of the two adjacent data lines are opposite, the pixel electrode and the electrically connected data line adjacent to one side form a coupling capacitance C pd1 , and the pixel electrode and the electrically isolated data line adjacent to the other side form a coupling capacitance C pd2 . Ideally, C pd1 =C pd2 , because the polarities of the two adjacent data lines are opposite, so that the effects of the two adjacent data lines on the pixel electrode cancel each other out. However, in the actual process, the pixel pattern is offset to a certain extent, so that C pd1 ≠C pd2 . It should be noted that electrical connection includes direct contact between two elements, and also includes connection between two elements through a conductive line or other entity line that can transmit electrical signals; electrical isolation includes direct separation between two elements in space, and also includes separation between two elements by an insulating material.

[0076] Taking a white window picture as an example, Figure 2The following are schematic diagrams of the signal waveforms of the white window image and the two data lines adjacent to the pixel electrode (assuming that the current polarity of the adjacent electrically connected data lines is positive). Figure 2 (a) is a schematic diagram of the normal white window image and the signal waveforms of the two data lines adjacent to the pixel electrode. There are two cases of pixel pattern offset. One is that the pixel pattern offsets to the adjacent electrically connected data line, making C pd1 Increase, and C pd2 Decrease, that is, C pd1 >C pd2 In this case, if Figure 2 As shown in (b), when the signal scans to area B, the adjacent electrically connected data lines are positive and the signal increases, while the adjacent electrically isolated data lines are negative and the amplitude decreases. Due to the influence of the coupling capacitance C pd1 >C pd2 , the signals of area A & C are both pulled high, and area A becomes brighter. At this time, area C is the negative polarity signal of the previous frame. After the signal is pulled high, the voltage difference between the pixel electrode and the common electrode decreases, causing area C to darken. Another is that the pixel pattern shifts to the adjacent electrically isolated data line, making area C pd1 Decrease, C pd2 Increase, that is, C pd1 <C pd2 In this case, if Figure 2 As shown in (c), when the signal line scans to area B, the adjacent electrically isolated data line signal increases in negative polarity due to the influence of the coupling capacitor C pd1 <C pd2 , the signals in areas A & C are both pulled low, area A becomes darker, and area C is the negative polarity signal of the previous frame. After the signal is pulled low, the voltage difference between the pixel electrode and the common electrode increases, causing area C to become brighter.

[0077] In order to reduce the crosstalk problem in pixel display, embodiments of the present disclosure provide an array substrate and a display device.

[0078] Figure 3A is a schematic plan view of an array substrate according to some exemplary embodiments of the present disclosure, Figure 3B According to some exemplary embodiments of the present disclosure, the array substrate is Figure 3A A cross-sectional view taken along line AA' in FIG.

[0079] The array substrate 10 includes: a base substrate 11; a plurality of pixel electrodes 16, located on the base substrate 11 and arranged in an array along a first direction and a second direction to form pixel electrode rows extending in the first direction and pixel electrode columns extending in the second direction; and data lines 14, located on the base substrate 11 and extending along the second direction, with the orthographic projections of the data lines 14 on the base substrate 11 and the orthographic projections of the first electrode columns on the base substrate 11 alternately arranged.

[0080] In the illustrated embodiment, the scanning signal line 17 extends along a first direction, and the data line 14 extends along a second direction. The multiple scanning signal lines 17 and the multiple data lines 14 define multiple pixel units. The pixel units include: thin film transistors, pixel electrodes and common electrodes. The pixel electrodes are located on the side of the common electrode away from the substrate.

[0081] Herein, unless otherwise specifically stated, the expression “first electrode” may refer to one of a pixel electrode and a common electrode, and the expression “second electrode” may refer to the other of the pixel electrode and the common electrode.

[0082] Reference Figure 3A The array substrate 10 includes a plurality of pixel electrodes 16, which are arranged in an array along a first direction and a second direction. For example, the first direction intersects the second direction. For example, the first direction is perpendicular to the second direction. For example, the first direction is the X-axis direction, and the second direction is the Y-axis direction.

[0083] Exemplarily, the data line 14 is located between adjacent pixel electrode columns, and the data line 14 is electrically connected to the pixel electrode column on one side thereof and electrically isolated from the pixel electrode column on the other side thereof. Exemplarily, the first data line 141 is electrically connected to the pixel electrode on its right side and electrically isolated from the pixel electrode on its left side. The first data line 141 is a first data line electrically connected relative to the pixel electrode on its right side, and the first data line 141 is a second data line electrically isolated relative to the pixel electrode on its left side, that is, the first data line 141 and the second data line 142 are both data lines 14. In order to clearly illustrate the positional relationship between the data line 14 and the pixel electrode 16 in the embodiment of the present disclosure, the first data line 141 and the second data line 142 are used to distinguish them. The signals transmitted by adjacent data lines 14 have opposite polarities. For example, the current polarity of the first data line 141 is positive, and the current polarity of the second data line 142 is negative.

[0084] The array substrate 10 further includes a plurality of common electrodes 12. Pixel electrodes 16 are disposed opposite the common electrodes 12. The pixel electrodes 16 and the common electrodes 12 are located on different layers of the array substrate 11. The orthographic projections of the pixel electrodes 16 on the base substrate 11 at least partially overlap with the orthographic projections of the common electrodes 12 on the base substrate 11. Exemplarily, the common electrodes 12 are electrically connected to corresponding common electrode lines 121. The common electrode lines 121 extend along a first direction. Multiple pixel units arranged along the first direction correspond to the same common electrode line 121. The common electrode lines 121 are disposed on the same layer as the scan signal lines 17.

[0085] Reference Figure 5AThe array substrate 10 further includes a thin film transistor 18, which includes at least a gate electrode and an active layer 140 corresponding to the gate electrode. The active layer 140 may include a source electrode and a drain electrode. For example, the gate electrode is connected to the scanning signal line 17, and the gate line extends perpendicular to the direction in which the data line 14 extends. One of the source electrode and the drain electrode is electrically connected to the pixel electrode of the array substrate 10, and the other is electrically connected to the data line 14.

[0086] Reference Figure 3B The first insulating layer 13 and the second insulating layer 15 serve as electrical isolation. For example, the first insulating layer 13 is a gate insulating layer, and its preparation material can be silicon oxide; the second insulating layer 15 is a passivation layer, and its preparation material can be silicon nitride, silicon oxynitride, etc.

[0087] In an exemplary embodiment of the present disclosure, the first electrode may be a pixel electrode 16. Exemplarily, at least one first electrode 16 includes: a first electrode body 161; a first electrode protrusion 162, located on a side of the first electrode body 161 close to the first data line 141; a second electrode protrusion 163, located on a side of the first electrode body 161 close to the second data line 142; the distance between the first electrode body 161 and the first data line 141 is less than or equal to the distance between the first electrode body 161 and the second data line 142; and the overlapping area between the orthographic projection of the first electrode protrusion 162 on the base substrate 11 and the orthographic projection of the first data line 141 on the base substrate 11 is less than or equal to the overlapping area between the first electrode protrusion 162 and the orthographic projection of the first data line 141 on the base substrate 11. The overlapping area of ​​the orthographic projection of the second electrode protrusion 163 on the base substrate 11 and the orthographic projection of the second data line 142 on the base substrate 11; or the distance between the first electrode body 161 and the first data line 141 is greater than or equal to the distance between the first electrode body 161 and the second data line 142, and the overlapping area of ​​the orthographic projection of the first electrode protrusion 162 on the base substrate 11 and the orthographic projection of the first data line 141 on the base substrate 11 is greater than or equal to the overlapping area of ​​the orthographic projection of the second electrode protrusion 163 on the base substrate 11 and the orthographic projection of the second data line 142 on the base substrate 11.

[0088] The first electrode body 161 is provided with a partial opening area 1611, which can be composed of a plurality of strip-shaped slits, which is conducive to improving the light transmittance of the array substrate and display panel made of the electrode. Figure 3A As shown, the single-layer structure includes a first electrode protrusion 162 and a second electrode protrusion 163. In the embodiment of the present disclosure, the first electrode protrusion 162 and the second electrode protrusion 163 are provided on both sides of the first electrode body 161 to offset the vertical crosstalk problem caused by the unequal coupling capacitance on both sides due to the offset of the pixel pattern.

[0089] Figure 3C1 is a plan view schematically showing a first electrode offset in an array substrate according to some exemplary embodiments of the present disclosure.

[0090] In an exemplary embodiment of the present disclosure, the first electrode protrusion 162 is arranged on the same layer as the first electrode body 161 and is electrically connected, and the first electrode protrusion 162 protrudes from the first electrode body 161 toward the first data line 141; and / or, the second electrode protrusion 163 is arranged on the same layer as the first electrode body 161 and is electrically connected, and the second electrode protrusion 163 protrudes from the first electrode body 161 toward the second data line 142.

[0091] In some embodiments, the distance between the pixel electrode 16 and the adjacent first data line 141 is small, and a coupling capacitor is formed between the two. In this article, the coupling capacitor is referred to as coupling capacitor C. pd1 The distance between the pixel electrode 16 and the adjacent second data line 142 is small, and a coupling capacitor is formed between the two. In this article, the coupling capacitor is referred to as coupling capacitor C. pd2 .

[0092] In this embodiment, the first electrode protrusion 162 partially overlaps with the first data line 141, and a coupling capacitor is formed between the two. The coupling capacitor is referred to as coupling capacitor C. pd1 The second electrode protrusion 163 partially overlaps with the first data line 141, and a coupling capacitor is formed between the two. The coupling capacitor is referred to as coupling capacitor C. pd2 '.

[0093] For example, in an ideal case, the pixel electrode 16 is located in the middle of two adjacent data lines 14. pd1 =C pd2 , C pd1 '=C pd2 ', the effects of adjacent data lines 14 cancel each other out and no crosstalk occurs.

[0094] In the actual production process, the pixel electrode 16 may shift to a certain extent toward the first data line 141 or the second data line 142. In the first case, the pixel electrode 16 shifts toward the first data line 141, such as Figure 3C As shown in (a), in this case C pd1 Increase, C pd2 Decrease. C pd1 'As the overlapping area between the first electrode protrusion 162 and the first data line 141 decreases, C pd2 ' increases with the increase of the overlapping area between the second electrode protrusion 163 and the second data line 142. In the second case, the pixel electrode 16 is offset toward the second data line 142, as shown in FIG. Figure 3C As shown in (b), in this case Cpd1 Decrease, C pd2 Increase. C pd1 As the overlapping area between the first electrode protrusion 162 and the first data line 141 increases, C pd2 ' decreases as the overlapping area between the second electrode protrusion 163 and the second data line 142 decreases.

[0095] As shown in Example 1 in Table 1, the changes in coupling capacitance when the first electrode is offset are listed. During the product design process, the size and shape of the additional structure of the first electrode protrusion 162 and the second electrode protrusion 163 are determined through simulation according to the product characteristics so that ΔC pd1 =ΔC pd2 ', ΔC pd1 '=ΔC pd2 ; or ΔC pd1 =ΔC pd1 ', ΔC pd2 =ΔC pd2 In this way, since the polarities of adjacent data lines are opposite, the effects of the coupling capacitors on the first electrodes cancel each other out, which can effectively solve the vertical crosstalk problem in the product.

[0096] Table 1

[0097]

[0098] It should be noted that the relevant technical solution is the above Figure 2 The scheme described in the corresponding part is that the first electrode is a conventional pixel electrode and does not include any additional structure. In the embodiment of the present disclosure, the additional structure of the first electrode protrusion 162 and the second electrode protrusion 163 is provided on both sides of the first electrode body 161, through C' pd1 and C' pd2 The coupling capacitance is adjusted to meet the requirements of C pd1 +C pd1 '=C pd2 +C pd2 ', thereby at least alleviating or even solving the problem of vertical crosstalk.

[0099] Figure 4A is a schematic plan view of an array substrate according to some other exemplary embodiments of the present disclosure, Figure 4B According to some other exemplary embodiments of the present disclosure, the array substrate is Figure 4A A cross-sectional view taken along line BB'.

[0100] In an exemplary embodiment of the present disclosure, the first data line 141 includes: a first data line body 1411; and a first data line protrusion 1412, which is located on a side of the first data line body 1411 close to the pixel electrode 16. The second data line 142 includes: a second data line body 1421; and a second data line protrusion 1422, which is located on a side of the second data line body 1421 close to the pixel electrode 16. The distance between the first data line protrusion 1412 and the first electrode body 161 is less than or equal to the distance between the second data line protrusion 1422 and the first electrode body 161. The orthographic projection of the first data line protrusion 1412 on the substrate 11 is aligned with the orthographic projection of the first electrode protrusion 162 on the substrate 16. The overlapping area of ​​the orthographic projection of the first data line protrusion 1412 on the substrate 11 is less than or equal to the overlapping area of ​​the orthographic projection of the second data line protrusion 1422 on the substrate 11 and the orthographic projection of the second electrode protrusion 163 on the substrate 11; or the distance between the first data line protrusion 1412 and the first electrode body 161 is greater than or equal to the distance between the second data line protrusion 1422 and the first electrode body 161, and the overlapping area of ​​the orthographic projection of the first data line protrusion 1412 on the substrate 11 and the orthographic projection of the first electrode protrusion 162 on the substrate 11 is greater than or equal to the overlapping area of ​​the orthographic projection of the second data line protrusion 1422 on the substrate 11 and the orthographic projection of the second electrode protrusion 163 on the substrate 11.

[0101] In an exemplary embodiment of the present disclosure, the first data line protrusion 1412 and the first data line body 1411 are disposed in the same layer and are electrically connected; and / or the second data line protrusion 1422 and the second data line body 1421 are disposed in the same layer and are electrically connected.

[0102] In this embodiment, the additional structure is a double-layer structure. In this double-layer structure, a first electrode protrusion 162 and a second electrode protrusion 163 are provided on a first conductive layer, and a first data line protrusion 1412 and a second data line protrusion 1422 are provided on a second conductive layer. For example, the first conductive layer may be the layer where the pixel electrode 16 resides, i.e., the first electrode protrusion 162 and the second electrode protrusion 163 are fabricated on the same layer as the pixel electrode 16 and are electrically connected. For another example, the second conductive layer may be the layer where the data line 14 resides, i.e., the first data line protrusion 1412 and the second data line protrusion 1422 are fabricated on the same layer as the main body of the data line and are electrically connected.

[0103] In an exemplary embodiment of the present disclosure, the first data line protrusion 1412 and the second data line protrusion 1422 are located between adjacent first electrode columns, and the first data line protrusion 1412 and the second data line protrusion 1422 are spaced apart along the first direction. Exemplarily, the array substrate 10 further includes a scan signal line 17 extending along the first direction, and the orthographic projections of the first data line protrusion 1412 and the second data line protrusion 1422 on the base substrate 11 do not overlap with the orthographic projection of the scan signal line 17 on the base substrate 11.

[0104] The first electrode protrusion 162 , the second electrode protrusion 163 , the first data line protrusion 1412 , and the second data line protrusion 1422 are disposed between the gaps between the first electrode columns, which helps to make the structure more compact and save space.

[0105] Figure 4C 1 is a plan view schematically showing a first electrode offset in an array substrate according to some other exemplary embodiments of the present disclosure.

[0106] In this embodiment, the first electrode protrusion 162 and the first data line protrusion 1412 at least partially overlap, and a coupling capacitor is formed between the two. The coupling capacitor is referred to as coupling capacitor C. pd1 The second electrode protrusion 163 and the second data line protrusion 1422 at least partially overlap, and a coupling capacitor is formed between the two, which is referred to as a coupling capacitor C. pd2 '.

[0107] For example, in an ideal case, the double-layer structure has some overlapping areas, and the resulting coupling capacitances are C pd1 ' and C pd2 ', according to the required product characteristics, the final shape and size of the pattern are confirmed through simulation, so that ideally C pd1 '=C pd2 '. And C pd1 =C pd2 , so no crosstalk occurs. When the pixel electrode 16 is offset, if it is offset toward the first data line 141, then Figure 4C As shown in (a), at this time C pd1 Increase, C pd2 decreases, the overlapping area of ​​the additional structure on the left decreases, C pd1 'decreases, the overlapping area of ​​the additional structure on the right increases, C pd2 On the contrary, when the pixel electrode 16 is offset toward the second data line 142, as shown in FIG. Figure 4C As shown in (b), C pd1 Decrease, C pd2 Increase, the overlapping area of ​​the additional structure on the left increases, C pd1C pd2 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd1 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd2 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd1 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd2 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd1 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd1 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd2 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd2 decreases. As shown in Example 2 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC

[0108] Figure 5A is a plan view of an array substrate according to another exemplary embodiment of the present disclosure, Figure 5B is a cross-sectional view of the array substrate taken along line CC' in Figure 5A .

[0109] In the exemplary implementation of the present disclosure, the array substrate 10 comprises: an active layer 140 located between the substrate substrate 11 and the first electrode 16, at least a portion of the active layer 140 has an orthogonal projection on the substrate substrate 11 at least partially overlapping with an orthogonal projection of the data line 14 on the substrate substrate 11, and the at least a portion of the active layer 140 is electrically connected with the data line 14. The at least a portion of the active layer 140, the first data line protruding portion 162 and the second data line protruding portion 163 are formed in the same layer.

[0110] In this embodiment, the additional structure is a double-layer structure, as shown in Figure 5A and Figure 5B , in which a first electrode protruding portion 162 and a second electrode protruding portion 163 are provided in a first conductive layer, and a first data line protruding portion 1412 and a second data line protruding portion 1422 are provided in a second conductive layer. For example, the first conductive layer can be the layer in which the pixel electrode 16 is located, i.e., the first electrode protruding portion 162 and the second electrode protruding portion 163 are formed in the same layer as the pixel electrode 16 and are electrically connected with the pixel electrode 16. For another example, the second conductive layer can be the active layer 140, i.e., the first data line protruding portion 1412 and the second data line protruding portion 1422 are located in the active layer 140. It should be noted that the active layer 140 can be exposed separately, in which case the first data line protruding portion 1412 and the second data line protruding portion 1422 are formed in the same layer as the active layer 140 and are electrically connected with the data line 14; or a Halftone exposure process can be used, for example, the layer in which the active layer 140 and the data line 14 are located is exposed in one Mask, in which case the first data line protruding portion 1412 and the second data line protruding portion 1422 are obtained by etching the surface metal of the data line 14 after ashing.

[0111] Figure 5C is a plan view of the array substrate according to another exemplary embodiment of the present disclosure, in which the first electrodes are offset.

[0112] Exemplarily, in the ideal case, the double-layer structure has a partial area overlap, and the coupling capacitances generated are C pd1 and C pd2 ', and at this time, C pd1 ' = C pd2 '. At this time, C pd1 = C pd2 , and no crosstalk occurs. If the pattern is offset, as shown in (a) and (b) of Figure 5C , C pd1 , C pd2 , C pd1 ' and C pd2 ' change as in Embodiment 2, as shown in Embodiment 3 in Table 2, by reasonably designing the shape and size of the additional structure, ΔC pd1 = ΔC pd2 ', ΔC pd1 ' = ΔC pd2 ; or ΔC pd1 = ΔC pd1 ', ΔC pd2 = ΔC pd2 ', the problem of vertical crosstalk can be at least alleviated or even solved.

[0113] Table 2

[0114]

[0115]

[0116] It should be noted that in Embodiment 2, the additional structure of the first electrode protruding portion 162 and the second electrode protruding portion 163 arranged on both sides of the first electrode body 161, and the first data line protruding portion 1412 and the second data line protruding portion 1422 arranged on both sides of the data line. In Embodiment 3, the first data line protruding portion 1412 and the second data line protruding portion 1422 are different in position in the data line. By adjusting C' pd1 and C' pd2 , the coupling capacitances satisfy C pd1 + C pd1 ' = C pd2 + C pd2 ', thereby at least partially alleviating or even solving the problem of vertical crosstalk.

[0117] Figure 6A is a plan view of the array substrate according to another exemplary embodiment of the present disclosure, Figure 6BAccording to some other exemplary embodiments of the present disclosure, the array substrate is Figure 6A A cross-sectional view taken along line DD' in FIG.

[0118] In an exemplary embodiment of the present disclosure, the first electrode may be the common electrode 12. For example, at least portions of the first electrode protrusion 162 and the second electrode protrusion 163 are disposed in the same layer as the common electrode 12 and are electrically connected thereto.

[0119] In this embodiment, the additional structure is a single-layer structure, such as Figure 6A As shown, the single-layer structure includes a first electrode protrusion 162 and a second electrode protrusion 163. The first electrode protrusion 162 and the second electrode protrusion 163 are made in the same layer as the common electrode 12 and are electrically connected.

[0120] Figure 6C 1 is a planar schematic diagram of a second electrode offset in an array substrate according to some other exemplary embodiments of the present disclosure.

[0121] In some embodiments, the distance between the common electrode 12 and the adjacent first data line 141 is small, and a coupling capacitor is formed between the two. In this article, the coupling capacitor is referred to as coupling capacitor C. dc1 The distance between the common electrode 12 and the adjacent second data line 142 is small, and a coupling capacitor is formed between the two. In this article, the coupling capacitor is referred to as coupling capacitor C. dc2 .

[0122] In this embodiment, the first electrode protrusion 162 partially overlaps with the first data line 141, and a coupling capacitor is formed between the two. The coupling capacitor is referred to as coupling capacitor C. dc1 The second electrode protrusion 163 partially overlaps with the first data line 141, and a coupling capacitor is formed between the two. The coupling capacitor is referred to as coupling capacitor C. dc2 '.

[0123] For example, in an ideal case, the coupling capacitance C between the additional structures on the left and right sides of the common electrode 12 and the data line 14 is dc1 '=C dc2 ', the coupling capacitance C between the common electrode 12 and the data line 14 dc1 =C dc2 , the coupling capacitance C between the pixel electrode 16 and the data line 14 pd1 =C pd2 , no vertical crosstalk problem occurs at this time.

[0124] During the product manufacturing process, process fluctuations may cause the common electrode 12 to shift relative to the first data line 141 or the second data line 142. For example, the common electrode 12 may shift to a certain extent toward the first data line 141 or the second data line 142. Figure 6C As shown in (a), the overlapping area between the first electrode protrusion 162 of the additional structure on the left side of the common electrode 12 and the data line 14 is reduced. dc1 'decreases, the overlapping area between the second electrode protrusion 163 of the additional structure on the right and the data line 14 increases, C dc2 'Increases, at the same time, the distance between the common electrode 12 and the first data line 141 decreases, and the distance between the common electrode 12 and the second data line 142 increases, so that C dc1 Increase, Cd c2 When the common electrode 12 deviates toward the second data line 142, as shown in FIG. Figure 6C As shown in (b), the change in coupling capacitance between the common electrode 12 and the additional structure and the data line 14 is opposite to the change in capacitance toward the first data line 141. As shown in Example 4 in Table 3, the shape and size of the additional structure are determined by simulation so that ΔC dc1 =ΔC dc1 ',ΔC dc2 =ΔC dc2 ', or ΔC dc1 =ΔC dc2 ',ΔC dc1 '=ΔC dc2 In this way, the coupling capacitance of the data line 14 to the common electrode 12 remains unchanged, and the total coupling capacitance between the common electrode 12 and the data line 14 also remains unchanged, thereby at least alleviating or even solving the problem of vertical crosstalk.

[0125] Figure 7A is a schematic plan view of an array substrate according to some other exemplary embodiments of the present disclosure, Figure 7B According to some other exemplary embodiments of the present disclosure, the array substrate is Figure 7A A cross-sectional view taken along line EE'.

[0126] In an exemplary embodiment of the present disclosure, the first electrode may be the pixel electrode 16 , and the second electrode may be the common electrode 12 ; or, the first electrode may be the common electrode 12 , and the second electrode may be the pixel electrode 16 .

[0127] In an exemplary embodiment of the present disclosure, the first electrode protrusion 162 includes a first sub-electrode protrusion 162' and a second sub-electrode protrusion 162", and the second electrode protrusion 163 includes a third sub-electrode protrusion 163' and a fourth sub-electrode protrusion 163". The first sub-electrode protrusion 162' and the third sub-electrode protrusion 163' are arranged on the same layer as the pixel electrode 16 and are electrically connected; the second sub-electrode protrusion 162" and the fourth sub-electrode protrusion 163" are arranged on the same layer as the common electrode 12 and are electrically connected. The orthographic projections of the first sub-electrode protrusion 162', the second sub-electrode protrusion 162", the third sub-electrode protrusion 163' and the fourth sub-electrode protrusion 163" on the base substrate 11 do not overlap with each other.

[0128] In this embodiment, the additional structure is a double-layer structure, and the additional structure includes a first electrode protrusion 162 and a second electrode protrusion 163. In the double-layer structure, a first sub-electrode protrusion 162' and a third sub-electrode protrusion 163' are provided on the first conductive layer, and a second sub-electrode protrusion 162" and a fourth sub-electrode protrusion 163" are provided on the second conductive layer. For example, the first conductive layer may be the layer where the pixel electrode 16 is located, that is, the first sub-electrode protrusion 162' and the third sub-electrode protrusion 163' are made in the same layer as the pixel electrode 16 and are electrically connected. For another example, the second conductive layer may be the common electrode 12, that is, the second sub-electrode protrusion 162" and the fourth sub-electrode protrusion 163" are made in the same layer as the common electrode 12 and are electrically connected. When the common electrode 12 is relatively offset, the additional structure located in the second conductive layer is used to compensate for the offset. dc1 and C dc2 The change of C keeps the coupling capacitance between the common electrode 12 and the two adjacent data lines 14 unchanged. When the pixel electrode 16 deviates, the additional structure located in the first conductive layer compensates C pd1 and C pd2 , so that it remains unchanged, thereby at least alleviating or even solving the problem of vertical crosstalk.

[0129] Figure 7C 1 is a planar schematic diagram of pixel electrodes and / or common electrodes in an array substrate according to some other exemplary embodiments of the present disclosure that are offset.

[0130] The four situations in which the pixel electrode 16 and the common electrode 12 are offset and the corresponding coupling capacitance changes are shown in Example 5 in Table 3.

[0131] Figure 7C (a) is a schematic diagram of the pixel electrode 16 and the common electrode 12 in Example 5, both of which are offset toward the first data line 141 ; Figure 7C (b) is a schematic diagram of the pixel electrode 16 and the common electrode 12 in Example 5, both of which are offset toward the second data line 142 ;Figure 7C (c) is a schematic diagram of the common electrode 12 shifting toward the first data line 141 and the pixel electrode 16 shifting toward the second data line 142 in Example 5; Figure 7C (d) is a schematic diagram of Example 5 in which the common electrode 12 is offset toward the second data line 142 and the pixel electrode 16 is offset toward the first data line 141. All four cases can achieve C dc1 +C dc1 '=C dc2 +C dc2 ', C pd1 +C pd1 '=C pd2 +C pd2 ', thereby at least alleviating or even solving the problem of vertical crosstalk.

[0132] Table 3

[0133]

[0134]

[0135] In an exemplary embodiment of the present disclosure, the plurality of first electrode protrusions 162 and the plurality of second electrode protrusions 163 on the same first electrode column are staggered along the second direction, as shown in FIG. Figure 3A 、 Figure 5A 、 Figure 6A 、 Figure 7A As shown, the staggered arrangement of the additional structures is conducive to making the structure more compact. The multiple first electrode protrusions 162 and the multiple second electrode protrusions 163 on the same first electrode row are arranged in parallel along the first direction, as shown in FIG. Figure 4A The first electrode protrusion 162 and the second electrode protrusion 163 are symmetrical with respect to the center of the pixel electrode 16, as shown in FIG. Figure 3A 、 Figure 5A 、 Figure 6A 、 Figure 7A The first electrode protrusion 162 and the second electrode protrusion 163 are symmetrical with respect to the pixel electrode 16. Figure 4A The additional structure is connected to the pixel electrode 16 and is manufactured in the same layer as the pixel electrode 16, which does not increase the number of masks and facilitates the manufacturing process.

[0136] In the exemplary embodiment of the present disclosure, the orthographic projections of the first electrode protrusion 162 and the second electrode protrusion 163 on the base substrate 11 are one of a triangle, a sector, a rectangle, and an ellipse. The size and shape of the additional structure can be determined by computational simulation according to the characteristics of different products.

[0137] The embodiment of the present disclosure further provides a display device, such as Figure 8 As shown, Figure 8This is a schematic diagram of the structure of a display device 100 provided in an embodiment of the present disclosure. The display device 100 includes a device body 40, an array substrate 10, a liquid crystal layer 20, and a color filter substrate 30 disposed on the device body 40. The liquid crystal layer 20 includes a plurality of liquid crystal molecules and is sandwiched between the array substrate 10 and the color filter substrate 30. The device body 40 includes a housing and components such as a processor, a power supply, and a camera disposed therein. The display device 100 can employ the array substrate 10 provided in the above embodiment.

[0138] In an exemplary embodiment of the present disclosure, the color filter substrate 30 is arranged opposite to the array substrate 10; wherein the color filter substrate 30 and the array substrate 10 include: a light shielding layer 19, the orthographic projection of the light shielding layer 19 on the base substrate 11 at least partially overlaps with the orthographic projection of the data line 14 on the base substrate 11; the first electrode protrusion 162 and the second electrode protrusion 163 are located on the side of the light shielding layer 19 close to the base substrate 11, and the orthographic projections of the first electrode protrusion 162 and the second electrode protrusion 163 on the base substrate 11 are respectively located within the orthographic projection of the light shielding layer 19 on the base substrate 11.

[0139] Reference Figure 8 The light-shielding layer 19 is located on the color filter substrate 30 and is, for example, a black matrix. The additional structure is located below the light-shielding layer 19 (the placement can be flexibly adjusted according to the design). Any abnormal brightness caused by an abnormal electric field near the additional structure is blocked and does not affect the display image. Furthermore, the size of the light-shielding layer 19 and the pixel structure does not require additional adjustment, and optical properties such as pixel transmittance and contrast are not affected.

[0140] In the embodiments of the present disclosure, the number of masks is not increased. By adding additional structures on both sides of at least one of the common electrode and the pixel electrode, the vertical crosstalk problem of the liquid crystal display product can be improved and the display quality can be enhanced. Moreover, the additional structure is located under the light-shielding layer, and there is no need to change the structure and size of the pixel and the light-shielding layer, and the optical properties such as pixel transmittance and contrast are not affected.

[0141] The display device 100 may include any device or product having a display function. For example, the display device 100 may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0142] It should be understood that the display device 100 according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate 10 , which can be referred to in the above description of the display substrate 10 and will not be repeated here.

[0143] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0144] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, characterized in that: include: substrate; a plurality of first electrodes, located on the base substrate and arranged in an array along a first direction and a second direction to form first electrode rows extending in the first direction and first electrode columns extending in the second direction; as well as Data lines are located on the base substrate and extend along the second direction, wherein the orthographic projections of the data lines on the base substrate and the orthographic projections of the first electrode columns on the base substrate are alternately arranged; the data lines include a first data line and a second data line; Wherein, at least one of the first electrodes comprises: a first electrode body; The first electrode protrusion is located on a side of the first electrode body close to the first data line. The second electrode protrusion is located on a side of the first electrode body close to the second data line. The distance between the first electrode body and the first data line is less than or equal to the distance between the first electrode body and the second data line, and the overlapping area between the orthographic projection of the first electrode protrusion on the base substrate and the orthographic projection of the first data line on the base substrate is less than or equal to the overlapping area between the orthographic projection of the second electrode protrusion on the base substrate and the orthographic projection of the second data line on the base substrate; or The distance between the first electrode body and the first data line is greater than or equal to the distance between the first electrode body and the second data line, and the overlapping area between the orthographic projection of the first electrode protrusion on the base substrate and the orthographic projection of the first data line on the base substrate is greater than or equal to the overlapping area between the orthographic projection of the second electrode protrusion on the base substrate and the orthographic projection of the second data line on the base substrate.

2. The array substrate according to claim 1, wherein: The first electrode protrusion is provided in the same layer as the first electrode body and is electrically connected thereto, and the first electrode protrusion protrudes from the first electrode body toward the first data line; and / or, The second electrode protrusion is provided in the same layer as the first electrode body and is electrically connected thereto. The second electrode protrusion protrudes from the first electrode body toward the second data line.

3. The array substrate according to claim 2, wherein: The first data line includes: a first data line body; and The first data line protrusion is located on a side of the first data line body close to the first electrode body, and the second data line includes: a second data line body; and The second data line protrusion is located on a side of the second data line body close to the first electrode body. The distance between the first data line protrusion and the first electrode body is less than or equal to the distance between the second data line protrusion and the first electrode body, and the overlapping area between the orthographic projection of the first data line protrusion on the base substrate and the orthographic projection of the first electrode protrusion on the base substrate is less than or equal to the overlapping area between the orthographic projection of the second data line protrusion on the base substrate and the orthographic projection of the second electrode protrusion on the base substrate; or The distance between the first data line protrusion and the first electrode body is greater than or equal to the distance between the second data line protrusion and the first electrode body, and the overlapping area between the orthographic projection of the first data line protrusion on the base substrate and the orthographic projection of the first electrode protrusion on the base substrate is greater than or equal to the overlapping area between the orthographic projection of the second data line protrusion on the base substrate and the orthographic projection of the second electrode protrusion on the base substrate.

4. The array substrate according to claim 3, wherein: The first data line protrusion and the first data line body are provided in the same layer and are electrically connected; and / or, The second data line protrusion and the second data line body are arranged in the same layer and are electrically connected.

5. The array substrate according to claim 3, wherein: The first data line protrusion and the second data line protrusion are located between adjacent first electrode columns, and the first data line protrusion and the second data line protrusion are spaced apart along the first direction; and / or, The array substrate further includes a scan signal line extending along a first direction, and the orthographic projections of the first data line protrusion and the second data line protrusion on the base substrate do not overlap with the orthographic projection of the scan signal line on the base substrate.

6. The array substrate according to claim 3, further comprising: an active layer located between the base substrate and the first electrode, wherein an orthographic projection of at least a portion of the active layer on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate, and the at least a portion of the active layer is electrically connected to the data line; At least a portion of the active layer, the first data line protrusion, and at least a portion of the second data line protrusion are disposed in the same layer.

7. The array substrate according to claim 1, wherein: The array substrate further includes: a plurality of second electrodes located between the base substrate and the first electrodes, the plurality of second electrodes and the plurality of first electrodes being located on different layers of the array substrate, wherein orthographic projections of the plurality of second electrodes on the base substrate at least partially overlap with orthographic projections of the plurality of first electrodes on the base substrate; The first electrode protrusion includes a first sub-electrode protrusion and a second sub-electrode protrusion, and the second electrode protrusion includes a third sub-electrode protrusion and a fourth sub-electrode protrusion; The first sub-electrode protrusion and the third sub-electrode protrusion are provided in the same layer as the first electrode and are electrically connected; The second sub-electrode protrusion and the fourth sub-electrode protrusion are provided in the same layer as the second electrode and are electrically connected; and The orthographic projections of the first sub-electrode protrusion, the second sub-electrode protrusion, the third sub-electrode protrusion, and the fourth sub-electrode protrusion on the base substrate do not overlap with each other.

8. The array substrate according to claim 1 or 7, wherein: The first electrode is one of a pixel electrode and a common electrode.

9. The array substrate according to claim 1, wherein: The plurality of first electrode protrusions and the plurality of second electrode protrusions on the same first electrode column are staggered along the second direction.

10. The array substrate according to claim 1, wherein: The first electrode protrusion and the second electrode protrusion are symmetrical with respect to the center of the first electrode.

11. The array substrate according to claim 1, wherein: The orthographic projections of the first electrode protrusion and the second electrode protrusion on the base substrate are one of a triangle, a sector, a rectangle, and an ellipse.

12. A display device, characterized in that: The invention comprises an array substrate according to any one of claims 1 to 11.

13. The display device according to claim 12, wherein: The display device further includes a color filter substrate, which is arranged opposite to the array substrate; Wherein, the color film substrate comprises: a light shielding layer, wherein an orthographic projection of the light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate; The first electrode protrusion and the second electrode protrusion are located on a side of the light shielding layer close to the base substrate, and the orthographic projections of the first electrode protrusion and the second electrode protrusion on the base substrate are respectively located within the orthographic projections of the light shielding layer on the base substrate.

Images